diff options
| author | David Lechner <david@pybricks.com> | 2019-06-27 16:43:05 -0500 |
|---|---|---|
| committer | Damien George <damien.p.george@gmail.com> | 2019-07-03 01:24:22 +1000 |
| commit | f3a5b313e55e8853928702eec16c932481f370fc (patch) | |
| tree | f9d01fea7cd4e68d3420f86405d05c9e64add7d9 /py | |
| parent | 62b00dd5d8cd6207147d37222e1c249ef6381841 (diff) | |
py/nlrthumb: Check __thumb2__ instead of __ARM_ARCH_6M__.
This fixes compiling for older architectures (e.g. armv5tej).
According to [1], the limit of R0-R7 for the STR and LDR instructions is
tied to the Thumb instruction set and not any specific processor
architectures.
[1]: http://www.keil.com/support/man/docs/armasm/armasm_dom1361289906890.htm
Diffstat (limited to 'py')
| -rw-r--r-- | py/nlrthumb.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/py/nlrthumb.c b/py/nlrthumb.c index 32fa6b117..eef05229d 100644 --- a/py/nlrthumb.c +++ b/py/nlrthumb.c @@ -44,7 +44,7 @@ __attribute__((naked)) unsigned int nlr_push(nlr_buf_t *nlr) { "str r6, [r0, #20] \n" // store r6 into nlr_buf "str r7, [r0, #24] \n" // store r7 into nlr_buf -#if defined(__ARM_ARCH_6M__) +#if !defined(__thumb2__) "mov r1, r8 \n" "str r1, [r0, #28] \n" // store r8 into nlr_buf "mov r1, r9 \n" @@ -71,7 +71,7 @@ __attribute__((naked)) unsigned int nlr_push(nlr_buf_t *nlr) { "str lr, [r0, #8] \n" // store lr into nlr_buf #endif -#if defined(__ARM_ARCH_6M__) +#if !defined(__thumb2__) "ldr r1, nlr_push_tail_var \n" "bx r1 \n" // do the rest in C ".align 2 \n" @@ -102,7 +102,7 @@ NORETURN void nlr_jump(void *val) { "ldr r6, [r0, #20] \n" // load r6 from nlr_buf "ldr r7, [r0, #24] \n" // load r7 from nlr_buf -#if defined(__ARM_ARCH_6M__) +#if !defined(__thumb2__) "ldr r1, [r0, #28] \n" // load r8 from nlr_buf "mov r8, r1 \n" "ldr r1, [r0, #32] \n" // load r9 from nlr_buf |