py/emitinlinerv32: Add Zba opcodes to the inline assembler.

This commit adds support for Zba opcodes to the RV32 inline assembler.

Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs
a scaled addition (by 1, 2, or 3 bits respectively).  At the moment only
qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these
opcodes (the latter only when using the RISCV variant).

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

1 files changed, 18 insertions, 0 deletions

diff --git a/tests/inlineasm/rv32/asmzba.py b/tests/inlineasm/rv32/asmzba.py
new file mode 100644
index 000000000..75f3573c8
--- /dev/null
+++ b/tests/inlineasm/rv32/asmzba.py
@@ -0,0 +1,18 @@
+@micropython.asm_rv32
+def test_sh1add(a0, a1):
+    sh1add(a0, a0, a1)
+
+
+@micropython.asm_rv32
+def test_sh2add(a0, a1):
+    sh2add(a0, a0, a1)
+
+
+@micropython.asm_rv32
+def test_sh3add(a0, a1):
+    sh3add(a0, a0, a1)
+
+
+print(hex(test_sh1add(10, 20)))
+print(hex(test_sh2add(10, 20)))
+print(hex(test_sh3add(10, 20)))