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| author | Alessandro Gatti <a.gatti@frob.it> | 2025-07-07 22:09:25 +0200 |
|---|---|---|
| committer | Alessandro Gatti <a.gatti@frob.it> | 2025-09-19 15:52:20 +0200 |
| commit | 40dbf774151140839c74e0bf226bb7d254129eb9 (patch) | |
| tree | f11bec6e39485dde654ed3a0257707f24f8c3798 /tests/internal_bench/class_instance-0-object.py | |
| parent | 965c77ade9512532529379e26b37eaa7ed4a6e02 (diff) | |
py/emitinlinerv32: Add Zba opcodes to the inline assembler.
This commit adds support for Zba opcodes to the RV32 inline assembler.
Three new opcodes were added, SH1ADD, SH2ADD, and SH3ADD, which performs
a scaled addition (by 1, 2, or 3 bits respectively). At the moment only
qemu's VIRT_RV32 and rp2's RPI_PICO2/RPI_PICO2_W ports support these
opcodes (the latter only when using the RISCV variant).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
Diffstat (limited to 'tests/internal_bench/class_instance-0-object.py')
0 files changed, 0 insertions, 0 deletions