diff options
| -rw-r--r-- | ports/stm32/mpconfigboard_common.h | 19 | ||||
| -rw-r--r-- | ports/stm32/powerctrl.c | 4 | ||||
| -rw-r--r-- | ports/stm32/system_stm32.c | 34 |
3 files changed, 38 insertions, 19 deletions
diff --git a/ports/stm32/mpconfigboard_common.h b/ports/stm32/mpconfigboard_common.h index 948897b21..6fb9289e0 100644 --- a/ports/stm32/mpconfigboard_common.h +++ b/ports/stm32/mpconfigboard_common.h @@ -310,6 +310,25 @@ #endif #endif +// Configure the default bus clock divider values +#ifndef MICROPY_HW_CLK_AHB_DIV +#if defined(STM32H7) +#define MICROPY_HW_CLK_AHB_DIV (RCC_HCLK_DIV2) +#define MICROPY_HW_CLK_APB1_DIV (RCC_APB1_DIV2) +#define MICROPY_HW_CLK_APB2_DIV (RCC_APB2_DIV2) +#define MICROPY_HW_CLK_APB3_DIV (RCC_APB3_DIV2) +#define MICROPY_HW_CLK_APB4_DIV (RCC_APB4_DIV2) +#elif defined(STM32L4) +#define MICROPY_HW_CLK_AHB_DIV (RCC_SYSCLK_DIV1) +#define MICROPY_HW_CLK_APB1_DIV (RCC_HCLK_DIV1) +#define MICROPY_HW_CLK_APB2_DIV (RCC_HCLK_DIV1) +#else +#define MICROPY_HW_CLK_AHB_DIV (RCC_SYSCLK_DIV1) +#define MICROPY_HW_CLK_APB1_DIV (RCC_HCLK_DIV4) +#define MICROPY_HW_CLK_APB2_DIV (RCC_HCLK_DIV2) +#endif +#endif + // If disabled then try normal (non-bypass) LSE first, with fallback to LSI. // If enabled first try LSE in bypass mode. If that fails to start, try non-bypass mode, with fallback to LSI. #ifndef MICROPY_HW_RTC_USE_BYPASS diff --git a/ports/stm32/powerctrl.c b/ports/stm32/powerctrl.c index a579713b6..a34927798 100644 --- a/ports/stm32/powerctrl.c +++ b/ports/stm32/powerctrl.c @@ -377,8 +377,8 @@ set_clk: RCC_ClkInitStruct.APB2CLKDivider = calc_apb2_div(ahb / apb2); #if defined(STM32H7) RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + RCC_ClkInitStruct.APB3CLKDivider = MICROPY_HW_CLK_APB3_DIV; + RCC_ClkInitStruct.APB4CLKDivider = MICROPY_HW_CLK_APB4_DIV; #endif #if MICROPY_HW_CLK_LAST_FREQ diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c index 2160e0ac9..72918bbc5 100644 --- a/ports/stm32/system_stm32.c +++ b/ports/stm32/system_stm32.c @@ -272,9 +272,9 @@ void SystemClock_Config(void) { n = MICROPY_HW_CLK_PLLN; p = MICROPY_HW_CLK_PLLP; q = MICROPY_HW_CLK_PLLQ; - h = RCC_SYSCLK_DIV1; - b1 = RCC_HCLK_DIV4; - b2 = RCC_HCLK_DIV2; + h = MICROPY_HW_CLK_AHB_DIV; + b1 = MICROPY_HW_CLK_APB1_DIV; + b2 = MICROPY_HW_CLK_APB2_DIV; } else { h <<= 4; b1 <<= 10; @@ -285,9 +285,9 @@ void SystemClock_Config(void) { RCC_OscInitStruct.PLL.PLLP = p; // MICROPY_HW_CLK_PLLP; RCC_OscInitStruct.PLL.PLLQ = q; // MICROPY_HW_CLK_PLLQ; - RCC_ClkInitStruct.AHBCLKDivider = h; // RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = b1; // RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = b2; // RCC_HCLK_DIV2; + RCC_ClkInitStruct.AHBCLKDivider = h; + RCC_ClkInitStruct.APB1CLKDivider = b1; + RCC_ClkInitStruct.APB2CLKDivider = b2; #else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM; RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN; @@ -304,20 +304,20 @@ void SystemClock_Config(void) { #endif #if defined(STM32F4) || defined(STM32F7) - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV; + RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV; + RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV; #elif defined(STM32L4) - RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; - RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; + RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV; + RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV; + RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV; #elif defined(STM32H7) RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1; - RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2; - RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2; - RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2; - RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2; - RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2; + RCC_ClkInitStruct.AHBCLKDivider = MICROPY_HW_CLK_AHB_DIV; + RCC_ClkInitStruct.APB3CLKDivider = MICROPY_HW_CLK_APB3_DIV; + RCC_ClkInitStruct.APB1CLKDivider = MICROPY_HW_CLK_APB1_DIV; + RCC_ClkInitStruct.APB2CLKDivider = MICROPY_HW_CLK_APB2_DIV; + RCC_ClkInitStruct.APB4CLKDivider = MICROPY_HW_CLK_APB4_DIV; #endif #endif |