diff options
| -rw-r--r-- | docs/mimxrt/pinout.rst | 3 | ||||
| -rw-r--r-- | docs/mimxrt/quickref.rst | 8 | ||||
| -rw-r--r-- | ports/mimxrt/machine_spi.c | 13 |
3 files changed, 17 insertions, 7 deletions
diff --git a/docs/mimxrt/pinout.rst b/docs/mimxrt/pinout.rst index b82c153fc..ef53fa63b 100644 --- a/docs/mimxrt/pinout.rst +++ b/docs/mimxrt/pinout.rst @@ -322,7 +322,8 @@ Olimex RT1010Py - CS0/-/SDO/SDI/SCK SDCARD wi Seeed ARCH MIX J4_12/-/J4_14/J4_13/J4_15 J3_09/J3_05/J3_08_J3_11 ================= ========================= ======================= =============== -Pins denoted with (*) are by default not wired at the board. +Pins denoted with (*) are by default not wired at the board. The CS0 and CS1 signals +are enabled with the keyword option cs=0 or cs=1 of the SPI object constructor. .. _mimxrt_i2c_pinout: diff --git a/docs/mimxrt/quickref.rst b/docs/mimxrt/quickref.rst index 0a14c632a..c75fe60c8 100644 --- a/docs/mimxrt/quickref.rst +++ b/docs/mimxrt/quickref.rst @@ -301,13 +301,19 @@ There are up to four hardware SPI channels that allow faster transmission rates (up to 30Mhz). Hardware SPI is accessed via the :ref:`machine.SPI <machine.SPI>` class and has the same methods as software SPI above:: - from machine import SPI + from machine import SPI, Pin spi = SPI(0, 10000000) + cs_pin = Pin(6, Pin.OUT, value=1) + cs_pin(0) spi.write('Hello World') + cs_pin(1) For the assignment of Pins to SPI signals, refer to :ref:`Hardware SPI pinout <mimxrt_spi_pinout>`. +The keyword option cs=n can be used to enable the cs pin 0 or 1 for an automatic cs signal. The +default is cs=-1. Using cs=-1 the automatic cs signal is not created. +In that case, cs has to be set by the script. Clearing that assignment requires a power cycle. Notes: diff --git a/ports/mimxrt/machine_spi.c b/ports/mimxrt/machine_spi.c index 805ed9a0a..32bc77c34 100644 --- a/ports/mimxrt/machine_spi.c +++ b/ports/mimxrt/machine_spi.c @@ -77,7 +77,7 @@ static const iomux_table_t iomux_table[] = { IOMUX_TABLE_SPI }; -bool lpspi_set_iomux(int8_t spi, uint8_t drive, uint8_t cs) { +bool lpspi_set_iomux(int8_t spi, uint8_t drive, int8_t cs) { int index = (spi - 1) * 5; if (SCK.muxRegister != 0) { @@ -93,7 +93,7 @@ bool lpspi_set_iomux(int8_t spi, uint8_t drive, uint8_t cs) { IOMUXC_SetPinMux(CS1.muxRegister, CS1.muxMode, CS1.inputRegister, CS1.inputDaisy, CS1.configRegister, 0U); IOMUXC_SetPinConfig(CS1.muxRegister, CS1.muxMode, CS1.inputRegister, CS1.inputDaisy, CS1.configRegister, pin_generate_config(PIN_PULL_UP_100K, PIN_MODE_OUT, drive, CS1.configRegister)); - } else { + } else if (cs != -1) { mp_raise_ValueError(MP_ERROR_TEXT("The chosen CS is not available")); } @@ -131,7 +131,7 @@ mp_obj_t machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_FIRSTBIT} }, { MP_QSTR_gap_ns, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, { MP_QSTR_drive, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = DEFAULT_SPI_DRIVE} }, - { MP_QSTR_cs, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_cs, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, }; // Parse the arguments. @@ -173,8 +173,11 @@ mp_obj_t machine_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n } self->master_config->lastSckToPcsDelayInNanoSec = self->master_config->betweenTransferDelayInNanoSec; self->master_config->pcsToSckDelayInNanoSec = self->master_config->betweenTransferDelayInNanoSec; - uint8_t cs = args[ARG_cs].u_int; - if (cs <= 1) { + int8_t cs = args[ARG_cs].u_int; + // In the SPI master_config for automatic CS the value cs=0 is set already, + // so only cs=1 has to be addressed here. The case cs == -1 for manual CS is handled + // in the function spi_set_iomux() and the value in the master_config can stay at 0. + if (cs == 1) { self->master_config->whichPcs = cs; } LPSPI_MasterInit(self->spi_inst, self->master_config, BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT); |