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272 files changed, 30866 insertions, 0 deletions
diff --git a/ports/renesas-ra/Makefile b/ports/renesas-ra/Makefile new file mode 100644 index 000000000..efbcb5f70 --- /dev/null +++ b/ports/renesas-ra/Makefile @@ -0,0 +1,540 @@ +# Select the board to build for: if not given on the command line, +# then default to RA6M2_EK. +BOARD ?= RA6M2_EK + +# If the build directory is not given, make it reflect the board name. +BUILD ?= build-$(BOARD) + +BOARD_DIR ?= boards/$(BOARD) +ifeq ($(wildcard $(BOARD_DIR)/.),) +$(error Invalid BOARD specified: $(BOARD_DIR)) +endif + +ifeq ($(BOARD),RA4M1_CLICKER) +BOARD_LOW = ra4m1_ek +CMSIS_MCU_LOW = ra4m1 +CMSIS_MCU_CAP = RA4M1 +USE_FSP_LPM = 0 +endif + +ifeq ($(BOARD),RA4M1_EK) +BOARD_LOW = ra4m1_ek +CMSIS_MCU_LOW = ra4m1 +CMSIS_MCU_CAP = RA4M1 +USE_FSP_LPM = 0 +endif + +ifeq ($(BOARD),RA4W1_EK) +BOARD_LOW = ra4w1_ek +CMSIS_MCU_LOW = ra4w1 +CMSIS_MCU_CAP = RA4W1 +USE_FSP_LPM = 1 +endif + +ifeq ($(BOARD),RA6M1_EK) +BOARD_LOW = ra6m1_ek +CMSIS_MCU_LOW = ra6m1 +CMSIS_MCU_CAP = RA6M1 +USE_FSP_LPM = 1 +endif + +ifeq ($(BOARD),RA6M2_EK) +BOARD_LOW = ra6m2_ek +CMSIS_MCU_LOW = ra6m2 +CMSIS_MCU_CAP = RA6M2 +USE_FSP_LPM = 1 +endif + +# select use wrapper function of FSP library +USE_FSP_FLASH = 1 + +include ../../py/mkenv.mk +-include mpconfigport.mk +include $(BOARD_DIR)/mpconfigboard.mk + +# Files that are generated and needed before the QSTR build. +#QSTR_GENERATED_HEADERS = $(BUILD)/pins_qstr.h $(BUILD)/modstm_qstr.h +QSTR_GENERATED_HEADERS = $(BUILD)/pins_qstr.h +# qstr definitions (must come before including py.mk) +QSTR_DEFS += qstrdefsport.h $(QSTR_GENERATED_HEADERS) +QSTR_GLOBAL_DEPENDENCIES += mpconfigboard_common.h $(BOARD_DIR)/mpconfigboard.h $(QSTR_GENERATED_HEADERS) + +# MicroPython feature configurations +MICROPY_ROM_TEXT_COMPRESSION ?= 1 + +# File containing description of content to be frozen into firmware. +FROZEN_MANIFEST ?= boards/manifest.py + +# include py core make definitions +include $(TOP)/py/py.mk + +GIT_SUBMODULES += lib/fsp + +MCU_SERIES_UPPER = $(shell echo $(MCU_SERIES) | tr '[:lower:]' '[:upper:]') +CMSIS_MCU_LOWER = $(shell echo $(CMSIS_MCU) | tr '[:upper:]' '[:lower:]') + +LD_DIR=boards +CMSIS_DIR=lib/cmsis/inc +HAL_DIR=lib/fsp +STARTUP_FILE ?= lib/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/startup.o +SYSTEM_FILE ?= lib/fsp/ra/fsp/src/bsp/cmsis/Device/RENESAS/Source/system.o + +# Select the cross compile prefix +CROSS_COMPILE ?= arm-none-eabi- + +INC += -I. +INC += -I$(TOP) +INC += -I$(BUILD) +INC += -I$(TOP)/$(CMSIS_DIR) +INC += -I$(TOP)/$(HAL_DIR) +INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc +INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc/api +INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/inc/instances +INC += -I$(TOP)/$(HAL_DIR)/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include +#INC += -Ilwip_inc +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2)) +INC += -Ira +endif +INC += -I$(BOARD_DIR)/ra_gen +INC += -I$(BOARD_DIR)/ra_cfg/fsp_cfg +INC += -I$(BOARD_DIR)/ra_cfg/fsp_cfg/bsp +INC += -Idebug + +CFLAGS += -D$(CMSIS_MCU) +CFLAGS += -DRA_HAL_H='<$(CMSIS_MCU)_hal.h>' + +# Basic Cortex-M flags +CFLAGS_CORTEX_M = -mthumb + +# Select hardware floating-point support +SUPPORTS_HARDWARE_FP_SINGLE = 0 +SUPPORTS_HARDWARE_FP_DOUBLE = 0 +ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES),m4)) +CFLAGS_CORTEX_M += -mfpu=fpv4-sp-d16 -mfloat-abi=hard +SUPPORTS_HARDWARE_FP_SINGLE = 1 +endif + +# Options for particular MCU series +CFLAGS_MCU_RA4M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 +CFLAGS_MCU_RA4W1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 +CFLAGS_MCU_RA6M1 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 +CFLAGS_MCU_RA6M2 = $(CFLAGS_CORTEX_M) -mtune=cortex-m4 -mcpu=cortex-m4 + +CFLAGS += $(INC) -Wall -Wpointer-arith -Werror -Wdouble-promotion -Wfloat-conversion -std=gnu99 -nostdlib $(CFLAGS_MOD) $(CFLAGS_EXTRA) +#CFLAGS += -D$(CMSIS_MCU) +CFLAGS += $(CFLAGS_MCU_$(CMSIS_MCU)) +CFLAGS += $(COPT) +CFLAGS += -I$(BOARD_DIR) + +# Configure floating point support +ifeq ($(MICROPY_FLOAT_IMPL),double) +CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_DOUBLE +else +ifeq ($(MICROPY_FLOAT_IMPL),none) +CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_NONE +else +CFLAGS += -DMICROPY_FLOAT_IMPL=MICROPY_FLOAT_IMPL_FLOAT +CFLAGS += -fsingle-precision-constant +endif +endif + +LDFLAGS = -nostdlib -L $(LD_DIR) $(addprefix -T,$(LD_FILES)) -Map=$(@:.elf=.map) --cref +LDFLAGS += --defsym=_estack_reserve=8 +LIBS += "$(shell $(CC) $(CFLAGS) -print-libgcc-file-name)" + +# Remove uncalled code from the final image. +CFLAGS += -fdata-sections -ffunction-sections +LDFLAGS += --gc-sections + +# Debugging/Optimization +ifeq ($(DEBUG), 1) +CFLAGS += -g -DPENDSV_DEBUG +#COPT = -Og +COPT = -Os +# Disable text compression in debug builds +MICROPY_ROM_TEXT_COMPRESSION = 0 +else +COPT += -Os -DNDEBUG +endif + +# Flags for optional C++ source code +CXXFLAGS += $(filter-out -Wmissing-prototypes -Wold-style-definition -std=gnu99,$(CFLAGS)) +CXXFLAGS += $(CXXFLAGS_MOD) +ifneq ($(SRC_CXX)$(SRC_MOD_CXX),) +LIBSTDCPP_FILE_NAME = "$(shell $(CXX) $(CXXFLAGS) -print-file-name=libstdc++.a)" +LDFLAGS += -L"$(shell dirname $(LIBSTDCPP_FILE_NAME))" +endif + +# Options for mpy-cross +MPY_CROSS_FLAGS += -march=armv7m + +SHARED_SRC_C += $(addprefix shared/,\ + libc/string0.c \ + netutils/dhcpserver.c \ + netutils/netutils.c \ + netutils/trace.c \ + readline/readline.c \ + runtime/gchelper_native.c \ + runtime/interrupt_char.c \ + runtime/mpirq.c \ + runtime/pyexec.c \ + runtime/stdout_helpers.c \ + runtime/sys_stdio_mphal.c \ + timeutils/timeutils.c \ + ) + +ifeq ($(MICROPY_FLOAT_IMPL),double) +LIBM_SRC_C += $(addprefix lib/libm_dbl/,\ + __cos.c \ + __expo2.c \ + __fpclassify.c \ + __rem_pio2.c \ + __rem_pio2_large.c \ + __signbit.c \ + __sin.c \ + __tan.c \ + acos.c \ + acosh.c \ + asin.c \ + asinh.c \ + atan.c \ + atan2.c \ + atanh.c \ + ceil.c \ + cos.c \ + cosh.c \ + copysign.c \ + erf.c \ + exp.c \ + expm1.c \ + floor.c \ + fmod.c \ + frexp.c \ + ldexp.c \ + lgamma.c \ + log.c \ + log10.c \ + log1p.c \ + modf.c \ + nearbyint.c \ + pow.c \ + rint.c \ + round.c \ + scalbn.c \ + sin.c \ + sinh.c \ + tan.c \ + tanh.c \ + tgamma.c \ + trunc.c \ + ) +ifeq ($(SUPPORTS_HARDWARE_FP_DOUBLE),1) +LIBM_SRC_C += lib/libm_dbl/thumb_vfp_sqrt.c +else +LIBM_SRC_C += lib/libm_dbl/sqrt.c +endif +else +LIBM_SRC_C += $(addprefix lib/libm/,\ + math.c \ + acoshf.c \ + asinfacosf.c \ + asinhf.c \ + atan2f.c \ + atanf.c \ + atanhf.c \ + ef_rem_pio2.c \ + erf_lgamma.c \ + fmodf.c \ + kf_cos.c \ + kf_rem_pio2.c \ + kf_sin.c \ + kf_tan.c \ + log1pf.c \ + nearbyintf.c \ + roundf.c \ + sf_cos.c \ + sf_erf.c \ + sf_frexp.c \ + sf_ldexp.c \ + sf_modf.c \ + sf_sin.c \ + sf_tan.c \ + wf_lgamma.c \ + wf_tgamma.c \ + ) +ifeq ($(SUPPORTS_HARDWARE_FP_SINGLE),1) +LIBM_SRC_C += lib/libm/thumb_vfp_sqrtf.c +else +LIBM_SRC_C += lib/libm/ef_sqrt.c +endif +endif + +LIBM_O = $(addprefix $(BUILD)/, $(LIBM_SRC_C:.c=.o)) + +# Too many warnings in libm_dbl, disable for now. +ifeq ($(MICROPY_FLOAT_IMPL),double) +$(LIBM_O): CFLAGS := $(filter-out -Wdouble-promotion -Wfloat-conversion, $(CFLAGS)) +endif + +EXTMOD_SRC_C += $(addprefix extmod/,\ + modonewire.c \ + ) + +DRIVERS_SRC_C += $(addprefix drivers/,\ + bus/softspi.c \ + bus/softqspi.c \ + memory/spiflash.c \ + dht/dht.c \ + ) + +SRC_C += \ + boardctrl.c \ + main.c \ + ra_it.c \ + mphalport.c \ + mpthreadport.c \ + irq.c \ + pendsv.c \ + systick.c \ + softtimer.c \ + powerctrl.c \ + powerctrlboot.c \ + pybthread.c \ + factoryreset.c \ + timer.c \ + led.c \ + uart.c \ + gccollect.c \ + help.c \ + machine_adc.c \ + machine_i2c.c \ + machine_spi.c \ + machine_timer.c \ + machine_uart.c \ + machine_pin.c \ + machine_rtc.c \ + modmachine.c \ + modutime.c \ + extint.c \ + usrsw.c \ + flash.c \ + flashbdev.c \ + storage.c \ + fatfs_port.c \ + $(BOARD_DIR)/src/hal_entry.c \ + $(wildcard $(BOARD_DIR)/*.c) + +SRC_C += $(addprefix $(BOARD_DIR)/ra_gen/,\ + common_data.c \ + hal_data.c \ + main.c \ + pin_data.c \ + vector_data.c \ + ) + +SRC_CXX += \ + $(SRC_MOD_CXX) + +SRC_O += \ + $(STARTUP_FILE) \ + $(SYSTEM_FILE) + +SRC_O += \ + shared/runtime/gchelper_m3.o + +HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/board/$(BOARD_LOW)/,\ + board_init.c \ + board_leds.c \ + ) + +HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/bsp/mcu/all/,\ + bsp_clocks.c \ + bsp_common.c \ + bsp_delay.c \ + bsp_group_irq.c \ + bsp_guard.c \ + bsp_io.c \ + bsp_irq.c \ + bsp_register_protection.c \ + bsp_rom_registers.c \ + bsp_sbrk.c \ + bsp_security.c \ + ) + +HAL_SRC_C += $(addprefix $(HAL_DIR)/ra/fsp/src/,\ + r_ioport/r_ioport.c \ + ) + +ifeq ($(USE_FSP_LPM), 1) +CFLAGS += -DUSE_FSP_LPM +HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_lpm/r_lpm.c +endif + +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1)) +ifeq ($(USE_FSP_FLASH), 1) +CFLAGS += -DUSE_FSP_FLASH +HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_lp/r_flash_lp.c +endif +endif + +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1 RA6M2)) +ifeq ($(USE_FSP_FLASH), 1) +CFLAGS += -DUSE_FSP_FLASH +HAL_SRC_C += $(HAL_DIR)/ra/fsp/src/r_flash_hp/r_flash_hp.c +endif +endif + +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1 RA4W1 RA6M1 RA6M2)) +HAL_SRC_C += $(addprefix ra/,\ + ra_adc.c \ + ra_flash.c \ + ra_gpio.c \ + ra_i2c.c \ + ra_icu.c \ + ra_init.c \ + ra_int.c \ + ra_rtc.c \ + ra_sci.c \ + ra_spi.c \ + ra_timer.c \ + ra_utils.c \ + ) + +endif + +OBJ += $(PY_O) +OBJ += $(addprefix $(BUILD)/, $(LIB_SRC_C:.c=.o)) +OBJ += $(LIBM_O) +OBJ += $(addprefix $(BUILD)/, $(SHARED_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(EXTMOD_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(DRIVERS_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(HAL_SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_C:.c=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_CXX:.cpp=.o)) +OBJ += $(addprefix $(BUILD)/, $(SRC_O)) +OBJ += $(addprefix $(BUILD)/, $(SRC_MOD:.c=.o)) +OBJ += $(BUILD)/pins_$(BOARD).o + +# This file contains performance critical functions so turn up the optimisation +# level. It doesn't add much to the code size and improves performance a bit. +# Don't use -O3 with this file because gcc tries to optimise memset in terms of itself. +$(BUILD)/shared/libc/string0.o: COPT += -O2 + +# We put several files into the first 16K section with the ISRs. +# If we compile these using -O0 then it won't fit. So if you really want these +# to be compiled with -O0, then edit boards/common.ld (in the .isr_vector section) +# and comment out the following lines. +$(BUILD)/$(OOFATFS_DIR)/ff.o: COPT += -Os +$(filter $(PY_BUILD)/../extmod/vfs_fat_%.o, $(PY_O)): COPT += -Os +$(PY_BUILD)/formatfloat.o: COPT += -Os +$(PY_BUILD)/parsenum.o: COPT += -Os +$(PY_BUILD)/mpprint.o: COPT += -Os + +all: $(TOP)/lib/fsp/README.md $(BUILD)/firmware.hex + +# For convenience, automatically fetch required submodules if they don't exist +$(TOP)/lib/fsp/README.md: + $(ECHO) "fsp submodule not found, fetching it now..." + (cd $(TOP) && git submodule update --init lib/fsp) + +ifneq ($(FROZEN_MANIFEST)$(FROZEN_DIR),) +# To use frozen source modules, put your .py files in a subdirectory (eg scripts/) +# and then invoke make with FROZEN_DIR=scripts (be sure to build from scratch). +CFLAGS += -DMICROPY_MODULE_FROZEN_STR +endif + +ifneq ($(FROZEN_MANIFEST)$(FROZEN_MPY_DIR),) +# To use frozen bytecode, put your .py files in a subdirectory (eg frozen/) and +# then invoke make with FROZEN_MPY_DIR=frozen (be sure to build from scratch). +CFLAGS += -DMICROPY_QSTR_EXTRA_POOL=mp_qstr_frozen_const_pool +CFLAGS += -DMICROPY_MODULE_FROZEN_MPY +endif + +define GENERATE_ELF + $(ECHO) "LINK $(1)" + $(Q)$(LD) $(LDFLAGS) -o $(1) $(2) $(LDFLAGS_MOD) $(LIBS) + $(Q)$(SIZE) $(1) +endef + +define GENERATE_BIN + $(ECHO) "GEN $(1)" + $(Q)$(OBJCOPY) -O binary $(addprefix -j ,$(3)) $(2) $(1) +endef + +define GENERATE_HEX + $(ECHO) "GEN $(1)" + $(Q)$(OBJCOPY) -O ihex $(2) $(1) +endef + +.PHONY: + +# A board should specify TEXT0_ADDR if to use a different location than the +# default for the firmware memory location. A board can also optionally define +# TEXT1_ADDR to split the firmware into two sections; see below for details. +TEXT0_ADDR ?= 0x00000000 + +# No TEXT1_ADDR given so put all firmware at TEXT0_ADDR location + +TEXT0_SECTIONS ?= .isr_vector .text .data + +$(BUILD)/firmware.bin: $(BUILD)/firmware.elf + $(call GENERATE_BIN,$@,$^,$(TEXT0_SECTIONS)) + +$(BUILD)/firmware.hex: $(BUILD)/firmware.elf + $(call GENERATE_HEX,$@,$^) + +$(BUILD)/firmware.elf: $(OBJ) + $(call GENERATE_ELF,$@,$^) + +MAKE_PINS = boards/make-pins.py +BOARD_PINS = $(BOARD_DIR)/pins.csv +PREFIX_FILE = boards/ra_pin_prefix.c +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4M1)) +AF_FILE = boards/ra4m1_af.csv +endif +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA4W1)) +AF_FILE = boards/ra4w1_af.csv +endif +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M1)) +AF_FILE = boards/ra6m1_af.csv +endif +ifeq ($(CMSIS_MCU),$(filter $(CMSIS_MCU),RA6M2)) +AF_FILE = boards/ra6m2_af.csv +endif +GEN_PINS_SRC = $(BUILD)/pins_$(BOARD).c +GEN_PINS_HDR = $(HEADER_BUILD)/pins.h +GEN_PINS_QSTR = $(BUILD)/pins_qstr.h +GEN_PINS_AD_CONST = $(HEADER_BUILD)/pins_ad_const.h +GEN_PINS_AF_CONST = $(HEADER_BUILD)/pins_af_const.h +#GEN_PINS_AF_DEFS = $(HEADER_BUILD)/pins_af_defs.h +GEN_PINS_AF_PY = $(BUILD)/pins_af.py + +FILE2H = $(TOP)/tools/file2h.py + +# List of sources for qstr extraction +SRC_QSTR += $(SRC_C) $(SRC_CXX) $(SRC_MOD) $(SHARED_SRC_C) $(EXTMOD_SRC_C) + +# Making OBJ use an order-only depenedency on the generated pins.h file +# has the side effect of making the pins.h file before we actually compile +# any of the objects. The normal dependency generation will deal with the +# case when pins.h is modified. But when it doesn't exist, we don't know +# which source files might need it. +$(OBJ): | $(GEN_PINS_HDR) + +# With conditional pins, we may need to regenerate qstrdefs.h when config +# options change. +$(HEADER_BUILD)/qstrdefs.generated.h: $(BOARD_DIR)/mpconfigboard.h + +# Use a pattern rule here so that make will only call make-pins.py once to make +# both pins_$(BOARD).c and pins.h +.PRECIOUS: $(GEN_PINS_SRC) +$(BUILD)/%_$(BOARD).c $(HEADER_BUILD)/%.h $(HEADER_BUILD)/%_af_const.h $(HEADER_BUILD)/%_af_defs.h $(BUILD)/%_qstr.h: $(BOARD_DIR)/%.csv $(MAKE_PINS) $(AF_FILE) $(PREFIX_FILE) | $(HEADER_BUILD) + $(ECHO) "GEN $@" + $(Q)$(PYTHON) $(MAKE_PINS) --board $(BOARD_PINS) --af $(AF_FILE) --prefix $(PREFIX_FILE) --hdr $(GEN_PINS_HDR) --qstr $(GEN_PINS_QSTR) --ad-const $(GEN_PINS_AD_CONST) --af-const $(GEN_PINS_AF_CONST) --af-py $(GEN_PINS_AF_PY) > $(GEN_PINS_SRC) + +#$(BUILD)/pins_$(BOARD).o: $(BUILD)/pins_$(BOARD).c +# $(call compile_c) + +CMSIS_MCU_HDR = $(CMSIS_DIR)/$(CMSIS_MCU_LOWER).h + +include $(TOP)/py/mkrules.mk diff --git a/ports/renesas-ra/RA4M1_hal.h b/ports/renesas-ra/RA4M1_hal.h new file mode 100644 index 000000000..7f0ad9666 --- /dev/null +++ b/ports/renesas-ra/RA4M1_hal.h @@ -0,0 +1,103 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA4M1_HAL_H_ +#define PORTS_RA_RA4M1_HAL_H_ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +// #include "hal_data.h" +#include "bsp_api.h" +#include "common_data.h" + +#define SCI_CH 0 +#define SCI_BAUD 115200 +#define UART_CH SCI_CH +#define UART_TxStr sci_tx_str +#define PCLK 48000000 + +#define RA_PRI_SYSTICK (0) +#define RA_PRI_UART (1) +#define RA_PRI_SDIO (4) +#define RA_PRI_DMA (5) +#define RA_PRI_FLASH (6) +#define RA_PRI_OTG_FS (6) +#define RA_PRI_OTG_HS (6) +#define RA_PRI_TIM5 (6) +#define RA_PRI_CAN (7) +#define RA_PRI_SPI (8) +#define RA_PRI_I2C (8) +#define RA_PRI_TIMX (13) +#define RA_PRI_EXTINT (14) +#define RA_PRI_PENDSV (15) +#define RA_PRI_RTC_WKUP (15) + +#include "ra_config.h" +#include "ra_adc.h" +#include "ra_flash.h" +#include "ra_gpio.h" +#include "ra_i2c.h" +#include "ra_icu.h" +#include "ra_init.h" +#include "ra_int.h" +#include "ra_rtc.h" +#include "ra_sci.h" +#include "ra_spi.h" +#include "ra_timer.h" +#include "ra_utils.h" + +typedef enum { + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +#define __IO volatile + +#if defined(USE_DBG_PRINT) +#if !defined(DEBUG_CH) +#define DEBUG_CH SCI_CH +#endif +#if (DEBUG_CH == 0) +#define DEBUG_TX_PIN P411 +#define DEBUG_RX_PIN P410 +#endif +#if (DEBUG_CH == 1) +#define DEBUG_TX_PIN P401 +#define DEBUG_RX_PIN P402 +#endif +#if (DEBUG_CH == 9) +#define DEBUG_TX_PIN P203 +#define DEBUG_RX_PIN P202 +#endif +#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s) +#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c) +#else +#define DEBUG_TXSTR(s) +#define DEBUG_TXCH(c) +#endif + +#endif /* PORTS_RA_RA4M1_HAL_H_ */ diff --git a/ports/renesas-ra/RA4W1_hal.h b/ports/renesas-ra/RA4W1_hal.h new file mode 100644 index 000000000..774ec46b3 --- /dev/null +++ b/ports/renesas-ra/RA4W1_hal.h @@ -0,0 +1,103 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA4W1_HAL_H_ +#define PORTS_RA_RA4W1_HAL_H_ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +// #include "hal_data.h" +#include "bsp_api.h" +#include "common_data.h" + +#define SCI_CH 0 +#define SCI_BAUD 115200 +#define UART_CH SCI_CH +#define UART_TxStr sci_tx_str +#define PCLK 48000000 + +#define RA_PRI_SYSTICK (0) +#define RA_PRI_UART (1) +#define RA_PRI_SDIO (4) +#define RA_PRI_DMA (5) +#define RA_PRI_FLASH (6) +#define RA_PRI_OTG_FS (6) +#define RA_PRI_OTG_HS (6) +#define RA_PRI_TIM5 (6) +#define RA_PRI_CAN (7) +#define RA_PRI_SPI (8) +#define RA_PRI_I2C (8) +#define RA_PRI_TIMX (13) +#define RA_PRI_EXTINT (14) +#define RA_PRI_PENDSV (15) +#define RA_PRI_RTC_WKUP (15) + +#include "ra_config.h" +#include "ra_adc.h" +#include "ra_flash.h" +#include "ra_gpio.h" +#include "ra_i2c.h" +#include "ra_icu.h" +#include "ra_init.h" +#include "ra_int.h" +#include "ra_rtc.h" +#include "ra_sci.h" +#include "ra_spi.h" +#include "ra_timer.h" +#include "ra_utils.h" + +typedef enum { + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +#define __IO volatile + +#if defined(USE_DBG_PRINT) +#if !defined(DEBUG_CH) +#define DEBUG_CH SCI_CH +#endif +#if (DEBUG_CH == 0) +#define DEBUG_TX_PIN P411 +#define DEBUG_RX_PIN P410 +#endif +#if (DEBUG_CH == 1) +#define DEBUG_TX_PIN P401 +#define DEBUG_RX_PIN P402 +#endif +#if (DEBUG_CH == 9) +#define DEBUG_TX_PIN P203 +#define DEBUG_RX_PIN P202 +#endif +#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s) +#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c) +#else +#define DEBUG_TXSTR(s) +#define DEBUG_TXCH(c) +#endif + +#endif /* PORTS_RA_RA4W1_HAL_H_ */ diff --git a/ports/renesas-ra/RA6M1_hal.h b/ports/renesas-ra/RA6M1_hal.h new file mode 100644 index 000000000..9929d29b5 --- /dev/null +++ b/ports/renesas-ra/RA6M1_hal.h @@ -0,0 +1,103 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA6M1_HAL_H_ +#define PORTS_RA_RA6M1_HAL_H_ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +// #include "hal_data.h" +#include "bsp_api.h" +#include "common_data.h" + +#define SCI_CH 0 +#define SCI_BAUD 115200 +#define UART_CH SCI_CH +#define UART_TxStr sci_tx_str +#define PCLK 120000000 + +#define RA_PRI_SYSTICK (0) +#define RA_PRI_UART (1) +#define RA_PRI_SDIO (4) +#define RA_PRI_DMA (5) +#define RA_PRI_FLASH (6) +#define RA_PRI_OTG_FS (6) +#define RA_PRI_OTG_HS (6) +#define RA_PRI_TIM5 (6) +#define RA_PRI_CAN (7) +#define RA_PRI_SPI (8) +#define RA_PRI_I2C (8) +#define RA_PRI_TIMX (13) +#define RA_PRI_EXTINT (14) +#define RA_PRI_PENDSV (15) +#define RA_PRI_RTC_WKUP (15) + +#include "ra_config.h" +#include "ra_adc.h" +#include "ra_flash.h" +#include "ra_gpio.h" +#include "ra_i2c.h" +#include "ra_icu.h" +#include "ra_init.h" +#include "ra_int.h" +#include "ra_rtc.h" +#include "ra_sci.h" +#include "ra_spi.h" +#include "ra_timer.h" +#include "ra_utils.h" + +typedef enum { + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +#define __IO volatile + +#if defined(USE_DBG_PRINT) +#if !defined(DEBUG_CH) +#define DEBUG_CH SCI_CH +#endif +#if (DEBUG_CH == 0) +#define DEBUG_TX_PIN P411 +#define DEBUG_RX_PIN P410 +#endif +#if (DEBUG_CH == 1) +#define DEBUG_TX_PIN P401 +#define DEBUG_RX_PIN P402 +#endif +#if (DEBUG_CH == 9) +#define DEBUG_TX_PIN P203 +#define DEBUG_RX_PIN P202 +#endif +#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s) +#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c) +#else +#define DEBUG_TXSTR(s) +#define DEBUG_TXCH(c) +#endif + +#endif /* PORTS_RA_RA6M1_HAL_H_ */ diff --git a/ports/renesas-ra/RA6M2_hal.h b/ports/renesas-ra/RA6M2_hal.h new file mode 100644 index 000000000..75877cc0f --- /dev/null +++ b/ports/renesas-ra/RA6M2_hal.h @@ -0,0 +1,103 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA6M2_HAL_H_ +#define PORTS_RA_RA6M2_HAL_H_ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +// #include "hal_data.h" +#include "bsp_api.h" +#include "common_data.h" + +#define SCI_CH 0 +#define SCI_BAUD 115200 +#define UART_CH SCI_CH +#define UART_TxStr sci_tx_str +#define PCLK 120000000 + +#define RA_PRI_SYSTICK (0) +#define RA_PRI_UART (1) +#define RA_PRI_SDIO (4) +#define RA_PRI_DMA (5) +#define RA_PRI_FLASH (6) +#define RA_PRI_OTG_FS (6) +#define RA_PRI_OTG_HS (6) +#define RA_PRI_TIM5 (6) +#define RA_PRI_CAN (7) +#define RA_PRI_SPI (8) +#define RA_PRI_I2C (8) +#define RA_PRI_TIMX (13) +#define RA_PRI_EXTINT (14) +#define RA_PRI_PENDSV (15) +#define RA_PRI_RTC_WKUP (15) + +#include "ra_config.h" +#include "ra_adc.h" +#include "ra_flash.h" +#include "ra_gpio.h" +#include "ra_i2c.h" +#include "ra_icu.h" +#include "ra_init.h" +#include "ra_int.h" +#include "ra_rtc.h" +#include "ra_sci.h" +#include "ra_spi.h" +#include "ra_timer.h" +#include "ra_utils.h" + +typedef enum { + HAL_OK = 0x00, + HAL_ERROR = 0x01, + HAL_BUSY = 0x02, + HAL_TIMEOUT = 0x03 +} HAL_StatusTypeDef; + +#define __IO volatile + +#if defined(USE_DBG_PRINT) +#if !defined(DEBUG_CH) +#define DEBUG_CH SCI_CH +#endif +#if (DEBUG_CH == 0) +#define DEBUG_TX_PIN P411 +#define DEBUG_RX_PIN P410 +#endif +#if (DEBUG_CH == 1) +#define DEBUG_TX_PIN P401 +#define DEBUG_RX_PIN P402 +#endif +#if (DEBUG_CH == 9) +#define DEBUG_TX_PIN P203 +#define DEBUG_RX_PIN P202 +#endif +#define DEBUG_TXSTR(s) ra_sci_tx_str(DEBUG_CH, (unsigned char *)s) +#define DEBUG_TXCH(c) ra_sci_tx_ch(DEBUG_CH, c) +#else +#define DEBUG_TXSTR(s) +#define DEBUG_TXCH(c) +#endif + +#endif /* PORTS_RA_RA6M2_HAL_H_ */ diff --git a/ports/renesas-ra/README.md b/ports/renesas-ra/README.md new file mode 100644 index 000000000..482870e1c --- /dev/null +++ b/ports/renesas-ra/README.md @@ -0,0 +1,81 @@ +# The Renesas RA port + +This is a port of MicroPython to the Renesas RA family of microcontrollers. +Currently supported features are: + +- Filesystem on the internal flash using FatFs. +- `utime` module with sleep, time, and ticks functions. +- `uos` module with VFS support. +- `machine` module with the following classes: `Pin`, `ADC`, `I2C`, `SPI`, + `SoftI2C`, `SoftSPI`, `UART`, `RTC` +- sdcard driver if frozen driver is installed. + +Currently supported board product names are: + +- EK-RA6M2 +- RA4M1 CLICKER +- EK-RA6M1 +- EK-RA4M1 +- EK-RA4W1 + +Please refer to the quick reference of `renesas-ra` port for more +information about the boards. + +## Build instructions + +* MicroPython cross-compier +The MicroPython cross-compiler must be built first, which will be +used to pre-compile (freeze) built-in Python code. THis cross-compiler +is built and run on the host machine, using: + + $ make -C mpy-cross + + This command should be executed from the root directory of this repository. +All other commands below should be executed from the ports/renesas-ra/ directory. + +* Arm compiler +An `Arm compiler` is required for the build, along with the associated binary +utilities. The default compiler is `arm-none-eabi-gcc`, which is available for +Arch Linux and Windows hosts via https://developer.arm.com/tools-and-software/open-source-software/developer-tools/gnu-toolchain/gnu-rm/downloads. +The compiler can be changed using the `CROSS_COMPILE` variable +when invoking `make`. + +* Obtain submodules +First the submodules must be obtained using: + + $ make submodules + +* Build binary image `.hex` +Then to build for a given board subdirectory name, run: + + $ make BOARD=RA6M2_EK clean + $ make BOARD=RA6M2_EK + + The default board subdirectory name is RA6M2_EK (which is for EK-RA6M2 board) +but any of the names of the subdirectories in the `boards/` directory can be +passed as the argument to `BOARD=`; for example `RA4M1_CLICKER`, `RA4M1_EK`, +`RA4W1_EK` and `RA6M1_EK`. +The above command should produce binary images `firmware.hex` in the +build-RA6M2_EK/` subdirectory (or the equivalent directory for the board specified). + +## Supported/Unsupprted funtions +Please refer to the `renesas-ra` quick reference. + +## Known issues + +### all boards +* machine.lightsleep(time_ms) and machine.deepsleep(time_ms) raise uncaught exceptions. + + >>> machine.deepsleep(1000) + >>> Uncaught exception in ExtInt interrupt handler line 16 + TypeError: + +### RA4M1-CLICKER +* mpremote: mount command is not available due to limited memory resources. + +### EK-RA4M1 +* mpremote: mount command is not available due to limited memory resources. + +### EK-RA4W1 +* mpremote: "Execution: timeout waiting for remote" error happens when importing a file on /remote. + diff --git a/ports/renesas-ra/boardctrl.c b/ports/renesas-ra/boardctrl.c new file mode 100644 index 000000000..b6f0a9093 --- /dev/null +++ b/ports/renesas-ra/boardctrl.c @@ -0,0 +1,171 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2020 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mphal.h" +#include "shared/runtime/pyexec.h" +#include "boardctrl.h" +#include "led.h" +#include "usrsw.h" + +STATIC void flash_error(int n) { + for (int i = 0; i < n; i++) { + led_state(RA_LED1, 1); + mp_hal_delay_ms(250); + led_state(RA_LED1, 0); + mp_hal_delay_ms(250); + } +} + +#if !MICROPY_HW_USES_BOOTLOADER +STATIC uint update_reset_mode(uint reset_mode) { + #if MICROPY_HW_HAS_SWITCH + bool press_status; + + if (switch_get()) { + press_status = true; + mp_printf(&mp_plat_print, "\nEntering select boot mode\n"); + mp_printf(&mp_plat_print, "Normal: release switch after LED1 flashes 4 times or more.\n"); + mp_printf(&mp_plat_print, "Safe: release switch after LED1 flashes 2 times.\n"); + mp_printf(&mp_plat_print, "Factory filesystem: release switch after LED1 flashes 3 times.\n"); + // For boards with only a single LED, we'll flash that LED the + // appropriate number of times, with a pause between each one + for (uint i = 0; i < 100; i++) { + led_state(RA_LED1, 1); + mp_hal_delay_ms(1000); + led_state(RA_LED1, 0); + for (uint i = 0; i < 50; i++) { + mp_hal_delay_ms(20); + if (!switch_get()) { + press_status = false; + break; + } + } + if (press_status == false) { + break; + } + ++reset_mode; + } + if (reset_mode > BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM) { + reset_mode = BOARDCTRL_RESET_MODE_NORMAL; + } + #if 0 // if selected mode is displayed, LED1 flash is unnecessary. + // Flash the selected reset mode twice. + // We'll flash LED selected number of times, and wait for 2 secs, then flash again: + // BOARDCTRL_RESET_MODE_NORMAL = 1, + // BOARDCTRL_RESET_MODE_SAFE_MODE = 2, + // BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM = 3, + mp_hal_delay_ms(1000); + for (uint i = 0; i < 2; i++) { + for (uint j = 0; j < reset_mode; j++) { + led_state(RA_LED1, 1); + mp_hal_delay_ms(1000); + led_state(RA_LED1, 0); + mp_hal_delay_ms(1000); + } + mp_hal_delay_ms(2000); + } + #endif + if (reset_mode == BOARDCTRL_RESET_MODE_SAFE_MODE) { + mp_printf(&mp_plat_print, "\nBoot with safe mode\n"); + } else if (reset_mode == BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM) { + mp_printf(&mp_plat_print, "\nBoot with factory filesystem mode\n"); + } else { + mp_printf(&mp_plat_print, "\nBoot with Normal mode\n"); + } + } + #endif + return reset_mode; +} +#endif + +void boardctrl_before_soft_reset_loop(boardctrl_state_t *state) { + #if !MICROPY_HW_USES_BOOTLOADER + // Update the reset_mode via the default + // method which uses the board switch/button and LEDs. + state->reset_mode = update_reset_mode(BOARDCTRL_RESET_MODE_NORMAL); + #endif +} + +void boardctrl_top_soft_reset_loop(boardctrl_state_t *state) { +} + +int boardctrl_run_boot_py(boardctrl_state_t *state) { + bool run_boot_py = state->reset_mode != BOARDCTRL_RESET_MODE_SAFE_MODE; + + if (run_boot_py) { + // Run boot.py, if it exists. + const char *boot_py = "boot.py"; + int ret = pyexec_file_if_exists(boot_py); + + // Take action based on the execution result. + if (ret & PYEXEC_FORCED_EXIT) { + return BOARDCTRL_GOTO_SOFT_RESET_EXIT; + } + if (!ret) { + // There was an error, prevent main.py from running and flash LEDs. + state->reset_mode = BOARDCTRL_RESET_MODE_SAFE_MODE; + flash_error(4); + } + } + return BOARDCTRL_CONTINUE; +} + +int boardctrl_run_main_py(boardctrl_state_t *state) { + bool run_main_py = state->reset_mode != BOARDCTRL_RESET_MODE_SAFE_MODE + && pyexec_mode_kind == PYEXEC_MODE_FRIENDLY_REPL; + + if (run_main_py) { + // Run main.py (or what it was configured to be), if it exists. + const char *main_py; + if (MP_STATE_PORT(pyb_config_main) == MP_OBJ_NULL) { + main_py = "main.py"; + } else { + main_py = mp_obj_str_get_str(MP_STATE_PORT(pyb_config_main)); + } + int ret = pyexec_file_if_exists(main_py); + + // Take action based on the execution result. + if (ret & PYEXEC_FORCED_EXIT) { + return BOARDCTRL_GOTO_SOFT_RESET_EXIT; + } + if (!ret) { + flash_error(3); + } + } + + return BOARDCTRL_CONTINUE; +} + +void boardctrl_start_soft_reset(boardctrl_state_t *state) { + state->log_soft_reset = true; +} + +void boardctrl_end_soft_reset(boardctrl_state_t *state) { + // Set reset_mode to normal boot. + state->reset_mode = BOARDCTRL_RESET_MODE_NORMAL; +} diff --git a/ports/renesas-ra/boardctrl.h b/ports/renesas-ra/boardctrl.h new file mode 100644 index 000000000..cc7918c35 --- /dev/null +++ b/ports/renesas-ra/boardctrl.h @@ -0,0 +1,93 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2020 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_BOARDCTRL_H +#define MICROPY_INCLUDED_RENESAS_RA_BOARDCTRL_H + +#include "py/mpconfig.h" + +// Additional entries for use with pendsv_schedule_dispatch. +#ifndef MICROPY_BOARD_PENDSV_ENTRIES +#define MICROPY_BOARD_PENDSV_ENTRIES +#endif + +#ifndef MICROPY_BOARD_STARTUP +#define MICROPY_BOARD_STARTUP powerctrl_check_enter_bootloader +#endif + +#ifndef MICROPY_BOARD_EARLY_INIT +#define MICROPY_BOARD_EARLY_INIT() +#endif + +#ifndef MICROPY_BOARD_BEFORE_SOFT_RESET_LOOP +#define MICROPY_BOARD_BEFORE_SOFT_RESET_LOOP boardctrl_before_soft_reset_loop +#endif + +#ifndef MICROPY_BOARD_TOP_SOFT_RESET_LOOP +#define MICROPY_BOARD_TOP_SOFT_RESET_LOOP boardctrl_top_soft_reset_loop +#endif + +#ifndef MICROPY_BOARD_RUN_BOOT_PY +#define MICROPY_BOARD_RUN_BOOT_PY boardctrl_run_boot_py +#endif + +#ifndef MICROPY_BOARD_RUN_MAIN_PY +#define MICROPY_BOARD_RUN_MAIN_PY boardctrl_run_main_py +#endif + +#ifndef MICROPY_BOARD_START_SOFT_RESET +#define MICROPY_BOARD_START_SOFT_RESET boardctrl_start_soft_reset +#endif + +#ifndef MICROPY_BOARD_END_SOFT_RESET +#define MICROPY_BOARD_END_SOFT_RESET boardctrl_end_soft_reset +#endif + +// Constants to return from boardctrl_run_boot_py, boardctrl_run_main_py. +enum { + BOARDCTRL_CONTINUE, + BOARDCTRL_GOTO_SOFT_RESET_EXIT, +}; + +// Constants for boardctrl_state_t.reset_mode. +enum { + BOARDCTRL_RESET_MODE_NORMAL = 1, + BOARDCTRL_RESET_MODE_SAFE_MODE = 2, + BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM = 3, +}; + +typedef struct _boardctrl_state_t { + uint8_t reset_mode; + bool log_soft_reset; +} boardctrl_state_t; + +void boardctrl_before_soft_reset_loop(boardctrl_state_t *state); +void boardctrl_top_soft_reset_loop(boardctrl_state_t *state); +int boardctrl_run_boot_py(boardctrl_state_t *state); +int boardctrl_run_main_py(boardctrl_state_t *state); +void boardctrl_start_soft_reset(boardctrl_state_t *state); +void boardctrl_end_soft_reset(boardctrl_state_t *state); + +#endif // MICROPY_INCLUDED_RENESAS_RA_BOARDCTRL_H diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/board.json b/ports/renesas-ra/boards/RA4M1_CLICKER/board.json new file mode 100644 index 000000000..1c3c4c8e9 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/board.json @@ -0,0 +1,22 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "UART", + "SPI", + "I2C", + "ADC" + ], + "id": "RA4M1-CLICKER", + "images": [ + "ra4m1_clicker_board.jpg", + "ra4m1_clicker_pins.jpg" + ], + "mcu": "RA4M1", + "product": "Mikroe RA4M1 Clicker", + "thumbnail": "", + "url": "https://www.mikroe.com/ra4m1-clicker", + "vendor": "MikroElektronika" +} diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/manifest.py b/ports/renesas-ra/boards/RA4M1_CLICKER/manifest.py new file mode 100644 index 000000000..4a387915d --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/manifest.py @@ -0,0 +1,2 @@ +# We do not want to include default frozen modules, +freeze("$(MPY_DIR)/drivers/sdcard", "sdcard.py") diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.h b/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.h new file mode 100644 index 000000000..ec67d68b6 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.h @@ -0,0 +1,59 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "RA4M1_CLICKER" +#define MICROPY_HW_MCU_NAME "RA4M1" +#define MICROPY_HW_MCU_SYSCLK 48000000 +#define MICROPY_HW_MCU_PCLK 48000000 + +// module config +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_PY_BUILTINS_COMPLEX (0) +#define MICROPY_PY_GENERATOR_PEND_THROW (0) +#define MICROPY_PY_MATH (0) +#define MICROPY_PY_UHEAPQ (0) +#define MICROPY_PY_UTIMEQ (0) +#define MICROPY_PY_THREAD (0) + +// peripheral config +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (0) // 0: subclock, 1:LOCO +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +// board config + +// UART +#define MICROPY_HW_UART0_TX (pin_P411) // MBTX0 +#define MICROPY_HW_UART0_RX (pin_P410) // MBRX0 +// #define MICROPY_HW_UART0_CTS (pin_P103) // Disable (Conflict with SSLA0) +#define MICROPY_HW_UART1_TX (pin_P401) // REPL +#define MICROPY_HW_UART1_RX (pin_P402) // REPL +#define MICROPY_HW_UART_REPL HW_UART_1 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C +// #define MICROPY_HW_I2C0_SCL (pin_P400) // Disable (Conflict with REPL) +// #define MICROPY_HW_I2C0_SDA (pin_P401) // Disable (Conflict with REPL) +#define MICROPY_HW_I2C1_SCL (pin_P205) +#define MICROPY_HW_I2C1_SDA (pin_P206) + +// SPI +#define MICROPY_HW_SPI0_SSL (pin_P103) +#define MICROPY_HW_SPI0_RSPCK (pin_P102) +#define MICROPY_HW_SPI0_MISO (pin_P100) +#define MICROPY_HW_SPI0_MOSI (pin_P101) + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pin_P304) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pin_P409) +#define MICROPY_HW_LED2 (pin_P408) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk b/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk new file mode 100644 index 000000000..1758ce673 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/mpconfigboard.mk @@ -0,0 +1,9 @@ +CMSIS_MCU = RA4M1 +MCU_SERIES = m4 +LD_FILES = boards/RA4M1_CLICKER/ra4m1_clicker.ld + +# MicroPython settings +MICROPY_VFS_FAT = 1 + +# Don't include default frozen modules because MCU is tight on flash space +FROZEN_MANIFEST ?= boards/RA4M1_CLICKER/manifest.py diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/pins.csv b/ports/renesas-ra/boards/RA4M1_CLICKER/pins.csv new file mode 100644 index 000000000..f051cf0bb --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/pins.csv @@ -0,0 +1,65 @@ +P000,P000 +P012,P012 +P013,P013 +P014,P014 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P107,P107 +P108,P108 +P109,P109 +P110,P110 +P112,P112 +P201,P201 +P205,P205 +P206,P206 +P300,P300 +P301,P301 +P302,P302 +P304,P304 +P400,P400 +P401,P401 +P402,P402 +P407,P407 +P408,P408 +P409,P409 +P410,P410 +P411,P411 +P501,P501 +P502,P502 +P914,P914 +P915,P915 +MBAN,P000 +GPIOHD10,P012 +GPIOHD9,P013 +GPIOHD8,P014 +MBMISO,P100 +MBMOSI,P101 +MBSCK,P102 +MBSSL,P103 +MBPWM,P107 +SWDIO,P108 +SWO,P109 +TDI,P110 +TSCAP,P112 +MD,P201 +MBSCLI,P205 +MBSDA1,P206 +SWCLK,P300 +SW2,P301 +MBINT,P302 +SW1,P304 +GPIOHD5,P400 +GPIOHD4,P401 +GPIOHD3,P402 +MBRST,P407 +LED2,P408 +LED1,P409 +MBRX0,P410 +MBTX0,P411 +GPIOHD7,P501 +GPIOHD6,P502 +USBDP,P914 +USBDM,P915 + diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker.ld b/ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker.ld new file mode 100644 index 000000000..0ce4e9267 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker.ld @@ -0,0 +1,298 @@ +/* + Linker File for RA4M1 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256KB */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* 32KB */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */ + ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker_conf.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker_conf.h new file mode 100644 index 000000000..6427e964b --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra4m1_clicker_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA4M1_CLICKER_CONF_H +#define RA4M1_CLICKER_CONF_H + +#define DEBUG_CH 0 + +#endif /* RA4M1_CLICKER_CONF_H */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000..87cb51e00 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +void bsp_init(void *p_args); +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..9940d7ed3 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,49 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x4980) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) + +#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..713af295b --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,10 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CFM +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (64) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..4766823b3 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,74 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 +#define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 +#define BSP_HOCO_HZ (64000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 000000000..9c59889ca --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 000000000..d3ab55923 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) +#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 000000000..21405f967 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,6 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" +#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h new file mode 100644 index 000000000..26879f9f4 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) +#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 000000000..5e77b6980 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h new file mode 100644 index 000000000..595ea938d --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_iic_master_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (0) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..6b4353d23 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 000000000..5f4d5c4a7 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 000000000..484b7ed04 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 000000000..c70c0be34 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,8 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (0) +#define SCI_UART_CFG_DTC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 000000000..861fe1219 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_DTC_SUPPORT_ENABLE (1) +#define SPI_TRANSMIT_FROM_RXI_ISR (0) +#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/R7FA4M1AB3CFM.csv b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/R7FA4M1AB3CFM.csv new file mode 100644 index 000000000..da414f0e8 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/R7FA4M1AB3CFM.csv @@ -0,0 +1,352 @@ +"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities" +"AVCC0","56","ADC_AVCC0","","","","","","" +"AVSS0","57","ADC_AVSS0","","","","","","" +"P000","64","","","","Disabled","","","ADC0: AN00 +CTSU0: TS21 +IRQ0: IRQ06 +OPAMP0: AMP+" +"P001","63","","","","Disabled","","","ADC0: AN01 +CTSU0: TS22 +IRQ0: IRQ07 +OPAMP0: AMP-" +"P002","62","","","","Disabled","","","ADC0: AN02 +IRQ0: IRQ02 +OPAMP0: AMPO" +"P003","61","","","","Disabled","","","ADC0: AN03 +OPAMP1: AMPO" +"P004","60","","","","Disabled","","","ADC0: AN04 +IRQ0: IRQ03 +OPAMP2: AMPO" +"P010","59","","","","Disabled","","","ADC: VREFH0 +ADC0: AN05 +CTSU0: TS30 +OPAMP2: AMP-" +"P011","58","","","","Disabled","","","ADC: VREFL0 +ADC0: AN06 +CTSU0: TS31 +IRQ0: IRQ15 +OPAMP2: AMP+" +"P012","55","","","","Disabled","","","ADC: VREFH +ADC0: AN07 +OPAMP1: AMP-" +"P013","54","","","","Disabled","","","ADC: VREFL +ADC0: AN08 +OPAMP1: AMP+" +"P014","53","","","","Disabled","","","ADC0: AN09 +DAC120: DA" +"P015","52","","","","Disabled","","","ADC0: AN10 +CTSU0: TS28 +IRQ0: IRQ07" +"P100","48","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ADC0: AN22 +AGT0: AGTIO +CMP0: CMPIN0 +GPT5: GTIOCB +IIC1: SCL +IRQ0: IRQ02 +KINT0: KRM0 +POEG0: GTETRG +SCI0: RXD_MISO +SCI0: SCL +SCI1: SCK +SLCDC0: VL1 +SPI0: MISO" +"P101","47","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ADC0: AN21 +AGT0: AGTEE +CMP0: CMPREF0 +GPT5: GTIOCA +IIC1: SDA +IRQ0: IRQ01 +KINT0: KRM1 +POEG1: GTETRG +SCI0: SDA +SCI0: TXD_MOSI +SCI1: CTS_RTS_SS +SLCDC0: VL2 +SPI0: MOSI" +"P102","46","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +ADC0: AN20 +AGT0: AGTO +CAN0: CRX +CMP0: CMPIN1 +GPT2: GTIOCB +KINT0: KRM2 +OPS0: GTOWLO +SCI0: SCK +SCI2: SDA +SCI2: TXD_MOSI +SLCDC0: VL3 +SPI0: RSPCK" +"P103","45","","","","Disabled","","","ADC0: AN19 +CAN0: CTX +CMP0: CMPREF1 +GPT2: GTIOCA +KINT0: KRM3 +OPS0: GTOWUP +SCI0: CTS_RTS_SS +SLCDC0: VL4 +SPI0: SSL0" +"P104","44","","","","Disabled","","","CTSU0: TS13 +GPT1: GTIOCB +IRQ0: IRQ01 +KINT0: KRM4 +POEG1: GTETRG +SCI0: RXD_MISO +SCI0: SCL +SLCDC0: COM0 +SPI0: SSL1" +"P105","43","","","","Disabled","","","CTSU0: TS34 +GPT1: GTIOCA +IRQ0: IRQ00 +KINT0: KRM5 +POEG0: GTETRG +SLCDC0: COM1 +SPI0: SSL2" +"P106","42","","","","Disabled","","","GPT0: GTIOCB +KINT0: KRM6 +SLCDC0: COM2 +SPI0: SSL3" +"P107","41","","","","Disabled","","","GPT0: GTIOCA +KINT0: KRM7 +SLCDC0: COM3" +"P108","33","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO +DEBUG0: TMS +GPT0: GTIOCB +OPS0: GTOULO +SCI9: CTS_RTS_SS +SPI1: SSL0" +"P109","34","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN0: CTX +CGC0: CLKOUT +CTSU0: TS10 +DEBUG0: SWO +DEBUG0: TDO +GPT1: GTIOCA +OPS0: GTOVUP +SCI1: SCK +SCI9: SDA +SCI9: TXD_MOSI +SLCDC0: SEG23 +SPI1: MOSI" +"P110","35","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","CAN0: CRX +CMP0: VCOUT +DEBUG0: TDI +GPT1: GTIOCB +IRQ0: IRQ03 +OPS0: GTOVLO +SCI2: CTS_RTS_SS +SCI9: RXD_MISO +SCI9: SCL +SLCDC0: SEG24 +SPI1: MISO" +"P111","36","","","","Disabled","","","CTSU0: TS12 +GPT3: GTIOCA +IRQ0: IRQ04 +SCI2: SCK +SCI9: SCK +SLCDC0: CAPH +SPI1: RSPCK" +"P112","37","","","","Disabled","","","CTSU0: TSCAP +GPT3: GTIOCB +SCI1: SCK +SCI2: SDA +SCI2: TXD_MOSI +SLCDC0: CAPL +SPI1: SSL0" +"P113","38","","","","Disabled","","","CTSU0: TS27 +GPT2: GTIOCA +SLCDC0: COM4 +SLCDC0: SEG00" +"P200","27","","","","Disabled","","","IRQ0: NMI" +"P201","26","","","","Disabled","","","" +"P204","24","","","","Disabled","","","AGT1: AGTIO +CAC0: CACREF +CTSU0: TS00 +GPT4: GTIOCB +IIC0: SCL +OPS0: GTIW +SCI0: SCK +SCI9: SCK +SLCDC0: SEG14 +SPI1: RSPCK +USBFS0: OVRCURB" +"P205","23","","","","Disabled","","","AGT1: AGTO +CGC0: CLKOUT +CTSU0: TSCAP +GPT4: GTIOCA +IIC1: SCL +IRQ0: IRQ01 +OPS0: GTIV +SCI0: SDA +SCI0: TXD_MOSI +SCI9: CTS_RTS_SS +SLCDC0: SEG13 +SPI1: SSL0 +USBFS0: OVRCURA" +"P206","22","","","","Disabled","","","CTSU0: TS01 +IIC1: SDA +IRQ0: IRQ00 +OPS0: GTIU +SCI0: RXD_MISO +SCI0: SCL +SLCDC0: SEG12 +SPI1: SSL1 +USBFS0: VBUSEN" +"P212","10","","","","Disabled","","","AGT1: AGTEE +CGC0: EXTAL +GPT0: GTIOCB +IRQ0: IRQ03 +POEG1: GTETRG +SCI1: RXD_MISO +SCI1: SCL" +"P213","9","","","","Disabled","","","CGC0: XTAL +GPT0: GTIOCA +IRQ0: IRQ02 +POEG0: GTETRG +SCI1: SDA +SCI1: TXD_MOSI" +"P214","7","","","","Disabled","","","CGC0: XCOUT" +"P215","6","","","","Disabled","","","CGC0: XCIN" +"P300","32","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK +DEBUG0: TCK +GPT0: GTIOCA +OPS0: GTOUUP +SPI1: SSL1" +"P301","31","GPIO","","IRQ6","Input mode","","None","AGT0: AGTIO +CTSU0: TS09 +GPT4: GTIOCB +IRQ0: IRQ06 +OPS0: GTOULO +SCI2: RXD_MISO +SCI2: SCL +SCI9: CTS_RTS_SS +SLCDC0: COM5 +SLCDC0: SEG01 +SPI1: SSL2" +"P302","30","GPIO","","IRQ5","Input mode","","None","CTSU0: TS08 +GPT4: GTIOCA +IRQ0: IRQ05 +OPS0: GTOUUP +SCI2: SDA +SCI2: TXD_MOSI +SLCDC0: COM6 +SLCDC0: SEG02 +SPI1: SSL3" +"P303","29","","","","Disabled","","","CTSU0: TS02 +GPT7: GTIOCB +SLCDC0: COM7 +SLCDC0: SEG03" +"P304","28","GPIO","","IRQ9","Input mode","","None","CTSU0: TS11 +GPT7: GTIOCA +IRQ0: IRQ09 +SLCDC0: SEG20" +"P400","1","","","","Disabled","","","AGT1: AGTIO +CAC0: CACREF +CTSU0: TS20 +GPT6: GTIOCA +IIC0: SCL +IRQ0: IRQ00 +SCI0: SCK +SCI1: SCK +SLCDC0: SEG04 +SSI: AUDIO_CLK" +"P401","2","SCI1_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CAN0: CTX +CTSU0: TS19 +GPT6: GTIOCB +IIC0: SDA +IRQ0: IRQ05 +POEG0: GTETRG +SCI0: CTS_RTS_SS +SCI1: SDA +SCI1: TXD_MOSI +SLCDC0: SEG05" +"P402","3","SCI1_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +AGT1: AGTIO +CAN0: CRX +CTSU0: TS18 +IRQ0: IRQ04 +RTC0: RTCIC0 +SCI1: RXD_MISO +SCI1: SCL +SLCDC0: SEG06" +"P407","16","","","","Disabled","","","ADC0: ADTRG +AGT0: AGTIO +CTSU0: TS03 +IIC0: SDA +RTC0: RTCOUT +SCI0: CTS_RTS_SS +SLCDC0: SEG11 +SPI1: SSL3 +USBFS0: VBUS" +"P408","15","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","CTSU0: TS04 +GPT5: GTIOCB +IIC0: SCL +IRQ0: IRQ07 +OPS0: GTOWLO +SCI1: CTS_RTS_SS +SCI9: RXD_MISO +SCI9: SCL +SLCDC0: SEG10 +USBFS0: ID" +"P409","14","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","CTSU0: TS05 +GPT5: GTIOCA +IRQ0: IRQ06 +OPS0: GTOWUP +SCI9: SDA +SCI9: TXD_MOSI +SLCDC0: SEG09 +USBFS0: EXICEN" +"P410","13","SCI0_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOB +CTSU0: TS06 +GPT6: GTIOCB +IRQ0: IRQ05 +OPS0: GTOVLO +SCI0: RXD_MISO +SCI0: SCL +SLCDC0: SEG08 +SPI0: MISO" +"P411","12","SCI0_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOA +CTSU0: TS07 +GPT6: GTIOCA +IRQ0: IRQ04 +OPS0: GTOVUP +SCI0: SDA +SCI0: TXD_MOSI +SLCDC0: SEG07 +SPI0: MOSI" +"P500","49","","","","Disabled","","","ADC0: AN16 +AGT0: AGTOA +CMP0: CMPREF1 +GPT2: GTIOCA +OPS0: GTIU +SLCDC0: SEG34 +USBFS0: VBUSEN" +"P501","50","","","","Disabled","","","ADC0: AN17 +AGT0: AGTOB +CMP0: CMPIN1 +GPT2: GTIOCB +IRQ0: IRQ11 +OPS0: GTIV +SCI1: SDA +SCI1: TXD_MOSI +SLCDC0: SEG35 +USBFS0: OVRCURA" +"P502","51","","","","Disabled","","","ADC0: AN18 +CMP0: CMPREF0 +GPT3: GTIOCB +IRQ0: IRQ12 +OPS0: GTIW +SCI1: RXD_MISO +SCI1: SCL +SLCDC0: SEG36 +USBFS0: OVRCURB" +"P914","19","","","","Disabled","","","USBFS0: USBDP" +"P915","18","","","","Disabled","","","USBFS0: USBDM" +"RES","25","","","","","","","" +"VBAT","4","","","","","","","" +"VCC","11","","","","","","","" +"VCC","39","","","","","","","" +"VCCUSB","20","USBFS0_VCCUSB","","","","","","" +"VCCUSBLDO","21","USBFS0_VCCUSBLDO","","","","","","" +"VCL","5","","","","","","","" +"VSS","8","","","","","","","" +"VSS","40","","","","","","","" +"VSSUSB","17","USBFS0_VSSUSB","","","","","","" diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..cf28c33d7 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_pin_cfg.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_pin_cfg.h new file mode 100644 index 000000000..8b6a627f9 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/bsp_pin_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "bsp_api.h" +#include "r_ioport_api.h" +extern const ioport_cfg_t g_bsp_pin_cfg; /* R7FA4M1AB3CFM.pincfg */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c new file mode 100644 index 000000000..34aad762f --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.c @@ -0,0 +1,7 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h new file mode 100644 index 000000000..e2eb70836 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c new file mode 100644 index 000000000..ebef37a7d --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.c @@ -0,0 +1,487 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +icu_instance_ctrl_t g_external_irq9_ctrl; +const external_irq_cfg_t g_external_irq9_cfg = +{ .channel = 9, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ9) + .irq = VECTOR_NUMBER_ICU_IRQ9, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq9 = +{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq6_ctrl; +const external_irq_cfg_t g_external_irq6_cfg = +{ .channel = 6, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ6) + .irq = VECTOR_NUMBER_ICU_IRQ6, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq6 = +{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu }; +iic_master_instance_ctrl_t g_i2c_master1_ctrl; +const iic_master_extended_cfg_t g_i2c_master1_extend = +{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, +/* Actual calculated bitrate: 99272. Actual calculated duty cycle: 49%. */ .clock_settings.brl_value = 27, + .clock_settings.brh_value = 26, .clock_settings.cks_value = 2, }; +const i2c_master_cfg_t g_i2c_master1_cfg = +{ .channel = 1, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .p_callback = callback_iic, + .p_context = NULL, + #if defined(VECTOR_NUMBER_IIC1_RXI) + .rxi_irq = VECTOR_NUMBER_IIC1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC1_TXI) + .txi_irq = VECTOR_NUMBER_IIC1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC1_TEI) + .tei_irq = VECTOR_NUMBER_IIC1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC1_ERI) + .eri_irq = VECTOR_NUMBER_IIC1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + .ipl = (12), + .p_extend = &g_i2c_master1_extend, }; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master1 = +{ .p_ctrl = &g_i2c_master1_ctrl, .p_cfg = &g_i2c_master1_cfg, .p_api = &g_i2c_master_on_iic }; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc0_cfg = +{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, + #if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc0_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ .low_power_mode = LPM_MODE_SLEEP, + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = 0, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = 0, + .power_supply_state = 0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, }; + +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; +const transfer_cfg_t g_transfer1_cfg = +{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; +const transfer_cfg_t g_transfer0_cfg = +{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = + { + /* Actual calculated bitrate: 12000000. */ .spbr = 1, + .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ .channel = 0, + + #if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; +icu_instance_ctrl_t g_external_irq5_ctrl; +const external_irq_cfg_t g_external_irq5_cfg = +{ .channel = 5, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ5) + .irq = VECTOR_NUMBER_ICU_IRQ5, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq5 = +{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; +flash_lp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, }; +const rtc_cfg_t g_rtc0_cfg = +{ .clock_source = RTC_CLOCK_SOURCE_SUBCLK, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = + NULL, + .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), + #if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, + #else + .alarm_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, + #else + .periodic_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, + #else + .carry_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; +sci_uart_instance_ctrl_t g_uart1_ctrl; + +baud_setting_t g_uart1_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart1_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart1_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart1_cfg = +{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart1_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI1_RXI) + .rxi_irq = VECTOR_NUMBER_SCI1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_TXI) + .txi_irq = VECTOR_NUMBER_SCI1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_TEI) + .tei_irq = VECTOR_NUMBER_SCI1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_ERI) + .eri_irq = VECTOR_NUMBER_SCI1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart1 = +{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart0_ctrl; + +baud_setting_t g_uart0_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart0_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart0_cfg = +{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h new file mode 100644 index 000000000..2c95755ee --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/hal_data.h @@ -0,0 +1,175 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "common_data.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_flash_lp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq9; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq9_ctrl; +extern const external_irq_cfg_t g_external_irq9_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq6; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq6_ctrl; +extern const external_irq_cfg_t g_external_irq6_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master1; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master1_ctrl; +extern const i2c_master_cfg_t g_i2c_master1_cfg; + +#ifndef callback_iic +void callback_iic(i2c_master_callback_args_t *p_args); +#endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else +#define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else +#define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq5; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq5_ctrl; +extern const external_irq_cfg_t g_external_irq5_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/* Flash on Flash LP Instance. */ +extern const flash_instance_t g_flash0; + +/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_lp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart1; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart1_ctrl; +extern const uart_cfg_t g_uart1_cfg; +extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart0; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart0_ctrl; +extern const uart_cfg_t g_uart0_cfg; +extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/main.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/main.c new file mode 100644 index 000000000..5b9f98055 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) { + hal_entry(); + return 0; +} diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c new file mode 100644 index 000000000..2479b76a0 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/pin_data.c @@ -0,0 +1,73 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_03_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_03_PIN_04, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_08, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_04_PIN_09, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, +}; +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c new file mode 100644 index 000000000..ea2f3b066 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.c @@ -0,0 +1,57 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [4] = sci_uart_rxi_isr, /* SCI1 RXI (Received data full) */ + [5] = sci_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */ + [6] = sci_uart_tei_isr, /* SCI1 TEI (Transmit end) */ + [7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */ + [8] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [9] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [10] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [11] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [12] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [13] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [14] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [15] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [16] = spi_eri_isr, /* SPI0 ERI (Error) */ + [17] = iic_master_rxi_isr, /* IIC1 RXI (Receive data full) */ + [18] = iic_master_txi_isr, /* IIC1 TXI (Transmit data empty) */ + [19] = iic_master_tei_isr, /* IIC1 TEI (Transmit end) */ + [20] = iic_master_eri_isr, /* IIC1 ERI (Transfer error) */ + [21] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [22] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SCI1_RXI), /* SCI1 RXI (Received data full) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TXI), /* SCI1 TXI (Transmit data empty) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TEI), /* SCI1 TEI (Transmit end) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_IIC1_RXI), /* IIC1 RXI (Receive data full) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TXI), /* IIC1 TXI (Transmit data empty) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_IIC1_TEI), /* IIC1 TEI (Transmit end) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_IIC1_ERI), /* IIC1 ERI (Transfer error) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ +}; +#endif diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h new file mode 100644 index 000000000..5481e446c --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/ra_gen/vector_data.h @@ -0,0 +1,87 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (23) +#endif +/* ISR prototypes */ +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); +void agt_int_isr(void); +void r_icu_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ +#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)8) /* RTC ALARM (Alarm interrupt) */ +#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)9) /* RTC PERIOD (Periodic interrupt) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)10) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)11) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)12) /* ICU IRQ5 (External pin interrupt 5) */ +#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)13) /* SPI0 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)14) /* SPI0 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)15) /* SPI0 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)16) /* SPI0 ERI (Error) */ +#define VECTOR_NUMBER_IIC1_RXI ((IRQn_Type)17) /* IIC1 RXI (Receive data full) */ +#define VECTOR_NUMBER_IIC1_TXI ((IRQn_Type)18) /* IIC1 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_IIC1_TEI ((IRQn_Type)19) /* IIC1 TEI (Transmit end) */ +#define VECTOR_NUMBER_IIC1_ERI ((IRQn_Type)20) /* IIC1 ERI (Transfer error) */ +#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)21) /* ICU IRQ6 (External pin interrupt 6) */ +#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)22) /* ICU IRQ9 (External pin interrupt 9) */ +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ + SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ + SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ + SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ + SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */ + SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */ + SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */ + SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */ + RTC_ALARM_IRQn = 8, /* RTC ALARM (Alarm interrupt) */ + RTC_PERIOD_IRQn = 9, /* RTC PERIOD (Periodic interrupt) */ + RTC_CARRY_IRQn = 10, /* RTC CARRY (Carry interrupt) */ + AGT0_INT_IRQn = 11, /* AGT0 INT (AGT interrupt) */ + ICU_IRQ5_IRQn = 12, /* ICU IRQ5 (External pin interrupt 5) */ + SPI0_RXI_IRQn = 13, /* SPI0 RXI (Receive buffer full) */ + SPI0_TXI_IRQn = 14, /* SPI0 TXI (Transmit buffer empty) */ + SPI0_TEI_IRQn = 15, /* SPI0 TEI (Transmission complete event) */ + SPI0_ERI_IRQn = 16, /* SPI0 ERI (Error) */ + IIC1_RXI_IRQn = 17, /* IIC1 RXI (Receive data full) */ + IIC1_TXI_IRQn = 18, /* IIC1 TXI (Transmit data empty) */ + IIC1_TEI_IRQn = 19, /* IIC1 TEI (Transmit end) */ + IIC1_ERI_IRQn = 20, /* IIC1 ERI (Transfer error) */ + ICU_IRQ6_IRQn = 21, /* ICU IRQ6 (External pin interrupt 6) */ + ICU_IRQ9_IRQn = 22, /* ICU IRQ9 (External pin interrupt 9) */ +} IRQn_Type; +#endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/RA4M1_CLICKER/src/hal_entry.c b/ports/renesas-ra/boards/RA4M1_CLICKER/src/hal_entry.c new file mode 100644 index 000000000..c922cfd17 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_CLICKER/src/hal_entry.c @@ -0,0 +1,58 @@ +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); +FSP_CPP_FOOTER + +void ra_main(uint32_t reset_mode); + +/*******************************************************************************************************************//** + * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function + * is called by main() when no RTOS is used. + **********************************************************************************************************************/ +void hal_entry(void) { + /* TODO: add your own code here */ + + ra_main(1); + + #if BSP_TZ_SECURE_BUILD + /* Enter non-secure code */ + R_BSP_NonSecureEnter(); + #endif +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { + #if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ + #endif + } + + if (BSP_WARM_START_POST_C == event) { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + } +} + +#if BSP_TZ_SECURE_BUILD + +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable(); + +/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */ +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() { + +} +#endif diff --git a/ports/renesas-ra/boards/RA4M1_EK/board.json b/ports/renesas-ra/boards/RA4M1_EK/board.json new file mode 100644 index 000000000..bab3bcace --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/board.json @@ -0,0 +1,21 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "UART", + "SPI", + "I2C", + "ADC" + ], + "id": "EK-RA4M1", + "images": [ + "ek_ra4m1_board.jpg" + ], + "mcu": "RA4M1", + "product": "EK-RA4M1", + "thumbnail": "", + "url": "https://www.renesas.com/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4m1-evaluation-kit-ra4m1-mcu-group", + "vendor": "Renesas Electronics" +} diff --git a/ports/renesas-ra/boards/RA4M1_EK/manifest.py b/ports/renesas-ra/boards/RA4M1_EK/manifest.py new file mode 100644 index 000000000..4a387915d --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/manifest.py @@ -0,0 +1,2 @@ +# We do not want to include default frozen modules, +freeze("$(MPY_DIR)/drivers/sdcard", "sdcard.py") diff --git a/ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.h b/ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.h new file mode 100644 index 000000000..500fe78b9 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.h @@ -0,0 +1,70 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "RA4M1_EK" +#define MICROPY_HW_MCU_NAME "RA4M1" +#define MICROPY_HW_MCU_SYSCLK 48000000 +#define MICROPY_HW_MCU_PCLK 48000000 + +// module config +#define MICROPY_EMIT_THUMB (0) +#define MICROPY_EMIT_INLINE_THUMB (0) +#define MICROPY_PY_BUILTINS_COMPLEX (0) +#define MICROPY_PY_GENERATOR_PEND_THROW (0) +#define MICROPY_PY_MATH (0) +#define MICROPY_PY_UHEAPQ (0) +#define MICROPY_PY_UTIMEQ (0) +#define MICROPY_PY_THREAD (0) + +// peripheral config +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (0) // 0: subclock, 1:LOCO +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +// board config + +// UART +#define MICROPY_HW_UART0_TX (pin_P411) // REPL +#define MICROPY_HW_UART0_RX (pin_P410) // REPL +#define MICROPY_HW_UART1_TX (pin_P401) // PMOD B +#define MICROPY_HW_UART1_RX (pin_P402) // PMOD B +#define MICROPY_HW_UART1_CTS (pin_P403) // PMOD B +#define MICROPY_HW_UART2_TX (pin_P302) +#define MICROPY_HW_UART2_RX (pin_P301) +#define MICROPY_HW_UART2_CTS (pin_P203) // (Conflict with SPI1) +// #define MICROPY_HW_UART9_TX (pin_P602) // Disable (vector not registered) +// #define MICROPY_HW_UART9_RX (pin_P601) // Disable (vector not registered) +// #define MICROPY_HW_UART9_CTS (pin_P603) // Disable (vector not registered) +#define MICROPY_HW_UART_REPL HW_UART_0 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C (not supported) +// #define MICROPY_HW_I2C0_SCL (pin_P204) // Conflict with SPI1 +// #define MICROPY_HW_I2C0_SDA (pin_P407) // Conflict with USB_VBUS +// #define MICROPY_HW_I2C0_SCL (pin_P400) // Conflict wiht PMOD B (GPIO) +// #define MICROPY_HW_I2C0_SDA (pin_P401) // Conflict with PMOD B (TXD1) +// #define MICROPY_HW_I2C1_SCL (pin_P100) // Conflict with PMOD A (MISOA_A) +// #define MICROPY_HW_I2C1_SDA (pin_P101) // Conflict with PMOD A (MOSIA_A) + +// SPI +#define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD A +#define MICROPY_HW_SPI0_RSPCK (pin_P102) // PMOD A +#define MICROPY_HW_SPI0_MISO (pin_P100) // PMOD A +#define MICROPY_HW_SPI0_MOSI (pin_P101) // PMOD A +#define MICROPY_HW_SPI1_SSL (pin_P206) // Use SSLB1 due to SSLB0 is used for TSCAP +// #define MICROPY_HW_SPI1_RSPCK (pin_P204) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_MISO (pin_P202) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_MOSI (pin_P203) // Disable (vector not registered) + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pin_P105) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pin_P106) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.mk b/ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.mk new file mode 100644 index 000000000..1213fa322 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/mpconfigboard.mk @@ -0,0 +1,9 @@ +CMSIS_MCU = RA4M1 +MCU_SERIES = m4 +LD_FILES = boards/RA4M1_EK/ra4m1_ek.ld + +# MicroPython settings +MICROPY_VFS_FAT = 1 + +# Don't include default frozen modules because MCU is tight on flash space +FROZEN_MANIFEST ?= boards/RA4M1_EK/manifest.py diff --git a/ports/renesas-ra/boards/RA4M1_EK/pins.csv b/ports/renesas-ra/boards/RA4M1_EK/pins.csv new file mode 100644 index 000000000..910321b96 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/pins.csv @@ -0,0 +1,104 @@ +P000,P000 +P001,P001 +P002,P002 +P003,P003 +P004,P004 +P005,P005 +P006,P006 +P007,P007 +P008,P008 +P010,P010 +P011,P011 +P012,P012 +P013,P013 +P014,P014 +P015,P015 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P104,P104 +P105,P105 +P106,P106 +P107,P107 +P108,P108 +P109,P109 +P110,P110 +P111,P111 +P112,P112 +P113,P113 +P114,P114 +P115,P115 +P200,P200 +P201,P201 +P202,P202 +P203,P203 +P204,P204 +P205,P205 +P206,P206 +P212,P212 +P213,P213 +P214,P214 +P215,P215 +P300,P300 +P301,P301 +P302,P302 +P303,P303 +P304,P304 +P400,P400 +P401,P401 +P402,P402 +P403,P403 +P404,P404 +P405,P405 +P406,P406 +P407,P407 +P408,P408 +P409,P409 +P410,P410 +P411,P411 +P412,P412 +P413,P413 +P414,P414 +P415,P415 +P500,P500 +P501,P501 +P502,P502 +P503,P503 +P504,P504 +P505,P505 +P600,P601 +P601,P601 +P602,P602 +P603,P603 +P608,P608 +P609,P609 +P610,P610 +P808,P808 +P809,P809 +P708,P708 +P914,P914 +P915,P915 +MBAN,P000 +MBMISO,P100 +MBMOSI,P101 +MBSCK,P102 +MBSSL,P103 +MBPWM,P107 +SWDIO,P108 +SWO,P109 +TDI,P110 +TSCAP,P112 +MD,P201 +MBSCLI,P205 +MBSDA1,P206 +SWCLK,P300 +MBINT,P302 +SW1,P105 +MBRST,P407 +LED1,P106 +MBRX0,P410 +MBTX0,P411 +USBDP,P914 +USBDM,P915 + diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek.ld b/ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek.ld new file mode 100644 index 000000000..0ce4e9267 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek.ld @@ -0,0 +1,298 @@ +/* + Linker File for RA4M1 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00040000 /* 256KB */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00008000 /* 32KB */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */ + ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek_conf.h b/ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek_conf.h new file mode 100644 index 000000000..261073cfe --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra4m1_ek_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA4M1_EK_CONF_H +#define RA4M1_EK_CONF_H + +#define DEBUG_CH 0 + +#endif /* RA4M1_EK_CONF_H */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000..4fab9f48c --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../ra/board/ra4m1_ek/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..9940d7ed3 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,49 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x1000) +#define BSP_CFG_HEAP_BYTES (0x4980) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) + +#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..f52adbafa --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,10 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4M1AB3CFP +#define BSP_ROM_SIZE_BYTES (262144) +#define BSP_RAM_SIZE_BYTES (32768) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..4766823b3 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,74 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra4m1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA4M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 +#define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 +#define BSP_HOCO_HZ (64000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 000000000..9c59889ca --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 000000000..d3ab55923 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) +#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 000000000..21405f967 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,6 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" +#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h new file mode 100644 index 000000000..26879f9f4 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) +#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 000000000..5e77b6980 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..6b4353d23 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 000000000..5f4d5c4a7 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 000000000..484b7ed04 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 000000000..c70c0be34 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,8 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (0) +#define SCI_UART_CFG_DTC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 000000000..861fe1219 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_DTC_SUPPORT_ENABLE (1) +#define SPI_TRANSMIT_FROM_RXI_ISR (0) +#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/RA4M1-EK.csv b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/RA4M1-EK.csv new file mode 100644 index 000000000..a4118a682 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/RA4M1-EK.csv @@ -0,0 +1,450 @@ +"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities" +"AVCC0","88","ADC_AVCC0","","","","","","" +"AVSS0","89","ADC_AVSS0","","","","","","" +"P000","100","ADC0_AN00","","","Analog mode","","","ADC0: AN00 +CTSU0: TS21 +IRQ0: IRQ06 +OPAMP0: AMP+" +"P001","99","","","","Disabled","","","ADC0: AN01 +CTSU0: TS22 +IRQ0: IRQ07 +OPAMP0: AMP-" +"P002","98","","","","Disabled","","","ADC0: AN02 +IRQ0: IRQ02 +OPAMP0: AMPO" +"P003","97","","","","Disabled","","","ADC0: AN03 +OPAMP1: AMPO" +"P004","96","","","","Disabled","","","ADC0: AN04 +IRQ0: IRQ03 +OPAMP2: AMPO" +"P005","95","","","","Disabled","","","ADC0: AN11 +IRQ0: IRQ10 +OPAMP3: AMP+" +"P006","94","","","","Disabled","","","ADC0: AN12 +OPAMP3: AMP-" +"P007","93","","","","Disabled","","","ADC0: AN13 +OPAMP3: AMPO" +"P008","92","","","","Disabled","","","ADC0: AN14" +"P010","91","","","","Disabled","","","ADC: VREFH0 +ADC0: AN05 +CTSU0: TS30 +OPAMP2: AMP-" +"P011","90","","","","Disabled","","","ADC: VREFL0 +ADC0: AN06 +CTSU0: TS31 +IRQ0: IRQ15 +OPAMP2: AMP+" +"P012","87","","","","Disabled","","","ADC: VREFH +ADC0: AN07 +OPAMP1: AMP-" +"P013","86","","","","Disabled","","","ADC: VREFL +ADC0: AN08 +OPAMP1: AMP+" +"P014","85","","","","Disabled","","","ADC0: AN09 +DAC120: DA" +"P015","84","","","","Disabled","","","ADC0: AN10 +CTSU0: TS28 +IRQ0: IRQ07" +"P100","75","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ADC0: AN22 +AGT0: AGTIO +CMP0: CMPIN0 +GPT5: GTIOCB +IIC1: SCL +IRQ0: IRQ02 +KINT0: KRM0 +POEG0: GTETRG +SCI0: RXD_MISO +SCI0: SCL +SCI1: SCK +SLCDC0: VL1 +SPI0: MISO" +"P101","74","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ADC0: AN21 +AGT0: AGTEE +CMP0: CMPREF0 +GPT5: GTIOCA +IIC1: SDA +IRQ0: IRQ01 +KINT0: KRM1 +POEG1: GTETRG +SCI0: SDA +SCI0: TXD_MOSI +SCI1: CTS_RTS_SS +SLCDC0: VL2 +SPI0: MOSI" +"P102","73","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +ADC0: AN20 +AGT0: AGTO +CAN0: CRX +CMP0: CMPIN1 +GPT2: GTIOCB +KINT0: KRM2 +OPS0: GTOWLO +SCI0: SCK +SCI2: SDA +SCI2: TXD_MOSI +SLCDC0: VL3 +SPI0: RSPCK" +"P103","72","SPI0_SSL0","Low","","Peripheral mode","CMOS","None","ADC0: AN19 +CAN0: CTX +CMP0: CMPREF1 +GPT2: GTIOCA +KINT0: KRM3 +OPS0: GTOWUP +SCI0: CTS_RTS_SS +SLCDC0: VL4 +SPI0: SSL0" +"P104","71","","","","Disabled","","","CTSU0: TS13 +GPT1: GTIOCB +IRQ0: IRQ01 +KINT0: KRM4 +POEG1: GTETRG +SCI0: RXD_MISO +SCI0: SCL +SLCDC0: COM0 +SPI0: SSL1" +"P105","70","GPIO","","IRQ0","Input mode","","None","CTSU0: TS34 +GPT1: GTIOCA +IRQ0: IRQ00 +KINT0: KRM5 +POEG0: GTETRG +SLCDC0: COM1 +SPI0: SSL2" +"P106","69","GPIO","Low","","Output mode (Initial Low)","CMOS","None","GPT0: GTIOCB +KINT0: KRM6 +SLCDC0: COM2 +SPI0: SSL3" +"P107","68","","","","Disabled","","","GPT0: GTIOCA +KINT0: KRM7 +SLCDC0: COM3" +"P108","51","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO +DEBUG0: TMS +GPT0: GTIOCB +OPS0: GTOULO +SCI9: CTS_RTS_SS +SPI1: SSL0" +"P109","52","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN0: CTX +CGC0: CLKOUT +CTSU0: TS10 +DEBUG0: SWO +DEBUG0: TDO +GPT1: GTIOCA +OPS0: GTOVUP +SCI1: SCK +SCI9: SDA +SCI9: TXD_MOSI +SLCDC0: SEG23 +SPI1: MOSI" +"P110","53","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","CAN0: CRX +CMP0: VCOUT +DEBUG0: TDI +GPT1: GTIOCB +IRQ0: IRQ03 +OPS0: GTOVLO +SCI2: CTS_RTS_SS +SCI9: RXD_MISO +SCI9: SCL +SLCDC0: SEG24 +SPI1: MISO" +"P111","54","","","","Disabled","","","CTSU0: TS12 +GPT3: GTIOCA +IRQ0: IRQ04 +SCI2: SCK +SCI9: SCK +SLCDC0: CAPH +SPI1: RSPCK" +"P112","55","","","","Disabled","","","CTSU0: TSCAP +GPT3: GTIOCB +SCI1: SCK +SCI2: SDA +SCI2: TXD_MOSI +SLCDC0: CAPL +SPI1: SSL0 +SSI0: SSISCK" +"P113","56","","","","Disabled","","","CTSU0: TS27 +GPT2: GTIOCA +SLCDC0: COM4 +SLCDC0: SEG00 +SSI0: SSIWS" +"P114","57","","","","Disabled","","","CTSU0: TS29 +GPT2: GTIOCB +SLCDC0: SEG25 +SSI0: SSIRXD" +"P115","58","CTSU0_TS35","Low","","Peripheral mode","CMOS","None","CTSU0: TS35 +GPT4: GTIOCA +SLCDC0: SEG26 +SSI0: SSITXD" +"P200","40","","","","Disabled","","","IRQ0: NMI" +"P201","39","","","","Disabled","","","" +"P202","35","","","","Disabled","","","GPT5: GTIOCB +SCI2: SCK +SCI9: RXD_MISO +SCI9: SCL +SLCDC0: SEG16 +SPI1: MISO" +"P203","34","","","","Disabled","","","CTSU0: TSCAP +GPT5: GTIOCA +SCI2: CTS_RTS_SS +SCI9: SDA +SCI9: TXD_MOSI +SLCDC0: SEG15 +SPI1: MOSI" +"P204","33","","","","Disabled","","","AGT1: AGTIO +CAC0: CACREF +CTSU0: TS00 +GPT4: GTIOCB +IIC0: SCL +OPS0: GTIW +SCI0: SCK +SCI9: SCK +SLCDC0: SEG14 +SPI1: RSPCK +USBFS0: OVRCURB" +"P205","32","CTSU0_TSCAP","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO +CGC0: CLKOUT +CTSU0: TSCAP +GPT4: GTIOCA +IIC1: SCL +IRQ0: IRQ01 +OPS0: GTIV +SCI0: SDA +SCI0: TXD_MOSI +SCI9: CTS_RTS_SS +SLCDC0: SEG13 +SPI1: SSL0 +USBFS0: OVRCURA" +"P206","31","","","","Disabled","","","CTSU0: TS01 +IIC1: SDA +IRQ0: IRQ00 +OPS0: GTIU +SCI0: RXD_MISO +SCI0: SCL +SLCDC0: SEG12 +SPI1: SSL1 +USBFS0: VBUSEN" +"P212","14","","","","Disabled","","","AGT1: AGTEE +CGC0: EXTAL +GPT0: GTIOCB +IRQ0: IRQ03 +POEG1: GTETRG +SCI1: RXD_MISO +SCI1: SCL" +"P213","13","","","","Disabled","","","CGC0: XTAL +GPT0: GTIOCA +IRQ0: IRQ02 +POEG0: GTETRG +SCI1: SDA +SCI1: TXD_MOSI" +"P214","11","","","","Disabled","","","CGC0: XCOUT" +"P215","10","","","","Disabled","","","CGC0: XCIN" +"P300","50","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK +DEBUG0: TCK +GPT0: GTIOCA +OPS0: GTOUUP +SPI1: SSL1" +"P301","49","SCI2_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +CTSU0: TS09 +GPT4: GTIOCB +IRQ0: IRQ06 +OPS0: GTOULO +SCI2: RXD_MISO +SCI2: SCL +SCI9: CTS_RTS_SS +SLCDC0: COM5 +SLCDC0: SEG01 +SPI1: SSL2" +"P302","48","SCI2_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CTSU0: TS08 +GPT4: GTIOCA +IRQ0: IRQ05 +OPS0: GTOUUP +SCI2: SDA +SCI2: TXD_MOSI +SLCDC0: COM6 +SLCDC0: SEG02 +SPI1: SSL3" +"P303","47","","","","Disabled","","","CTSU0: TS02 +GPT7: GTIOCB +SLCDC0: COM7 +SLCDC0: SEG03" +"P304","44","","","","Disabled","","","CTSU0: TS11 +GPT7: GTIOCA +IRQ0: IRQ09 +SLCDC0: SEG20" +"P305","43","","","","Disabled","","","IRQ0: IRQ08 +SLCDC0: SEG19" +"P306","42","","","","Disabled","","","SLCDC0: SEG18" +"P307","41","","","","Disabled","","","SLCDC0: SEG17" +"P400","1","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","AGT1: AGTIO +CAC0: CACREF +CTSU0: TS20 +GPT6: GTIOCA +IIC0: SCL +IRQ0: IRQ00 +SCI0: SCK +SCI1: SCK +SLCDC0: SEG04 +SSI: AUDIO_CLK" +"P401","2","SCI1_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CAN0: CTX +CTSU0: TS19 +GPT6: GTIOCB +IIC0: SDA +IRQ0: IRQ05 +POEG0: GTETRG +SCI0: CTS_RTS_SS +SCI1: SDA +SCI1: TXD_MOSI +SLCDC0: SEG05" +"P402","3","SCI1_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +AGT1: AGTIO +CAN0: CRX +CTSU0: TS18 +IRQ0: IRQ04 +RTC0: RTCIC0 +SCI1: RXD_MISO +SCI1: SCL +SLCDC0: SEG06" +"P403","4","GPIO","Low","","Output mode (Initial Low)","CMOS","None","AGT0: AGTIO +AGT1: AGTIO +CTSU0: TS17 +GPT3: GTIOCA +RTC0: RTCIC1 +SCI1: CTS_RTS_SS +SSI0: SSISCK" +"P404","5","","","","Disabled","","","GPT3: GTIOCB +RTC0: RTCIC2 +SSI0: SSIWS" +"P405","6","","","","Disabled","","","GPT1: GTIOCA +SSI0: SSITXD" +"P406","7","","","","Disabled","","","GPT1: GTIOCB +SSI0: SSIRXD" +"P407","25","USBFS0_VBUS","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +AGT0: AGTIO +CTSU0: TS03 +IIC0: SDA +RTC0: RTCOUT +SCI0: CTS_RTS_SS +SLCDC0: SEG11 +SPI1: SSL3 +USBFS0: VBUS" +"P408","24","","","","Disabled","","","CTSU0: TS04 +GPT5: GTIOCB +IIC0: SCL +IRQ0: IRQ07 +OPS0: GTOWLO +SCI1: CTS_RTS_SS +SCI9: RXD_MISO +SCI9: SCL +SLCDC0: SEG10 +USBFS0: ID" +"P409","23","","","","Disabled","","","CTSU0: TS05 +GPT5: GTIOCA +IRQ0: IRQ06 +OPS0: GTOWUP +SCI9: SDA +SCI9: TXD_MOSI +SLCDC0: SEG09 +USBFS0: EXICEN" +"P410","22","SCI0_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOB +CTSU0: TS06 +GPT6: GTIOCB +IRQ0: IRQ05 +OPS0: GTOVLO +SCI0: RXD_MISO +SCI0: SCL +SLCDC0: SEG08 +SPI0: MISO" +"P411","21","SCI0_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOA +CTSU0: TS07 +GPT6: GTIOCA +IRQ0: IRQ04 +OPS0: GTOVUP +SCI0: SDA +SCI0: TXD_MOSI +SLCDC0: SEG07 +SPI0: MOSI" +"P412","20","","","","Disabled","","","SCI0: SCK +SPI0: RSPCK" +"P413","19","","","","Disabled","","","SCI0: CTS_RTS_SS +SPI0: SSL0" +"P414","18","","","","Disabled","","","GPT0: GTIOCB +IRQ0: IRQ09 +SPI0: SSL1" +"P415","17","","","","Disabled","","","GPT0: GTIOCA +IRQ0: IRQ08 +SPI0: SSL2" +"P500","76","","","","Disabled","","","ADC0: AN16 +AGT0: AGTOA +CMP0: CMPREF1 +GPT2: GTIOCA +OPS0: GTIU +SLCDC0: SEG34 +USBFS0: VBUSEN" +"P501","77","","","","Disabled","","","ADC0: AN17 +AGT0: AGTOB +CMP0: CMPIN1 +GPT2: GTIOCB +IRQ0: IRQ11 +OPS0: GTIV +SCI1: SDA +SCI1: TXD_MOSI +SLCDC0: SEG35 +USBFS0: OVRCURA" +"P502","78","","","","Disabled","","","ADC0: AN18 +CMP0: CMPREF0 +GPT3: GTIOCB +IRQ0: IRQ12 +OPS0: GTIW +SCI1: RXD_MISO +SCI1: SCL +SLCDC0: SEG36 +USBFS0: OVRCURB" +"P503","79","","","","Disabled","","","ADC0: AN23 +CMP0: CMPIN0 +SCI1: SCK +SLCDC0: SEG37 +USBFS0: EXICEN" +"P504","80","","","","Disabled","","","ADC0: AN24 +SCI1: CTS_RTS_SS +USBFS0: ID" +"P505","81","","","","Disabled","","","ADC0: AN25 +IRQ0: IRQ14" +"P600","67","","","","Disabled","","","GPT6: GTIOCB +SCI9: SCK +SLCDC0: SEG33" +"P601","66","","","","Disabled","","","GPT6: GTIOCA +SCI9: RXD_MISO +SCI9: SCL +SLCDC0: SEG32" +"P602","65","","","","Disabled","","","GPT7: GTIOCB +SCI9: SDA +SCI9: TXD_MOSI +SLCDC0: SEG31" +"P603","64","","","","Disabled","","","GPT7: GTIOCA +SCI9: CTS_RTS_SS +SLCDC0: SEG30" +"P608","59","","","","Disabled","","","GPT4: GTIOCB +SLCDC0: SEG27" +"P609","60","","","","Disabled","","","GPT5: GTIOCA +SLCDC0: SEG28" +"P610","61","","","","Disabled","","","GPT5: GTIOCB +SLCDC0: SEG29" +"P708","16","","","","Disabled","","","SCI1: RXD_MISO +SCI1: SCL +SPI0: SSL3" +"P808","45","","","","Disabled","","","SLCDC0: SEG21" +"P809","46","","","","Disabled","","","SLCDC0: SEG22" +"P914","28","USBFS0_USBDP","","","Peripheral mode","","","USBFS0: USBDP" +"P915","27","USBFS0_USBDM","","","Peripheral mode","","","USBFS0: USBDM" +"RES","38","","","","","","","" +"VBAT","8","","","","","","","" +"VCC","15","","","","","","","" +"VCC","37","","","","","","","" +"VCC","82","","","","","","","" +"VCC","62","","","","","","","" +"VCCUSB","29","USBFS0_VCCUSB","","","","","","" +"VCCUSBLDO","30","USBFS0_VCCUSBLDO","","","","","","" +"VCL","9","","","","","","","" +"VSS","12","","","","","","","" +"VSS","36","","","","","","","" +"VSS","83","","","","","","","" +"VSS","63","","","","","","","" +"VSSUSB","26","USBFS0_VSSUSB","","","","","","" diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..cf28c33d7 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,21 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (0) /* HOCO 24MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_8_0 /* PLL Mul x8 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* UCLK Src: PLL */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_pin_cfg.h b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_pin_cfg.h new file mode 100644 index 000000000..9aea535b5 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/bsp_pin_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "bsp_api.h" +#include "r_ioport_api.h" +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4M1-EK.pincfg */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.c b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.c new file mode 100644 index 000000000..34aad762f --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.c @@ -0,0 +1,7 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.h b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.h new file mode 100644 index 000000000..e2eb70836 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.c b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.c new file mode 100644 index 000000000..cfaa1abd0 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.c @@ -0,0 +1,471 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc0_cfg = +{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, + #if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc0_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ .low_power_mode = LPM_MODE_SLEEP, + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = 0, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = 0, + .power_supply_state = 0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, }; + +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; +const transfer_cfg_t g_transfer1_cfg = +{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; +const transfer_cfg_t g_transfer0_cfg = +{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = + { + /* Actual calculated bitrate: 12000000. */ .spbr = 1, + .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ .channel = 0, + + #if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; +flash_lp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, }; +const rtc_cfg_t g_rtc0_cfg = +{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = + NULL, + .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), + #if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, + #else + .alarm_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, + #else + .periodic_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, + #else + .carry_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; +sci_uart_instance_ctrl_t g_uart2_ctrl; + +baud_setting_t g_uart2_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart2_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart2_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart2_cfg = +{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart2_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI2_RXI) + .rxi_irq = VECTOR_NUMBER_SCI2_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI2_TXI) + .txi_irq = VECTOR_NUMBER_SCI2_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI2_TEI) + .tei_irq = VECTOR_NUMBER_SCI2_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI2_ERI) + .eri_irq = VECTOR_NUMBER_SCI2_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart2 = +{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart1_ctrl; + +baud_setting_t g_uart1_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart1_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart1_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart1_cfg = +{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart1_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI1_RXI) + .rxi_irq = VECTOR_NUMBER_SCI1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_TXI) + .txi_irq = VECTOR_NUMBER_SCI1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_TEI) + .tei_irq = VECTOR_NUMBER_SCI1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_ERI) + .eri_irq = VECTOR_NUMBER_SCI1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart1 = +{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart0_ctrl; + +baud_setting_t g_uart0_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart0_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart0_cfg = +{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.h b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.h new file mode 100644 index 000000000..4120a4803 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/hal_data.h @@ -0,0 +1,154 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "common_data.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_flash_lp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else +#define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else +#define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/* Flash on Flash LP Instance. */ +extern const flash_instance_t g_flash0; + +/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_lp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart2; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart2_ctrl; +extern const uart_cfg_t g_uart2_cfg; +extern const sci_uart_extended_cfg_t g_uart2_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart1; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart1_ctrl; +extern const uart_cfg_t g_uart1_cfg; +extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart0; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart0_ctrl; +extern const uart_cfg_t g_uart0_cfg; +extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/main.c b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/main.c new file mode 100644 index 000000000..5b9f98055 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) { + hal_entry(); + return 0; +} diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/pin_data.c b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/pin_data.c new file mode 100644 index 000000000..bc928d63f --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/pin_data.c @@ -0,0 +1,105 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE), + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_15, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_03_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_03, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_09_PIN_14, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), + }, + { + .pin = BSP_IO_PORT_09_PIN_15, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), + }, +}; +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.c b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.c new file mode 100644 index 000000000..a5f0092a5 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.c @@ -0,0 +1,53 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [4] = sci_uart_rxi_isr, /* SCI1 RXI (Received data full) */ + [5] = sci_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */ + [6] = sci_uart_tei_isr, /* SCI1 TEI (Transmit end) */ + [7] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */ + [8] = sci_uart_rxi_isr, /* SCI2 RXI (Received data full) */ + [9] = sci_uart_txi_isr, /* SCI2 TXI (Transmit data empty) */ + [10] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [17] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [18] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [19] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [20] = spi_eri_isr, /* SPI0 ERI (Error) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SCI1_RXI), /* SCI1 RXI (Received data full) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TXI), /* SCI1 TXI (Transmit data empty) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TEI), /* SCI1 TEI (Transmit end) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SCI2_RXI), /* SCI2 RXI (Received data full) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TXI), /* SCI2 TXI (Transmit data empty) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ +}; +#endif diff --git a/ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.h b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.h new file mode 100644 index 000000000..1e23b674c --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/ra_gen/vector_data.h @@ -0,0 +1,79 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (21) +#endif +/* ISR prototypes */ +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); +void agt_int_isr(void); +void r_icu_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)4) /* SCI1 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)5) /* SCI1 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)6) /* SCI1 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)7) /* SCI1 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)8) /* SCI2 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)9) /* SCI2 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)10) /* SCI2 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)11) /* SCI2 ERI (Receive error) */ +#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ +#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)17) /* SPI0 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)18) /* SPI0 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)19) /* SPI0 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)20) /* SPI0 ERI (Error) */ +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ + SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ + SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ + SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ + SCI1_RXI_IRQn = 4, /* SCI1 RXI (Received data full) */ + SCI1_TXI_IRQn = 5, /* SCI1 TXI (Transmit data empty) */ + SCI1_TEI_IRQn = 6, /* SCI1 TEI (Transmit end) */ + SCI1_ERI_IRQn = 7, /* SCI1 ERI (Receive error) */ + SCI2_RXI_IRQn = 8, /* SCI2 RXI (Received data full) */ + SCI2_TXI_IRQn = 9, /* SCI2 TXI (Transmit data empty) */ + SCI2_TEI_IRQn = 10, /* SCI2 TEI (Transmit end) */ + SCI2_ERI_IRQn = 11, /* SCI2 ERI (Receive error) */ + RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ + RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ + RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ + AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ + ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */ + SPI0_RXI_IRQn = 17, /* SPI0 RXI (Receive buffer full) */ + SPI0_TXI_IRQn = 18, /* SPI0 TXI (Transmit buffer empty) */ + SPI0_TEI_IRQn = 19, /* SPI0 TEI (Transmission complete event) */ + SPI0_ERI_IRQn = 20, /* SPI0 ERI (Error) */ +} IRQn_Type; +#endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/RA4M1_EK/src/hal_entry.c b/ports/renesas-ra/boards/RA4M1_EK/src/hal_entry.c new file mode 100644 index 000000000..c922cfd17 --- /dev/null +++ b/ports/renesas-ra/boards/RA4M1_EK/src/hal_entry.c @@ -0,0 +1,58 @@ +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); +FSP_CPP_FOOTER + +void ra_main(uint32_t reset_mode); + +/*******************************************************************************************************************//** + * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function + * is called by main() when no RTOS is used. + **********************************************************************************************************************/ +void hal_entry(void) { + /* TODO: add your own code here */ + + ra_main(1); + + #if BSP_TZ_SECURE_BUILD + /* Enter non-secure code */ + R_BSP_NonSecureEnter(); + #endif +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { + #if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ + #endif + } + + if (BSP_WARM_START_POST_C == event) { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + } +} + +#if BSP_TZ_SECURE_BUILD + +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable(); + +/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */ +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() { + +} +#endif diff --git a/ports/renesas-ra/boards/RA4W1_EK/board.json b/ports/renesas-ra/boards/RA4W1_EK/board.json new file mode 100644 index 000000000..db06b6751 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/board.json @@ -0,0 +1,21 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "UART", + "SPI", + "I2C", + "ADC" + ], + "id": "EK-RA4W1", + "images": [ + "ek_ra4w1_board.jpg" + ], + "mcu": "RA4W1", + "product": "EK-RA4W1", + "thumbnail": "", + "url": "https://www.renesas.com/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra4w1-evaluation-kit-ra4w1-mcu-group", + "vendor": "Renesas Electronics" +} diff --git a/ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.h b/ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.h new file mode 100644 index 000000000..0e0dff147 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.h @@ -0,0 +1,70 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "RA4W1_EK" +#define MICROPY_HW_MCU_NAME "RA4W1" +#define MICROPY_HW_MCU_SYSCLK 48000000 +#define MICROPY_HW_MCU_PCLK 48000000 + +// module config +#define MICROPY_EMIT_THUMB (1) +#define MICROPY_EMIT_INLINE_THUMB (1) +#define MICROPY_PY_BUILTINS_COMPLEX (1) +#define MICROPY_PY_GENERATOR_PEND_THROW (1) +#define MICROPY_PY_MATH (1) +#define MICROPY_PY_UHEAPQ (1) +#define MICROPY_PY_UTIMEQ (1) +#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only + +// peripheral config +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (1) // 0: subclock, 1: LOCO (32.768khz) +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +// board config + +// UART +// #define MICROPY_HW_UART0_TX (pin_P101) // Disable (Conflict with PMOD) +// #define MICROPY_HW_UART0_RX (pin_P100) // Disable (Conflict with PMOD) +// #define MICROPY_HW_UART0_CTS (pin_P103) // Disable (Conflict with PMOD) +#define MICROPY_HW_UART1_TX (pin_P213) +#define MICROPY_HW_UART1_RX (pin_P212) +// #define MICROPY_HW_UART1_CTS (pin_P101) // Disable (Conflict with PMOD) +#define MICROPY_HW_UART4_TX (pin_P205) // REPL +#define MICROPY_HW_UART4_RX (pin_P206) // REPL +// #define MICROPY_HW_UART4_CTS (pin_P407) // Conflict with PMOD1-IO1 +#define MICROPY_HW_UART9_TX (pin_P109) +#define MICROPY_HW_UART9_RX (pin_P110) +// #define MICROPY_HW_UART9_CTS (pin_P108) // NC +#define MICROPY_HW_UART_REPL HW_UART_4 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C +#define MICROPY_HW_I2C0_SCL (pin_P204) // Note that conflict with PMOD IO0 +#define MICROPY_HW_I2C0_SDA (pin_P407) // Note that conflict with PMOD IO1 +// #define MICROPY_HW_I2C1_SCL (pin_P100) // Disable (Conflict with SPI0) +// #define MICROPY_HW_I2C1_SDA (pin_P101) // Disable (Conflict with SPI0) + +// SPI +#define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD +#define MICROPY_HW_SPI0_RSPCK (pin_P102) // PMOD +#define MICROPY_HW_SPI0_MISO (pin_P100) // PMOD +#define MICROPY_HW_SPI0_MOSI (pin_P101) // PMOD +// #define MICROPY_HW_SPI1_SSL (pin_P108) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_RSPCK (pin_P111) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_MISO (pin_P110) // Disable (vector not registered) +// #define MICROPY_HW_SPI1_MOSI (pin_P109) // Disable (vector not registered) + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pin_P402) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pin_P106) +#define MICROPY_HW_LED2 (pin_P404) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.mk b/ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.mk new file mode 100644 index 000000000..a22e577fc --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/mpconfigboard.mk @@ -0,0 +1,6 @@ +CMSIS_MCU = RA4W1 +MCU_SERIES = m4 +LD_FILES = boards/RA4W1_EK/ra4w1_ek.ld + +# MicroPython settings +MICROPY_VFS_FAT = 1 diff --git a/ports/renesas-ra/boards/RA4W1_EK/pins.csv b/ports/renesas-ra/boards/RA4W1_EK/pins.csv new file mode 100644 index 000000000..43afa5271 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/pins.csv @@ -0,0 +1,67 @@ +P004,P004 +P010,P010 +P011,P011 +P014,P014 +P015,P015 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P104,P104 +P105,P105 +P106,P106 +P107,P107 +P108,P108 +P109,P109 +P110,P110 +P111,P111 +P200,P200 +P201,P201 +P204,P204 +P205,P205 +P206,P206 +P212,P212 +P213,P213 +P214,P214 +P215,P215 +P300,P300 +P402,P402 +P404,P404 +P407,P407 +P409,P409 +P414,P414 +P501,P501 +P914,P914 +P915,P915 +A0,P004 +A1,P014 +A2,P015 +A3,P501 +A4,P101 +A5,P100 +SDA1,P101 +SCL1,P100 +SCK,P204 +SDA,P407 +D13,P102 +D12,P100 +D11,P101 +D10,P103 +D9,P104 +D8,P106 +D7,P212 +D6,P213 +D5,P414 +D4,P409 +D3,P105 +D2,P111 +D1,P109 +D0,P110 +SWDIO,P108 +SWO,P109 +TDI,P110 +MD,P201 +SWCLK,P300 +SW1,P402 +LED1,P106 +LED2,P404 diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek.ld b/ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek.ld new file mode 100644 index 000000000..172f124fc --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek.ld @@ -0,0 +1,298 @@ +/* + Linker File for RA4W1 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512KB */ + RAM (rwx) : ORIGIN = 0x20000000, LENGTH = 0x00018000 /* 96KB */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */ + ID_CODE (rx) : ORIGIN = 0x01010018, LENGTH = 0x00000020 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek_conf.h b/ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek_conf.h new file mode 100644 index 000000000..261073cfe --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra4w1_ek_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA4M1_EK_CONF_H +#define RA4M1_EK_CONF_H + +#define DEBUG_CH 0 + +#endif /* RA4M1_EK_CONF_H */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000..fd7b0ccb8 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../ra/board/ra4w1_ek/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..9ebcbf977 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,49 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x4000) +#define BSP_CFG_HEAP_BYTES (0xf000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) + +#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (0) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..444d32e56 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (4) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..70984c8ef --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,10 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA4W1AD2CNG +#define BSP_ROM_SIZE_BYTES (524288) +#define BSP_RAM_SIZE_BYTES (98304) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_QFN +#define BSP_PACKAGE_PINS (56) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..fd26bb64e --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,74 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra4w1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA4W1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (24000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (32000000) +#elif BSP_CFG_HOCO_FREQUENCY == 4 +#define BSP_HOCO_HZ (48000000) +#elif BSP_CFG_HOCO_FREQUENCY == 5 +#define BSP_HOCO_HZ (64000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (48U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEC3 | (1 << 2) | (3 << 3) | (0 << 8)) +#define BSP_CFG_USE_LOW_VOLTAGE_MODE ((0)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 000000000..9c59889ca --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 000000000..d3ab55923 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) +#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 000000000..21405f967 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,6 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" +#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h new file mode 100644 index 000000000..26879f9f4 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_flash_lp_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_LP_CFG_H_ +#define R_FLASH_LP_CFG_H_ +#define FLASH_LP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_LP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) +#define FLASH_LP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) +#endif /* R_FLASH_LP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 000000000..5e77b6980 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h new file mode 100644 index 000000000..595ea938d --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (0) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..6b4353d23 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 000000000..5f4d5c4a7 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 000000000..484b7ed04 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 000000000..c70c0be34 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,8 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (0) +#define SCI_UART_CFG_DTC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 000000000..861fe1219 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_DTC_SUPPORT_ENABLE (1) +#define SPI_TRANSMIT_FROM_RXI_ISR (0) +#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/RA4W1-EK.csv b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/RA4W1-EK.csv new file mode 100644 index 000000000..b686a5c0c --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/RA4W1-EK.csv @@ -0,0 +1,257 @@ +"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities" +"ANT","30","RADIO0_ANT","","","","","","" +"AVCC0","35","ANALOG0_AVCC0","","","","","","" +"AVDDRF","39","RADIO0_AVDDRF","","","","","","" +"AVSS0","36","ANALOG0_AVSS0","","","","","","" +"FBIN","45","RADIO0_FBIN","","","","","","" +"LX","41","RADIO0_LX","","","","","","" +"P004","40","","","","Disabled","","","ADC0: AN04 +ICU0: IRQ03 +OPAMP2: AMPO" +"P010","38","","","","Disabled","","","ADC0: AN05 +CTSU0: TS30 +ICU0: IRQ14 +OPAMP2: AMP-" +"P011","37","","","","Disabled","","","ADC0: AN06 +CTSU0: TS31 +ICU0: IRQ15 +OPAMP2: AMP+" +"P014","32","","","","Disabled","","","ADC0: AN09 +DAC0: DA" +"P015","31","","","","Disabled","","","ADC0: AN10 +CTSU0: TS28 +ICU0: IRQ07" +"P100","27","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPIN +AGT0: AGTIO +BUS_ASYNCH0: D00 +GPT_POEG0: GTETRG +GPT5: GTIOCB +ICU0: IRQ02 +IIC1: SCL +KINT0: KRM0 +SCI0: RXD +SCI0: SCL +SCI1: SCK +SLCDC0: VL1 +SPI0: MISO" +"P101","26","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","ACMPLP0: CMPREF +AGT0: AGTEE +BUS_ASYNCH0: D01 +GPT_POEG1: GTETRG +GPT5: GTIOCA +ICU0: IRQ01 +IIC1: SDA +KINT0: KRM1 +SCI0: SDA +SCI0: TXD +SCI1: CTS +SLCDC0: VL2 +SPI0: MOSI" +"P102","25","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ACMPLP1: CMPIN +ADC0: ADTRG +ADC0: AN20 +AGT0: AGTO +BUS_ASYNCH0: D02 +CAN0: CRX +GPT_OPS0: GTOWLO +GPT2: GTIOCB +KINT0: KRM2 +SCI0: SCK +SLCDC0: VL3 +SPI0: RSPCK" +"P103","24","GPIO","Low","","Output mode (Initial High)","CMOS","","ACMPLP1: CMPREF +ADC0: AN19 +BUS_ASYNCH0: D03 +CAN0: CTX +GPT_OPS0: GTOWUP +GPT2: GTIOCA +KINT0: KRM3 +SCI0: CTS +SLCDC0: VL4 +SPI0: SSL0" +"P104","23","","","","Disabled","","","BUS_ASYNCH0: D04 +CTSU0: TS13 +GPT_POEG1: GTETRG +GPT1: GTIOCB +ICU0: IRQ01 +KINT0: KRM4 +SCI0: RXD +SCI0: SCL +SLCDC0: COM0 +SPI0: SSL1" +"P105","22","","","","Disabled","","","BUS_ASYNCH0: D05 +CTSU0: TS34 +GPT_POEG0: GTETRG +GPT1: GTIOCA +ICU0: IRQ00 +KINT0: KRM5 +SLCDC0: COM1 +SPI0: SSL2" +"P106","21","GPIO","Low","","Output mode (Initial High)","CMOS","","BUS_ASYNCH0: D06 +GPT8: GTIOCB +KINT0: KRM6 +SLCDC0: COM2 +SPI0: SSL3" +"P107","20","","","","Disabled","","","BUS_ASYNCH0: D07 +GPT8: GTIOCA +KINT0: KRM7 +SLCDC0: COM3" +"P108","14","","","","Disabled","","","DEBUG0: SWDIO +DEBUG0: TMS +GPT_OPS0: GTOULO +GPT0: GTIOCB +SCI9: CTS +SPI1: SSL0" +"P109","15","SCI9_TXD","Low","","Peripheral mode","CMOS","None","CAN0: CTX +CGC0: CLKOUT +CTSU0: TS10 +DEBUG0: TDO +DEBUG0: TRACESWO +GPT_OPS0: GTOVUP +GPT1: GTIOCA +SCI1: SCK +SCI9: SDA +SCI9: TXD +SLCDC0: SEG52 +SPI1: MOSI" +"P110","16","SCI9_RXD","Low","None","Peripheral mode","CMOS","None","ACMP(0-1): VCOUT +CAN0: CRX +DEBUG0: TDI +GPT_OPS0: GTOVLO +GPT1: GTIOCB +ICU0: IRQ03 +SCI9: RXD +SCI9: SCL +SLCDC0: SEG53 +SPI1: MISO" +"P111","17","GPIO","Low","None","Output mode (Initial High)","CMOS","","BUS_ASYNCH0: A05 +CTSU0: TS12 +GPT3: GTIOCA +ICU0: IRQ04 +SCI9: SCK +SLCDC0: CAPH +SPI1: RSPCK" +"P200","12","","","","Disabled","","","ICU0: NMI" +"P201","11","","","","Disabled","","","SYSTEM0: MD +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC +SYSTEM0: VCC" +"P204","9","GPIO","Low","","Output mode (Initial High)","CMOS","","AGT1: AGTIO +BUS_ASYNCH0: A18 +CAC0: CACREF +CTSU0: TS00 +GPT_OPS0: GTIW +GPT4: GTIOCB +IIC0: SCL +SCI4: SCK +SCI9: SCK +SDHI0: DAT4 +SLCDC0: SEG23 +SPI1: RSPCK +USB_FS0: OVRCURB" +"P205","8","SCI4_TXD","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO +BUS_ASYNCH0: A16 +CGC0: CLKOUT +CTSU0: TSCAP +GPT_OPS0: GTIV +GPT4: GTIOCA +ICU0: IRQ01 +IIC1: SCL +SCI4: SDA +SCI4: TXD +SCI9: CTS +SDHI0: DAT3 +SLCDC0: SEG20 +SPI1: SSL0 +USB_FS0: OVRCURA" +"P206","7","SCI4_RXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: WAIT +CTSU0: TS01 +GPT_OPS0: GTIU +ICU0: IRQ00 +IIC1: SDA +SCI4: RXD +SCI4: SCL +SDHI0: DAT2 +SLCDC0: SEG12 +SPI1: SSL1 +USB_FS0: VBUSEN" +"P212","53","SCI1_RXD","","None","Peripheral mode","CMOS","None","AGT1: AGTEE +CGC0: EXTAL +GPT_POEG1: GTETRG +GPT0: GTIOCB +ICU0: IRQ03 +SCI1: RXD +SCI1: SCL" +"P213","52","SCI1_TXD","","None","Peripheral mode","CMOS","None","CGC0: XTAL +GPT_POEG0: GTETRG +GPT0: GTIOCA +ICU0: IRQ02 +SCI1: SDA +SCI1: TXD" +"P214","50","","","","Disabled","","","CGC0: XCOUT" +"P215","49","","","","Disabled","","","CGC0: XCIN" +"P300","13","","","","Disabled","","","DEBUG0: SWCLK +DEBUG0: TCK +GPT_OPS0: GTOUUP +GPT0: GTIOCA +SPI1: SSL1" +"P305","","","","","Disabled","","","" +"P402","44","IRQ0_IRQ04","","IRQ04","IRQ mode","","None","AGT0: AGTIO +AGT1: AGTIO +CAN0: CRX +CTSU0: TS18 +ICU0: IRQ04 +RTC0: RTCIC0 +SCI1: RXD +SCI1: SCL +SLCDC0: SEG06" +"P404","46","GPIO","Low","","Output mode (Initial High)","CMOS","","GPT3: GTIOCB +RTC0: RTCIC2 +SSI0: SSIWS" +"P407","1","","","","Disabled","","","ADC0: ADTRG +AGT0: AGTIO +CTSU0: TS03 +IIC0: SDA +RTC0: RTCOUT +SCI4: CTS +SLCDC0: SEG11 +SPI1: SSL3 +USBFS0: VBUS" +"P409","56","","","","Disabled","","","GPT_OPS0: GTOWUP +GPT5: GTIOCA +ICU0: IRQ06 +SLCDC0: SEG09" +"P414","55","","","","Disabled","","","GPT0: GTIOCB +ICU0: IRQ09 +SDHI0: WP +SPI0: SSL1" +"P501","29","","","","Disabled","","","ACMPLP1: CMPIN +ADC0: AN17 +AGT0: AGTOB +GPT_OPS0: GTIV +GPT2: GTIOCB +ICU0: IRQ11 +QSPI0: QSSL +SLCDC0: SEG49 +USB_FS0: OVRCURA" +"P914","4","","","","Disabled","","","USB_FS0: DP" +"P915","3","","","","Disabled","","","USB_FS0: DM" +"Q1","34","RADIO0_Q1","","","","","","" +"Q2","33","RADIO0_Q2","","","","","","" +"RES#","10","SYSTEM0_RES","","","","","","" +"TEST0","28","RADIO0_TEST0","","","","","","" +"VBATT","47","SYSTEM0_VBATT","","","","","","" +"VCC","18","SYSTEM0_VCC","","","","","","" +"VCC","54","SYSTEM0_VCC","","","","","","" +"VCCUSB","5","USBFS0_VCC","","","","","","" +"VCCUSBLDO","6","USBFS0_VCCLDO","","","","","","" +"VCL","48","SYSTEM0_VCL","","","","","","" +"VDDDIG","43","RADIO0_VDDDIG","","","","","","" +"VDDRF","42","RADIO0_VDDRF","","","","","","" +"VSS","19","SYSTEM0_VSS","","","","","","" +"VSS","51","SYSTEM0_VSS","","","","","","" +"VSSUSB","2","USBFS0_VSS","","","","","","" diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..9432ad009 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,23 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (8000000) /* XTAL 8000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (4) /* HOCO 48MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_2) /* PLL Div /2 */ +#define BSP_CFG_PLL_MUL (BSP_CLOCKS_PLL_MUL_12_0) /* PLL Mul x12 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* Clock Src: HOCO */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* ICLK Div /1 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKA Div /1 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKB Div /2 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKC Div /1 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* PCLKD Div /1 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* FCLK Div /2 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#define BSP_CFG_UCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_HOCO) /* UCLK Src: HOCO */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/bsp_pin_cfg.h b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/bsp_pin_cfg.h new file mode 100644 index 000000000..497c92d06 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/bsp_pin_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "bsp_api.h" +#include "r_ioport_api.h" +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA4W1-EK.pincfg */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/common_data.c b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/common_data.c new file mode 100644 index 000000000..34aad762f --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/common_data.c @@ -0,0 +1,7 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/common_data.h b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/common_data.h new file mode 100644 index 000000000..e2eb70836 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/hal_data.c b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/hal_data.c new file mode 100644 index 000000000..8e7ee1bd4 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/hal_data.c @@ -0,0 +1,624 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc0_cfg = +{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_14_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, + #if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc0_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; +iic_master_instance_ctrl_t g_i2c_master0_ctrl; +const iic_master_extended_cfg_t g_i2c_master0_extend = +{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, +/* Actual calculated bitrate: 99272. Actual calculated duty cycle: 49%. */ .clock_settings.brl_value = 27, + .clock_settings.brh_value = 26, .clock_settings.cks_value = 2, }; +const i2c_master_cfg_t g_i2c_master0_cfg = +{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .p_callback = callback_iic, + .p_context = NULL, + #if defined(VECTOR_NUMBER_IIC0_RXI) + .rxi_irq = VECTOR_NUMBER_IIC0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC0_TXI) + .txi_irq = VECTOR_NUMBER_IIC0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC0_TEI) + .tei_irq = VECTOR_NUMBER_IIC0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC0_ERI) + .eri_irq = VECTOR_NUMBER_IIC0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + .ipl = (12), + .p_extend = &g_i2c_master0_extend, }; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master0 = +{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic }; +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ .low_power_mode = LPM_MODE_SLEEP, + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = 0, + .power_supply_state = 0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, }; + +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; +const transfer_cfg_t g_transfer1_cfg = +{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; +const transfer_cfg_t g_transfer0_cfg = +{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = + { + /* Actual calculated bitrate: 12000000. */ .spbr = 1, + .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ .channel = 0, + + #if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; +icu_instance_ctrl_t g_external_irq4_ctrl; +const external_irq_cfg_t g_external_irq4_cfg = +{ .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq4 = +{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq3_ctrl; +const external_irq_cfg_t g_external_irq3_cfg = +{ .channel = 3, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ3) + .irq = VECTOR_NUMBER_ICU_IRQ3, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq3 = +{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq2_ctrl; +const external_irq_cfg_t g_external_irq2_cfg = +{ .channel = 2, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ2) + .irq = VECTOR_NUMBER_ICU_IRQ2, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq2 = +{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq1_ctrl; +const external_irq_cfg_t g_external_irq1_cfg = +{ .channel = 1, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ1) + .irq = VECTOR_NUMBER_ICU_IRQ1, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq1 = +{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; +agt_instance_ctrl_t g_timer1_ctrl; +const agt_extended_cfg_t g_timer1_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer1_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer1_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT1_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer1 = +{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.002730666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; +flash_lp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, .ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_lp }; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, }; +const rtc_cfg_t g_rtc0_cfg = +{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = + NULL, + .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), + #if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, + #else + .alarm_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, + #else + .periodic_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, + #else + .carry_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; +sci_uart_instance_ctrl_t g_uart9_ctrl; + +baud_setting_t g_uart9_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart9_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart9_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart9_cfg = +{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = +{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart4_ctrl; + +baud_setting_t g_uart4_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart4_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart4_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart4_cfg = +{ .channel = 4, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart4_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI4_RXI) + .rxi_irq = VECTOR_NUMBER_SCI4_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI4_TXI) + .txi_irq = VECTOR_NUMBER_SCI4_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI4_TEI) + .tei_irq = VECTOR_NUMBER_SCI4_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI4_ERI) + .eri_irq = VECTOR_NUMBER_SCI4_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart4 = +{ .p_ctrl = &g_uart4_ctrl, .p_cfg = &g_uart4_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart1_ctrl; + +baud_setting_t g_uart1_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 25, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart1_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart1_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart1_cfg = +{ .channel = 1, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart1_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI1_RXI) + .rxi_irq = VECTOR_NUMBER_SCI1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_TXI) + .txi_irq = VECTOR_NUMBER_SCI1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_TEI) + .tei_irq = VECTOR_NUMBER_SCI1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI1_ERI) + .eri_irq = VECTOR_NUMBER_SCI1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart1 = +{ .p_ctrl = &g_uart1_ctrl, .p_cfg = &g_uart1_cfg, .p_api = &g_uart_on_sci }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/hal_data.h b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/hal_data.h new file mode 100644 index 000000000..cf3f00771 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/hal_data.h @@ -0,0 +1,216 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "common_data.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_flash_lp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master0; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; +extern const i2c_master_cfg_t g_i2c_master0_cfg; + +#ifndef callback_iic +void callback_iic(i2c_master_callback_args_t *p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else +#define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else +#define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq4; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq4_ctrl; +extern const external_irq_cfg_t g_external_irq4_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq3; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq3_ctrl; +extern const external_irq_cfg_t g_external_irq3_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq2; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq2_ctrl; +extern const external_irq_cfg_t g_external_irq2_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq1; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq1_ctrl; +extern const external_irq_cfg_t g_external_irq1_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer1_ctrl; +extern const timer_cfg_t g_timer1_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/* Flash on Flash LP Instance. */ +extern const flash_instance_t g_flash0; + +/** Access the Flash LP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_lp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart9; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart9_ctrl; +extern const uart_cfg_t g_uart9_cfg; +extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart4; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart4_ctrl; +extern const uart_cfg_t g_uart4_cfg; +extern const sci_uart_extended_cfg_t g_uart4_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart1; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart1_ctrl; +extern const uart_cfg_t g_uart1_cfg; +extern const sci_uart_extended_cfg_t g_uart1_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/main.c b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/main.c new file mode 100644 index 000000000..5b9f98055 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) { + hal_entry(); + return 0; +} diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/pin_data.c b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/pin_data.c new file mode 100644 index 000000000..2a5a8764c --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/pin_data.c @@ -0,0 +1,69 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_01_PIN_11, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), + }, + { + .pin = BSP_IO_PORT_02_PIN_04, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_02_PIN_06, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_02_PIN_12, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_02_PIN_13, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_04_PIN_04, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_HIGH), + }, +}; +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/vector_data.c b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/vector_data.c new file mode 100644 index 000000000..1867e7383 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/vector_data.c @@ -0,0 +1,71 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = sci_uart_rxi_isr, /* SCI1 RXI (Received data full) */ + [1] = sci_uart_txi_isr, /* SCI1 TXI (Transmit data empty) */ + [2] = sci_uart_tei_isr, /* SCI1 TEI (Transmit end) */ + [3] = sci_uart_eri_isr, /* SCI1 ERI (Receive error) */ + [4] = sci_uart_rxi_isr, /* SCI4 RXI (Received data full) */ + [5] = sci_uart_txi_isr, /* SCI4 TXI (Transmit data empty) */ + [6] = sci_uart_tei_isr, /* SCI4 TEI (Transmit end) */ + [7] = sci_uart_eri_isr, /* SCI4 ERI (Receive error) */ + [8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ + [9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ + [17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [22] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [23] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [24] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [25] = spi_eri_isr, /* SPI0 ERI (Error) */ + [26] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ + [27] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ + [28] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ + [29] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_SCI1_RXI), /* SCI1 RXI (Received data full) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TXI), /* SCI1 TXI (Transmit data empty) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_SCI1_TEI), /* SCI1 TEI (Transmit end) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SCI1_ERI), /* SCI1 ERI (Receive error) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SCI4_RXI), /* SCI4 RXI (Received data full) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TXI), /* SCI4 TXI (Transmit data empty) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SCI4_TEI), /* SCI4 TEI (Transmit end) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI4_ERI), /* SCI4 ERI (Receive error) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */ +}; +#endif diff --git a/ports/renesas-ra/boards/RA4W1_EK/ra_gen/vector_data.h b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/vector_data.h new file mode 100644 index 000000000..c45ef8d95 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/ra_gen/vector_data.h @@ -0,0 +1,101 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (30) +#endif +/* ISR prototypes */ +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); +void agt_int_isr(void); +void r_icu_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI1_RXI ((IRQn_Type)0) /* SCI1 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI1_TXI ((IRQn_Type)1) /* SCI1 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI1_TEI ((IRQn_Type)2) /* SCI1 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI1_ERI ((IRQn_Type)3) /* SCI1 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI4_RXI ((IRQn_Type)4) /* SCI4 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI4_TXI ((IRQn_Type)5) /* SCI4 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI4_TEI ((IRQn_Type)6) /* SCI4 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI4_ERI ((IRQn_Type)7) /* SCI4 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ +#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */ +#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */ +#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */ +#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */ +#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */ +#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)22) /* SPI0 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)23) /* SPI0 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)24) /* SPI0 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)25) /* SPI0 ERI (Error) */ +#define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)26) /* IIC0 RXI (Receive data full) */ +#define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)27) /* IIC0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)28) /* IIC0 TEI (Transmit end) */ +#define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)29) /* IIC0 ERI (Transfer error) */ +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + SCI1_RXI_IRQn = 0, /* SCI1 RXI (Received data full) */ + SCI1_TXI_IRQn = 1, /* SCI1 TXI (Transmit data empty) */ + SCI1_TEI_IRQn = 2, /* SCI1 TEI (Transmit end) */ + SCI1_ERI_IRQn = 3, /* SCI1 ERI (Receive error) */ + SCI4_RXI_IRQn = 4, /* SCI4 RXI (Received data full) */ + SCI4_TXI_IRQn = 5, /* SCI4 TXI (Transmit data empty) */ + SCI4_TEI_IRQn = 6, /* SCI4 TEI (Transmit end) */ + SCI4_ERI_IRQn = 7, /* SCI4 ERI (Receive error) */ + SCI9_RXI_IRQn = 8, /* SCI9 RXI (Received data full) */ + SCI9_TXI_IRQn = 9, /* SCI9 TXI (Transmit data empty) */ + SCI9_TEI_IRQn = 10, /* SCI9 TEI (Transmit end) */ + SCI9_ERI_IRQn = 11, /* SCI9 ERI (Receive error) */ + RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ + RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ + RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ + AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ + AGT1_INT_IRQn = 16, /* AGT1 INT (AGT interrupt) */ + ICU_IRQ0_IRQn = 17, /* ICU IRQ0 (External pin interrupt 0) */ + ICU_IRQ1_IRQn = 18, /* ICU IRQ1 (External pin interrupt 1) */ + ICU_IRQ2_IRQn = 19, /* ICU IRQ2 (External pin interrupt 2) */ + ICU_IRQ3_IRQn = 20, /* ICU IRQ3 (External pin interrupt 3) */ + ICU_IRQ4_IRQn = 21, /* ICU IRQ4 (External pin interrupt 4) */ + SPI0_RXI_IRQn = 22, /* SPI0 RXI (Receive buffer full) */ + SPI0_TXI_IRQn = 23, /* SPI0 TXI (Transmit buffer empty) */ + SPI0_TEI_IRQn = 24, /* SPI0 TEI (Transmission complete event) */ + SPI0_ERI_IRQn = 25, /* SPI0 ERI (Error) */ + IIC0_RXI_IRQn = 26, /* IIC0 RXI (Receive data full) */ + IIC0_TXI_IRQn = 27, /* IIC0 TXI (Transmit data empty) */ + IIC0_TEI_IRQn = 28, /* IIC0 TEI (Transmit end) */ + IIC0_ERI_IRQn = 29, /* IIC0 ERI (Transfer error) */ +} IRQn_Type; +#endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/RA4W1_EK/src/hal_entry.c b/ports/renesas-ra/boards/RA4W1_EK/src/hal_entry.c new file mode 100644 index 000000000..3e53787c6 --- /dev/null +++ b/ports/renesas-ra/boards/RA4W1_EK/src/hal_entry.c @@ -0,0 +1,59 @@ +#include "stdbool.h" +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); +FSP_CPP_FOOTER + +void ra_main(uint32_t reset_mode); + +/*******************************************************************************************************************//** + * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function + * is called by main() when no RTOS is used. + **********************************************************************************************************************/ +void hal_entry(void) { + /* TODO: add your own code here */ + + ra_main(1); + + #if BSP_TZ_SECURE_BUILD + /* Enter non-secure code */ + R_BSP_NonSecureEnter(); + #endif +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { + #if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ + #endif + } + + if (BSP_WARM_START_POST_C == event) { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + } +} + +#if BSP_TZ_SECURE_BUILD + +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable(); + +/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */ +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() { + +} +#endif diff --git a/ports/renesas-ra/boards/RA6M1_EK/board.json b/ports/renesas-ra/boards/RA6M1_EK/board.json new file mode 100644 index 000000000..babcc5c16 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/board.json @@ -0,0 +1,21 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "UART", + "SPI", + "I2C", + "ADC" + ], + "id": "EK-RA6M1", + "images": [ + "ek_ra6m1_board.jpg" + ], + "mcu": "RA6M1", + "product": "EK-RA6M1", + "thumbnail": "", + "url": "https://www.renesas.com/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m1-evaluation-kit-ra6m1-mcu-group", + "vendor": "Renesas Electronics" +} diff --git a/ports/renesas-ra/boards/RA6M1_EK/mpconfigboard.h b/ports/renesas-ra/boards/RA6M1_EK/mpconfigboard.h new file mode 100644 index 000000000..0693e404f --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/mpconfigboard.h @@ -0,0 +1,75 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "RA6M1_EK" +#define MICROPY_HW_MCU_NAME "RA6M1" +#define MICROPY_HW_MCU_SYSCLK 120000000 +#define MICROPY_HW_MCU_PCLK 60000000 + +// module config +#define MICROPY_EMIT_THUMB (1) +#define MICROPY_EMIT_INLINE_THUMB (1) +#define MICROPY_PY_BUILTINS_COMPLEX (1) +#define MICROPY_PY_GENERATOR_PEND_THROW (1) +#define MICROPY_PY_MATH (1) +#define MICROPY_PY_UHEAPQ (1) +#define MICROPY_PY_UTIMEQ (1) +#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only + +// peripheral config +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (0) // subclock +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +// board config + +// UART +#define MICROPY_HW_UART0_TX (pin_P411) // REPL +#define MICROPY_HW_UART0_RX (pin_P410) // REPL +// #define MICROPY_HW_UART1_TX (pin_P213) // Disable (Conflict with XTAL) +// #define MICROPY_HW_UART1_RX (pin_P212) // Disable (Conflict with XTAL) +#define MICROPY_HW_UART2_TX (pin_P302) +#define MICROPY_HW_UART2_RX (pin_P301) +// #define MICROPY_HW_UART3_TX (pin_P409) // Disable +// #define MICROPY_HW_UART3_RX (pin_P408) // Disable +// #define MICROPY_HW_UART3_CTS (pin_P411) // Disable (Conflict with UART0_TX) +// #define MICROPY_HW_UART4_TX (pin_P205) // Disable (Conflict with TSCAP-A) +// #define MICROPY_HW_UART4_RX (pin_P206) // Disable +// #define MICROPY_HW_UART4_CTS (pin_P401) // Disable +#define MICROPY_HW_UART8_TX (pin_P105) // PMOD B +#define MICROPY_HW_UART8_RX (pin_P104) // PMOD B +#define MICROPY_HW_UART8_CTS (pin_P107) // PMOD B +// #define MICROPY_HW_UART9_TX (pin_P602) // Disable (does not work properly) +// #define MICROPY_HW_UART9_RX (pin_P601) // Disable (does not work properly) +// #define MICROPY_HW_UART9_CTS (pin_P301) // Disable (does not work properly) +#define MICROPY_HW_UART_REPL HW_UART_0 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C +#define MICROPY_HW_I2C0_SCL (pin_P400) +#define MICROPY_HW_I2C0_SDA (pin_P401) +// #define MICROPY_HW_I2C1_SCL (pin_P100) // Disable (Conflict with SPI0) +// #define MICROPY_HW_I2C1_SDA (pin_P101) // Disable (Conflict with SPI0) + +// SPI +#define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD A +#define MICROPY_HW_SPI0_RSPCK (pin_P102) // PMOD A +#define MICROPY_HW_SPI0_MISO (pin_P100) // PMOD A +#define MICROPY_HW_SPI0_MOSI (pin_P101) // PMOD A +// #define MICROPY_HW_SPI1_SSL (pin_P108) // Disable (Used for J-Link) +// #define MICROPY_HW_SPI1_RSPCK (pin_P111) +// #define MICROPY_HW_SPI1_MISO (pin_P110) +// #define MICROPY_HW_SPI1_MOSI (pin_P109) + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pin_P415) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pin_P112) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/RA6M1_EK/mpconfigboard.mk b/ports/renesas-ra/boards/RA6M1_EK/mpconfigboard.mk new file mode 100644 index 000000000..06f5f97bd --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/mpconfigboard.mk @@ -0,0 +1,6 @@ +CMSIS_MCU = RA6M1 +MCU_SERIES = m4 +LD_FILES = boards/RA6M1_EK/ra6m1_ek.ld + +# MicroPython settings +MICROPY_VFS_FAT = 1 diff --git a/ports/renesas-ra/boards/RA6M1_EK/pins.csv b/ports/renesas-ra/boards/RA6M1_EK/pins.csv new file mode 100644 index 000000000..6f685fa37 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/pins.csv @@ -0,0 +1,85 @@ +P000,P000 +P001,P001 +P002,P002 +P003,P003 +P004,P004 +P005,P005 +P006,P006 +P007,P007 +P008,P008 +P014,P014 +P015,P015 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P104,P104 +P105,P105 +P106,P106 +P107,P107 +P108,P108 +P109,P109 +P110,P110 +P111,P111 +P112,P112 +P113,P113 +P114,P114 +P115,P115 +P200,P200 +P201,P201 +P205,P205 +P206,P206 +P207,P207 +P208,P208 +P209,P209 +P210,P210 +P211,P211 +P212,P212 +P213,P213 +P214,P214 +P300,P300 +P301,P301 +P302,P302 +P303,P303 +P304,P304 +P305,P305 +P306,P306 +P307,P307 +P400,P400 +P401,P401 +P402,P402 +P403,P403 +P404,P404 +P405,P405 +P406,P406 +P407,P407 +P408,P408 +P409,P409 +P410,P410 +P411,P411 +P412,P412 +P413,P413 +P414,P414 +P415,P415 +P500,P500 +P501,P501 +P502,P502 +P503,P503 +P504,P504 +P508,P508 +P600,P600 +P601,P601 +P602,P602 +P603,P603 +P608,P608 +P609,P609 +P610,P610 +P708,P708 +P808,P808 +P809,P809 +P914,P914 +P915,P915 +SW1,P415 +LED1,P112 +USBDP,P914 +USBDM,P915 diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra6m1_ek.ld b/ports/renesas-ra/boards/RA6M1_EK/ra6m1_ek.ld new file mode 100644 index 000000000..10ec87aaa --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra6m1_ek.ld @@ -0,0 +1,298 @@ +/* + Linker File for RA6M1 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00080000 /* 512KB */ + RAM (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 0x00040000 /* 256KB */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00002000 /* 8KB */ + ID_CODE (rx) : ORIGIN = 0x0100A150, LENGTH = 0x00000010 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra6m1_ek_conf.h b/ports/renesas-ra/boards/RA6M1_EK/ra6m1_ek_conf.h new file mode 100644 index 000000000..4ef32aefb --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra6m1_ek_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA6M1_EK_CONF_H +#define RA6M1_EK_CONF_H + +#define DEBUG_CH 0 + +#endif /* RA6M1_EK_CONF_H */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000..f518a94aa --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../ra/board/ra6m1_ek/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..54b41a45d --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,49 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x4000) +#define BSP_CFG_HEAP_BYTES (0x2d000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) + +#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..bd6a901c3 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..5fc7730d2 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,10 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M1AD3CFP +#define BSP_ROM_SIZE_BYTES (524288) +#define BSP_RAM_SIZE_BYTES (262144) +#define BSP_DATA_FLASH_SIZE_BYTES (8192) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (100) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..720eee2d7 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,74 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m1/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA6M1 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 +#define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (20000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 000000000..9c59889ca --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 000000000..d3ab55923 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) +#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 000000000..21405f967 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,6 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" +#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_flash_hp_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_flash_hp_cfg.h new file mode 100644 index 000000000..48c9dec4e --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_flash_hp_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_HP_CFG_H_ +#define R_FLASH_HP_CFG_H_ +#define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) +#define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) +#endif /* R_FLASH_HP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 000000000..5e77b6980 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h new file mode 100644 index 000000000..595ea938d --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (0) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..6b4353d23 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 000000000..5f4d5c4a7 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 000000000..484b7ed04 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 000000000..c70c0be34 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,8 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (0) +#define SCI_UART_CFG_DTC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 000000000..861fe1219 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_DTC_SUPPORT_ENABLE (1) +#define SPI_TRANSMIT_FROM_RXI_ISR (0) +#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/RA6M1-EK.csv b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/RA6M1-EK.csv new file mode 100644 index 000000000..3e1b00116 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/RA6M1-EK.csv @@ -0,0 +1,462 @@ +"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities" +"AVCC0","88","ANALOG0_AVCC0","","","","","","" +"AVSS0","89","ANALOG0_AVSS0","","","","","","" +"P000","100","","","","Disabled","","","ACMPHS0: IVCMP +ADC0: AN00 +ICU0: IRQ06" +"P001","99","","","","Disabled","","","ACMPHS1: IVCMP +ADC0: AN01 +ICU0: IRQ07" +"P002","98","","","","Disabled","","","ACMPHS2: IVCMP +ADC0: AN02 +ICU0: IRQ08" +"P003","97","","","","Disabled","","","ADC0: AN07" +"P004","96","ADC1_AN00","","","Analog mode","","","ACMPHS3: IVCMP +ADC1: AN00 +ICU0: IRQ09" +"P005","95","","","","Disabled","","","ACMPHS4: IVCMP +ADC1: AN01 +ICU0: IRQ10" +"P006","94","","","","Disabled","","","ACMPHS5: IVCMP +ADC1: AN02 +ICU0: IRQ11" +"P007","93","","","","Disabled","","","ADC1: AN07" +"P008","92","","","","Disabled","","","ADC0: AN03 +ICU0: IRQ12" +"P014","85","","","","Disabled","","","ACMPHS0: IVREF +ACMPHS1: IVREF +ACMPHS2: IVREF +ACMPHS3: IVREF +ACMPHS4: IVREF +ACMPHS5: IVREF +ADC0: AN05 +ADC1: AN05 +DAC0: DA" +"P015","84","","","","Disabled","","","ACMPHS0: IVCMP +ACMPHS1: IVCMP +ACMPHS2: IVCMP +ACMPHS3: IVCMP +ACMPHS4: IVCMP +ACMPHS5: IVCMP +ADC0: AN06 +ADC1: AN06 +DAC1: DA +ICU0: IRQ13" +"P100","75","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +BUS_ASYNCH0: D00 +GPT_POEG0: GTETRG +GPT5: GTIOCB +ICU0: IRQ02 +IIC1: SCL +KINT0: KRM0 +SCI0: RXD +SCI0: SCL +SCI1: SCK +SPI0: MISO" +"P101","74","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","AGT0: AGTEE +BUS_ASYNCH0: D01 +GPT_POEG1: GTETRG +GPT5: GTIOCA +ICU0: IRQ01 +IIC1: SDA +KINT0: KRM1 +SCI0: SDA +SCI0: TXD +SCI1: CTS +SPI0: MOSI" +"P102","73","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +AGT0: AGTO +BUS_ASYNCH0: D02 +CAN0: CRX +GPT_OPS0: GTOWLO +GPT2: GTIOCB +KINT0: KRM2 +SCI0: SCK +SPI0: RSPCK" +"P103","72","SPI0_SSL0","Low","","Peripheral mode","CMOS","None","BUS_ASYNCH0: D03 +CAN0: CTX +GPT_OPS0: GTOWUP +GPT2: GTIOCA +KINT0: KRM3 +SCI0: CTS +SPI0: SSL0" +"P104","71","SCI8_RXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: D04 +GPT_POEG1: GTETRG +GPT1: GTIOCB +ICU0: IRQ01 +KINT0: KRM4 +QSPI0: QIO0 +SCI8: RXD +SCI8: SCL +SPI0: SSL1" +"P105","70","SCI8_TXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: D05 +GPT_POEG0: GTETRG +GPT1: GTIOCA +ICU0: IRQ00 +KINT0: KRM5 +QSPI0: QIO1 +SCI8: SDA +SCI8: TXD +SPI0: SSL2" +"P106","69","GPIO","Low","","Output mode (Initial Low)","CMOS","","AGT0: AGTOB +BUS_ASYNCH0: D06 +GPT8: GTIOCB +KINT0: KRM6 +QSPI0: QIO2 +SCI8: SCK +SPI0: SSL3" +"P107","68","GPIO","Low","","Output mode (Initial Low)","CMOS","","AGT0: AGTOA +BUS_ASYNCH0: D07 +GPT8: GTIOCA +KINT0: KRM7 +QSPI0: QIO3 +SCI8: CTS" +"P108","51","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO +DEBUG0: TMS +GPT_OPS0: GTOULO +GPT0: GTIOCB +SCI9: CTS +SPI1: SSL0" +"P109","52","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN1: CTX +CGC0: CLKOUT +DEBUG0: TDO +DEBUG0: TRACESWO +GPT_OPS0: GTOVUP +GPT1: GTIOCA +SCI9: SDA +SCI9: TXD +SPI1: MOSI" +"P110","53","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","ACMP(0-5): VCOUT +CAN1: CRX +DEBUG0: TDI +GPT_OPS0: GTOVLO +GPT1: GTIOCB +ICU0: IRQ03 +SCI2: CTS +SCI9: RXD +SCI9: SCL +SPI1: MISO" +"P111","54","","","","Disabled","","","BUS_ASYNCH0: A05 +GPT3: GTIOCA +ICU0: IRQ04 +SCI2: SCK +SCI9: SCK +SPI1: RSPCK" +"P112","55","GPIO","Low","","Output mode (Initial Low)","CMOS","","BUS_ASYNCH0: A04 +GPT3: GTIOCB +SCI1: SCK +SCI2: SDA +SCI2: TXD +SPI1: SSL0 +SSI0: SSISCK" +"P113","56","","","","Disabled","","","BUS_ASYNCH0: A03 +GPT2: GTIOCA +SCI2: RXD +SCI2: SCL +SSI0: SSIWS" +"P114","57","","","","Disabled","","","BUS_ASYNCH0: A02 +GPT2: GTIOCB +SSI0: SSIRXD" +"P115","58","","","","Disabled","","","BUS_ASYNCH0: A01 +GPT4: GTIOCA +SSI0: SSITXD" +"P200","40","","","","Disabled","","","ICU0: NMI" +"P201","39","GPIO","","","Input mode","","None","SYSTEM0: MD" +"P205","32","CTSU0_TSCAP","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO +CGC0: CLKOUT +CTSU0: TSCAP +GPT_OPS0: GTIV +GPT4: GTIOCA +ICU0: IRQ01 +IIC1: SCL +SCI4: SDA +SCI4: TXD +SCI9: CTS +SDHI0: DAT3 +USB_FS0: OVRCURA" +"P206","31","","","","Disabled","","","BUS_ASYNCH0: WAIT +CTSU0: TS01 +GPT_OPS0: GTIU +ICU0: IRQ00 +IIC1: SDA +SCI4: RXD +SCI4: SCL +SDHI0: DAT2 +USB_FS0: VBUSEN" +"P207","30","CTSU0_TS02","Low","","Peripheral mode","CMOS","None","CTSU0: TS02 +QSPI0: QSSL" +"P208","37","","","","Disabled","","","BUS_ASYNCH0: CS4 +DEBUG_TRACE0: TDATA3 +GPT_OPS0: GTOVLO +QSPI0: QIO3 +SDHI0: DAT0" +"P209","36","","","","Disabled","","","BUS_ASYNCH0: CS5 +DEBUG_TRACE0: TDATA2 +GPT_OPS0: GTOVUP +QSPI0: QIO2 +SDHI0: WP" +"P210","35","","","","Disabled","","","BUS_ASYNCH0: CS6 +DEBUG_TRACE0: TDATA1 +GPT_OPS0: GTIW +QSPI0: QIO1 +SDHI0: CD" +"P211","34","","","","Disabled","","","BUS_ASYNCH0: CS7 +DEBUG_TRACE0: TDATA0 +GPT_OPS0: GTIV +QSPI0: QIO0 +SDHI0: CMD" +"P212","14","","","","Disabled","","","AGT1: AGTEE +CGC0: EXTAL +GPT_POEG3: GTETRG +GPT0: GTIOCB +ICU0: IRQ03 +SCI1: RXD +SCI1: SCL" +"P213","13","","","","Disabled","","","ADC1: ADTRG +CGC0: XTAL +GPT_POEG2: GTETRG +GPT0: GTIOCA +ICU0: IRQ02 +SCI1: SDA +SCI1: TXD" +"P214","33","","","","Disabled","","","DEBUG_TRACE0: TCLK +GPT_OPS0: GTIU +QSPI0: QSPCLK +SDHI0: CLK" +"P300","50","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK +DEBUG0: TCK +GPT_OPS0: GTOUUP +GPT0: GTIOCA +SPI1: SSL1" +"P301","49","SCI2_RXD","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +BUS_ASYNCH0: A06 +GPT_OPS0: GTOULO +GPT4: GTIOCB +ICU0: IRQ06 +SCI2: RXD +SCI2: SCL +SCI9: CTS +SPI1: SSL2" +"P302","48","SCI2_TXD","Low","None","Peripheral mode","CMOS","None","BUS_ASYNCH0: A07 +GPT_OPS0: GTOUUP +GPT4: GTIOCA +ICU0: IRQ05 +SCI2: SDA +SCI2: TXD +SPI1: SSL3" +"P303","47","","","","Disabled","","","BUS_ASYNCH0: A08 +GPT7: GTIOCB" +"P304","44","","","","Disabled","","","BUS_ASYNCH0: A09 +GPT_OPS0: GTOWLO +GPT7: GTIOCA +ICU0: IRQ09" +"P305","43","","","","Disabled","","","BUS_ASYNCH0: A10 +GPT_OPS0: GTOWUP +ICU0: IRQ08 +QSPI0: QSPCLK" +"P306","42","","","","Disabled","","","BUS_ASYNCH0: A11 +GPT_OPS0: GTOULO +QSPI0: QSSL" +"P307","41","","","","Disabled","","","BUS_ASYNCH0: A12 +GPT_OPS0: GTOUUP +QSPI0: QIO0" +"P400","1","IIC0_SCL","Medium","None","Peripheral mode","CMOS","None","ADC1: ADTRG +AGT1: AGTIO +GPT6: GTIOCA +ICU0: IRQ00 +IIC0: SCL +SCI4: SCK +SSI_COMMON0: AUDIO_CLK" +"P401","2","IIC0_SDA","Medium","None","Peripheral mode","CMOS","None","CAN0: CTX +GPT_POEG0: GTETRG +GPT6: GTIOCB +ICU0: IRQ05 +IIC0: SDA +SCI4: CTS" +"P402","3","","","","Disabled","","","AGT0: AGTIO +AGT1: AGTIO +CAC0: CACREF +CAN0: CRX +ICU0: IRQ04 +RTC0: RTCIC0 +SSI_COMMON0: AUDIO_CLK" +"P403","4","","","","Disabled","","","AGT0: AGTIO +AGT1: AGTIO +GPT3: GTIOCA +RTC0: RTCIC1 +SSI0: SSISCK" +"P404","5","","","","Disabled","","","GPT3: GTIOCB +RTC0: RTCIC2 +SSI0: SSIWS" +"P405","6","","","","Disabled","","","GPT1: GTIOCA +SSI0: SSITXD" +"P406","7","","","","Disabled","","","GPT1: GTIOCB +SSI0: SSIRXD" +"P407","25","USBFS0_VBUS","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +AGT0: AGTIO +CTSU0: TS03 +IIC0: SDA +RTC0: RTCOUT +SCI4: CTS +USB_FS0: VBUS" +"P408","24","","","","Disabled","","","CTSU0: TS04 +GPT_OPS0: GTOWLO +GPT10: GTIOCB +ICU0: IRQ07 +IIC0: SCL +SCI3: RXD +SCI3: SCL +USB_FS0: ID" +"P409","23","","","","Disabled","","","CTSU0: TS05 +GPT_OPS0: GTOWUP +GPT10: GTIOCA +ICU0: IRQ06 +SCI3: SDA +SCI3: TXD +USB_FS0: EXICEN" +"P410","22","SCI0_RXD","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOB +CTSU0: TS06 +GPT_OPS0: GTOVLO +GPT9: GTIOCB +ICU0: IRQ05 +SCI0: RXD +SCI0: SCL +SCI3: SCK +SDHI0: DAT1 +SPI0: MISO" +"P411","21","SCI0_TXD","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOA +CTSU0: TS07 +GPT_OPS0: GTOVUP +GPT9: GTIOCA +ICU0: IRQ04 +SCI0: SDA +SCI0: TXD +SCI3: CTS +SDHI0: DAT0 +SPI0: MOSI" +"P412","20","","","","Disabled","","","AGT1: AGTEE +CTSU0: TS08 +GPT_OPS0: GTOULO +SCI0: SCK +SDHI0: CMD +SPI0: RSPCK" +"P413","19","","","","Disabled","","","CTSU0: TS09 +GPT_OPS0: GTOUUP +SCI0: CTS +SDHI0: CLK +SPI0: SSL0" +"P414","18","","","","Disabled","","","CTSU0: TS10 +GPT0: GTIOCB +ICU0: IRQ09 +SDHI0: WP +SPI0: SSL1" +"P415","17","GPIO","","IRQ08","Input mode","","None","CTSU0: TS11 +GPT0: GTIOCA +ICU0: IRQ08 +SDHI0: CD +SPI0: SSL2 +USB_FS0: VBUSEN" +"P500","76","","","","Disabled","","","ACMPHS0: IVREF +ACMPHS1: IVREF +ACMPHS2: IVREF +ACMPHS3: IVREF +ACMPHS4: IVREF +ACMPHS5: IVREF +ADC0: AN16 +AGT0: AGTOA +GPT_OPS0: GTIU +GPT11: GTIOCA +QSPI0: QSPCLK +SDHI1: CLK +USB_FS0: VBUSEN" +"P501","77","","","","Disabled","","","ACMPHS0: IVREF +ACMPHS1: IVREF +ACMPHS2: IVREF +ACMPHS3: IVREF +ACMPHS4: IVREF +ACMPHS5: IVREF +ADC1: AN16 +AGT0: AGTOB +GPT_OPS0: GTIV +GPT11: GTIOCB +ICU0: IRQ11 +QSPI0: QSSL +SDHI1: CMD +USB_FS0: OVRCURA" +"P502","78","","","","Disabled","","","ACMPHS0: IVCMP +ACMPHS1: IVCMP +ACMPHS2: IVCMP +ACMPHS3: IVCMP +ACMPHS4: IVCMP +ACMPHS5: IVCMP +ADC0: AN17 +GPT_OPS0: GTIW +GPT12: GTIOCA +ICU0: IRQ12 +QSPI0: QIO0 +SDHI1: DAT0 +USB_FS0: OVRCURB" +"P503","79","","","","Disabled","","","ADC1: AN17 +GPT_POEG2: GTETRG +GPT12: GTIOCB +QSPI0: QIO1 +SDHI1: DAT1 +USB_FS0: EXICEN" +"P504","80","","","","Disabled","","","ADC0: AN18 +BUS_ASYNCH0: ALE +GPT_POEG3: GTETRG +QSPI0: QIO2 +SDHI1: DAT2 +USB_FS0: ID" +"P508","81","","","","Disabled","","","ADC0: AN20 +SDHI1: DAT3" +"P600","67","","","","Disabled","","","BUS_ASYNCH0: RD +CAC0: CACREF +CGC0: CLKOUT +GPT6: GTIOCB +SCI9: SCK" +"P601","66","","","","Disabled","","","BUS_ASYNCH0: WR0 +GPT6: GTIOCA +SCI9: RXD +SCI9: SCL" +"P602","65","","","","Disabled","","","BUS_ASYNCH0: BCLK +GPT7: GTIOCB +SCI9: SDA +SCI9: TXD" +"P608","59","","","","Disabled","","","BUS_ASYNCH0: A00 +GPT4: GTIOCB" +"P609","60","","","","Disabled","","","BUS_ASYNCH0: CS1 +CAN1: CTX +GPT5: GTIOCA" +"P610","61","","","","Disabled","","","BUS_ASYNCH0: CS0 +CAN1: CRX +GPT5: GTIOCB" +"P708","16","","","","Disabled","","","CAC0: CACREF +CTSU0: TS12 +ICU0: IRQ11 +SCI1: RXD +SCI1: SCL +SPI0: SSL3 +SSI_COMMON0: AUDIO_CLK" +"RES#","38","SYSTEM0_RES","","","","","","" +"USBDM","27","USBFS0_DM","","","","","","" +"USBDP","28","USBFS0_DP","","","","","","" +"VBATT","8","SYSTEM0_VBATT","","","","","","" +"VCC","46","SYSTEM0_VCC","","","","","","" +"VCC","15","SYSTEM0_VCC","","","","","","" +"VCC","82","SYSTEM0_VCC","","","","","","" +"VCC","62","SYSTEM0_VCC","","","","","","" +"VCCUSB","29","USBFS0_VCC","","","","","","" +"VCL","64","SYSTEM0_VCL","","","","","","" +"VCL0","9","SYSTEM0_VCL0","","","","","","" +"VREFH","87","ANALOG0_VREFH","","","","","","" +"VREFH0","91","ANALOG0_VREFH0","","","","","","" +"VREFL","86","ANALOG0_VREFL","","","","","","" +"VREFL0","90","ANALOG0_VREFL0","","","","","","" +"VSS","12","SYSTEM0_VSS","","","","","","" +"VSS","45","SYSTEM0_VSS","","","","","","" +"VSS","83","SYSTEM0_VSS","","","","","","" +"VSS","63","SYSTEM0_VSS","","","","","","" +"VSSUSB","26","USBFS0_VSS","","","","","","" +"XCIN","10","CGC0_XCIN","","","","","","" +"XCOUT","11","CGC0_XCOUT","","","","","","" diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..013621000 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,23 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/bsp_pin_cfg.h b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/bsp_pin_cfg.h new file mode 100644 index 000000000..cc0fd2fe7 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/bsp_pin_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "bsp_api.h" +#include "r_ioport_api.h" +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M1-EK.pincfg */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/common_data.c b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/common_data.c new file mode 100644 index 000000000..34aad762f --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/common_data.c @@ -0,0 +1,7 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/common_data.h b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/common_data.h new file mode 100644 index 000000000..e2eb70836 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/hal_data.c b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/hal_data.c new file mode 100644 index 000000000..56f173511 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/hal_data.c @@ -0,0 +1,834 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +adc_instance_ctrl_t g_adc1_ctrl; +const adc_extended_cfg_t g_adc1_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc1_cfg = +{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend, + #if defined(VECTOR_NUMBER_ADC1_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC1_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc1_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc1 = +{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc }; +iic_master_instance_ctrl_t g_i2c_master0_ctrl; +const iic_master_extended_cfg_t g_i2c_master0_extend = +{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, +/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15, + .clock_settings.brh_value = 16, .clock_settings.cks_value = 4, }; +const i2c_master_cfg_t g_i2c_master0_cfg = +{ .channel = 0, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .p_callback = callback_iic, + .p_context = NULL, + #if defined(VECTOR_NUMBER_IIC0_RXI) + .rxi_irq = VECTOR_NUMBER_IIC0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC0_TXI) + .txi_irq = VECTOR_NUMBER_IIC0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC0_TEI) + .tei_irq = VECTOR_NUMBER_IIC0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC0_ERI) + .eri_irq = VECTOR_NUMBER_IIC0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + .ipl = (12), + .p_extend = &g_i2c_master0_extend, }; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master0 = +{ .p_ctrl = &g_i2c_master0_ctrl, .p_cfg = &g_i2c_master0_cfg, .p_api = &g_i2c_master_on_iic }; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc0_cfg = +{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, + #if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc0_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ .low_power_mode = LPM_MODE_SLEEP, + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, }; + +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; +const transfer_cfg_t g_transfer1_cfg = +{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; +const transfer_cfg_t g_transfer0_cfg = +{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = + { + /* Actual calculated bitrate: 15000000. */ .spbr = 3, + .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ .channel = 0, + + #if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; +icu_instance_ctrl_t g_external_irq13_ctrl; +const external_irq_cfg_t g_external_irq13_cfg = +{ .channel = 13, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ13) + .irq = VECTOR_NUMBER_ICU_IRQ13, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq13 = +{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq12_ctrl; +const external_irq_cfg_t g_external_irq12_cfg = +{ .channel = 12, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ12) + .irq = VECTOR_NUMBER_ICU_IRQ12, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq12 = +{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq11_ctrl; +const external_irq_cfg_t g_external_irq11_cfg = +{ .channel = 11, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ11) + .irq = VECTOR_NUMBER_ICU_IRQ11, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq11 = +{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq10_ctrl; +const external_irq_cfg_t g_external_irq10_cfg = +{ .channel = 10, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ10) + .irq = VECTOR_NUMBER_ICU_IRQ10, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq10 = +{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq9_ctrl; +const external_irq_cfg_t g_external_irq9_cfg = +{ .channel = 9, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ9) + .irq = VECTOR_NUMBER_ICU_IRQ9, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq9 = +{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq8_ctrl; +const external_irq_cfg_t g_external_irq8_cfg = +{ .channel = 8, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ8) + .irq = VECTOR_NUMBER_ICU_IRQ8, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq8 = +{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq7_ctrl; +const external_irq_cfg_t g_external_irq7_cfg = +{ .channel = 7, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ7) + .irq = VECTOR_NUMBER_ICU_IRQ7, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq7 = +{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq6_ctrl; +const external_irq_cfg_t g_external_irq6_cfg = +{ .channel = 6, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ6) + .irq = VECTOR_NUMBER_ICU_IRQ6, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq6 = +{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq5_ctrl; +const external_irq_cfg_t g_external_irq5_cfg = +{ .channel = 5, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ5) + .irq = VECTOR_NUMBER_ICU_IRQ5, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq5 = +{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq4_ctrl; +const external_irq_cfg_t g_external_irq4_cfg = +{ .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq4 = +{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq3_ctrl; +const external_irq_cfg_t g_external_irq3_cfg = +{ .channel = 3, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ3) + .irq = VECTOR_NUMBER_ICU_IRQ3, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq3 = +{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq2_ctrl; +const external_irq_cfg_t g_external_irq2_cfg = +{ .channel = 2, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ2) + .irq = VECTOR_NUMBER_ICU_IRQ2, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq2 = +{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq1_ctrl; +const external_irq_cfg_t g_external_irq1_cfg = +{ .channel = 1, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ1) + .irq = VECTOR_NUMBER_ICU_IRQ1, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq1 = +{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; +agt_instance_ctrl_t g_timer1_ctrl; +const agt_extended_cfg_t g_timer1_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer1_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 1, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer1_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT1_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT1_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer1 = +{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; +flash_hp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, + #if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, + #else + .irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_FCU_FIFERR) + .err_irq = VECTOR_NUMBER_FCU_FIFERR, + #else + .err_irq = FSP_INVALID_VECTOR, + #endif + .err_ipl = (BSP_IRQ_DISABLED), + .ipl = (BSP_IRQ_DISABLED), }; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp }; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, }; +const rtc_cfg_t g_rtc0_cfg = +{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = + NULL, + .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), + #if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, + #else + .alarm_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, + #else + .periodic_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, + #else + .carry_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; +sci_uart_instance_ctrl_t g_uart8_ctrl; + +baud_setting_t g_uart8_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart8_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart8_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart8_cfg = +{ .channel = 8, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart8_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI8_RXI) + .rxi_irq = VECTOR_NUMBER_SCI8_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI8_TXI) + .txi_irq = VECTOR_NUMBER_SCI8_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI8_TEI) + .tei_irq = VECTOR_NUMBER_SCI8_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI8_ERI) + .eri_irq = VECTOR_NUMBER_SCI8_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart8 = +{ .p_ctrl = &g_uart8_ctrl, .p_cfg = &g_uart8_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart2_ctrl; + +baud_setting_t g_uart2_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart2_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart2_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart2_cfg = +{ .channel = 2, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart2_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI2_RXI) + .rxi_irq = VECTOR_NUMBER_SCI2_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI2_TXI) + .txi_irq = VECTOR_NUMBER_SCI2_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI2_TEI) + .tei_irq = VECTOR_NUMBER_SCI2_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI2_ERI) + .eri_irq = VECTOR_NUMBER_SCI2_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart2 = +{ .p_ctrl = &g_uart2_ctrl, .p_cfg = &g_uart2_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart0_ctrl; + +baud_setting_t g_uart0_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart0_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart0_cfg = +{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/hal_data.h b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/hal_data.h new file mode 100644 index 000000000..d8773ab5e --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/hal_data.h @@ -0,0 +1,317 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "common_data.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc1; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc1_ctrl; +extern const adc_cfg_t g_adc1_cfg; +extern const adc_channel_cfg_t g_adc1_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master0; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master0_ctrl; +extern const i2c_master_cfg_t g_i2c_master0_cfg; + +#ifndef callback_iic +void callback_iic(i2c_master_callback_args_t *p_args); +#endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else +#define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else +#define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq13; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq13_ctrl; +extern const external_irq_cfg_t g_external_irq13_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq12; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq12_ctrl; +extern const external_irq_cfg_t g_external_irq12_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq11; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq11_ctrl; +extern const external_irq_cfg_t g_external_irq11_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq10; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq10_ctrl; +extern const external_irq_cfg_t g_external_irq10_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq9; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq9_ctrl; +extern const external_irq_cfg_t g_external_irq9_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq8; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq8_ctrl; +extern const external_irq_cfg_t g_external_irq8_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq7; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq7_ctrl; +extern const external_irq_cfg_t g_external_irq7_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq6; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq6_ctrl; +extern const external_irq_cfg_t g_external_irq6_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq5; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq5_ctrl; +extern const external_irq_cfg_t g_external_irq5_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq4; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq4_ctrl; +extern const external_irq_cfg_t g_external_irq4_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq3; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq3_ctrl; +extern const external_irq_cfg_t g_external_irq3_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq2; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq2_ctrl; +extern const external_irq_cfg_t g_external_irq2_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq1; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq1_ctrl; +extern const external_irq_cfg_t g_external_irq1_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer1_ctrl; +extern const timer_cfg_t g_timer1_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart8; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart8_ctrl; +extern const uart_cfg_t g_uart8_cfg; +extern const sci_uart_extended_cfg_t g_uart8_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart2; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart2_ctrl; +extern const uart_cfg_t g_uart2_cfg; +extern const sci_uart_extended_cfg_t g_uart2_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart0; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart0_ctrl; +extern const uart_cfg_t g_uart0_cfg; +extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/main.c b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/main.c new file mode 100644 index 000000000..5b9f98055 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) { + hal_entry(); + return 0; +} diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/pin_data.c b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/pin_data.c new file mode 100644 index 000000000..a2ddad010 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/pin_data.c @@ -0,0 +1,109 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE), + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_04, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_01_PIN_07, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_12, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_02_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_03_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_03_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_15, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, +}; +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/vector_data.c b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/vector_data.c new file mode 100644 index 000000000..cf17573a0 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/vector_data.c @@ -0,0 +1,89 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [4] = sci_uart_rxi_isr, /* SCI2 RXI (Received data full) */ + [5] = sci_uart_txi_isr, /* SCI2 TXI (Transmit data empty) */ + [6] = sci_uart_tei_isr, /* SCI2 TEI (Transmit end) */ + [7] = sci_uart_eri_isr, /* SCI2 ERI (Receive error) */ + [8] = sci_uart_rxi_isr, /* SCI8 RXI (Received data full) */ + [9] = sci_uart_txi_isr, /* SCI8 TXI (Transmit data empty) */ + [10] = sci_uart_tei_isr, /* SCI8 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI8 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = agt_int_isr, /* AGT1 INT (AGT interrupt) */ + [17] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [18] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [19] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [20] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [21] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [22] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [23] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [24] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [25] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [26] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [27] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ + [28] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [29] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [30] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [31] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [32] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [33] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [34] = spi_eri_isr, /* SPI0 ERI (Error) */ + [35] = iic_master_rxi_isr, /* IIC0 RXI (Receive data full) */ + [36] = iic_master_txi_isr, /* IIC0 TXI (Transmit data empty) */ + [37] = iic_master_tei_isr, /* IIC0 TEI (Transmit end) */ + [38] = iic_master_eri_isr, /* IIC0 ERI (Transfer error) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SCI2_RXI), /* SCI2 RXI (Received data full) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TXI), /* SCI2 TXI (Transmit data empty) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SCI2_TEI), /* SCI2 TEI (Transmit end) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI2_ERI), /* SCI2 ERI (Receive error) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SCI8_RXI), /* SCI8 RXI (Received data full) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TXI), /* SCI8 TXI (Transmit data empty) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI8_TEI), /* SCI8 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI8_ERI), /* SCI8 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_AGT1_INT), /* AGT1 INT (AGT interrupt) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ + [30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ + [31] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [35] = BSP_PRV_IELS_ENUM(EVENT_IIC0_RXI), /* IIC0 RXI (Receive data full) */ + [36] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TXI), /* IIC0 TXI (Transmit data empty) */ + [37] = BSP_PRV_IELS_ENUM(EVENT_IIC0_TEI), /* IIC0 TEI (Transmit end) */ + [38] = BSP_PRV_IELS_ENUM(EVENT_IIC0_ERI), /* IIC0 ERI (Transfer error) */ +}; +#endif diff --git a/ports/renesas-ra/boards/RA6M1_EK/ra_gen/vector_data.h b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/vector_data.h new file mode 100644 index 000000000..b812cff2e --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/ra_gen/vector_data.h @@ -0,0 +1,119 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (39) +#endif +/* ISR prototypes */ +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); +void agt_int_isr(void); +void r_icu_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI2_RXI ((IRQn_Type)4) /* SCI2 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI2_TXI ((IRQn_Type)5) /* SCI2 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI2_TEI ((IRQn_Type)6) /* SCI2 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI2_ERI ((IRQn_Type)7) /* SCI2 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI8_RXI ((IRQn_Type)8) /* SCI8 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI8_TXI ((IRQn_Type)9) /* SCI8 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI8_TEI ((IRQn_Type)10) /* SCI8 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI8_ERI ((IRQn_Type)11) /* SCI8 ERI (Receive error) */ +#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_AGT1_INT ((IRQn_Type)16) /* AGT1 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)17) /* ICU IRQ0 (External pin interrupt 0) */ +#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)18) /* ICU IRQ1 (External pin interrupt 1) */ +#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)19) /* ICU IRQ2 (External pin interrupt 2) */ +#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)20) /* ICU IRQ3 (External pin interrupt 3) */ +#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)21) /* ICU IRQ4 (External pin interrupt 4) */ +#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)22) /* ICU IRQ5 (External pin interrupt 5) */ +#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)23) /* ICU IRQ6 (External pin interrupt 6) */ +#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)24) /* ICU IRQ7 (External pin interrupt 7) */ +#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)25) /* ICU IRQ8 (External pin interrupt 8) */ +#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)26) /* ICU IRQ9 (External pin interrupt 9) */ +#define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)27) /* ICU IRQ10 (External pin interrupt 10) */ +#define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)28) /* ICU IRQ11 (External pin interrupt 11) */ +#define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)29) /* ICU IRQ12 (External pin interrupt 12) */ +#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)30) /* ICU IRQ13 (External pin interrupt 13) */ +#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)31) /* SPI0 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)32) /* SPI0 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)33) /* SPI0 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)34) /* SPI0 ERI (Error) */ +#define VECTOR_NUMBER_IIC0_RXI ((IRQn_Type)35) /* IIC0 RXI (Receive data full) */ +#define VECTOR_NUMBER_IIC0_TXI ((IRQn_Type)36) /* IIC0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_IIC0_TEI ((IRQn_Type)37) /* IIC0 TEI (Transmit end) */ +#define VECTOR_NUMBER_IIC0_ERI ((IRQn_Type)38) /* IIC0 ERI (Transfer error) */ +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ + SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ + SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ + SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ + SCI2_RXI_IRQn = 4, /* SCI2 RXI (Received data full) */ + SCI2_TXI_IRQn = 5, /* SCI2 TXI (Transmit data empty) */ + SCI2_TEI_IRQn = 6, /* SCI2 TEI (Transmit end) */ + SCI2_ERI_IRQn = 7, /* SCI2 ERI (Receive error) */ + SCI8_RXI_IRQn = 8, /* SCI8 RXI (Received data full) */ + SCI8_TXI_IRQn = 9, /* SCI8 TXI (Transmit data empty) */ + SCI8_TEI_IRQn = 10, /* SCI8 TEI (Transmit end) */ + SCI8_ERI_IRQn = 11, /* SCI8 ERI (Receive error) */ + RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ + RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ + RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ + AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ + AGT1_INT_IRQn = 16, /* AGT1 INT (AGT interrupt) */ + ICU_IRQ0_IRQn = 17, /* ICU IRQ0 (External pin interrupt 0) */ + ICU_IRQ1_IRQn = 18, /* ICU IRQ1 (External pin interrupt 1) */ + ICU_IRQ2_IRQn = 19, /* ICU IRQ2 (External pin interrupt 2) */ + ICU_IRQ3_IRQn = 20, /* ICU IRQ3 (External pin interrupt 3) */ + ICU_IRQ4_IRQn = 21, /* ICU IRQ4 (External pin interrupt 4) */ + ICU_IRQ5_IRQn = 22, /* ICU IRQ5 (External pin interrupt 5) */ + ICU_IRQ6_IRQn = 23, /* ICU IRQ6 (External pin interrupt 6) */ + ICU_IRQ7_IRQn = 24, /* ICU IRQ7 (External pin interrupt 7) */ + ICU_IRQ8_IRQn = 25, /* ICU IRQ8 (External pin interrupt 8) */ + ICU_IRQ9_IRQn = 26, /* ICU IRQ9 (External pin interrupt 9) */ + ICU_IRQ10_IRQn = 27, /* ICU IRQ10 (External pin interrupt 10) */ + ICU_IRQ11_IRQn = 28, /* ICU IRQ11 (External pin interrupt 11) */ + ICU_IRQ12_IRQn = 29, /* ICU IRQ12 (External pin interrupt 12) */ + ICU_IRQ13_IRQn = 30, /* ICU IRQ13 (External pin interrupt 13) */ + SPI0_RXI_IRQn = 31, /* SPI0 RXI (Receive buffer full) */ + SPI0_TXI_IRQn = 32, /* SPI0 TXI (Transmit buffer empty) */ + SPI0_TEI_IRQn = 33, /* SPI0 TEI (Transmission complete event) */ + SPI0_ERI_IRQn = 34, /* SPI0 ERI (Error) */ + IIC0_RXI_IRQn = 35, /* IIC0 RXI (Receive data full) */ + IIC0_TXI_IRQn = 36, /* IIC0 TXI (Transmit data empty) */ + IIC0_TEI_IRQn = 37, /* IIC0 TEI (Transmit end) */ + IIC0_ERI_IRQn = 38, /* IIC0 ERI (Transfer error) */ +} IRQn_Type; +#endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/RA6M1_EK/src/hal_entry.c b/ports/renesas-ra/boards/RA6M1_EK/src/hal_entry.c new file mode 100644 index 000000000..c922cfd17 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M1_EK/src/hal_entry.c @@ -0,0 +1,58 @@ +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); +FSP_CPP_FOOTER + +void ra_main(uint32_t reset_mode); + +/*******************************************************************************************************************//** + * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function + * is called by main() when no RTOS is used. + **********************************************************************************************************************/ +void hal_entry(void) { + /* TODO: add your own code here */ + + ra_main(1); + + #if BSP_TZ_SECURE_BUILD + /* Enter non-secure code */ + R_BSP_NonSecureEnter(); + #endif +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { + #if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ + #endif + } + + if (BSP_WARM_START_POST_C == event) { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + } +} + +#if BSP_TZ_SECURE_BUILD + +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable(); + +/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */ +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() { + +} +#endif diff --git a/ports/renesas-ra/boards/RA6M2_EK/board.json b/ports/renesas-ra/boards/RA6M2_EK/board.json new file mode 100644 index 000000000..63547d880 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/board.json @@ -0,0 +1,25 @@ +{ + "deploy": [ + "../deploy.md" + ], + "docs": "", + "features": [ + "UART", + "SPI", + "I2C", + "ADC" + ], + "id": "EK-RA6M2", + "images": [ + "ek_ra6m2_board.jpg", + "ek_ra6m2_j1_pins.jpg", + "ek_ra6m2_j2_pins.jpg", + "ek_ra6m2_j3_pins.jpg", + "ek_ra6m2_j4_pins.jpg" + ], + "mcu": "RA6M2", + "product": "EK-RA6M2", + "thumbnail": "", + "url": "https://www.renesas.com/products/microcontrollers-microprocessors/ra-cortex-m-mcus/ek-ra6m2-evaluation-kit-ra6m2-mcu-group", + "vendor": "Renesas Electronics" +} diff --git a/ports/renesas-ra/boards/RA6M2_EK/mpconfigboard.h b/ports/renesas-ra/boards/RA6M2_EK/mpconfigboard.h new file mode 100644 index 000000000..2d2dc326d --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/mpconfigboard.h @@ -0,0 +1,88 @@ +// MCU config +#define MICROPY_HW_BOARD_NAME "RA6M2_EK" +#define MICROPY_HW_MCU_NAME "RA6M2" +#define MICROPY_HW_MCU_SYSCLK 120000000 +#define MICROPY_HW_MCU_PCLK 60000000 + +// module config +#define MICROPY_EMIT_THUMB (1) +#define MICROPY_EMIT_INLINE_THUMB (1) +#define MICROPY_PY_BUILTINS_COMPLEX (1) +#define MICROPY_PY_GENERATOR_PEND_THROW (1) +#define MICROPY_PY_MATH (1) +#define MICROPY_PY_UHEAPQ (1) +#define MICROPY_PY_UTIMEQ (1) +#define MICROPY_PY_THREAD (0) // disable ARM_THUMB_FP using vldr due to RA has single float only + +// peripheral config +#define MICROPY_HW_ENABLE_RTC (1) +#define MICROPY_HW_RTC_SOURCE (0) // 0: subclock +#define MICROPY_HW_ENABLE_ADC (1) +#define MICROPY_HW_HAS_FLASH (1) +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) + +// board config + +// UART +#define MICROPY_HW_UART0_TX (pin_P411) // REPL +#define MICROPY_HW_UART0_RX (pin_P410) // REPL +// #define MICROPY_HW_UART0_CTS (pin_P413) // NC +// #define MICROPY_HW_UART1_TX (pin_P709) // Disable (read not work properly) +// #define MICROPY_HW_UART1_RX (pin_P708) // Disable (read not work properly) +// #define MICROPY_HW_UART1_CTS (pin_P711) // Disable (read not work properly) +// #define MICROPY_HW_UART2_TX (pin_P302) // Disable +// #define MICROPY_HW_UART2_RX (pin_P301) // Disable +// #define MICROPY_HW_UART2_CTS (pin_P203) // NC +// #define MICROPY_HW_UART3_TX (pin_P310) // Disable +// #define MICROPY_HW_UART3_RX (pin_P309) // Disable +// #define MICROPY_HW_UART3_CTS (pin_P312) // Disable +// #define MICROPY_HW_UART4_TX (pin_P512) // Disable (Conflict with I2C2) +// #define MICROPY_HW_UART4_RX (pin_P511) // Disable (Conflict with I2C2) +// #define MICROPY_HW_UART4_CTS (pin_P401) // Disable (Conflict with PMOD B) +// #define MICROPY_HW_UART5_TX (pin_P501) // Disable +// #define MICROPY_HW_UART5_RX (pin_P502) // Disable +// #define MICROPY_HW_UART5_CTS (pin_P504) // Disable +// #define MICROPY_HW_UART6_TX (pin_P506) // Disable (read not work properly) +// #define MICROPY_HW_UART6_RX (pin_P505) // Disable (read not work properly) +// #define MICROPY_HW_UART6_CTS (pin_P503) // Disable (read not work properly) +#define MICROPY_HW_UART7_TX (pin_P401) // PMOD B +#define MICROPY_HW_UART7_RX (pin_P402) // PMOD B +#define MICROPY_HW_UART7_CTS (pin_P403) // PMOD B +// #define MICROPY_HW_UART8_TX (pin_P105) // Disable (conflict with USER SW1) +// #define MICROPY_HW_UART8_RX (pin_P104) +#define MICROPY_HW_UART9_TX (pin_P602) +#define MICROPY_HW_UART9_RX (pin_P601) +#define MICROPY_HW_UART9_CTS (pin_P603) +#define MICROPY_HW_UART_REPL HW_UART_0 +#define MICROPY_HW_UART_REPL_BAUD 115200 + +// I2C +// #define MICROPY_HW_I2C0_SCL (pin_P400) // Disable (Conflict with PMOD B) +// #define MICROPY_HW_I2C0_SDA (pin_P401) // Disable (Conflict with PMOD B) +// #define MICROPY_HW_I2C1_SCL (pin_P100) // Disable (Conflict with SPI & SDcard) +// #define MICROPY_HW_I2C1_SDA (pin_P101) // Disable (Conflict with SPI & SDcard) +#define MICROPY_HW_I2C2_SCL (pin_P512) +#define MICROPY_HW_I2C2_SDA (pin_P511) + +// SPI +#define MICROPY_HW_SPI0_SSL (pin_P103) // PMOD A +#define MICROPY_HW_SPI0_RSPCK (pin_P102) +#define MICROPY_HW_SPI0_MISO (pin_P100) +#define MICROPY_HW_SPI0_MOSI (pin_P101) +#define MICROPY_HW_SPI1_SSL (pin_P703) // Pin Header +#define MICROPY_HW_SPI1_RSPCK (pin_P702) +#define MICROPY_HW_SPI1_MISO (pin_P700) +#define MICROPY_HW_SPI1_MOSI (pin_P701) + +// Switch +#define MICROPY_HW_HAS_SWITCH (1) +#define MICROPY_HW_USRSW_PIN (pin_P105) +#define MICROPY_HW_USRSW_PULL (GPIO_NOPULL) +#define MICROPY_HW_USRSW_EXTI_MODE (GPIO_MODE_IT_FALLING) +#define MICROPY_HW_USRSW_PRESSED (0) + +// LEDs +#define MICROPY_HW_LED1 (pin_P106) +#define MICROPY_HW_LED_ON(pin) mp_hal_pin_high(pin) +#define MICROPY_HW_LED_OFF(pin) mp_hal_pin_low(pin) +#define MICROPY_HW_LED_TOGGLE(pin) mp_hal_pin_toggle(pin) diff --git a/ports/renesas-ra/boards/RA6M2_EK/mpconfigboard.mk b/ports/renesas-ra/boards/RA6M2_EK/mpconfigboard.mk new file mode 100644 index 000000000..59d48c0e6 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/mpconfigboard.mk @@ -0,0 +1,6 @@ +CMSIS_MCU = RA6M2 +MCU_SERIES = m4 +LD_FILES = boards/RA6M2_EK/ra6m2_ek.ld + +# MicroPython settings +MICROPY_VFS_FAT = 1 diff --git a/ports/renesas-ra/boards/RA6M2_EK/pins.csv b/ports/renesas-ra/boards/RA6M2_EK/pins.csv new file mode 100644 index 000000000..5986d7212 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/pins.csv @@ -0,0 +1,118 @@ +P000,P000 +P001,P001 +P002,P002 +P003,P003 +P004,P004 +P005,P005 +P006,P006 +P007,P007 +P008,P008 +P009,P009 +P014,P014 +P015,P015 +P100,P100 +P101,P101 +P102,P102 +P103,P103 +P104,P104 +P105,P105 +P106,P106 +P107,P107 +P108,P108 +P109,P109 +P110,P110 +P111,P111 +P112,P112 +P113,P113 +P114,P114 +P115,P115 +P200,P200 +P201,P201 +P202,P202 +P203,P203 +P204,P204 +P205,P205 +P206,P206 +P207,P207 +P208,P208 +P209,P209 +P210,P210 +P211,P211 +P212,P212 +P213,P213 +P214,P214 +P300,P300 +P301,P301 +P302,P302 +P303,P303 +P304,P304 +P305,P305 +P306,P306 +P307,P307 +P308,P308 +P309,P309 +P310,P310 +P311,P311 +P312,P312 +P313,P313 +P400,P400 +P401,P401 +P402,P402 +P403,P403 +P404,P404 +P405,P405 +P406,P406 +P407,P407 +P408,P408 +P409,P409 +P410,P410 +P411,P411 +P412,P412 +P413,P413 +P414,P414 +P415,P415 +P500,P500 +P501,P501 +P502,P502 +P503,P503 +P504,P504 +P505,P505 +P506,P506 +P508,P508 +P511,P511 +P512,P512 +P600,P600 +P601,P601 +P602,P602 +P603,P603 +P604,P604 +P605,P605 +P608,P608 +P609,P609 +P610,P610 +P611,P611 +P612,P612 +P613,P613 +P614,P614 +P700,P700 +P701,P701 +P702,P702 +P703,P703 +P704,P704 +P705,P705 +P708,P708 +P709,P709 +P710,P710 +P711,P711 +P712,P712 +P713,P713 +P800,P800 +P801,P801 +P808,P808 +P809,P809 +P914,P914 +P915,P915 +SW1,P105 +LED1,P106 +USBDP,P914 +USBDM,P915 diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra6m2_ek.ld b/ports/renesas-ra/boards/RA6M2_EK/ra6m2_ek.ld new file mode 100644 index 000000000..4ad1b1ac1 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra6m2_ek.ld @@ -0,0 +1,298 @@ +/* + Linker File for RA6M2 MCU +*/ + +/* Linker script to configure memory regions. */ +MEMORY +{ + FLASH (rx) : ORIGIN = 0x00000000, LENGTH = 0x00100000 /* 1MB */ + RAM (rwx) : ORIGIN = 0x1FFE0000, LENGTH = 0x00060000 /* 384KB */ + DATA_FLASH (rx) : ORIGIN = 0x40100000, LENGTH = 0x00008000 /* 32KB */ + ID_CODE (rx) : ORIGIN = 0x0100A150, LENGTH = 0x00000010 /* 32bytes */ +} + +/* Library configurations */ +/*GROUP(libgcc.a libc.a libm.a libnosys.a) */ + +/* Linker script to place sections and symbol values. Should be used together + * with other linker script that defines memory regions FLASH and RAM. + * It references following symbols, which must be defined in code: + * Reset_Handler : Entry of reset handler + * + * It defines following symbols, which code can use without definition: + * __exidx_start + * __exidx_end + * __copy_table_start__ + * __copy_table_end__ + * __zero_table_start__ + * __zero_table_end__ + * __etext + * __data_start__ + * __preinit_array_start + * __preinit_array_end + * __init_array_start + * __init_array_end + * __fini_array_start + * __fini_array_end + * __data_end__ + * __bss_start__ + * __bss_end__ + * __end__ + * end + * __HeapLimit + * __StackLimit + * __StackTop + * __stack + * __Vectors_End + * __Vectors_Size + */ +ENTRY(Reset_Handler) + +SECTIONS +{ + .text : + { + _stext = .; + __ROM_Start = .; + + /* Even though the vector table is not 256 entries (1KB) long, we still allocate that much + * space because ROM registers are at address 0x400 and there is very little space + * in between. */ + KEEP(*(.fixed_vectors*)) + KEEP(*(.application_vectors*)) + __Vectors_End = .; + __end__ = .; + + /* ROM Registers start at address 0x00000400 */ + . = __ROM_Start + 0x400; + KEEP(*(.rom_registers*)) + + /* Reserving 0x100 bytes of space for ROM registers. */ + . = __ROM_Start + 0x500; + + *(.text*) + + KEEP(*(.version)) + KEEP(*(.init)) + KEEP(*(.fini)) + + /* .ctors */ + *crtbegin.o(.ctors) + *crtbegin?.o(.ctors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors) + *(SORT(.ctors.*)) + *(.ctors) + + /* .dtors */ + *crtbegin.o(.dtors) + *crtbegin?.o(.dtors) + *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors) + *(SORT(.dtors.*)) + *(.dtors) + + *(.rodata*) + __usb_dev_descriptor_start_fs = .; + KEEP(*(.usb_device_desc_fs*)) + __usb_cfg_descriptor_start_fs = .; + KEEP(*(.usb_config_desc_fs*)) + __usb_interface_descriptor_start_fs = .; + KEEP(*(.usb_interface_desc_fs*)) + __usb_descriptor_end_fs = .; + __usb_dev_descriptor_start_hs = .; + KEEP(*(.usb_device_desc_hs*)) + __usb_cfg_descriptor_start_hs = .; + KEEP(*(.usb_config_desc_hs*)) + __usb_interface_descriptor_start_hs = .; + KEEP(*(.usb_interface_desc_hs*)) + __usb_descriptor_end_hs = .; + + KEEP(*(.eh_frame*)) + + __ROM_End = .; + _etext = .; + } > FLASH = 0xFF + + __Vectors_Size = __Vectors_End - __Vectors; + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } > FLASH + __exidx_end = .; + + /* To copy multiple ROM to RAM sections, + * uncomment .copy.table section and, + * define __STARTUP_COPY_MULTIPLE in startup_ARMCMx.S */ + /* + .copy.table : + { + . = ALIGN(4); + __copy_table_start__ = .; + LONG (__etext) + LONG (__data_start__) + LONG (__data_end__ - __data_start__) + LONG (__etext2) + LONG (__data2_start__) + LONG (__data2_end__ - __data2_start__) + __copy_table_end__ = .; + } > FLASH + */ + + /* To clear multiple BSS sections, + * uncomment .zero.table section and, + * define __STARTUP_CLEAR_BSS_MULTIPLE in startup_ARMCMx.S */ + /* + .zero.table : + { + . = ALIGN(4); + __zero_table_start__ = .; + LONG (__bss_start__) + LONG (__bss_end__ - __bss_start__) + LONG (__bss2_start__) + LONG (__bss2_end__ - __bss2_start__) + __zero_table_end__ = .; + } > FLASH + */ + + __etext = .; + + /* If DTC is used, put the DTC vector table at the start of SRAM. + This avoids memory holes due to 1K alignment required by it. */ + .fsp_dtc_vector_table (NOLOAD) : + { + . = ORIGIN(RAM); + *(.fsp_dtc_vector_table) + } > RAM + + /* Initialized data section. */ + .data : + { + _sidata = .; + _sdata = .; + __data_start__ = .; + *(vtable) + *(.data.*) + + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + + + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + + KEEP(*(.jcr*)) + . = ALIGN(4); + + __Code_In_RAM_Start = .; + + KEEP(*(.code_in_ram*)) + __Code_In_RAM_End = .; + + /* All data end */ + __data_end__ = .; + _edata = .; + + } > RAM AT > FLASH + + + + .noinit (NOLOAD): + { + . = ALIGN(4); + __noinit_start = .; + KEEP(*(.noinit*)) + __noinit_end = .; + } > RAM + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = .; + *(.bss*) + *(COMMON) + . = ALIGN(4); + __bss_end__ = .; + _ebss = .; + } > RAM + + .heap (NOLOAD): + { + . = ALIGN(8); + __HeapBase = .; + __end__ = .; + end = __end__; + KEEP(*(.heap*)) + __HeapLimit = .; + } > RAM + + /* Stacks are stored in this section. */ + .stack_dummy (NOLOAD): + { + . = ALIGN(8); + _sstack = .; + __StackLimit = .; + /* Main stack */ + KEEP(*(.stack)) + __StackTop = .; + /* Thread stacks */ + KEEP(*(.stack*)) + __StackTopAll = .; + _estack = .; + } > RAM + + PROVIDE(__stack = __StackTopAll); + + /* This symbol represents the end of user allocated RAM. The RAM after this symbol can be used + at run time for things such as ThreadX memory pool allocations. */ + __RAM_segment_used_end__ = ALIGN(__StackTopAll , 4); + + /* Data flash. */ + .data_flash : + { + __Data_Flash_Start = .; + KEEP(*(.data_flash*)) + __Data_Flash_End = .; + } > DATA_FLASH + + .id_code : + { + __ID_Code_Start = .; + KEEP(*(.id_code*)) + __ID_Code_End = .; + } > ID_CODE +} +/* produce a link error if there is not this amount of RAM for these sections */ +/* _minimum_stack_size = 2K; */ +/* _minimum_heap_size = 16K; */ + +/* Define tho top end of the stack. The stack is full descending so begins just + above last byte of RAM. Note that EABI requires the stack to be 8-byte + aligned for a call. */ +_estack = ORIGIN(RAM) + LENGTH(RAM); + +/* RAM extents for the garbage collector */ +_ram_start = ORIGIN(RAM); +_ram_end = ORIGIN(RAM) + LENGTH(RAM); +_heap_start = __HeapBase; /* heap starts just after statically allocated memory */ +_heap_end = __HeapLimit; /* tunable */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra6m2_ek_conf.h b/ports/renesas-ra/boards/RA6M2_EK/ra6m2_ek_conf.h new file mode 100644 index 000000000..e34443e06 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra6m2_ek_conf.h @@ -0,0 +1,30 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA6M2_EK_CONF_H +#define RA6M2_EK_CONF_H + +#define DEBUG_CH 0 + +#endif /* RA6M2_EK_CONF_H */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h new file mode 100644 index 000000000..ecffc5a44 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/board_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BOARD_CFG_H_ +#define BOARD_CFG_H_ +#include "../../../ra/board/ra6m2_ek/board.h" +#endif /* BOARD_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h new file mode 100644 index 000000000..7255cdd17 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_cfg.h @@ -0,0 +1,49 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CFG_H_ +#define BSP_CFG_H_ +#include "bsp_clock_cfg.h" +#include "bsp_mcu_family_cfg.h" +#include "board_cfg.h" +#define RA_NOT_DEFINED 0 +#ifndef BSP_CFG_RTOS +#if (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (2) +#elif (RA_NOT_DEFINED) != (RA_NOT_DEFINED) +#define BSP_CFG_RTOS (1) +#else +#define BSP_CFG_RTOS (0) +#endif +#endif +#undef RA_NOT_DEFINED +#define BSP_CFG_MCU_VCC_MV (3300) +#define BSP_CFG_STACK_MAIN_BYTES (0x4000) +#define BSP_CFG_HEAP_BYTES (0x4d000) +#define BSP_CFG_PARAM_CHECKING_ENABLE (0) +#define BSP_CFG_ASSERT (0) +#define BSP_CFG_ERROR_LOG (0) + +#define BSP_CFG_PFS_PROTECT ((1)) + +#define BSP_CFG_C_RUNTIME_INIT ((1)) + +#define BSP_CFG_SOFT_RESET_SUPPORTED ((0)) + +#ifndef BSP_CLOCK_CFG_MAIN_OSC_POPULATED +#define BSP_CLOCK_CFG_MAIN_OSC_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_WAIT +#define BSP_CLOCK_CFG_MAIN_OSC_WAIT (9) +#endif +#ifndef BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE +#define BSP_CLOCK_CFG_MAIN_OSC_CLOCK_SOURCE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_DRIVE +#define BSP_CLOCK_CFG_SUBCLOCK_DRIVE (0) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_POPULATED +#define BSP_CLOCK_CFG_SUBCLOCK_POPULATED (1) +#endif +#ifndef BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS +#define BSP_CLOCK_CFG_SUBCLOCK_STABILIZATION_MS 1000 +#endif +#endif /* BSP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h new file mode 100644 index 000000000..bd6a901c3 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_CFG_H_ +#define BSP_MCU_DEVICE_CFG_H_ +#define BSP_CFG_MCU_PART_SERIES (6) +#endif /* BSP_MCU_DEVICE_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h new file mode 100644 index 000000000..6097e9d7d --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_device_pn_cfg.h @@ -0,0 +1,10 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_DEVICE_PN_CFG_H_ +#define BSP_MCU_R7FA6M2AF3CFB +#define BSP_ROM_SIZE_BYTES (1048576) +#define BSP_RAM_SIZE_BYTES (393216) +#define BSP_DATA_FLASH_SIZE_BYTES (32768) +#define BSP_PACKAGE_LQFP +#define BSP_PACKAGE_PINS (144) +#endif /* BSP_MCU_DEVICE_PN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h new file mode 100644 index 000000000..51f399e3c --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/bsp/bsp_mcu_family_cfg.h @@ -0,0 +1,74 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_MCU_FAMILY_CFG_H_ +#define BSP_MCU_FAMILY_CFG_H_ +#include "bsp_mcu_device_pn_cfg.h" +#include "bsp_mcu_device_cfg.h" +#include "../../../ra/fsp/src/bsp/mcu/ra6m2/bsp_mcu_info.h" +#include "bsp_clock_cfg.h" +#define BSP_MCU_GROUP_RA6M2 (1) +#define BSP_LOCO_HZ (32768) +#define BSP_MOCO_HZ (8000000) +#define BSP_SUB_CLOCK_HZ (32768) +#if BSP_CFG_HOCO_FREQUENCY == 0 +#define BSP_HOCO_HZ (16000000) +#elif BSP_CFG_HOCO_FREQUENCY == 1 +#define BSP_HOCO_HZ (18000000) +#elif BSP_CFG_HOCO_FREQUENCY == 2 +#define BSP_HOCO_HZ (20000000) +#else +#error "Invalid HOCO frequency chosen (BSP_CFG_HOCO_FREQUENCY) in bsp_clock_cfg.h" +#endif + +#define BSP_CFG_FLL_ENABLE (0) + +#define BSP_CORTEX_VECTOR_TABLE_ENTRIES (16U) +#define BSP_VECTOR_TABLE_MAX_ENTRIES (112U) +#define BSP_MCU_VBATT_SUPPORT (1) + +#define OFS_SEQ1 0xA001A001 | (1 << 1) | (3 << 2) +#define OFS_SEQ2 (15 << 4) | (3 << 8) | (3 << 10) +#define OFS_SEQ3 (1 << 12) | (1 << 14) | (1 << 17) +#define OFS_SEQ4 (3 << 18) | (15 << 20) | (3 << 24) | (3 << 26) +#define OFS_SEQ5 (1 << 28) | (1 << 30) +#define BSP_CFG_ROM_REG_OFS0 (OFS_SEQ1 | OFS_SEQ2 | OFS_SEQ3 | OFS_SEQ4 | OFS_SEQ5) +#define BSP_CFG_ROM_REG_OFS1 (0xFFFFFEF8 | (1 << 2) | (3) | (1 << 8)) +#define BSP_CFG_ROM_REG_MPU_PC0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC0_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC0_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_PC1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_PC1_START (0xFFFFFFFC) +#define BSP_CFG_ROM_REG_MPU_PC1_END (0xFFFFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION0_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION0_START (0x00FFFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION0_END (0x00FFFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION1_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION1_START (0x200FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION1_END (0x200FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION2_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION2_START (0x407FFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION2_END (0x407FFFFF) +#define BSP_CFG_ROM_REG_MPU_REGION3_ENABLE (1) +#define BSP_CFG_ROM_REG_MPU_REGION3_START (0x400DFFFC) +#define BSP_CFG_ROM_REG_MPU_REGION3_END (0x400DFFFF) + +/* Used to create IELS values for the interrupt initialization table g_interrupt_event_link_select. */ +#define BSP_PRV_IELS_ENUM(vector) (ELC_##vector) + +/* + ID Code + Note: To permanently lock and disable the debug interface define the BSP_ID_CODE_PERMANENTLY_LOCKED in the compiler settings. + WARNING: This will disable debug access to the part and cannot be reversed by a debug probe. + */ +#if defined(BSP_ID_CODE_PERMANENTLY_LOCKED) +#define BSP_CFG_ID_CODE_LONG_1 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_2 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_3 (0x00000000) +#define BSP_CFG_ID_CODE_LONG_4 (0x00000000) +#else +/* ID CODE: FFFFFFFFFFFFFFFFFFFFFFFFFFFFFFFF */ +#define BSP_CFG_ID_CODE_LONG_1 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_2 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_3 (0xFFFFFFFF) +#define BSP_CFG_ID_CODE_LONG_4 (0xffFFFFFF) +#endif +#endif /* BSP_MCU_FAMILY_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_adc_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_adc_cfg.h new file mode 100644 index 000000000..9c59889ca --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_adc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ADC_CFG_H_ +#define R_ADC_CFG_H_ +#define ADC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ADC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_agt_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_agt_cfg.h new file mode 100644 index 000000000..d3ab55923 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_agt_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_AGT_CFG_H_ +#define R_AGT_CFG_H_ +#define AGT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define AGT_CFG_OUTPUT_SUPPORT_ENABLE (0) +#define AGT_CFG_INPUT_SUPPORT_ENABLE (0) +#endif /* R_AGT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h new file mode 100644 index 000000000..21405f967 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_dtc_cfg.h @@ -0,0 +1,6 @@ +/* generated configuration header file - do not edit */ +#ifndef R_DTC_CFG_H_ +#define R_DTC_CFG_H_ +#define DTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define DTC_CFG_VECTOR_TABLE_SECTION_NAME ".fsp_dtc_vector_table" +#endif /* R_DTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_flash_hp_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_flash_hp_cfg.h new file mode 100644 index 000000000..48c9dec4e --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_flash_hp_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_FLASH_HP_CFG_H_ +#define R_FLASH_HP_CFG_H_ +#define FLASH_HP_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define FLASH_HP_CFG_CODE_FLASH_PROGRAMMING_ENABLE (1) +#define FLASH_HP_CFG_DATA_FLASH_PROGRAMMING_ENABLE (0) +#endif /* R_FLASH_HP_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_icu_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_icu_cfg.h new file mode 100644 index 000000000..5e77b6980 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_icu_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_ICU_CFG_H_ +#define R_ICU_CFG_H_ +#define ICU_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_ICU_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h new file mode 100644 index 000000000..595ea938d --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_iic_master_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IIC_MASTER_CFG_H_ +#define R_IIC_MASTER_CFG_H_ +#define IIC_MASTER_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define IIC_MASTER_CFG_DTC_ENABLE (0) +#define IIC_MASTER_CFG_ADDR_MODE_10_BIT_ENABLE (0) +#endif /* R_IIC_MASTER_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h new file mode 100644 index 000000000..6b4353d23 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_ioport_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_IOPORT_CFG_H_ +#define R_IOPORT_CFG_H_ +#define IOPORT_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_IOPORT_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h new file mode 100644 index 000000000..5f4d5c4a7 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_lpm_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_LPM_CFG_H_ +#define R_LPM_CFG_H_ +#define LPM_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_LPM_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h new file mode 100644 index 000000000..484b7ed04 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_rtc_cfg.h @@ -0,0 +1,5 @@ +/* generated configuration header file - do not edit */ +#ifndef R_RTC_CFG_H_ +#define R_RTC_CFG_H_ +#define RTC_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#endif /* R_RTC_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h new file mode 100644 index 000000000..c70c0be34 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_sci_uart_cfg.h @@ -0,0 +1,8 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SCI_UART_CFG_H_ +#define R_SCI_UART_CFG_H_ +#define SCI_UART_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SCI_UART_CFG_FIFO_SUPPORT (0) +#define SCI_UART_CFG_DTC_SUPPORTED (0) +#define SCI_UART_CFG_FLOW_CONTROL_SUPPORT (0) +#endif /* R_SCI_UART_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_spi_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_spi_cfg.h new file mode 100644 index 000000000..861fe1219 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_cfg/fsp_cfg/r_spi_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef R_SPI_CFG_H_ +#define R_SPI_CFG_H_ +#define SPI_CFG_PARAM_CHECKING_ENABLE (BSP_CFG_PARAM_CHECKING_ENABLE) +#define SPI_DTC_SUPPORT_ENABLE (1) +#define SPI_TRANSMIT_FROM_RXI_ISR (0) +#endif /* R_SPI_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/RA6M2-EK.csv b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/RA6M2-EK.csv new file mode 100644 index 000000000..ff82aa9ce --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/RA6M2-EK.csv @@ -0,0 +1,701 @@ +"Name","Pin","Function","Drive Capacity","IRQ","Mode","Output type","Pull up","Port Capabilities" +"AVCC0","127","ADC_AVCC0","","","","","","" +"AVSS0","128","ADC_AVSS0","","","","","","" +"P000","140","","","","Disabled","","","ADC0: AN00 +CMP0: IVCMP2 +IRQ0: IRQ06" +"P001","139","","","","Disabled","","","ADC0: AN01 +CMP0: IVCMP2 +IRQ0: IRQ07" +"P002","138","","","","Disabled","","","ADC0: AN02 +CMP0: IVCMP2 +IRQ0: IRQ08" +"P003","137","","","","Disabled","","","ADC0: AN07" +"P004","136","ADC1_AN00","","","Analog mode","","","ADC1: AN00 +CMP0: IVCMP2 +IRQ0: IRQ09" +"P005","135","","","","Disabled","","","ADC1: AN01 +CMP0: IVCMP2 +IRQ0: IRQ10" +"P006","134","","","","Disabled","","","ADC1: AN02 +CMP0: IVCMP2 +IRQ0: IRQ11" +"P007","133","","","","Disabled","","","ADC1: AN07" +"P008","132","","","","Disabled","","","ADC0: AN03 +IRQ0: IRQ12" +"P009","131","","","","Disabled","","","ADC0: AN04 +IRQ0: IRQ13" +"P014","124","","","","Disabled","","","ADC0: AN05 +ADC1: AN05 +CMP0: IVREF3 +DAC120: DA" +"P015","123","","","","Disabled","","","ADC0: AN06 +ADC1: AN06 +CMP0: IVCMP1 +DAC121: DA +IRQ0: IRQ13" +"P100","108","SPI0_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +BUS0: D0_DQ0 +GPT5: GTIOCB +IIC1: SCL +IRQ0: IRQ02 +KINT0: KRM0 +POEG0: GTETRG +SCI0: RXD_MISO +SCI0: SCL +SCI1: SCK +SPI0: MISO" +"P101","107","SPI0_MOSI","Low","None","Peripheral mode","CMOS","None","AGT0: AGTEE +BUS0: D1_DQ1 +GPT5: GTIOCA +IIC1: SDA +IRQ0: IRQ01 +KINT0: KRM1 +POEG1: GTETRG +SCI0: SDA +SCI0: TXD_MOSI +SCI1: CTS_RTS_SS +SPI0: MOSI" +"P102","106","SPI0_RSPCK","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +AGT0: AGTO +BUS0: D2_DQ2 +CAN0: CRX +GPT2: GTIOCB +KINT0: KRM2 +OPS0: GTOWLO +SCI0: SCK +SPI0: RSPCK" +"P103","105","SPI0_SSL0","Low","","Peripheral mode","CMOS","None","BUS0: D3_DQ3 +CAN0: CTX +GPT2: GTIOCA +KINT0: KRM3 +OPS0: GTOWUP +SCI0: CTS_RTS_SS +SPI0: SSL0" +"P104","104","","","","Disabled","","","BUS0: D4_DQ4 +GPT1: GTIOCB +IRQ0: IRQ01 +KINT0: KRM4 +POEG1: GTETRG +SCI8: RXD_MISO +SCI8: SCL +SPI0: SSL1" +"P105","103","GPIO","","IRQ0","Input mode","","None","BUS0: D5_DQ5 +GPT1: GTIOCA +IRQ0: IRQ00 +KINT0: KRM5 +POEG0: GTETRG +SCI8: SDA +SCI8: TXD_MOSI +SPI0: SSL2" +"P106","102","GPIO","Low","","Output mode (Initial Low)","CMOS","None","AGT0: AGTOB +BUS0: D6_DQ6 +GPT8: GTIOCB +KINT0: KRM6 +SCI8: SCK +SPI0: SSL3" +"P107","101","","","","Disabled","","","AGT0: AGTOA +BUS0: D7_DQ7 +GPT8: GTIOCA +KINT0: KRM7 +SCI8: CTS_RTS_SS" +"P108","73","DEBUG0_TMS","Low","","Peripheral mode","CMOS","None","DEBUG0: SWDIO +DEBUG0: TMS +GPT0: GTIOCB +OPS0: GTOULO +SCI9: CTS_RTS_SS +SPI1: SSL0" +"P109","74","DEBUG0_TDO","Low","","Peripheral mode","CMOS","None","CAN1: CTX +CGC0: CLKOUT +DEBUG0: SWO +DEBUG0: TDO +GPT1: GTIOCA +OPS0: GTOVUP +SCI9: SDA +SCI9: TXD_MOSI +SPI1: MOSI" +"P110","75","DEBUG0_TDI","Low","None","Peripheral mode","CMOS","None","CAN1: CRX +CMP0: VCOUT +DEBUG0: TDI +GPT1: GTIOCB +IRQ0: IRQ03 +OPS0: GTOVLO +SCI2: CTS_RTS_SS +SCI9: RXD_MISO +SCI9: SCL +SPI1: MISO" +"P111","76","","","","Disabled","","","BUS0: A05 +GPT3: GTIOCA +IRQ0: IRQ04 +SCI2: SCK +SCI9: SCK +SPI1: RSPCK" +"P112","77","","","","Disabled","","","BUS0: A04 +GPT3: GTIOCB +SCI1: SCK +SCI2: SDA +SCI2: TXD_MOSI +SPI1: SSL0 +SSI0: SSISCK" +"P113","78","","","","Disabled","","","BUS0: A03 +GPT2: GTIOCA +SCI2: RXD_MISO +SCI2: SCL +SSI0: SSIWS" +"P114","79","","","","Disabled","","","BUS0: A02 +GPT2: GTIOCB +SSI0: SSIRXD" +"P115","80","","","","Disabled","","","BUS0: A01 +GPT4: GTIOCA +SSI0: SSITXD" +"P200","57","","","","Disabled","","","IRQ0: NMI" +"P201","56","","","","Disabled","","","" +"P202","46","","","","Disabled","","","BUS0: WR1_BC1 +CAN0: CRX +ETHERC0: ERXD2 +GPT5: GTIOCB +IRQ0: IRQ03 +SCI2: SCK +SCI9: RXD_MISO +SCI9: SCL +SDHI0: DAT6 +SPI1: MISO" +"P203","45","","","","Disabled","","","BUS0: A19 +CAN0: CTX +CTSU0: TSCAP +ETHERC0: COL +GPT5: GTIOCA +IRQ0: IRQ02 +SCI2: CTS_RTS_SS +SCI9: SDA +SCI9: TXD_MOSI +SDHI0: DAT5 +SPI1: MOSI" +"P204","44","","","","Disabled","","","AGT1: AGTIO +BUS0: A18 +CAC0: CACREF +CTSU0: TS00 +ETHERC0: RX_DV +GPT4: GTIOCB +IIC0: SCL +OPS0: GTIW +SCI4: SCK +SCI9: SCK +SDHI0: DAT4 +SPI1: RSPCK +SSI0: SSISCK +USBFS0: OVRCURB" +"P205","43","CTSU0_TSCAP","Low","None","Peripheral mode","CMOS","None","AGT1: AGTO +BUS0: A16 +CGC0: CLKOUT +CTSU0: TSCAP +ETHERC0: WOL +ETHERC0: WOL +GPT4: GTIOCA +IIC1: SCL +IRQ0: IRQ01 +OPS0: GTIV +SCI4: SDA +SCI4: TXD_MOSI +SCI9: CTS_RTS_SS +SDHI0: DAT3 +SPI1: SSL0 +SSI0: SSIWS +USBFS0: OVRCURA" +"P206","42","","","","Disabled","","","BUS0: WAIT +CTSU0: TS01 +ETHERC0: LINKSTA +ETHERC0: LINKSTA +IIC1: SDA +IRQ0: IRQ00 +OPS0: GTIU +SCI4: RXD_MISO +SCI4: SCL +SDHI0: DAT2 +SPI1: SSL1 +SSI0: SSIDATA +USBFS0: VBUSEN" +"P207","41","CTSU0_TS02","Low","","Peripheral mode","CMOS","None","BUS0: A17 +CTSU0: TS02 +QSPI0: QSSL +SPI1: SSL2" +"P208","54","","","","Disabled","","","BUS0: CS4 +ETHERC0: LINKSTA +ETHERC0: LINKSTA +OPS0: GTOVLO +QSPI0: QIO3 +SDHI0: DAT0 +TRACE0: TDATA3" +"P209","53","","","","Disabled","","","BUS0: CS5 +ETHERC0: EXOUT +ETHERC0: EXOUT +OPS0: GTOVUP +QSPI0: QIO2 +SDHI0: WP +TRACE0: TDATA2" +"P210","52","","","","Disabled","","","BUS0: CS6 +ETHERC0: WOL +ETHERC0: WOL +OPS0: GTIW +QSPI0: QIO1 +SDHI0: CD +TRACE0: TDATA1" +"P211","51","","","","Disabled","","","BUS0: CS7 +ETHERC0: MDIO +ETHERC0: MDIO +OPS0: GTIV +QSPI0: QIO0 +SDHI0: CMD +TRACE0: TDATA0" +"P212","20","","","","Disabled","","","AGT1: AGTEE +CGC0: EXTAL +GPT0: GTIOCB +IRQ0: IRQ03 +POEG3: GTETRG +SCI1: RXD_MISO +SCI1: SCL" +"P213","19","","","","Disabled","","","ADC1: ADTRG +CGC0: XTAL +GPT0: GTIOCA +IRQ0: IRQ02 +POEG2: GTETRG +SCI1: SDA +SCI1: TXD_MOSI" +"P214","50","","","","Disabled","","","ETHERC0: MDC +ETHERC0: MDC +OPS0: GTIU +QSPI0: QSPCLK +SDHI0: CLK +TRACE0: TCLK" +"P300","72","DEBUG0_TCK","Low","","Peripheral mode","CMOS","None","DEBUG0: SWCLK +DEBUG0: TCK +GPT0: GTIOCA +OPS0: GTOUUP +SPI1: SSL1" +"P301","71","","","","Disabled","","","AGT0: AGTIO +BUS0: A06 +GPT4: GTIOCB +IRQ0: IRQ06 +OPS0: GTOULO +SCI2: RXD_MISO +SCI2: SCL +SCI9: CTS_RTS_SS +SPI1: SSL2" +"P302","70","","","","Disabled","","","BUS0: A07 +GPT4: GTIOCA +IRQ0: IRQ05 +OPS0: GTOUUP +SCI2: SDA +SCI2: TXD_MOSI +SPI1: SSL3" +"P303","69","","","","Disabled","","","BUS0: A08 +GPT7: GTIOCB" +"P304","66","","","","Disabled","","","BUS0: A09 +GPT7: GTIOCA +IRQ0: IRQ09 +OPS0: GTOWLO +SCI6: RXD_MISO +SCI6: SCL" +"P305","65","","","","Disabled","","","BUS0: A10 +IRQ0: IRQ08 +OPS0: GTOWUP +QSPI0: QSPCLK +SCI6: SDA +SCI6: TXD_MOSI" +"P306","64","","","","Disabled","","","BUS0: A11 +OPS0: GTOULO +QSPI0: QSSL +SCI6: SCK" +"P307","63","","","","Disabled","","","BUS0: A12 +OPS0: GTOUUP +QSPI0: QIO0 +SCI6: CTS_RTS_SS" +"P308","62","","","","Disabled","","","BUS0: A13 +QSPI0: QIO1" +"P309","61","","","","Disabled","","","BUS0: A14 +QSPI0: QIO2 +SCI3: RXD_MISO +SCI3: SCL" +"P310","60","","","","Disabled","","","AGT1: AGTEE +BUS0: A15 +QSPI0: QIO3 +SCI3: SDA +SCI3: TXD_MOSI" +"P311","59","","","","Disabled","","","AGT1: AGTOB +BUS0: CS2_RAS +SCI3: SCK" +"P312","58","","","","Disabled","","","AGT1: AGTOA +BUS0: CS3_CAS +SCI3: CTS_RTS_SS" +"P313","47","","","","Disabled","","","BUS0: A20 +ETHERC0: ERXD3 +SDHI0: DAT7" +"P400","1","GPIO","Low","None","Output mode (Initial Low)","CMOS","None","ADC1: ADTRG +AGT1: AGTIO +ETHERC0: WOL +ETHERC0: WOL +GPT6: GTIOCA +IIC0: SCL +IRQ0: IRQ00 +SCI4: SCK +SCI7: SCK +SSI: AUDIO_CLK" +"P401","2","SCI7_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","CAN0: CTX +ETHERC0: MDC +ETHERC0: MDC +GPT6: GTIOCB +IIC0: SDA +IRQ0: IRQ05 +POEG0: GTETRG +SCI4: CTS_RTS_SS +SCI7: SDA +SCI7: TXD_MOSI" +"P402","3","SCI7_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT0: AGTIO +AGT1: AGTIO +CAC0: CACREF +CAN0: CRX +ETHERC0: MDIO +ETHERC0: MDIO +IRQ0: IRQ04 +PDC0: VSYNC +RTC0: RTCIC0 +SCI7: RXD_MISO +SCI7: SCL +SSI: AUDIO_CLK" +"P403","4","","","","Disabled","","","AGT0: AGTIO +AGT1: AGTIO +ETHERC0: LINKSTA +ETHERC0: LINKSTA +GPT3: GTIOCA +PDC0: PIXD7 +RTC0: RTCIC1 +SCI7: CTS_RTS_SS +SDHI1: DAT7 +SSI0: SSISCK" +"P404","5","","","","Disabled","","","ETHERC0: EXOUT +ETHERC0: EXOUT +GPT3: GTIOCB +PDC0: PIXD6 +RTC0: RTCIC2 +SDHI1: DAT6 +SSI0: SSIWS" +"P405","6","","","","Disabled","","","ETHERC0: TX_EN +ETHERC0: TXD_EN +GPT1: GTIOCA +PDC0: PIXD5 +SDHI1: DAT5 +SSI0: SSITXD" +"P406","7","","","","Disabled","","","ETHERC0: RX_ER +ETHERC0: TXD1 +GPT1: GTIOCB +PDC0: PIXD4 +SDHI1: DAT4 +SPI1: SSL3 +SSI0: SSIRXD" +"P407","36","USBFS0_VBUS","Low","","Peripheral mode","CMOS","None","ADC0: ADTRG +AGT0: AGTIO +CTSU0: TS03 +ETHERC0: EXOUT +ETHERC0: EXOUT +IIC0: SDA +RTC0: RTCOUT +SCI4: CTS_RTS_SS +SPI1: SSL3 +USBFS0: VBUS" +"P408","35","","","","Disabled","","","CTSU0: TS04 +ETHERC0: CRS +ETHERC0: CRS_DV +GPT10: GTIOCB +IIC0: SCL +IRQ0: IRQ07 +OPS0: GTOWLO +PDC0: PIXCLK +SCI3: RXD_MISO +SCI3: SCL +USBFS0: ID" +"P409","34","","","","Disabled","","","CTSU0: TS05 +ETHERC0: RX_CLK +ETHERC0: RX_ER +GPT10: GTIOCA +IRQ0: IRQ06 +OPS0: GTOWUP +PDC0: HSYNC +SCI3: SDA +SCI3: TXD_MOSI +USBFS0: EXICEN" +"P410","33","SCI0_RXD_MISO","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOB +CTSU0: TS06 +ETHERC0: ERXD0 +ETHERC0: RXD1 +GPT9: GTIOCB +IRQ0: IRQ05 +OPS0: GTOVLO +PDC0: PIXD0 +SCI0: RXD_MISO +SCI0: SCL +SCI3: SCK +SDHI0: DAT1 +SPI0: MISO" +"P411","32","SCI0_TXD_MOSI","Low","None","Peripheral mode","CMOS","None","AGT1: AGTOA +CTSU0: TS07 +ETHERC0: ERXD1 +ETHERC0: RXD0 +GPT9: GTIOCA +IRQ0: IRQ04 +OPS0: GTOVUP +PDC0: PIXD1 +SCI0: SDA +SCI0: TXD_MOSI +SCI3: CTS_RTS_SS +SDHI0: DAT0 +SPI0: MOSI" +"P412","31","","","","Disabled","","","AGT1: AGTEE +CTSU0: TS08 +ETHERC0: ETXD0 +ETHERC0: REF50CK +OPS0: GTOULO +PDC0: PIXD2 +SCI0: SCK +SDHI0: CMD +SPI0: RSPCK" +"P413","30","","","","Disabled","","","CTSU0: TS09 +ETHERC0: ETXD1 +ETHERC0: TXD0 +OPS0: GTOUUP +PDC0: PIXD3 +SCI0: CTS_RTS_SS +SDHI0: CLK +SPI0: SSL0" +"P414","29","","","","Disabled","","","CTSU0: TS10 +ETHERC0: RX_ER +ETHERC0: TXD1 +GPT0: GTIOCB +IRQ0: IRQ09 +PDC0: PIXD4 +SDHI0: WP +SPI0: SSL1" +"P415","28","","","","Disabled","","","CTSU0: TS11 +ETHERC0: TX_EN +ETHERC0: TXD_EN +GPT0: GTIOCA +IRQ0: IRQ08 +PDC0: PIXD5 +SDHI0: CD +SPI0: SSL2 +USBFS0: VBUSEN" +"P500","113","","","","Disabled","","","ADC0: AN16 +AGT0: AGTOA +CMP0: IVREF0 +GPT11: GTIOCA +OPS0: GTIU +QSPI0: QSPCLK +SDHI1: CLK +USBFS0: VBUSEN" +"P501","114","","","","Disabled","","","ADC1: AN16 +AGT0: AGTOB +CMP0: IVREF1 +GPT11: GTIOCB +IRQ0: IRQ11 +OPS0: GTIV +QSPI0: QSSL +SCI5: SDA +SCI5: TXD_MOSI +SDHI1: CMD +USBFS0: OVRCURA" +"P502","115","","","","Disabled","","","ADC0: AN17 +CMP0: IVCMP0 +GPT12: GTIOCA +IRQ0: IRQ12 +OPS0: GTIW +QSPI0: QIO0 +SCI5: RXD_MISO +SCI5: SCL +SDHI1: DAT0 +USBFS0: OVRCURB" +"P503","116","","","","Disabled","","","ADC1: AN17 +GPT12: GTIOCB +POEG2: GTETRG +QSPI0: QIO1 +SCI5: SCK +SCI6: CTS_RTS_SS +SDHI1: DAT1 +USBFS0: EXICEN" +"P504","117","","","","Disabled","","","ADC0: AN18 +BUS0: ALE +GPT13: GTIOCA +POEG3: GTETRG +QSPI0: QIO2 +SCI5: CTS_RTS_SS +SCI6: SCK +SDHI1: DAT2 +USBFS0: ID" +"P505","118","","","","Disabled","","","ADC1: AN18 +GPT13: GTIOCB +IRQ0: IRQ14 +QSPI0: QIO3 +SCI6: RXD_MISO +SCI6: SCL +SDHI1: DAT3" +"P506","119","","","","Disabled","","","ADC0: AN19 +IRQ0: IRQ15 +SCI6: SDA +SCI6: TXD_MOSI +SDHI1: CD" +"P508","120","","","","Disabled","","","ADC0: AN20 +SCI5: SCK +SCI6: SCK +SDHI1: DAT3" +"P511","144","IIC2_SDA","Medium","None","Peripheral mode","CMOS","None","CAN1: CRX +GPT0: GTIOCB +IIC2: SDA +IRQ0: IRQ15 +PDC0: PCKO +SCI4: RXD_MISO +SCI4: SCL" +"P512","143","IIC2_SCL","Medium","None","Peripheral mode","CMOS","None","CAN1: CTX +GPT0: GTIOCA +IIC2: SCL +IRQ0: IRQ14 +PDC0: VSYNC +SCI4: SDA +SCI4: TXD_MOSI" +"P600","98","","","","Disabled","","","BUS0: RD +CAC0: CACREF +CGC0: CLKOUT +GPT6: GTIOCB +SCI9: SCK" +"P601","97","SCI9_RXD_MISO","Low","","Peripheral mode","CMOS","None","BUS0: WR_WR0_DQM0 +GPT6: GTIOCA +SCI9: RXD_MISO +SCI9: SCL" +"P602","96","SCI9_TXD_MOSI","Low","","Peripheral mode","CMOS","None","BUS0: BCLK_SDCLK +GPT7: GTIOCB +SCI9: SDA +SCI9: TXD_MOSI" +"P603","95","","","","Disabled","","","BUS0: D13_DQ13 +GPT7: GTIOCA +SCI9: CTS_RTS_SS" +"P604","94","","","","Disabled","","","BUS0: D12_DQ12 +GPT8: GTIOCB" +"P605","93","","","","Disabled","","","BUS0: D11_DQ11 +GPT8: GTIOCA" +"P608","83","","","","Disabled","","","BUS0: A00_BC0_DQM1 +GPT4: GTIOCB" +"P609","84","","","","Disabled","","","BUS0: CS1_CKE +CAN1: CTX +GPT5: GTIOCA" +"P610","85","","","","Disabled","","","BUS0: CS0_WE +CAN1: CRX +GPT5: GTIOCB" +"P611","86","","","","Disabled","","","BUS0: SDCS +CAC0: CACREF +CGC0: CLKOUT +SCI7: CTS_RTS_SS" +"P612","87","","","","Disabled","","","BUS0: D8_DQ8 +SCI7: SCK" +"P613","88","","","","Disabled","","","BUS0: D9_DQ9 +SCI7: SDA +SCI7: TXD_MOSI" +"P614","89","","","","Disabled","","","BUS0: D10_DQ10 +SCI7: RXD_MISO +SCI7: SCL" +"P700","8","SPI1_MISO","Low","","Peripheral mode","CMOS","None","ETHERC0: ETXD1 +ETHERC0: TXD0 +GPT5: GTIOCA +PDC0: PIXD3 +SDHI1: DAT3 +SPI1: MISO" +"P701","9","SPI1_MOSI","Low","","Peripheral mode","CMOS","None","ETHERC0: ETXD0 +ETHERC0: REF50CK +GPT5: GTIOCB +PDC0: PIXD2 +SDHI1: DAT2 +SPI1: MOSI" +"P702","10","SPI1_RSPCK","Low","","Peripheral mode","CMOS","None","ETHERC0: ERXD1 +ETHERC0: RXD0 +GPT6: GTIOCA +PDC0: PIXD1 +SDHI1: DAT1 +SPI1: RSPCK" +"P703","11","SPI1_SSL0","Low","","Peripheral mode","CMOS","None","CMP0: VCOUT +ETHERC0: ERXD0 +ETHERC0: RXD1 +GPT6: GTIOCB +PDC0: PIXD0 +SDHI1: DAT0 +SPI1: SSL0" +"P704","12","","","","Disabled","","","AGT0: AGTO +CAN0: CTX +ETHERC0: RX_CLK +ETHERC0: RX_ER +PDC0: HSYNC +SDHI1: CLK +SPI1: SSL1" +"P705","13","","","","Disabled","","","AGT0: AGTIO +CAN0: CRX +ETHERC0: CRS +ETHERC0: CRS_DV +PDC0: PIXCLK +SDHI1: CMD +SPI1: SSL2" +"P708","27","","","","Disabled","","","CAC0: CACREF +CTSU0: TS12 +ETHERC0: ETXD3 +IRQ0: IRQ11 +PDC0: PCKO +SCI1: RXD_MISO +SCI1: SCL +SPI0: SSL3 +SSI: AUDIO_CLK" +"P709","26","","","","Disabled","","","CTSU0: TS13 +ETHERC0: ETXD2 +IRQ0: IRQ10 +SCI1: SDA +SCI1: TXD_MOSI" +"P710","25","","","","Disabled","","","CTSU0: TS14 +ETHERC0: TX_ER +SCI1: SCK" +"P711","24","","","","Disabled","","","AGT0: AGTEE +CTSU0: TS15 +ETHERC0: TX_CLK +SCI1: CTS_RTS_SS" +"P712","23","","","","Disabled","","","AGT0: AGTOB +CTSU0: TS16 +GPT2: GTIOCB" +"P713","22","","","","Disabled","","","AGT0: AGTOA +CTSU0: TS17 +GPT2: GTIOCA" +"P800","109","","","","Disabled","","","BUS0: D14_DQ14" +"P801","110","","","","Disabled","","","BUS0: D15_DQ15" +"RES","55","","","","","","","" +"USBDM","38","USBFS0_USBDM","","","","","","" +"USBDP","39","USBFS0_USBDP","","","","","","" +"VBAT","14","","","","","","","" +"VCC","99","","","","","","","" +"VCC","121","","","","","","","" +"VCC","111","","","","","","","" +"VCC","68","","","","","","","" +"VCC","49","","","","","","","" +"VCC","90","","","","","","","" +"VCC","81","","","","","","","" +"VCC","21","","","","","","","" +"VCC","142","","","","","","","" +"VCCUSB","40","USBFS0_VCCUSB","","","","","","" +"VCL","15","","","","","","","" +"VCL1","92","","","","","","","" +"VREFH","126","ADC_VREFH","","","","","","" +"VREFH0","130","ADC_VREFH0","","","","","","" +"VREFL","125","ADC_VREFL","","","","","","" +"VREFL0","129","ADC_VREFL0","","","","","","" +"VSS","122","","","","","","","" +"VSS","67","","","","","","","" +"VSS","100","","","","","","","" +"VSS","112","","","","","","","" +"VSS","48","","","","","","","" +"VSS","18","","","","","","","" +"VSS","91","","","","","","","" +"VSS","82","","","","","","","" +"VSS","141","","","","","","","" +"VSSUSB","37","USBFS0_VSSUSB","","","","","","" +"XCIN","16","CGC0_XCIN","","","","","","" +"XCOUT","17","CGC0_XCOUT","","","","","","" diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/bsp_clock_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/bsp_clock_cfg.h new file mode 100644 index 000000000..2c93a573b --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/bsp_clock_cfg.h @@ -0,0 +1,24 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_CLOCK_CFG_H_ +#define BSP_CLOCK_CFG_H_ +#define BSP_CFG_CLOCKS_SECURE (0) +#define BSP_CFG_CLOCKS_OVERRIDE (0) +#define BSP_CFG_XTAL_HZ (12000000) /* XTAL 12000000Hz */ +#define BSP_CFG_PLL_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) /* PLL Src: XTAL */ +#define BSP_CFG_HOCO_FREQUENCY (2) /* HOCO 20MHz */ +#define BSP_CFG_PLL_DIV (BSP_CLOCKS_PLL_DIV_1) /* PLL Div /1 */ +#define BSP_CFG_PLL_MUL BSP_CLOCKS_PLL_MUL_20_0 /* PLL Mul x20.0 */ +#define BSP_CFG_CLOCK_SOURCE (BSP_CLOCKS_SOURCE_CLOCK_PLL) /* Clock Src: PLL */ +#define BSP_CFG_ICLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* ICLK Div /2 */ +#define BSP_CFG_PCLKA_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKA Div /2 */ +#define BSP_CFG_PCLKB_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKB Div /4 */ +#define BSP_CFG_PCLKC_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* PCLKC Div /4 */ +#define BSP_CFG_PCLKD_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* PCLKD Div /2 */ +#define BSP_CFG_SDCLK_OUTPUT (1) /* SDCLKout On */ +#define BSP_CFG_BCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_2) /* BCLK Div /2 */ +#define BSP_CFG_BCLK_OUTPUT (2) /* BCK/2 */ +#define BSP_CFG_UCK_DIV (BSP_CLOCKS_USB_CLOCK_DIV_5) /* UCLK Div /5 */ +#define BSP_CFG_FCLK_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_4) /* FCLK Div /4 */ +#define BSP_CFG_CLKOUT_SOURCE (BSP_CLOCKS_CLOCK_DISABLED) /* CLKOUT Disabled */ +#define BSP_CFG_CLKOUT_DIV (BSP_CLOCKS_SYS_CLOCK_DIV_1) /* CLKOUT Div /1 */ +#endif /* BSP_CLOCK_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/bsp_pin_cfg.h b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/bsp_pin_cfg.h new file mode 100644 index 000000000..c5b93301a --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/bsp_pin_cfg.h @@ -0,0 +1,7 @@ +/* generated configuration header file - do not edit */ +#ifndef BSP_PIN_CFG_H_ +#define BSP_PIN_CFG_H_ +#include "bsp_api.h" +#include "r_ioport_api.h" +extern const ioport_cfg_t g_bsp_pin_cfg; /* RA6M2-EK.pincfg */ +#endif /* BSP_PIN_CFG_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/common_data.c b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/common_data.c new file mode 100644 index 000000000..34aad762f --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/common_data.c @@ -0,0 +1,7 @@ +/* generated common source file - do not edit */ +#include "common_data.h" +ioport_instance_ctrl_t g_ioport_ctrl; +const ioport_instance_t g_ioport = +{ .p_api = &g_ioport_on_ioport, .p_ctrl = &g_ioport_ctrl, .p_cfg = &g_bsp_pin_cfg, }; +void g_common_init(void) { +} diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/common_data.h b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/common_data.h new file mode 100644 index 000000000..e2eb70836 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/common_data.h @@ -0,0 +1,16 @@ +/* generated common header file - do not edit */ +#ifndef COMMON_DATA_H_ +#define COMMON_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "r_ioport.h" +#include "bsp_pin_cfg.h" +FSP_HEADER +/* IOPORT Instance */ +extern const ioport_instance_t g_ioport; + +/* IOPORT control structure. */ +extern ioport_instance_ctrl_t g_ioport_ctrl; +void g_common_init(void); +FSP_FOOTER +#endif /* COMMON_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/hal_data.c b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/hal_data.c new file mode 100644 index 000000000..b0d38881e --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/hal_data.c @@ -0,0 +1,983 @@ +/* generated HAL source file - do not edit */ +#include "hal_data.h" +/* Macros to tie dynamic ELC links to ADC_TRIGGER_SYNC_ELC option in adc_trigger_t. */ +#define ADC_TRIGGER_ADC0 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC0_B ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1 ADC_TRIGGER_SYNC_ELC +#define ADC_TRIGGER_ADC1_B ADC_TRIGGER_SYNC_ELC +iic_master_instance_ctrl_t g_i2c_master2_ctrl; +const iic_master_extended_cfg_t g_i2c_master2_extend = +{ .timeout_mode = IIC_MASTER_TIMEOUT_MODE_SHORT, +/* Actual calculated bitrate: 98945. Actual calculated duty cycle: 51%. */ .clock_settings.brl_value = 15, + .clock_settings.brh_value = 16, .clock_settings.cks_value = 4, }; +const i2c_master_cfg_t g_i2c_master2_cfg = +{ .channel = 2, .rate = I2C_MASTER_RATE_STANDARD, .slave = 0x00, .addr_mode = I2C_MASTER_ADDR_MODE_7BIT, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .p_callback = callback_iic, + .p_context = NULL, + #if defined(VECTOR_NUMBER_IIC2_RXI) + .rxi_irq = VECTOR_NUMBER_IIC2_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC2_TXI) + .txi_irq = VECTOR_NUMBER_IIC2_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC2_TEI) + .tei_irq = VECTOR_NUMBER_IIC2_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_IIC2_ERI) + .eri_irq = VECTOR_NUMBER_IIC2_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + .ipl = (12), + .p_extend = &g_i2c_master2_extend, }; +/* Instance structure to use this module. */ +const i2c_master_instance_t g_i2c_master2 = +{ .p_ctrl = &g_i2c_master2_ctrl, .p_cfg = &g_i2c_master2_cfg, .p_api = &g_i2c_master_on_iic }; +adc_instance_ctrl_t g_adc1_ctrl; +const adc_extended_cfg_t g_adc1_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc1_cfg = +{ .unit = 1, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc1_cfg_extend, + #if defined(VECTOR_NUMBER_ADC1_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC1_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC1_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC1_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc1_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc1 = +{ .p_ctrl = &g_adc1_ctrl, .p_cfg = &g_adc1_cfg, .p_channel_cfg = &g_adc1_channel_cfg, .p_api = &g_adc_on_adc }; +adc_instance_ctrl_t g_adc0_ctrl; +const adc_extended_cfg_t g_adc0_cfg_extend = +{ .add_average_count = ADC_ADD_OFF, + .clearing = ADC_CLEAR_AFTER_READ_ON, + .trigger_group_b = ADC_TRIGGER_SYNC_ELC, + .double_trigger_mode = ADC_DOUBLE_TRIGGER_DISABLED, + .adc_vref_control = ADC_VREF_CONTROL_VREFH, }; +const adc_cfg_t g_adc0_cfg = +{ .unit = 0, .mode = ADC_MODE_SINGLE_SCAN, .resolution = ADC_RESOLUTION_12_BIT, .alignment = + (adc_alignment_t)ADC_ALIGNMENT_RIGHT, + .trigger = ADC_TRIGGER_SOFTWARE, .p_callback = NULL, .p_context = NULL, .p_extend = &g_adc0_cfg_extend, + #if defined(VECTOR_NUMBER_ADC0_SCAN_END) + .scan_end_irq = VECTOR_NUMBER_ADC0_SCAN_END, + #else + .scan_end_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_ipl = (BSP_IRQ_DISABLED), + #if defined(VECTOR_NUMBER_ADC0_SCAN_END_B) + .scan_end_b_irq = VECTOR_NUMBER_ADC0_SCAN_END_B, + #else + .scan_end_b_irq = FSP_INVALID_VECTOR, + #endif + .scan_end_b_ipl = (BSP_IRQ_DISABLED), }; +const adc_channel_cfg_t g_adc0_channel_cfg = +{ .scan_mask = 0, + .scan_mask_group_b = 0, + .priority_group_a = ADC_GROUP_A_PRIORITY_OFF, + .add_mask = 0, + .sample_hold_mask = 0, + .sample_hold_states = 24, }; +/* Instance structure to use this module. */ +const adc_instance_t g_adc0 = +{ .p_ctrl = &g_adc0_ctrl, .p_cfg = &g_adc0_cfg, .p_channel_cfg = &g_adc0_channel_cfg, .p_api = &g_adc_on_adc }; +lpm_instance_ctrl_t g_lpm0_ctrl; + +const lpm_cfg_t g_lpm0_cfg = +{ .low_power_mode = LPM_MODE_SLEEP, + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = LPM_STANDBY_WAKE_SOURCE_RTCALM | (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, }; + +const lpm_instance_t g_lpm0 = +{ .p_api = &g_lpm_on_lpm, .p_ctrl = &g_lpm0_ctrl, .p_cfg = &g_lpm0_cfg }; +dtc_instance_ctrl_t g_transfer3_ctrl; + +transfer_info_t g_transfer3_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer3_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI1_RXI, }; +const transfer_cfg_t g_transfer3_cfg = +{ .p_info = &g_transfer3_info, .p_extend = &g_transfer3_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer3 = +{ .p_ctrl = &g_transfer3_ctrl, .p_cfg = &g_transfer3_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer2_ctrl; + +transfer_info_t g_transfer2_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer2_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI1_TXI, }; +const transfer_cfg_t g_transfer2_cfg = +{ .p_info = &g_transfer2_info, .p_extend = &g_transfer2_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer2 = +{ .p_ctrl = &g_transfer2_ctrl, .p_cfg = &g_transfer2_cfg, .p_api = &g_transfer_on_dtc }; +spi_instance_ctrl_t g_spi1_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi1_ext_cfg = +{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = + { + /* Actual calculated bitrate: 15000000. */ .spbr = 3, + .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi1_cfg = +{ .channel = 1, + + #if defined(VECTOR_NUMBER_SPI1_RXI) + .rxi_irq = VECTOR_NUMBER_SPI1_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI1_TXI) + .txi_irq = VECTOR_NUMBER_SPI1_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI1_TEI) + .tei_irq = VECTOR_NUMBER_SPI1_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI1_ERI) + .eri_irq = VECTOR_NUMBER_SPI1_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi1_P_TRANSFER_TX, + .p_transfer_rx = g_spi1_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi1_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi1 = +{ .p_ctrl = &g_spi1_ctrl, .p_cfg = &g_spi1_cfg, .p_api = &g_spi_on_spi }; +dtc_instance_ctrl_t g_transfer1_ctrl; + +transfer_info_t g_transfer1_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .repeat_area = TRANSFER_REPEAT_AREA_DESTINATION, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer1_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_RXI, }; +const transfer_cfg_t g_transfer1_cfg = +{ .p_info = &g_transfer1_info, .p_extend = &g_transfer1_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer1 = +{ .p_ctrl = &g_transfer1_ctrl, .p_cfg = &g_transfer1_cfg, .p_api = &g_transfer_on_dtc }; +dtc_instance_ctrl_t g_transfer0_ctrl; + +transfer_info_t g_transfer0_info = +{ .dest_addr_mode = TRANSFER_ADDR_MODE_FIXED, + .repeat_area = TRANSFER_REPEAT_AREA_SOURCE, + .irq = TRANSFER_IRQ_END, + .chain_mode = TRANSFER_CHAIN_MODE_DISABLED, + .src_addr_mode = TRANSFER_ADDR_MODE_INCREMENTED, + .size = TRANSFER_SIZE_2_BYTE, + .mode = TRANSFER_MODE_NORMAL, + .p_dest = (void *)NULL, + .p_src = (void const *)NULL, + .num_blocks = 0, + .length = 0, }; +const dtc_extended_cfg_t g_transfer0_cfg_extend = +{ .activation_source = VECTOR_NUMBER_SPI0_TXI, }; +const transfer_cfg_t g_transfer0_cfg = +{ .p_info = &g_transfer0_info, .p_extend = &g_transfer0_cfg_extend, }; + +/* Instance structure to use this module. */ +const transfer_instance_t g_transfer0 = +{ .p_ctrl = &g_transfer0_ctrl, .p_cfg = &g_transfer0_cfg, .p_api = &g_transfer_on_dtc }; +spi_instance_ctrl_t g_spi0_ctrl; + +/** SPI extended configuration for SPI HAL driver */ +const spi_extended_cfg_t g_spi0_ext_cfg = +{ .spi_clksyn = SPI_SSL_MODE_CLK_SYN, + .spi_comm = SPI_COMMUNICATION_FULL_DUPLEX, + .ssl_polarity = SPI_SSLP_LOW, + .ssl_select = SPI_SSL_SELECT_SSL0, + .mosi_idle = SPI_MOSI_IDLE_VALUE_FIXING_DISABLE, + .parity = SPI_PARITY_MODE_DISABLE, + .byte_swap = SPI_BYTE_SWAP_DISABLE, + .spck_div = + { + /* Actual calculated bitrate: 15000000. */ .spbr = 3, + .brdv = 0 + }, + .spck_delay = SPI_DELAY_COUNT_1, + .ssl_negation_delay = SPI_DELAY_COUNT_1, + .next_access_delay = SPI_DELAY_COUNT_1 }; + +/** SPI configuration for SPI HAL driver */ +const spi_cfg_t g_spi0_cfg = +{ .channel = 0, + + #if defined(VECTOR_NUMBER_SPI0_RXI) + .rxi_irq = VECTOR_NUMBER_SPI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TXI) + .txi_irq = VECTOR_NUMBER_SPI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_TEI) + .tei_irq = VECTOR_NUMBER_SPI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SPI0_ERI) + .eri_irq = VECTOR_NUMBER_SPI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif + + .rxi_ipl = (12), + .txi_ipl = (12), + .tei_ipl = (12), + .eri_ipl = (12), + + .operating_mode = SPI_MODE_MASTER, + + .clk_phase = SPI_CLK_PHASE_EDGE_ODD, + .clk_polarity = SPI_CLK_POLARITY_LOW, + + .mode_fault = SPI_MODE_FAULT_ERROR_DISABLE, + .bit_order = SPI_BIT_ORDER_MSB_FIRST, + .p_transfer_tx = g_spi0_P_TRANSFER_TX, + .p_transfer_rx = g_spi0_P_TRANSFER_RX, + .p_callback = spi_callback, + + .p_context = NULL, + .p_extend = (void *)&g_spi0_ext_cfg, }; + +/* Instance structure to use this module. */ +const spi_instance_t g_spi0 = +{ .p_ctrl = &g_spi0_ctrl, .p_cfg = &g_spi0_cfg, .p_api = &g_spi_on_spi }; +icu_instance_ctrl_t g_external_irq15_ctrl; +const external_irq_cfg_t g_external_irq15_cfg = +{ .channel = 15, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ15) + .irq = VECTOR_NUMBER_ICU_IRQ15, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq15 = +{ .p_ctrl = &g_external_irq15_ctrl, .p_cfg = &g_external_irq15_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq14_ctrl; +const external_irq_cfg_t g_external_irq14_cfg = +{ .channel = 14, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ14) + .irq = VECTOR_NUMBER_ICU_IRQ14, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq14 = +{ .p_ctrl = &g_external_irq14_ctrl, .p_cfg = &g_external_irq14_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq13_ctrl; +const external_irq_cfg_t g_external_irq13_cfg = +{ .channel = 13, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ13) + .irq = VECTOR_NUMBER_ICU_IRQ13, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq13 = +{ .p_ctrl = &g_external_irq13_ctrl, .p_cfg = &g_external_irq13_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq12_ctrl; +const external_irq_cfg_t g_external_irq12_cfg = +{ .channel = 12, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ12) + .irq = VECTOR_NUMBER_ICU_IRQ12, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq12 = +{ .p_ctrl = &g_external_irq12_ctrl, .p_cfg = &g_external_irq12_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq11_ctrl; +const external_irq_cfg_t g_external_irq11_cfg = +{ .channel = 11, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ11) + .irq = VECTOR_NUMBER_ICU_IRQ11, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq11 = +{ .p_ctrl = &g_external_irq11_ctrl, .p_cfg = &g_external_irq11_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq10_ctrl; +const external_irq_cfg_t g_external_irq10_cfg = +{ .channel = 10, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ10) + .irq = VECTOR_NUMBER_ICU_IRQ10, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq10 = +{ .p_ctrl = &g_external_irq10_ctrl, .p_cfg = &g_external_irq10_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq9_ctrl; +const external_irq_cfg_t g_external_irq9_cfg = +{ .channel = 9, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ9) + .irq = VECTOR_NUMBER_ICU_IRQ9, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq9 = +{ .p_ctrl = &g_external_irq9_ctrl, .p_cfg = &g_external_irq9_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq8_ctrl; +const external_irq_cfg_t g_external_irq8_cfg = +{ .channel = 8, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ8) + .irq = VECTOR_NUMBER_ICU_IRQ8, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq8 = +{ .p_ctrl = &g_external_irq8_ctrl, .p_cfg = &g_external_irq8_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq7_ctrl; +const external_irq_cfg_t g_external_irq7_cfg = +{ .channel = 7, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ7) + .irq = VECTOR_NUMBER_ICU_IRQ7, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq7 = +{ .p_ctrl = &g_external_irq7_ctrl, .p_cfg = &g_external_irq7_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq6_ctrl; +const external_irq_cfg_t g_external_irq6_cfg = +{ .channel = 6, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ6) + .irq = VECTOR_NUMBER_ICU_IRQ6, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq6 = +{ .p_ctrl = &g_external_irq6_ctrl, .p_cfg = &g_external_irq6_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq5_ctrl; +const external_irq_cfg_t g_external_irq5_cfg = +{ .channel = 5, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ5) + .irq = VECTOR_NUMBER_ICU_IRQ5, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq5 = +{ .p_ctrl = &g_external_irq5_ctrl, .p_cfg = &g_external_irq5_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq4_ctrl; +const external_irq_cfg_t g_external_irq4_cfg = +{ .channel = 4, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ4) + .irq = VECTOR_NUMBER_ICU_IRQ4, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq4 = +{ .p_ctrl = &g_external_irq4_ctrl, .p_cfg = &g_external_irq4_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq3_ctrl; +const external_irq_cfg_t g_external_irq3_cfg = +{ .channel = 3, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ3) + .irq = VECTOR_NUMBER_ICU_IRQ3, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq3 = +{ .p_ctrl = &g_external_irq3_ctrl, .p_cfg = &g_external_irq3_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq2_ctrl; +const external_irq_cfg_t g_external_irq2_cfg = +{ .channel = 2, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ2) + .irq = VECTOR_NUMBER_ICU_IRQ2, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq2 = +{ .p_ctrl = &g_external_irq2_ctrl, .p_cfg = &g_external_irq2_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq1_ctrl; +const external_irq_cfg_t g_external_irq1_cfg = +{ .channel = 1, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ1) + .irq = VECTOR_NUMBER_ICU_IRQ1, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq1 = +{ .p_ctrl = &g_external_irq1_ctrl, .p_cfg = &g_external_irq1_cfg, .p_api = &g_external_irq_on_icu }; +icu_instance_ctrl_t g_external_irq0_ctrl; +const external_irq_cfg_t g_external_irq0_cfg = +{ .channel = 0, + .trigger = EXTERNAL_IRQ_TRIG_RISING, + .filter_enable = false, + .pclk_div = EXTERNAL_IRQ_PCLK_DIV_BY_64, + .p_callback = callback_icu, + .p_context = NULL, + .p_extend = NULL, + .ipl = (12), + #if defined(VECTOR_NUMBER_ICU_IRQ0) + .irq = VECTOR_NUMBER_ICU_IRQ0, + #else + .irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const external_irq_instance_t g_external_irq0 = +{ .p_ctrl = &g_external_irq0_ctrl, .p_cfg = &g_external_irq0_cfg, .p_api = &g_external_irq_on_icu }; +agt_instance_ctrl_t g_timer1_ctrl; +const agt_extended_cfg_t g_timer1_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer1_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer1_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer1 = +{ .p_ctrl = &g_timer1_ctrl, .p_cfg = &g_timer1_cfg, .p_api = &g_timer_on_agt }; +agt_instance_ctrl_t g_timer0_ctrl; +const agt_extended_cfg_t g_timer0_extend = +{ .count_source = AGT_CLOCK_PCLKB, + .agto = AGT_PIN_CFG_DISABLED, + .agtoa = AGT_PIN_CFG_DISABLED, + .agtob = AGT_PIN_CFG_DISABLED, + .measurement_mode = AGT_MEASURE_DISABLED, + .agtio_filter = AGT_AGTIO_FILTER_NONE, + .enable_pin = AGT_ENABLE_PIN_NOT_USED, + .trigger_edge = AGT_TRIGGER_EDGE_RISING, }; +const timer_cfg_t g_timer0_cfg = +{ .mode = TIMER_MODE_PERIODIC, +/* Actual period: 0.0010922666666666667 seconds. Actual duty: 50%. */ .period_counts = 0x10000, + .duty_cycle_counts = 0x8000, .source_div = (timer_source_div_t)0, .channel = 0, .p_callback = callback_agt, + /** If NULL then do not add & */ + #if defined(NULL) + .p_context = NULL, + #else + .p_context = &NULL, + #endif + .p_extend = &g_timer0_extend, + .cycle_end_ipl = (5), + #if defined(VECTOR_NUMBER_AGT0_INT) + .cycle_end_irq = VECTOR_NUMBER_AGT0_INT, + #else + .cycle_end_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const timer_instance_t g_timer0 = +{ .p_ctrl = &g_timer0_ctrl, .p_cfg = &g_timer0_cfg, .p_api = &g_timer_on_agt }; +flash_hp_instance_ctrl_t g_flash0_ctrl; +const flash_cfg_t g_flash0_cfg = +{ .data_flash_bgo = false, .p_callback = NULL, .p_context = NULL, + #if defined(VECTOR_NUMBER_FCU_FRDYI) + .irq = VECTOR_NUMBER_FCU_FRDYI, + #else + .irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_FCU_FIFERR) + .err_irq = VECTOR_NUMBER_FCU_FIFERR, + #else + .err_irq = FSP_INVALID_VECTOR, + #endif + .err_ipl = (BSP_IRQ_DISABLED), + .ipl = (BSP_IRQ_DISABLED), }; +/* Instance structure to use this module. */ +const flash_instance_t g_flash0 = +{ .p_ctrl = &g_flash0_ctrl, .p_cfg = &g_flash0_cfg, .p_api = &g_flash_on_flash_hp }; +rtc_instance_ctrl_t g_rtc0_ctrl; +const rtc_error_adjustment_cfg_t g_rtc0_err_cfg = +{ .adjustment_mode = RTC_ERROR_ADJUSTMENT_MODE_AUTOMATIC, + .adjustment_period = RTC_ERROR_ADJUSTMENT_PERIOD_10_SECOND, + .adjustment_type = RTC_ERROR_ADJUSTMENT_NONE, + .adjustment_value = 0, }; +const rtc_cfg_t g_rtc0_cfg = +{ .clock_source = RTC_CLOCK_SOURCE_LOCO, .freq_compare_value_loco = 255, .p_err_cfg = &g_rtc0_err_cfg, .p_callback = + NULL, + .p_context = NULL, .alarm_ipl = (14), .periodic_ipl = (14), .carry_ipl = (14), + #if defined(VECTOR_NUMBER_RTC_ALARM) + .alarm_irq = VECTOR_NUMBER_RTC_ALARM, + #else + .alarm_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + .periodic_irq = VECTOR_NUMBER_RTC_PERIOD, + #else + .periodic_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_RTC_CARRY) + .carry_irq = VECTOR_NUMBER_RTC_CARRY, + #else + .carry_irq = FSP_INVALID_VECTOR, + #endif +}; +/* Instance structure to use this module. */ +const rtc_instance_t g_rtc0 = +{ .p_ctrl = &g_rtc0_ctrl, .p_cfg = &g_rtc0_cfg, .p_api = &g_rtc_on_rtc }; +sci_uart_instance_ctrl_t g_uart9_ctrl; + +baud_setting_t g_uart9_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart9_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart9_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart9_cfg = +{ .channel = 9, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart9_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI9_RXI) + .rxi_irq = VECTOR_NUMBER_SCI9_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_TXI) + .txi_irq = VECTOR_NUMBER_SCI9_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_TEI) + .tei_irq = VECTOR_NUMBER_SCI9_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI9_ERI) + .eri_irq = VECTOR_NUMBER_SCI9_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart9 = +{ .p_ctrl = &g_uart9_ctrl, .p_cfg = &g_uart9_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart7_ctrl; + +baud_setting_t g_uart7_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart7_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart7_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart7_cfg = +{ .channel = 7, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart7_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI7_RXI) + .rxi_irq = VECTOR_NUMBER_SCI7_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI7_TXI) + .txi_irq = VECTOR_NUMBER_SCI7_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI7_TEI) + .tei_irq = VECTOR_NUMBER_SCI7_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI7_ERI) + .eri_irq = VECTOR_NUMBER_SCI7_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart7 = +{ .p_ctrl = &g_uart7_ctrl, .p_cfg = &g_uart7_cfg, .p_api = &g_uart_on_sci }; +sci_uart_instance_ctrl_t g_uart0_ctrl; + +baud_setting_t g_uart0_baud_setting = +{ +/* Baud rate calculated with 0.160% error. */ .abcse = 0, + .abcs = 0, .bgdm = 1, .cks = 0, .brr = 64, .mddr = (uint8_t)256, .brme = false +}; + +/** UART extended configuration for UARTonSCI HAL driver */ +const sci_uart_extended_cfg_t g_uart0_cfg_extend = +{ .clock = SCI_UART_CLOCK_INT, + .rx_edge_start = SCI_UART_START_BIT_FALLING_EDGE, + .noise_cancel = SCI_UART_NOISE_CANCELLATION_DISABLE, + .rx_fifo_trigger = SCI_UART_RX_FIFO_TRIGGER_MAX, + .p_baud_setting = &g_uart0_baud_setting, + .uart_mode = UART_MODE_RS232, + .ctsrts_en = SCI_UART_CTSRTS_RTS_OUTPUT, + #if 0 + .flow_control_pin = BSP_IO_PORT_00_PIN_00, + #else + .flow_control_pin = (bsp_io_port_pin_t)(0xFFFFU), + #endif +}; + +/** UART interface configuration */ +const uart_cfg_t g_uart0_cfg = +{ .channel = 0, .data_bits = UART_DATA_BITS_8, .parity = UART_PARITY_OFF, .stop_bits = UART_STOP_BITS_1, .p_callback = + user_uart_callback, + .p_context = NULL, .p_extend = &g_uart0_cfg_extend, +#define RA_NOT_DEFINED (1) + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_tx = NULL, + #else + .p_transfer_tx = &RA_NOT_DEFINED, + #endif + #if (RA_NOT_DEFINED == RA_NOT_DEFINED) + .p_transfer_rx = NULL, + #else + .p_transfer_rx = &RA_NOT_DEFINED, + #endif +#undef RA_NOT_DEFINED + .rxi_ipl = (12), + .txi_ipl = (12), .tei_ipl = (12), .eri_ipl = (12), + #if defined(VECTOR_NUMBER_SCI0_RXI) + .rxi_irq = VECTOR_NUMBER_SCI0_RXI, + #else + .rxi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TXI) + .txi_irq = VECTOR_NUMBER_SCI0_TXI, + #else + .txi_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_TEI) + .tei_irq = VECTOR_NUMBER_SCI0_TEI, + #else + .tei_irq = FSP_INVALID_VECTOR, + #endif + #if defined(VECTOR_NUMBER_SCI0_ERI) + .eri_irq = VECTOR_NUMBER_SCI0_ERI, + #else + .eri_irq = FSP_INVALID_VECTOR, + #endif +}; + +/* Instance structure to use this module. */ +const uart_instance_t g_uart0 = +{ .p_ctrl = &g_uart0_ctrl, .p_cfg = &g_uart0_cfg, .p_api = &g_uart_on_sci }; +void g_hal_init(void) { + g_common_init(); +} diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/hal_data.h b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/hal_data.h new file mode 100644 index 000000000..59d2a9122 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/hal_data.h @@ -0,0 +1,373 @@ +/* generated HAL header file - do not edit */ +#ifndef HAL_DATA_H_ +#define HAL_DATA_H_ +#include <stdint.h> +#include "bsp_api.h" +#include "common_data.h" +#include "r_iic_master.h" +#include "r_i2c_master_api.h" +#include "r_adc.h" +#include "r_adc_api.h" +#include "r_lpm.h" +#include "r_lpm_api.h" +#include "r_dtc.h" +#include "r_transfer_api.h" +#include "r_spi.h" +#include "r_icu.h" +#include "r_external_irq_api.h" +#include "r_agt.h" +#include "r_timer_api.h" +#include "r_flash_hp.h" +#include "r_flash_api.h" +#include "r_rtc.h" +#include "r_rtc_api.h" +#include "r_sci_uart.h" +#include "r_uart_api.h" +FSP_HEADER +/* I2C Master on IIC Instance. */ +extern const i2c_master_instance_t g_i2c_master2; + +/** Access the I2C Master instance using these structures when calling API functions directly (::p_api is not used). */ +extern iic_master_instance_ctrl_t g_i2c_master2_ctrl; +extern const i2c_master_cfg_t g_i2c_master2_cfg; + +#ifndef callback_iic +void callback_iic(i2c_master_callback_args_t *p_args); +#endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc1; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc1_ctrl; +extern const adc_cfg_t g_adc1_cfg; +extern const adc_channel_cfg_t g_adc1_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/** ADC on ADC Instance. */ +extern const adc_instance_t g_adc0; + +/** Access the ADC instance using these structures when calling API functions directly (::p_api is not used). */ +extern adc_instance_ctrl_t g_adc0_ctrl; +extern const adc_cfg_t g_adc0_cfg; +extern const adc_channel_cfg_t g_adc0_channel_cfg; + +#ifndef NULL +void NULL(adc_callback_args_t *p_args); +#endif +/** lpm Instance */ +extern const lpm_instance_t g_lpm0; + +/** Access the LPM instance using these structures when calling API functions directly (::p_api is not used). */ +extern lpm_instance_ctrl_t g_lpm0_ctrl; +extern const lpm_cfg_t g_lpm0_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer3; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer3_ctrl; +extern const transfer_cfg_t g_transfer3_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer2; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer2_ctrl; +extern const transfer_cfg_t g_transfer2_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi1; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi1_ctrl; +extern const spi_cfg_t g_spi1_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer2) + #define g_spi1_P_TRANSFER_TX (NULL) +#else +#define g_spi1_P_TRANSFER_TX (&g_transfer2) +#endif +#if (RA_NOT_DEFINED == g_transfer3) + #define g_spi1_P_TRANSFER_RX (NULL) +#else +#define g_spi1_P_TRANSFER_RX (&g_transfer3) +#endif +#undef RA_NOT_DEFINED +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer1; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer1_ctrl; +extern const transfer_cfg_t g_transfer1_cfg; +/* Transfer on DTC Instance. */ +extern const transfer_instance_t g_transfer0; + +/** Access the DTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern dtc_instance_ctrl_t g_transfer0_ctrl; +extern const transfer_cfg_t g_transfer0_cfg; +/** SPI on SPI Instance. */ +extern const spi_instance_t g_spi0; + +/** Access the SPI instance using these structures when calling API functions directly (::p_api is not used). */ +extern spi_instance_ctrl_t g_spi0_ctrl; +extern const spi_cfg_t g_spi0_cfg; + +/** Callback used by SPI Instance. */ +#ifndef spi_callback +void spi_callback(spi_callback_args_t *p_args); +#endif + +#define RA_NOT_DEFINED (1) +#if (RA_NOT_DEFINED == g_transfer0) + #define g_spi0_P_TRANSFER_TX (NULL) +#else +#define g_spi0_P_TRANSFER_TX (&g_transfer0) +#endif +#if (RA_NOT_DEFINED == g_transfer1) + #define g_spi0_P_TRANSFER_RX (NULL) +#else +#define g_spi0_P_TRANSFER_RX (&g_transfer1) +#endif +#undef RA_NOT_DEFINED +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq15; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq15_ctrl; +extern const external_irq_cfg_t g_external_irq15_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq14; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq14_ctrl; +extern const external_irq_cfg_t g_external_irq14_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq13; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq13_ctrl; +extern const external_irq_cfg_t g_external_irq13_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq12; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq12_ctrl; +extern const external_irq_cfg_t g_external_irq12_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq11; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq11_ctrl; +extern const external_irq_cfg_t g_external_irq11_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq10; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq10_ctrl; +extern const external_irq_cfg_t g_external_irq10_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq9; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq9_ctrl; +extern const external_irq_cfg_t g_external_irq9_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq8; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq8_ctrl; +extern const external_irq_cfg_t g_external_irq8_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq7; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq7_ctrl; +extern const external_irq_cfg_t g_external_irq7_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq6; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq6_ctrl; +extern const external_irq_cfg_t g_external_irq6_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq5; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq5_ctrl; +extern const external_irq_cfg_t g_external_irq5_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq4; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq4_ctrl; +extern const external_irq_cfg_t g_external_irq4_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq3; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq3_ctrl; +extern const external_irq_cfg_t g_external_irq3_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq2; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq2_ctrl; +extern const external_irq_cfg_t g_external_irq2_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq1; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq1_ctrl; +extern const external_irq_cfg_t g_external_irq1_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** External IRQ on ICU Instance. */ +extern const external_irq_instance_t g_external_irq0; + +/** Access the ICU instance using these structures when calling API functions directly (::p_api is not used). */ +extern icu_instance_ctrl_t g_external_irq0_ctrl; +extern const external_irq_cfg_t g_external_irq0_cfg; + +#ifndef callback_icu +void callback_icu(external_irq_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer1; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer1_ctrl; +extern const timer_cfg_t g_timer1_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/** AGT Timer Instance */ +extern const timer_instance_t g_timer0; + +/** Access the AGT instance using these structures when calling API functions directly (::p_api is not used). */ +extern agt_instance_ctrl_t g_timer0_ctrl; +extern const timer_cfg_t g_timer0_cfg; + +#ifndef callback_agt +void callback_agt(timer_callback_args_t *p_args); +#endif +/* Flash on Flash HP Instance */ +extern const flash_instance_t g_flash0; + +/** Access the Flash HP instance using these structures when calling API functions directly (::p_api is not used). */ +extern flash_hp_instance_ctrl_t g_flash0_ctrl; +extern const flash_cfg_t g_flash0_cfg; + +#ifndef NULL +void NULL(flash_callback_args_t *p_args); +#endif +/* RTC Instance. */ +extern const rtc_instance_t g_rtc0; + +/** Access the RTC instance using these structures when calling API functions directly (::p_api is not used). */ +extern rtc_instance_ctrl_t g_rtc0_ctrl; +extern const rtc_cfg_t g_rtc0_cfg; + +#ifndef NULL +void NULL(rtc_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart9; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart9_ctrl; +extern const uart_cfg_t g_uart9_cfg; +extern const sci_uart_extended_cfg_t g_uart9_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart7; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart7_ctrl; +extern const uart_cfg_t g_uart7_cfg; +extern const sci_uart_extended_cfg_t g_uart7_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +/** UART on SCI Instance. */ +extern const uart_instance_t g_uart0; + +/** Access the UART instance using these structures when calling API functions directly (::p_api is not used). */ +extern sci_uart_instance_ctrl_t g_uart0_ctrl; +extern const uart_cfg_t g_uart0_cfg; +extern const sci_uart_extended_cfg_t g_uart0_cfg_extend; + +#ifndef user_uart_callback +void user_uart_callback(uart_callback_args_t *p_args); +#endif +void hal_entry(void); +void g_hal_init(void); +FSP_FOOTER +#endif /* HAL_DATA_H_ */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/main.c b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/main.c new file mode 100644 index 000000000..5b9f98055 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/main.c @@ -0,0 +1,6 @@ +/* generated main source file - do not edit */ +#include "hal_data.h" +int main(void) { + hal_entry(); + return 0; +} diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/pin_data.c b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/pin_data.c new file mode 100644 index 000000000..28330830c --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/pin_data.c @@ -0,0 +1,117 @@ +/* generated pin source file - do not edit */ +#include "bsp_api.h" +#include "r_ioport_api.h" +const ioport_pin_cfg_t g_bsp_pin_cfg_data[] = { + { + .pin = BSP_IO_PORT_00_PIN_04, + .pin_cfg = ((uint32_t)IOPORT_CFG_ANALOG_ENABLE), + }, + { + .pin = BSP_IO_PORT_01_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_03, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_01_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_IRQ_ENABLE | (uint32_t)IOPORT_CFG_PORT_DIRECTION_INPUT), + }, + { + .pin = BSP_IO_PORT_01_PIN_06, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_01_PIN_08, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_09, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_01_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_02_PIN_05, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), + }, + { + .pin = BSP_IO_PORT_02_PIN_07, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_CTSU), + }, + { + .pin = BSP_IO_PORT_03_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_DEBUG), + }, + { + .pin = BSP_IO_PORT_04_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PORT_DIRECTION_OUTPUT | (uint32_t)IOPORT_CFG_PORT_OUTPUT_LOW), + }, + { + .pin = BSP_IO_PORT_04_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_04_PIN_07, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_USB_FS), + }, + { + .pin = BSP_IO_PORT_04_PIN_10, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_04_PIN_11, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI0_2_4_6_8), + }, + { + .pin = BSP_IO_PORT_05_PIN_11, + .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), + }, + { + .pin = BSP_IO_PORT_05_PIN_12, + .pin_cfg = ((uint32_t)IOPORT_CFG_DRIVE_MID | (uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_IIC), + }, + { + .pin = BSP_IO_PORT_06_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_06_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SCI1_3_5_7_9), + }, + { + .pin = BSP_IO_PORT_07_PIN_00, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_07_PIN_01, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_07_PIN_02, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, + { + .pin = BSP_IO_PORT_07_PIN_03, + .pin_cfg = ((uint32_t)IOPORT_CFG_PERIPHERAL_PIN | (uint32_t)IOPORT_PERIPHERAL_SPI), + }, +}; +const ioport_cfg_t g_bsp_pin_cfg = { + .number_of_pins = sizeof(g_bsp_pin_cfg_data) / sizeof(ioport_pin_cfg_t), + .p_pin_cfg_data = &g_bsp_pin_cfg_data[0], +}; diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/vector_data.c b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/vector_data.c new file mode 100644 index 000000000..35de44a48 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/vector_data.c @@ -0,0 +1,99 @@ +/* generated vector source file - do not edit */ +#include "bsp_api.h" +/* Do not build these data structures if no interrupts are currently allocated because IAR will have build errors. */ +#if VECTOR_DATA_IRQ_COUNT > 0 +BSP_DONT_REMOVE const fsp_vector_t g_vector_table[BSP_ICU_VECTOR_MAX_ENTRIES] BSP_PLACE_IN_SECTION(BSP_SECTION_APPLICATION_VECTORS) = +{ + [0] = sci_uart_rxi_isr, /* SCI0 RXI (Receive data full) */ + [1] = sci_uart_txi_isr, /* SCI0 TXI (Transmit data empty) */ + [2] = sci_uart_tei_isr, /* SCI0 TEI (Transmit end) */ + [3] = sci_uart_eri_isr, /* SCI0 ERI (Receive error) */ + [4] = sci_uart_rxi_isr, /* SCI7 RXI (Received data full) */ + [5] = sci_uart_txi_isr, /* SCI7 TXI (Transmit data empty) */ + [6] = sci_uart_tei_isr, /* SCI7 TEI (Transmit end) */ + [7] = sci_uart_eri_isr, /* SCI7 ERI (Receive error) */ + [8] = sci_uart_rxi_isr, /* SCI9 RXI (Received data full) */ + [9] = sci_uart_txi_isr, /* SCI9 TXI (Transmit data empty) */ + [10] = sci_uart_tei_isr, /* SCI9 TEI (Transmit end) */ + [11] = sci_uart_eri_isr, /* SCI9 ERI (Receive error) */ + [12] = rtc_alarm_periodic_isr, /* RTC ALARM (Alarm interrupt) */ + [13] = rtc_alarm_periodic_isr, /* RTC PERIOD (Periodic interrupt) */ + [14] = rtc_carry_isr, /* RTC CARRY (Carry interrupt) */ + [15] = agt_int_isr, /* AGT0 INT (AGT interrupt) */ + [16] = r_icu_isr, /* ICU IRQ0 (External pin interrupt 0) */ + [17] = r_icu_isr, /* ICU IRQ1 (External pin interrupt 1) */ + [18] = r_icu_isr, /* ICU IRQ2 (External pin interrupt 2) */ + [19] = r_icu_isr, /* ICU IRQ3 (External pin interrupt 3) */ + [20] = r_icu_isr, /* ICU IRQ4 (External pin interrupt 4) */ + [21] = r_icu_isr, /* ICU IRQ5 (External pin interrupt 5) */ + [22] = r_icu_isr, /* ICU IRQ6 (External pin interrupt 6) */ + [23] = r_icu_isr, /* ICU IRQ7 (External pin interrupt 7) */ + [24] = r_icu_isr, /* ICU IRQ8 (External pin interrupt 8) */ + [25] = r_icu_isr, /* ICU IRQ9 (External pin interrupt 9) */ + [26] = r_icu_isr, /* ICU IRQ10 (External pin interrupt 10) */ + [27] = r_icu_isr, /* ICU IRQ11 (External pin interrupt 11) */ + [28] = r_icu_isr, /* ICU IRQ12 (External pin interrupt 12) */ + [29] = r_icu_isr, /* ICU IRQ13 (External pin interrupt 13) */ + [30] = r_icu_isr, /* ICU IRQ14 (External pin interrupt 14) */ + [31] = r_icu_isr, /* ICU IRQ15 (External pin interrupt 15) */ + [32] = spi_rxi_isr, /* SPI0 RXI (Receive buffer full) */ + [33] = spi_txi_isr, /* SPI0 TXI (Transmit buffer empty) */ + [34] = spi_tei_isr, /* SPI0 TEI (Transmission complete event) */ + [35] = spi_eri_isr, /* SPI0 ERI (Error) */ + [36] = spi_rxi_isr, /* SPI1 RXI (Receive buffer full) */ + [37] = spi_txi_isr, /* SPI1 TXI (Transmit buffer empty) */ + [38] = spi_tei_isr, /* SPI1 TEI (Transmission complete event) */ + [39] = spi_eri_isr, /* SPI1 ERI (Error) */ + [40] = iic_master_rxi_isr, /* IIC2 RXI (Receive data full) */ + [41] = iic_master_txi_isr, /* IIC2 TXI (Transmit data empty) */ + [42] = iic_master_tei_isr, /* IIC2 TEI (Transmit end) */ + [43] = iic_master_eri_isr, /* IIC2 ERI (Transfer error) */ +}; +const bsp_interrupt_event_t g_interrupt_event_link_select[BSP_ICU_VECTOR_MAX_ENTRIES] = +{ + [0] = BSP_PRV_IELS_ENUM(EVENT_SCI0_RXI), /* SCI0 RXI (Receive data full) */ + [1] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TXI), /* SCI0 TXI (Transmit data empty) */ + [2] = BSP_PRV_IELS_ENUM(EVENT_SCI0_TEI), /* SCI0 TEI (Transmit end) */ + [3] = BSP_PRV_IELS_ENUM(EVENT_SCI0_ERI), /* SCI0 ERI (Receive error) */ + [4] = BSP_PRV_IELS_ENUM(EVENT_SCI7_RXI), /* SCI7 RXI (Received data full) */ + [5] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TXI), /* SCI7 TXI (Transmit data empty) */ + [6] = BSP_PRV_IELS_ENUM(EVENT_SCI7_TEI), /* SCI7 TEI (Transmit end) */ + [7] = BSP_PRV_IELS_ENUM(EVENT_SCI7_ERI), /* SCI7 ERI (Receive error) */ + [8] = BSP_PRV_IELS_ENUM(EVENT_SCI9_RXI), /* SCI9 RXI (Received data full) */ + [9] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TXI), /* SCI9 TXI (Transmit data empty) */ + [10] = BSP_PRV_IELS_ENUM(EVENT_SCI9_TEI), /* SCI9 TEI (Transmit end) */ + [11] = BSP_PRV_IELS_ENUM(EVENT_SCI9_ERI), /* SCI9 ERI (Receive error) */ + [12] = BSP_PRV_IELS_ENUM(EVENT_RTC_ALARM), /* RTC ALARM (Alarm interrupt) */ + [13] = BSP_PRV_IELS_ENUM(EVENT_RTC_PERIOD), /* RTC PERIOD (Periodic interrupt) */ + [14] = BSP_PRV_IELS_ENUM(EVENT_RTC_CARRY), /* RTC CARRY (Carry interrupt) */ + [15] = BSP_PRV_IELS_ENUM(EVENT_AGT0_INT), /* AGT0 INT (AGT interrupt) */ + [16] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ0), /* ICU IRQ0 (External pin interrupt 0) */ + [17] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ1), /* ICU IRQ1 (External pin interrupt 1) */ + [18] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ2), /* ICU IRQ2 (External pin interrupt 2) */ + [19] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ3), /* ICU IRQ3 (External pin interrupt 3) */ + [20] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ4), /* ICU IRQ4 (External pin interrupt 4) */ + [21] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ5), /* ICU IRQ5 (External pin interrupt 5) */ + [22] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ6), /* ICU IRQ6 (External pin interrupt 6) */ + [23] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ7), /* ICU IRQ7 (External pin interrupt 7) */ + [24] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ8), /* ICU IRQ8 (External pin interrupt 8) */ + [25] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ9), /* ICU IRQ9 (External pin interrupt 9) */ + [26] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ10), /* ICU IRQ10 (External pin interrupt 10) */ + [27] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ11), /* ICU IRQ11 (External pin interrupt 11) */ + [28] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ12), /* ICU IRQ12 (External pin interrupt 12) */ + [29] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ13), /* ICU IRQ13 (External pin interrupt 13) */ + [30] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ14), /* ICU IRQ14 (External pin interrupt 14) */ + [31] = BSP_PRV_IELS_ENUM(EVENT_ICU_IRQ15), /* ICU IRQ15 (External pin interrupt 15) */ + [32] = BSP_PRV_IELS_ENUM(EVENT_SPI0_RXI), /* SPI0 RXI (Receive buffer full) */ + [33] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TXI), /* SPI0 TXI (Transmit buffer empty) */ + [34] = BSP_PRV_IELS_ENUM(EVENT_SPI0_TEI), /* SPI0 TEI (Transmission complete event) */ + [35] = BSP_PRV_IELS_ENUM(EVENT_SPI0_ERI), /* SPI0 ERI (Error) */ + [36] = BSP_PRV_IELS_ENUM(EVENT_SPI1_RXI), /* SPI1 RXI (Receive buffer full) */ + [37] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TXI), /* SPI1 TXI (Transmit buffer empty) */ + [38] = BSP_PRV_IELS_ENUM(EVENT_SPI1_TEI), /* SPI1 TEI (Transmission complete event) */ + [39] = BSP_PRV_IELS_ENUM(EVENT_SPI1_ERI), /* SPI1 ERI (Error) */ + [40] = BSP_PRV_IELS_ENUM(EVENT_IIC2_RXI), /* IIC2 RXI (Receive data full) */ + [41] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TXI), /* IIC2 TXI (Transmit data empty) */ + [42] = BSP_PRV_IELS_ENUM(EVENT_IIC2_TEI), /* IIC2 TEI (Transmit end) */ + [43] = BSP_PRV_IELS_ENUM(EVENT_IIC2_ERI), /* IIC2 ERI (Transfer error) */ +}; +#endif diff --git a/ports/renesas-ra/boards/RA6M2_EK/ra_gen/vector_data.h b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/vector_data.h new file mode 100644 index 000000000..6629824be --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/ra_gen/vector_data.h @@ -0,0 +1,129 @@ +/* generated vector header file - do not edit */ +#ifndef VECTOR_DATA_H +#define VECTOR_DATA_H +/* Number of interrupts allocated */ +#ifndef VECTOR_DATA_IRQ_COUNT +#define VECTOR_DATA_IRQ_COUNT (44) +#endif +/* ISR prototypes */ +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_tei_isr(void); +void sci_uart_eri_isr(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); +void agt_int_isr(void); +void r_icu_isr(void); +void spi_rxi_isr(void); +void spi_txi_isr(void); +void spi_tei_isr(void); +void spi_eri_isr(void); +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); + +/* Vector table allocations */ +#define VECTOR_NUMBER_SCI0_RXI ((IRQn_Type)0) /* SCI0 RXI (Receive data full) */ +#define VECTOR_NUMBER_SCI0_TXI ((IRQn_Type)1) /* SCI0 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI0_TEI ((IRQn_Type)2) /* SCI0 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI0_ERI ((IRQn_Type)3) /* SCI0 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI7_RXI ((IRQn_Type)4) /* SCI7 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI7_TXI ((IRQn_Type)5) /* SCI7 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI7_TEI ((IRQn_Type)6) /* SCI7 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI7_ERI ((IRQn_Type)7) /* SCI7 ERI (Receive error) */ +#define VECTOR_NUMBER_SCI9_RXI ((IRQn_Type)8) /* SCI9 RXI (Received data full) */ +#define VECTOR_NUMBER_SCI9_TXI ((IRQn_Type)9) /* SCI9 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_SCI9_TEI ((IRQn_Type)10) /* SCI9 TEI (Transmit end) */ +#define VECTOR_NUMBER_SCI9_ERI ((IRQn_Type)11) /* SCI9 ERI (Receive error) */ +#define VECTOR_NUMBER_RTC_ALARM ((IRQn_Type)12) /* RTC ALARM (Alarm interrupt) */ +#define VECTOR_NUMBER_RTC_PERIOD ((IRQn_Type)13) /* RTC PERIOD (Periodic interrupt) */ +#define VECTOR_NUMBER_RTC_CARRY ((IRQn_Type)14) /* RTC CARRY (Carry interrupt) */ +#define VECTOR_NUMBER_AGT0_INT ((IRQn_Type)15) /* AGT0 INT (AGT interrupt) */ +#define VECTOR_NUMBER_ICU_IRQ0 ((IRQn_Type)16) /* ICU IRQ0 (External pin interrupt 0) */ +#define VECTOR_NUMBER_ICU_IRQ1 ((IRQn_Type)17) /* ICU IRQ1 (External pin interrupt 1) */ +#define VECTOR_NUMBER_ICU_IRQ2 ((IRQn_Type)18) /* ICU IRQ2 (External pin interrupt 2) */ +#define VECTOR_NUMBER_ICU_IRQ3 ((IRQn_Type)19) /* ICU IRQ3 (External pin interrupt 3) */ +#define VECTOR_NUMBER_ICU_IRQ4 ((IRQn_Type)20) /* ICU IRQ4 (External pin interrupt 4) */ +#define VECTOR_NUMBER_ICU_IRQ5 ((IRQn_Type)21) /* ICU IRQ5 (External pin interrupt 5) */ +#define VECTOR_NUMBER_ICU_IRQ6 ((IRQn_Type)22) /* ICU IRQ6 (External pin interrupt 6) */ +#define VECTOR_NUMBER_ICU_IRQ7 ((IRQn_Type)23) /* ICU IRQ7 (External pin interrupt 7) */ +#define VECTOR_NUMBER_ICU_IRQ8 ((IRQn_Type)24) /* ICU IRQ8 (External pin interrupt 8) */ +#define VECTOR_NUMBER_ICU_IRQ9 ((IRQn_Type)25) /* ICU IRQ9 (External pin interrupt 9) */ +#define VECTOR_NUMBER_ICU_IRQ10 ((IRQn_Type)26) /* ICU IRQ10 (External pin interrupt 10) */ +#define VECTOR_NUMBER_ICU_IRQ11 ((IRQn_Type)27) /* ICU IRQ11 (External pin interrupt 11) */ +#define VECTOR_NUMBER_ICU_IRQ12 ((IRQn_Type)28) /* ICU IRQ12 (External pin interrupt 12) */ +#define VECTOR_NUMBER_ICU_IRQ13 ((IRQn_Type)29) /* ICU IRQ13 (External pin interrupt 13) */ +#define VECTOR_NUMBER_ICU_IRQ14 ((IRQn_Type)30) /* ICU IRQ14 (External pin interrupt 14) */ +#define VECTOR_NUMBER_ICU_IRQ15 ((IRQn_Type)31) /* ICU IRQ15 (External pin interrupt 15) */ +#define VECTOR_NUMBER_SPI0_RXI ((IRQn_Type)32) /* SPI0 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI0_TXI ((IRQn_Type)33) /* SPI0 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI0_TEI ((IRQn_Type)34) /* SPI0 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI0_ERI ((IRQn_Type)35) /* SPI0 ERI (Error) */ +#define VECTOR_NUMBER_SPI1_RXI ((IRQn_Type)36) /* SPI1 RXI (Receive buffer full) */ +#define VECTOR_NUMBER_SPI1_TXI ((IRQn_Type)37) /* SPI1 TXI (Transmit buffer empty) */ +#define VECTOR_NUMBER_SPI1_TEI ((IRQn_Type)38) /* SPI1 TEI (Transmission complete event) */ +#define VECTOR_NUMBER_SPI1_ERI ((IRQn_Type)39) /* SPI1 ERI (Error) */ +#define VECTOR_NUMBER_IIC2_RXI ((IRQn_Type)40) /* IIC2 RXI (Receive data full) */ +#define VECTOR_NUMBER_IIC2_TXI ((IRQn_Type)41) /* IIC2 TXI (Transmit data empty) */ +#define VECTOR_NUMBER_IIC2_TEI ((IRQn_Type)42) /* IIC2 TEI (Transmit end) */ +#define VECTOR_NUMBER_IIC2_ERI ((IRQn_Type)43) /* IIC2 ERI (Transfer error) */ +typedef enum IRQn +{ + Reset_IRQn = -15, + NonMaskableInt_IRQn = -14, + HardFault_IRQn = -13, + MemoryManagement_IRQn = -12, + BusFault_IRQn = -11, + UsageFault_IRQn = -10, + SecureFault_IRQn = -9, + SVCall_IRQn = -5, + DebugMonitor_IRQn = -4, + PendSV_IRQn = -2, + SysTick_IRQn = -1, + SCI0_RXI_IRQn = 0, /* SCI0 RXI (Receive data full) */ + SCI0_TXI_IRQn = 1, /* SCI0 TXI (Transmit data empty) */ + SCI0_TEI_IRQn = 2, /* SCI0 TEI (Transmit end) */ + SCI0_ERI_IRQn = 3, /* SCI0 ERI (Receive error) */ + SCI7_RXI_IRQn = 4, /* SCI7 RXI (Received data full) */ + SCI7_TXI_IRQn = 5, /* SCI7 TXI (Transmit data empty) */ + SCI7_TEI_IRQn = 6, /* SCI7 TEI (Transmit end) */ + SCI7_ERI_IRQn = 7, /* SCI7 ERI (Receive error) */ + SCI9_RXI_IRQn = 8, /* SCI9 RXI (Received data full) */ + SCI9_TXI_IRQn = 9, /* SCI9 TXI (Transmit data empty) */ + SCI9_TEI_IRQn = 10, /* SCI9 TEI (Transmit end) */ + SCI9_ERI_IRQn = 11, /* SCI9 ERI (Receive error) */ + RTC_ALARM_IRQn = 12, /* RTC ALARM (Alarm interrupt) */ + RTC_PERIOD_IRQn = 13, /* RTC PERIOD (Periodic interrupt) */ + RTC_CARRY_IRQn = 14, /* RTC CARRY (Carry interrupt) */ + AGT0_INT_IRQn = 15, /* AGT0 INT (AGT interrupt) */ + ICU_IRQ0_IRQn = 16, /* ICU IRQ0 (External pin interrupt 0) */ + ICU_IRQ1_IRQn = 17, /* ICU IRQ1 (External pin interrupt 1) */ + ICU_IRQ2_IRQn = 18, /* ICU IRQ2 (External pin interrupt 2) */ + ICU_IRQ3_IRQn = 19, /* ICU IRQ3 (External pin interrupt 3) */ + ICU_IRQ4_IRQn = 20, /* ICU IRQ4 (External pin interrupt 4) */ + ICU_IRQ5_IRQn = 21, /* ICU IRQ5 (External pin interrupt 5) */ + ICU_IRQ6_IRQn = 22, /* ICU IRQ6 (External pin interrupt 6) */ + ICU_IRQ7_IRQn = 23, /* ICU IRQ7 (External pin interrupt 7) */ + ICU_IRQ8_IRQn = 24, /* ICU IRQ8 (External pin interrupt 8) */ + ICU_IRQ9_IRQn = 25, /* ICU IRQ9 (External pin interrupt 9) */ + ICU_IRQ10_IRQn = 26, /* ICU IRQ10 (External pin interrupt 10) */ + ICU_IRQ11_IRQn = 27, /* ICU IRQ11 (External pin interrupt 11) */ + ICU_IRQ12_IRQn = 28, /* ICU IRQ12 (External pin interrupt 12) */ + ICU_IRQ13_IRQn = 29, /* ICU IRQ13 (External pin interrupt 13) */ + ICU_IRQ14_IRQn = 30, /* ICU IRQ14 (External pin interrupt 14) */ + ICU_IRQ15_IRQn = 31, /* ICU IRQ15 (External pin interrupt 15) */ + SPI0_RXI_IRQn = 32, /* SPI0 RXI (Receive buffer full) */ + SPI0_TXI_IRQn = 33, /* SPI0 TXI (Transmit buffer empty) */ + SPI0_TEI_IRQn = 34, /* SPI0 TEI (Transmission complete event) */ + SPI0_ERI_IRQn = 35, /* SPI0 ERI (Error) */ + SPI1_RXI_IRQn = 36, /* SPI1 RXI (Receive buffer full) */ + SPI1_TXI_IRQn = 37, /* SPI1 TXI (Transmit buffer empty) */ + SPI1_TEI_IRQn = 38, /* SPI1 TEI (Transmission complete event) */ + SPI1_ERI_IRQn = 39, /* SPI1 ERI (Error) */ + IIC2_RXI_IRQn = 40, /* IIC2 RXI (Receive data full) */ + IIC2_TXI_IRQn = 41, /* IIC2 TXI (Transmit data empty) */ + IIC2_TEI_IRQn = 42, /* IIC2 TEI (Transmit end) */ + IIC2_ERI_IRQn = 43, /* IIC2 ERI (Transfer error) */ +} IRQn_Type; +#endif /* VECTOR_DATA_H */ diff --git a/ports/renesas-ra/boards/RA6M2_EK/src/hal_entry.c b/ports/renesas-ra/boards/RA6M2_EK/src/hal_entry.c new file mode 100644 index 000000000..c922cfd17 --- /dev/null +++ b/ports/renesas-ra/boards/RA6M2_EK/src/hal_entry.c @@ -0,0 +1,58 @@ +#include "hal_data.h" + +FSP_CPP_HEADER +void R_BSP_WarmStart(bsp_warm_start_event_t event); +FSP_CPP_FOOTER + +void ra_main(uint32_t reset_mode); + +/*******************************************************************************************************************//** + * main() is generated by the RA Configuration editor and is used to generate threads if an RTOS is used. This function + * is called by main() when no RTOS is used. + **********************************************************************************************************************/ +void hal_entry(void) { + /* TODO: add your own code here */ + + ra_main(1); + + #if BSP_TZ_SECURE_BUILD + /* Enter non-secure code */ + R_BSP_NonSecureEnter(); + #endif +} + +/*******************************************************************************************************************//** + * This function is called at various points during the startup process. This implementation uses the event that is + * called right before main() to set up the pins. + * + * @param[in] event Where at in the start up process the code is currently at + **********************************************************************************************************************/ +void R_BSP_WarmStart(bsp_warm_start_event_t event) { + if (BSP_WARM_START_RESET == event) { + #if BSP_FEATURE_FLASH_LP_VERSION != 0 + + /* Enable reading from data flash. */ + R_FACI_LP->DFLCTL = 1U; + + /* Would normally have to wait tDSTOP(6us) for data flash recovery. Placing the enable here, before clock and + * C runtime initialization, should negate the need for a delay since the initialization will typically take more than 6us. */ + #endif + } + + if (BSP_WARM_START_POST_C == event) { + /* C runtime environment and system clocks are setup. */ + + /* Configure pins. */ + R_IOPORT_Open(&g_ioport_ctrl, &g_bsp_pin_cfg); + } +} + +#if BSP_TZ_SECURE_BUILD + +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable(); + +/* Trustzone Secure Projects require at least one nonsecure callable function in order to build (Remove this if it is not required to build). */ +BSP_CMSE_NONSECURE_ENTRY void template_nonsecure_callable() { + +} +#endif diff --git a/ports/renesas-ra/boards/deploy.md b/ports/renesas-ra/boards/deploy.md new file mode 100644 index 000000000..1d0703999 --- /dev/null +++ b/ports/renesas-ra/boards/deploy.md @@ -0,0 +1,22 @@ +### Renesas RA Family Board via J-Flash Lite + +You can download [J-Link Software and Documentation pack](https://www.segger.com/downloads/jlink/) that includes a flash programming tool `J-Flash Lite`. + +A `.hex` file can be flashed using `J-Flash Lite`. + +1. Start `J-Flash Lite`. +2. Select devce name for board. + + | BOARD | DEVICE NAME | + | :------------------: | :--------------------: | + | RA4M1 Clicker | R7FA4M1AB | + | EK-RA6M2 | R7FA6M2AF | + | EK-RA4M1 | R7FA4M1AB | + | EK-RA6M1 | R7FA6M1AD | + | EK-RA4W1 | R7FA4W1AD2CNG | + +3. press `OK`. +4. Select `firmware.hex` file for Data File . +5. Press `Program Device`. + +Please refer to the [Renesas MicroPython Wiki](https://github.com/renesas/micropython/wiki) about cable connection between the board and your PC and more information.
\ No newline at end of file diff --git a/ports/renesas-ra/boards/make-pins.py b/ports/renesas-ra/boards/make-pins.py new file mode 100644 index 000000000..98d7026c2 --- /dev/null +++ b/ports/renesas-ra/boards/make-pins.py @@ -0,0 +1,333 @@ +#!/usr/bin/env python +"""Creates the pin file for the RAxxx.""" + +from __future__ import print_function + +import argparse +import sys +import csv + + +class PinAD(object): + def __init__(self, name, cpu_pin_name, pin_idx, bit, channel): + self._name = name + self._cpu_pin_name = cpu_pin_name + self._pin_idx = pin_idx + self._bit = bit + self._channel = channel + + def cpu_pin_name(self): + return self._cpu_pin_name + + def name(self): + return self._name + + def bit(self): + return self._bit + + def channel(self): + return self._channel + + def print(self): + print( + "const pin_ad_obj_t pin_{:s}_ad_obj = PIN_AD({:s}, {:d}, {:d}, {:d});".format( + self._cpu_pin_name, self._name, self._pin_idx, self._bit, self._channel + ) + ) + print("") + + def print_header(self, hdr_file): + n = self.cpu_pin_name() + hdr_file.write("extern const pin_ad_obj_t pin_{:s}_ad_obj;\n".format(n)) + hdr_file.write("#define pin_{:s}_ad (&pin_{:s}_ad_obj)\n".format(n, n)) + + def qstr_list(self): + return [self._name] + + +class Pin(object): + def __init__(self, name, port, bit): + self._name = name + self._pin_idx = port * 16 + bit + self._pin_ad = [] + self._board_pin = False + # print('// pin_{:s}_obj = PIN({:s}, {:d});'.format(self.name, self.name, self.pin)) + + def cpu_pin_name(self): + return self._name + + def pin_ad(self): + return self._pin_ad + + def is_board_pin(self): + return self._board_pin + + def set_is_board_pin(self): + self._board_pin = True + + def parse_ad(self, ad_str): + ad_bit = 0 + ad_channel = 0 + if (len(ad_str) == 5) and (ad_str[:3] == "AN0"): + ad_bit = 12 + ad_channel = int(ad_str[2:]) + self._pin_ad.append(PinAD(ad_str, self._name, self._pin_idx, ad_bit, ad_channel)) + elif (len(ad_str) == 5) and (ad_str[:3] == "AN1"): + ad_bit = 12 + ad_channel = int(ad_str[2:]) + self._pin_ad.append(PinAD(ad_str, self._name, self._pin_idx, ad_bit, ad_channel)) + elif ad_str[:2] == "AN": + ad_bit = 8 + ad_channel = int(ad_str[2:4]) + self._pin_ad.append(PinAD(ad_str, self._name, self._pin_idx, ad_bit, ad_channel)) + + def print(self): + pin_ad_name = "NULL" + for pin_ad in self._pin_ad: + pin_ad.print() + pin_ad_name = "pin_{:s}_ad".format(pin_ad.cpu_pin_name()) + print( + "const machine_pin_obj_t pin_{:s}_obj = PIN({:s}, {:d}, {:s});".format( + self._name, self._name, self._pin_idx, pin_ad_name + ) + ) + print("") + + def print_header(self, hdr_file): + n = self.cpu_pin_name() + hdr_file.write("extern const machine_pin_obj_t pin_{:s}_obj;\n".format(n)) + hdr_file.write("#define pin_{:s} (&pin_{:s}_obj)\n".format(n, n)) + + def qstr_list(self): + result = [] + for pin_ad in self._pin_ad: + result += pin_ad.qstr_list() + # for alt_fn in self.alt_fn: + # if alt_fn.is_supported(): + # result += alt_fn.qstr_list() + return result + + +class NamedPin(object): + def __init__(self, name, pin): + self._name = name + self._pin = pin + # print('// NamedPin {:s}'.format(self._name)) + + def pin(self): + return self._pin + + def name(self): + return self._name + + +class Pins(object): + def __init__(self): + self.cpu_pins = [] # list of NamedPin objects + self.board_pins = [] # list of NamedPin objects + + def find_pin(self, cpu_pin_name): + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.cpu_pin_name() == cpu_pin_name: + return pin + + # rx63n_al.csv + # cpu_pin_name, cpu_pin_port, cpu_pin_bit + def parse_af_file(self, filename): + with open(filename, "r") as csvfile: + rows = csv.reader(csvfile) + for row in rows: + try: + cpu_pin_name = row[0] + cpu_pin_port = int(row[1]) + cpu_pin_bit = int(row[2]) + except: + continue + pin = Pin(cpu_pin_name, cpu_pin_port, cpu_pin_bit) + self.cpu_pins.append(NamedPin(cpu_pin_name, pin)) + pin.parse_ad(row[3]) + + # pins.csv + # named_pin, cpu_pin_name + def parse_board_file(self, filename): + with open(filename, "r") as csvfile: + rows = csv.reader(csvfile) + for row in rows: + try: + board_pin_name = row[0] + cpu_pin_name = row[1] + except: + continue + pin = self.find_pin(cpu_pin_name) + if pin: + pin.set_is_board_pin() + self.board_pins.append(NamedPin(board_pin_name, pin)) + + def print_named(self, label, named_pins): + print( + "STATIC const mp_rom_map_elem_t pin_{:s}_pins_locals_dict_table[] = {{".format(label) + ) + for named_pin in named_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + print( + " {{ MP_ROM_QSTR(MP_QSTR_{:s}), MP_ROM_PTR(&pin_{:s}_obj) }},".format( + named_pin.name(), pin.cpu_pin_name() + ) + ) + print("};") + print( + "MP_DEFINE_CONST_DICT(pin_{:s}_pins_locals_dict, pin_{:s}_pins_locals_dict_table);".format( + label, label + ) + ) + + def print(self): + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + pin.print() + self.print_named("cpu", self.cpu_pins) + print("") + self.print_named("board", self.board_pins) + + def print_header(self, hdr_filename): + with open(hdr_filename, "wt") as hdr_file: + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + pin.print_header(hdr_file) + pin_ads = pin.pin_ad() + for pin_ad in pin_ads: + pin_ad.print_header(hdr_file) + # provide #define's mapping board to cpu name + for named_pin in self.board_pins: + hdr_file.write( + "#define pyb_pin_{:s} pin_{:s}\n".format( + named_pin.name(), named_pin.pin().cpu_pin_name() + ) + ) + + def print_qstr(self, qstr_filename): + with open(qstr_filename, "wt") as qstr_file: + qstr_set = set([]) + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + qstr_set |= set(pin.qstr_list()) + qstr_set |= set([named_pin.name()]) + for named_pin in self.board_pins: + qstr_set |= set([named_pin.name()]) + for qstr in sorted(qstr_set): + cond_var = None + if qstr.startswith("AF"): + af_words = qstr.split("_") + cond_var = conditional_var(af_words[1]) + print_conditional_if(cond_var, file=qstr_file) + print("Q({})".format(qstr), file=qstr_file) + # print_conditional_endif(cond_var, file=qstr_file) + + def print_ad_hdr(self, ad_const_filename): + with open(ad_const_filename, "wt") as ad_const_file: + for named_pin in self.cpu_pins: + pin = named_pin.pin() + if pin.is_board_pin(): + pin_ads = pin.pin_ad() + for pin_ad in pin_ads: + ad_const_file.write( + " {{ MP_ROM_QSTR(MP_QSTR_{:s}), MP_ROM_INT(GPIO_{:s}) }}, \n".format( + pin_ad.name(), pin_ad.name() + ) + ) + + +def main(): + parser = argparse.ArgumentParser( + prog="make-pins.py", + usage="%(prog)s [options] [command]", + description="Generate board specific pin file", + ) + parser.add_argument( + "-a", + "--af", + dest="af_filename", + help="Specifies the alternate function file for the chip", + default="ra4m1_af.csv", + ) + parser.add_argument( + "-b", "--board", dest="board_filename", help="Specifies the board file", default="pins.csv" + ) + parser.add_argument( + "-p", + "--prefix", + dest="prefix_filename", + help="Specifies beginning portion of generated pins file", + default="ra4m1_prefix.c", + ) + parser.add_argument( + "--ad-const", + dest="ad_const_filename", + help="Specifies header file for AD function constants.", + default="build/pins_ad_const.h", + ) + parser.add_argument( + "--af-const", + dest="af_const_filename", + help="Specifies header file for alternate function constants.", + default="build/pins_af_const.h", + ) + parser.add_argument( + "--af-py", + dest="af_py_filename", + help="Specifies the filename for the python alternate function mappings.", + default="build/pins_af.py", + ) + parser.add_argument( + "--af-defs", + dest="af_defs_filename", + help="Specifies the filename for the alternate function defines.", + default="build/pins_af_defs.h", + ) + parser.add_argument( + "-q", + "--qstr", + dest="qstr_filename", + help="Specifies name of generated qstr header file", + default="build/pins_qstr.h", + ) + parser.add_argument( + "-r", + "--hdr", + dest="hdr_filename", + help="Specifies name of generated pin header file", + default="build/pins.h", + ) + args = parser.parse_args(sys.argv[1:]) + + pins = Pins() + + print("// This file was automatically generated by make-pins.py") + print("//") + if args.af_filename: + print("// --af {:s}".format(args.af_filename)) + pins.parse_af_file(args.af_filename) + + if args.board_filename: + print("// --board {:s}".format(args.board_filename)) + pins.parse_board_file(args.board_filename) + + if args.prefix_filename: + print("// --prefix {:s}".format(args.prefix_filename)) + print("") + with open(args.prefix_filename, "r") as prefix_file: + print(prefix_file.read()) + + pins.print() + pins.print_header(args.hdr_filename) + pins.print_qstr(args.qstr_filename) + pins.print_ad_hdr(args.ad_const_filename) + + +if __name__ == "__main__": + main() diff --git a/ports/renesas-ra/boards/manifest.py b/ports/renesas-ra/boards/manifest.py new file mode 100644 index 000000000..836bf7ccc --- /dev/null +++ b/ports/renesas-ra/boards/manifest.py @@ -0,0 +1,4 @@ +include("$(MPY_DIR)/extmod/uasyncio/manifest.py") +freeze("$(MPY_DIR)/drivers/dht", "dht.py") +freeze("$(MPY_DIR)/drivers/onewire", "onewire.py") +freeze("$(MPY_DIR)/drivers/sdcard", "sdcard.py") diff --git a/ports/renesas-ra/boards/ra4m1_af.csv b/ports/renesas-ra/boards/ra4m1_af.csv new file mode 100644 index 000000000..a942a4900 --- /dev/null +++ b/ports/renesas-ra/boards/ra4m1_af.csv @@ -0,0 +1,161 @@ +CPU_PIN,PORT_IDX,PORT_BIT,Analog,IRQ,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,AF16,AF17,AF18,AF19 +P000,0,0,AN000,,,,,,,,,,,,,,,,,,,,, +P001,0,1,AN001,,,,,,,,,,,,,,,,,,,,, +P002,0,2,AN002,,,,,,,,,,,,,,,,,,,,, +P003,0,3,AN003,,,,,,,,,,,,,,,,,,,,, +P004,0,4,AN004,,,,,,,,,,,,,,,,,,,,, +P005,0,5,AN011,,,,,,,,,,,,,,,,,,,,, +P006,0,6,AN012,,,,,,,,,,,,,,,,,,,,, +P007,0,7,AN013,,,,,,,,,,,,,,,,,,,,, +P008,0,8,AN014,,,,,,,,,,,,,,,,,,,,, +-,0,9,,,,,,,,,,,,,,,,,,,,,, +P010,0,10,AN005,,,,,,,,,,,,,,,,,,,,, +P011,0,11,AN006,,,,,,,,,,,,,,,,,,,,, +P012,0,12,AN007,,,,,,,,,,,,,,,,,,,,, +P013,0,13,AN008,,,,,,,,,,,,,,,,,,,,, +P014,0,14,AN009,,,,,,,,,,,,,,,,,,,,, +P015,0,15,AN010,,,,,,,,,,,,,,,,,,,,, +P100,1,0,AN022,IRQ2,,AGTIO0,GTETRGA,GTIOC5B,RXD0/MISO0/SCL0,SCK1,MISOA,SCL1,KR00,,,,,VL1,,,,,, +P101,1,1,AN021,IRQ1,,AGTEE0,GTETRGB,GTIOC5A,TXD0/MOSI0/SDA0,CTS1_RTS1/SS1,MOSIA,SDA1,KR01,,,,,VL2,,,,,, +P102,1,2,AN020,,,AGTO0,GTOWLO,GTIOC2B,SCK0,TXD2/MOSI2/SDA2,RSPCKA,,KR02,,ADTRG0,,,VL3,,,CRX0,,, +P103,1,3,AN019,,,,GTOWUP,GTIOC2A,CTS0_RTS0/SS0,,SSLA0,,KR03,,,,,VL4,,,CTX0,,, +P104,1,4,,IRQ1,,,GTETRGB,GTIOC1B,RXD0/MISO0/SCL0,,SSLA1,,KR04,,,,,COM0,,,,,, +P105,1,5,,IRQ0,,,GTETRGA,GTIOC1A,,,SSLA2,,KR05,,,,,COM1,,,,,, +P106,1,6,,,,,,GTIOC0B,,,SSLA3,,KR06,,,,,COM2,,,,,, +P107,1,7,,,,,,GTIOC0A,,,,,KR07,,,,,COM3,,,,,, +P108,1,8,,,TMS/SWDIO,,GTOULO,GTIOC0B,,CTS9_RTS9/SS9,SSLB0,,,,,,,,,,,,, +P109,1,9,,,TDO/TRACESWO,,GTOVUP,GTIOC1A,SCK1,TXD9/MOSI9/SDA9,MOSIB,,,CLKOUT,,,TS10,SEG23,,,CTX0,,, +P110,1,10,,IRQ3,TDI,,GTOVLO,GTIOC1B,CTS2_RTS2/SS2,RXD9/MISO9/SCL9,MISOB,,,VCOUT,,,,SEG24,,,CRX0,,, +P111,1,11,,IRQ4,Hi-Z,,,GTIOC3A,SCK2,SCK9,RSPCKB,,,,,,TS12,CAPH,,,,,, +P112,1,12,,,,,,GTIOC3B,TXD2/MOSI2/SDA2,SCK1,SSLB0,,,,,,TSCAP,CAPL,,,,,SSIBCK0, +P113,1,13,,,,,,GTIOC2A,,,,,,,,,TS27,SEG00/COM4,,,,,SSILRCK0/SSIFS0, +P114,1,14,,,,,,GTIOC2B,,,,,,,,,TS29,SEG25,,,,,SSIRXD0, +P115,1,15,,,,,,GTIOC4A,,,,,,,,,TS35,SEG26,,,,,SSITXD0, +P200,2,0,,NMI,,,,,,,,,,,,,,,,,,,, +P201,2,1,,,MD,,,,,,,,,,,,,,,,,,, +P202,2,2,,,,,,GTIOC5B,SCK2,RXD9/MISO9/SCL9,MISOB,,,,,,,SEG16,,,,,, +P203,2,3,,,,,,GTIOC5A,CTS2_RTS2/SS2,TXD9/MOSI9/SDA9,MOSIB,,,,,,TSCAP,SEG15,,,,,, +P204,2,4,,,,,,GTIOC4B,SCK0,SCK9,RSPCKB,SCL0,,,CACREF,,TS00,SEG14,,,,,,USB_OVRCURB +P205,2,5,,IRQ1,,,,GTIOC4A,TXD0/MOSI0/SDA0,CTS9_RTS9/SS9,SSLB0,SCL1,,CLKOUT,,,TSCAP,SEG13,,,,,,USB_OVRCURA +P206,2,6,,IRQ0,,,,,RXD0/MISO0/SCL0,,SSLB1,SDA1,,,,,TS01,SEG12,,,,,,USB_VBUSEN +-,2,7,,,,,,,,,,,,,,,,,,,,,, +-,2,8,,,,,,,,,,,,,,,,,,,,,, +-,2,9,,,,,,,,,,,,,,,,,,,,,, +-,2,10,,,,,,,,,,,,,,,,,,,,,, +-,2,11,,,,,,,,,,,,,,,,,,,,,, +P212,2,12,,IRQ3,,AGTEE1,GTETRGB,GTIOC0B,,RXD1/MISO1/SCL1,,,,,,,,,,,,,, +P213,2,13,,IRQ2,,,GTETRGA,GTIOC0A,,TXD1/MOSI1/SDA1,,,,,,,,,,,,,, +P214,2,14,,,,,,,,,,,,,,,,,,,,,, +P215,2,15,,,,,,,,,,,,,,,,,,,,,, +P300,3,0,,,TCK/SWCLK,,GTOUUP,GTIOC0A,,,SSLB1,,,,,,,,,,,,, +P301,3,1,,IRQ6,,AGTIO0,GTOULO,GTIOC4B,RXD2/MISO2/SCL2,CTS9_RTS9/SS9,SSLB2,,,,,,TS09,SEG01/COM5,,,,,, +P302,3,2,,IRQ5,,,GTOUUP,GTIOC4A,TXD2/MOSI2/SDA2,,SSLB3,,,,,,TS08,SEG02/COM6,,,,,, +P303,3,3,,,,,,GTIOC7B,,,,,,,,,TS02,SEG03/COM7,,,,,, +P304,3,4,,IRQ9,,,,GTIOC7A,,,,,,,,,TS11,SEG20,,,,,, +P305,3,5,,IRQ8,,,,,,,,,,,,,,SEG19,,,,,, +P306,3,6,,,,,,,,,,,,,,,,SEG18,,,,,, +P307,3,7,,,,,,,,,,,,,,,,SEG17,,,,,, +-,3,8,,,,,,,,,,,,,,,,,,,,,, +-,3,8,,,,,,,,,,,,,,,,,,,,,, +-,3,10,,,,,,,,,,,,,,,,,,,,,, +-,3,11,,,,,,,,,,,,,,,,,,,,,, +-,3,12,,,,,,,,,,,,,,,,,,,,,, +-,3,13,,,,,,,,,,,,,,,,,,,,,, +-,3,14,,,,,,,,,,,,,,,,,,,,,, +-,3,15,,,,,,,,,,,,,,,,,,,,,, +P400,4,0,,IRQ0,,AGTIO1,,GTIOC6A,SCK0,SCK1,,SCL0,,,CACREF,,TS20,SEG04,,,,,AUDIO_CLK, +P401,4,1,,IRQ5,,,GTETRGA,GTIOC6B,CTS0_RTS0/SS0,TXD1/MOSI1/SDA1,,SDA0,,,,,TS19,SEG05,,,,,, +P402,4,2,,IRQ4,,AGTIO0*2/AGTIO1*2,,,,RXD1/MISO1/SCL1,,,,,,,TS18,SEG06,,,,,, +P403,4,3,,,,AGTIO0*2/AGTIO1*,,GTIOC3A,,CTS1_RTS1/SS1,,,,,,,TS17,,,,,,SSIBCK0, +P404,4,4,,,,,,GTIOC3B,,,,,,,,,,,,,,,SSILRCK0/SSIFS0, +P405,4,5,,,,,,GTIOC1A,,,,,,,,,,,,,,,SSITXD0, +P406,4,6,,,,,,GTIOC1B,,,,,,,,,,,,,,,SSIRXD0, +P407,4,7,,,,AGTIO0,,,CTS0_RTS0/SS0,,SSLB3,SDA0,,RTCOUT,ADTRG0,,TS03,SEG11,,,,,,USB_VBUS +P408,4,8,,IRQ7,,,GTOWLO,GTIOC5B,CTS1_RTS1/SS1,RXD9/MISO9/SCL9,,,,,,,TS04,SEG10,,,,,,USB_ID +P409,4,9,,IRQ6,,,GTOWUP,GTIOC5A,,TXD9/MOSI9/SDA9,,,,,,,TS05,SEG09,,,,,,USB_EXICEN +P410,4,10,,IRQ5,,AGTOB1,GTOVLO,GTIOC6B,RXD0/MISO0/SCL0,,MISOA,,,,,,TS06,SEG08,,,,,, +P411,4,11,,IRQ4,,AGTOA1,GTOVUP,GTIOC6A,TXD0/MOSI0/SDA0,,MOSIA,,,,,,TS07,SEG07,,,,,, +P412,4,12,,,,,,,SCK0,,RSPCKA,,,,,,,,,,,,, +P413,4,13,,,,,,,CTS0_RTS0/SS0,,SSLA0,,,,,,,,,,,,, +P414,4,14,,IRQ9,,,,GTIOC0B,,,SSLA1,,,,,,,,,,,,, +P415,4,15,,IRQ8,,,,GTIOC0A,,,SSLA2,,,,,,,,,,,,, +P500,5,0,AN016,,,AGTOA0,GTIU,GTIOC2A,,,,,,,,,,SEG34,,,,,,USB_VBUSEN +P501,5,1,AN017,IRQ11,,AGTOB0,GTIV,GTIOC2B,TXD1/MOSI1/SDA1,,,,,,,,,SEG35,,,,,,USB_OVRCURA +P502,5,2,AN018,IRQ12,,,GTIW,GTIOC3B,RXD1/MISO1/SCL1,,,,,,,,,SEG36,,,,,,USB_OVRCURB +P503,5,3,AN023,,,,,,SCK1,,,,,,,,,SEG37,,,,,,USB_EXICEN +P504,5,4,AN024,,,,,,CTS1_RTS1/SS1,,,,,,,,,,,,,,,USB_ID +P505,5,5,AN025,IRQ14,,,,,,,,,,,,,,,,,,,, +-,5,6,,,,,,,,,,,,,,,,,,,,,, +-,5,7,,,,,,,,,,,,,,,,,,,,,, +-,5,8,,,,,,,,,,,,,,,,,,,,,, +-,5,9,,,,,,,,,,,,,,,,,,,,,, +-,5,10,,,,,,,,,,,,,,,,,,,,,, +-,5,11,,,,,,,,,,,,,,,,,,,,,, +-,5,12,,,,,,,,,,,,,,,,,,,,,, +-,5,13,,,,,,,,,,,,,,,,,,,,,, +-,5,14,,,,,,,,,,,,,,,,,,,,,, +-,5,15,,,,,,,,,,,,,,,,,,,,,, +P600,6,0,,,,,,GTIOC6B,,SCK9,,,,,,,,SEG33,,,,,, +P601,6,1,,,,,,GTIOC6A,,RXD9/MISO9/SCL9,,,,,,,,SEG32,,,,,, +P602,6,2,,,,,,GTIOC7B,,TXD9/MOSI9/SDA9,,,,,,,,SEG31,,,,,, +P603,6,3,,,,,,GTIOC7A,,CTS9_RTS9/SS9,,,,,,,,SEG30,,,,,, +-,6,4,,,,,,,,,,,,,,,,,,,,,, +-,6,5,,,,,,,,,,,,,,,,,,,,,, +-,6,6,,,,,,,,,,,,,,,,,,,,,, +-,6,7,,,,,,,,,,,,,,,,,,,,,, +P608,6,8,,,,,,GTIOC4B,,,,,,,,,,SEG27,,,,,, +P609,6,9,,,,,,GTIOC5A,,,,,,,,,,SEG28,,,,,, +P610,6,10,,,,,,GTIOC5B,,,,,,,,,,SEG29,,,,,, +-,6,11,,,,,,,,,,,,,,,,,,,,,, +-,6,12,,,,,,,,,,,,,,,,,,,,,, +-,6,13,,,,,,,,,,,,,,,,,,,,,, +-,6,14,,,,,,,,,,,,,,,,,,,,,, +-,6,15,,,,,,,,,,,,,,,,,,,,,, +-,7,0,,,,,,,,,,,,,,,,,,,,,, +-,7,1,,,,,,,,,,,,,,,,,,,,,, +-,7,2,,,,,,,,,,,,,,,,,,,,,, +-,7,3,,,,,,,,,,,,,,,,,,,,,, +-,7,4,,,,,,,,,,,,,,,,,,,,,, +-,7,5,,,,,,,,,,,,,,,,,,,,,, +-,7,6,,,,,,,,,,,,,,,,,,,,,, +-,7,7,,,,,,,,,,,,,,,,,,,,,, +P708,7,8,,,,,,,,RXD1/MISO1/SCL1,SSLA3,,,,,,,,,,,,, +-,7,9,,,,,,,,,,,,,,,,,,,,,, +-,7,10,,,,,,,,,,,,,,,,,,,,,, +-,7,11,,,,,,,,,,,,,,,,,,,,,, +-,7,12,,,,,,,,,,,,,,,,,,,,,, +-,7,13,,,,,,,,,,,,,,,,,,,,,, +-,7,14,,,,,,,,,,,,,,,,,,,,,, +-,7,15,,,,,,,,,,,,,,,,,,,,,, +-,8,0,,,,,,,,,,,,,,,,,,,,,, +-,8,1,,,,,,,,,,,,,,,,,,,,,, +-,8,2,,,,,,,,,,,,,,,,,,,,,, +-,8,3,,,,,,,,,,,,,,,,,,,,,, +-,8,4,,,,,,,,,,,,,,,,,,,,,, +-,8,5,,,,,,,,,,,,,,,,,,,,,, +-,8,6,,,,,,,,,,,,,,,,,,,,,, +-,8,7,,,,,,,,,,,,,,,,,,,,,, +P808,8,8,,,,,,,,,,,,,,,,SEG21,,,,,, +P809,8,9,,,,,,,,,,,,,,,,SEG22,,,,,, +-,8,10,,,,,,,,,,,,,,,,,,,,,, +-,8,11,,,,,,,,,,,,,,,,,,,,,, +-,8,12,,,,,,,,,,,,,,,,,,,,,, +-,8,13,,,,,,,,,,,,,,,,,,,,,, +-,8,14,,,,,,,,,,,,,,,,,,,,,, +-,8,15,,,,,,,,,,,,,,,,,,,,,, +-,9,0,,,,,,,,,,,,,,,,,,,,,, +-,9,1,,,,,,,,,,,,,,,,,,,,,, +-,9,2,,,,,,,,,,,,,,,,,,,,,, +-,9,3,,,,,,,,,,,,,,,,,,,,,, +-,9,4,,,,,,,,,,,,,,,,,,,,,, +-,9,5,,,,,,,,,,,,,,,,,,,,,, +-,9,6,,,,,,,,,,,,,,,,,,,,,, +-,9,7,,,,,,,,,,,,,,,,,,,,,, +-,9,8,,,,,,,,,,,,,,,,,,,,,, +-,9,9,,,,,,,,,,,,,,,,,,,,,, +-,9,10,,,,,,,,,,,,,,,,,,,,,, +-,9,11,,,,,,,,,,,,,,,,,,,,,, +-,9,12,,,,,,,,,,,,,,,,,,,,,, +-,9,13,,,,,,,,,,,,,,,,,,,,,, +P914,9,14,,,,,,,,,,,,,,,,,,,,,,(USB_DP) +P915,9,14,,,,,,,,,,,,,,,,,,,,,,(USB_DM) diff --git a/ports/renesas-ra/boards/ra4w1_af.csv b/ports/renesas-ra/boards/ra4w1_af.csv new file mode 100644 index 000000000..8820846be --- /dev/null +++ b/ports/renesas-ra/boards/ra4w1_af.csv @@ -0,0 +1,161 @@ +CPU_PIN,PORT_IDX,PORT_BIT,Analog,IRQ,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,AF16,AF17,AF18,AF19 +-,0,0,,,,,,,,,,,,,,,,,,,,,, +-,0,1,,,,,,,,,,,,,,,,,,,,,, +-,0,2,,,,,,,,,,,,,,,,,,,,,, +-,0,3,,,,,,,,,,,,,,,,,,,,,, +P004,0,4,AN004,IRQ3,,,,,,,,,,,,,,,,,,,, +-,0,5,,,,,,,,,,,,,,,,,,,,,, +-,0,6,,,,,,,,,,,,,,,,,,,,,, +-,0,7,,,,,,,,,,,,,,,,,,,,,, +-,0,8,,,,,,,,,,,,,,,,,,,,,, +-,0,9,,,,,,,,,,,,,,,,,,,,,, +P010,0,10,AN005,IRQ14,,,,,,,,,,,,,,,,,,,, +P011,0,11,AN006,IRQ15,,,,,,,,,,,,,,,,,,,, +-,0,12,,,,,,,,,,,,,,,,,,,,,, +-,0,13,,,,,,,,,,,,,,,,,,,,,, +P014,0,14,AN009,,,,,,,,,,,,,,,,,,,,, +P015,0,15,AN010,IRQ7,,,,,,,,,,,,,,,,,,,, +P100,1,0,AN022,IRQ2,,AGTIO0,GTETRGA,GTIOC5B,RXD0/MISO0/SCL0,SCK1,MISOA,SCL1,KR00,,,,,VL1,,,,,, +P101,1,1,AN021,IRQ1,,AGTEE0,GTETRGB,GTIOC5A,TXD0/MOSI0/SDA0,CTS1_RTS1/SS1,MOSIA,SDA1,KR01,,,,,VL2,,,,,, +P102,1,2,AN020,,,AGTO0,GTOWLO,GTIOC2B,SCK0,TXD2/MOSI2/SDA2,RSPCKA,,KR02,,ADTRG0,,,VL3,,,CRX0,,, +P103,1,3,AN019,,,,GTOWUP,GTIOC2A,CTS0_RTS0/SS0,,SSLA0,,KR03,,,,,VL4,,,CTX0,,, +P104,1,4,,IRQ1,,,GTETRGB,GTIOC1B,RXD0/MISO0/SCL0,,SSLA1,,KR04,,,,TS13,COM0,,,,,, +P105,1,5,,IRQ0,,,GTETRGA,GTIOC1A,,,SSLA2,,KR05,,,,TS34,COM1,,,,,, +P106,1,6,,,,,,GTIOC0B,,,SSLA3,,KR06,,,,,COM2,,,,,, +P107,1,7,,,,,,GTIOC0A,,,,,KR07,,,,,COM3,,,,,, +P108,1,8,,,TMS/SWDIO,,GTOULO,GTIOC0B,,CTS9_RTS9/SS9,SSLB0,,,,,,,,,,,,, +P109,1,9,,,TDO/TRACESWO,,GTOVUP,GTIOC1A,SCK1,TXD9/MOSI9/SDA9,MOSIB,,,CLKOUT,,,TS10,SEG23,,,CTX0,,, +P110,1,10,,IRQ3,TDI,,GTOVLO,GTIOC1B,CTS2_RTS2/SS2,RXD9/MISO9/SCL9,MISOB,,,VCOUT,,,,SEG24,,,CRX0,,, +P111,1,11,,IRQ4,Hi-Z,,,GTIOC3A,SCK2,SCK9,RSPCKB,,,,,,TS12,CAPH,,,,,, +-,1,12,,,,,,,,,,,,,,,,,,,,,, +-,1,13,,,,,,,,,,,,,,,,,,,,,, +-,1,14,,,,,,,,,,,,,,,,,,,,,, +-,1,15,,,,,,,,,,,,,,,,,,,,,, +P200,2,0,,NMI,,,,,,,,,,,,,,,,,,,, +P201,2,1,,,MD,,,,,,,,,,,,,,,,,,, +-,2,2,,,,,,,,,,,,,,,,,,,,,, +-,2,3,,,,,,,,,,,,,,,,,,,,,, +P204,2,4,,,,AGTIO1,GTIW,GTIOC4B,SCK4,SCK9,RSPCKB,SCL0,,,CACREF,,TS00,SEG14,,,,,,USB_OVRCURB +P205,2,5,,IRQ1,,AGTO1,GTIV,GTIOC4A,TXD4/MOSI4/SDA4,CTS9_RTS9/SS9,SSLB0,SCL1,,CLKOUT,,,TSCAP,SEG13,,,,,,USB_OVRCURA +P206,2,6,,IRQ0,,,GTIU,,RXD4/MISO4/SCL4,,SSLB1,SDA1,,,,,TS01,SEG12,,,,,,USB_VBUSEN +-,2,7,,,,,,,,,,,,,,,,,,,,,, +-,2,8,,,,,,,,,,,,,,,,,,,,,, +-,2,9,,,,,,,,,,,,,,,,,,,,,, +-,2,10,,,,,,,,,,,,,,,,,,,,,, +-,2,11,,,,,,,,,,,,,,,,,,,,,, +P212,2,12,,IRQ3,,AGTEE1,GTETRGB,GTIOC0B,,RXD1/MISO1/SCL1,,,,,,,,,,,,,, +P213,2,13,,IRQ2,,,GTETRGA,GTIOC0A,,TXD1/MOSI1/SDA1,,,,,,,,,,,,,, +P214,2,14,,,,,,,,,,,,,,,,,,,,,, +P215,2,15,,,,,,,,,,,,,,,,,,,,,, +P300,3,0,,,TCK/SWCLK,,GTOUUP,GTIOC0A,,,SSLB1,,,,,,,,,,,,, +-,3,1,,,,,,,,,,,,,,,,,,,,,, +-,3,2,,,,,,,,,,,,,,,,,,,,,, +-,3,3,,,,,,,,,,,,,,,,,,,,,, +-,3,4,,,,,,,,,,,,,,,,,,,,,, +-,3,5,,,,,,,,,,,,,,,,,,,,,, +-,3,6,,,,,,,,,,,,,,,,,,,,,, +-,3,7,,,,,,,,,,,,,,,,,,,,,, +-,3,8,,, ,, , ,,, ,,,,,,,,,,,,, +-,3,9,,,,,,,,,,,,,,,,,,,,,, +-,3,10,,,,,,,,,,,,,,,,,,,,,, +-,3,11,,,,,,,,,,,,,,,,,,,,,, +-,3,12,,,,,,,,,,,,,,,,,,,,,, +-,3,13,,,,,,,,,,,,,,,,,,,,,, +-,3,14,,,,,,,,,,,,,,,,,,,,,, +-,3,15,,,,,,,,,,,,,,,,,,,,,, +-,4,0,,,,,,,,,,,,,,,,,,,,,, +-,4,1,,,,,,,,,,,,,,,,,,,,,, +P402,4,2,,IRQ4,,AGTIO0*2/AGTIO1*2,,,,RXD1/MISO1/SCL1,,,,,,,TS18,SEG06,,,,,, +-,4,3,,,,,,,,,,,,,,,,,,,,,, +P404,4,4,,,,,,GTIOC3B,,,,,,,,,,,,,,,SSILRCK0/SSIFS0, +-,4,5,,,,,,,,,,,,,,,,,,,,,, +-,4,6,,,,,,,,,,,,,,,,,,,,,, +P407,4,7,,,,AGTIO0,,,CTS4_RTS4/SS4,,SSLB3,SDA0,,RTCOUT,ADTRG0,,TS03,SEG11,,,,,,USB_VBUS +-,4,8,,,,,,,,,,,,,,,,,,,,,, +P409,4,9,,IRQ6,,,GTOWUP,GTIOC5A,,,,,,,,,,SEG09,,,,,, +-,4,10,,,,,,,,,,,,,,,,,,,,,, +-,4,11,,,,,,,,,,,,,,,,,,,,,, +-,4,12,,,,,,,,,,,,,,,,,,,,,, +-,4,13,,,,,,,,,,,,,,,,,,,,,, +P414,4,14,,IRQ9,,,,GTIOC0B,,,SSLA1,,,,,,,,,,,,, +-,4,15,,,,,,,,,,,,,,,,,,,,,, +-,5,0,,,,,,,,,,,,,,,,,,,,,, +P501,5,1,AN017,IRQ11,,AGTOB0,GTIV,GTIOC2B,,,,,,,,,,SEG49,,,,,, +-,5,2,,,,,,,,,,,,,,,,,,,,,, +-,5,3,,,,,,,,,,,,,,,,,,,,,, +-,5,4,,,,,,,,,,,,,,,,,,,,,, +-,5,5,,,,,,,,,,,,,,,,,,,,,, +-,5,6,,,,,,,,,,,,,,,,,,,,,, +-,5,7,,,,,,,,,,,,,,,,,,,,,, +-,5,8,,,,,,,,,,,,,,,,,,,,,, +-,5,9,,,,,,,,,,,,,,,,,,,,,, +-,5,10,,,,,,,,,,,,,,,,,,,,,, +-,5,11,,,,,,,,,,,,,,,,,,,,,, +-,5,12,,,,,,,,,,,,,,,,,,,,,, +-,5,13,,,,,,,,,,,,,,,,,,,,,, +-,5,14,,,,,,,,,,,,,,,,,,,,,, +-,5,15,,,,,,,,,,,,,,,,,,,,,, +-,6,0,,,,,,,,,,,,,,,,,,,,,, +-,6,1,,,,,,,,,,,,,,,,,,,,,, +-,6,2,,,,,,,,,,,,,,,,,,,,,, +-,6,3,,,,,,,,,,,,,,,,,,,,,, +-,6,4,,,,,,,,,,,,,,,,,,,,,, +-,6,5,,,,,,,,,,,,,,,,,,,,,, +-,6,6,,,,,,,,,,,,,,,,,,,,,, +-,6,7,,,,,,,,,,,,,,,,,,,,,, +-,6,8,,,,,,,,,,,,,,,,,,,,,, +-,6,9,,,,,,,,,,,,,,,,,,,,,, +-,6,10,,,,,,,,,,,,,,,,,,,,,, +-,6,11,,,,,,,,,,,,,,,,,,,,,, +-,6,12,,,,,,,,,,,,,,,,,,,,,, +-,6,13,,,,,,,,,,,,,,,,,,,,,, +-,6,14,,,,,,,,,,,,,,,,,,,,,, +-,6,15,,,,,,,,,,,,,,,,,,,,,, +-,7,0,,,,,,,,,,,,,,,,,,,,,, +-,7,1,,,,,,,,,,,,,,,,,,,,,, +-,7,2,,,,,,,,,,,,,,,,,,,,,, +-,7,3,,,,,,,,,,,,,,,,,,,,,, +-,7,4,,,,,,,,,,,,,,,,,,,,,, +-,7,5,,,,,,,,,,,,,,,,,,,,,, +-,7,6,,,,,,,,,,,,,,,,,,,,,, +-,7,7,,,,,,,,,,,,,,,,,,,,,, +-,7,8,,,,,,,,,,,,,,,,,,,,,, +-,7,9,,,,,,,,,,,,,,,,,,,,,, +-,7,10,,,,,,,,,,,,,,,,,,,,,, +-,7,11,,,,,,,,,,,,,,,,,,,,,, +-,7,12,,,,,,,,,,,,,,,,,,,,,, +-,7,13,,,,,,,,,,,,,,,,,,,,,, +-,7,14,,,,,,,,,,,,,,,,,,,,,, +-,7,15,,,,,,,,,,,,,,,,,,,,,, +-,8,0,,,,,,,,,,,,,,,,,,,,,, +-,8,1,,,,,,,,,,,,,,,,,,,,,, +-,8,2,,,,,,,,,,,,,,,,,,,,,, +-,8,3,,,,,,,,,,,,,,,,,,,,,, +-,8,4,,,,,,,,,,,,,,,,,,,,,, +-,8,5,,,,,,,,,,,,,,,,,,,,,, +-,8,6,,,,,,,,,,,,,,,,,,,,,, +-,8,7,,,,,,,,,,,,,,,,,,,,,, +-,8,8,,,,,,,,,,,,,,,,,,,,,, +-,8,9,,,,,,,,,,,,,,,,,,,,,, +-,8,10,,,,,,,,,,,,,,,,,,,,,, +-,8,11,,,,,,,,,,,,,,,,,,,,,, +-,8,12,,,,,,,,,,,,,,,,,,,,,, +-,8,13,,,,,,,,,,,,,,,,,,,,,, +-,8,14,,,,,,,,,,,,,,,,,,,,,, +-,8,15,,,,,,,,,,,,,,,,,,,,,, +-,9,0,,,,,,,,,,,,,,,,,,,,,, +-,9,1,,,,,,,,,,,,,,,,,,,,,, +-,9,2,,,,,,,,,,,,,,,,,,,,,, +-,9,3,,,,,,,,,,,,,,,,,,,,,, +-,9,4,,,,,,,,,,,,,,,,,,,,,, +-,9,5,,,,,,,,,,,,,,,,,,,,,, +-,9,6,,,,,,,,,,,,,,,,,,,,,, +-,9,7,,,,,,,,,,,,,,,,,,,,,, +-,9,8,,,,,,,,,,,,,,,,,,,,,, +-,9,9,,,,,,,,,,,,,,,,,,,,,, +-,9,10,,,,,,,,,,,,,,,,,,,,,, +-,9,11,,,,,,,,,,,,,,,,,,,,,, +-,9,12,,,,,,,,,,,,,,,,,,,,,, +-,9,13,,,,,,,,,,,,,,,,,,,,,, +P914,9,14,,,,,,,,,,,,,,,,,,,,,,(USB_DP) +P915,9,15,,,,,,,,,,,,,,,,,,,,,,(USB_DM) diff --git a/ports/renesas-ra/boards/ra6m1_af.csv b/ports/renesas-ra/boards/ra6m1_af.csv new file mode 100644 index 000000000..da7749e4c --- /dev/null +++ b/ports/renesas-ra/boards/ra6m1_af.csv @@ -0,0 +1,163 @@ +CPU_PIN,PORT_IDX,PORT_BIT,Analog,IRQ,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,AF16,AF17,AF18,AF19,AF20,AF21,AF22 +P000,0,0,AN000,IRQ6-DS,,,,,,,,,,,,,,,,,,,,,,, +P001,0,1,AN001,IRQ7-DS,,,,,,,,,,,,,,,,,,,,,,, +P002,0,2,AN002,IRQ8-DS,,,,,,,,,,,,,,,,,,,,,,, +P003,0,3,AN007,,,,,,,,,,,,,,,,,,,,,,,, +P004,0,4,AN100,IRQ9-DS,,,,,,,,,,,,,,,,,,,,,,, +P005,0,5,AN101,RQ10-DS,,,,,,,,,,,,,,,,,,,,,,, +P006,0,6,AN102,IRQ11-DS,,,,,,,,,,,,,,,,,,,,,,, +P007,0,7,AN107,,,,,,,,,,,,,,,,,,,,,,,, +P008,0,8,AN003,IRQ12-DS,,,,,,,,,,,,,,,,,,,,,,, +-,0,9,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,10,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,13,,,,,,,,,,,,,,,,,,,,,,,,, +P014,0,14,AN005,,,,,,,,,,,,,,,,,,,,,,,, +P015,0,15,AN006,IRQ13,,,,,,,,,,,,,,,,,,,,,,, +P100,1,0,AN022,IRQ2,,AGTIO0,GTETRGA,GTIOC5B,RXD0/MISO0/SCL0,SCK1,MISOA_A,SCL1_B,KR00,,,D00[A00/D00],,,,,,,,,,, +P101,1,1,AN021,IRQ1,,AGTEE0,GTETRGB,GTIOC5A,TXD0/MOSI0/SDA0,CTS1_RTS1/SS1,MOSIA_A,SDA1_B,KR01,,,D01[A01/D01],,,,,,,,,,, +P102,1,2,AN020,,,AGTO0,GTOWLO,GTIOC2B_A,SCK0,,RSPCKA_A,,KR02,,ADTRG0,D02[A02/D02],,,,,CRX0,,,,,, +P103,1,3,AN019,,,,GTOWUP,GTIOC2A_A,CTS0_RTS0/SS0,,SSLA0_A,,KR03,,,D03[A03/D03],,,,,CTX0,,,,,, +P104,1,4,,IRQ1,,,GTETRGB,GTIOC1B,RXD8/MISO8/SCL8,,SSLA1_A,,KR04,,,D04[A04/D04,,,,,,QIO0,,,,, +P105,1,5,,IRQ0,,,GTETRGA,GTIOC1A,TXD8/MOSI8/SDA8,,SSLA2_A,,KR05,,,D05[A05/D05],,,,,,QIO1,,,,, +P106,1,6,,,AGTOB0,,,GTIOC8B,SCK8,,SSLA3_A,,KR06,,,D06[A06/D06],,,,,,QIO2,,,,, +P107,1,7,,,AGTOA0,,,GTIOC8A,CTS8_RTS8/SS8,,,,KR07,,,D07[A07/D07],,,,,,QIO3,,,,, +P108,1,8,,,"TMS/ +SWDIO",,GTOULO,GTIOC0B_A,,CTS9_RTS9/SS9,SSLB0_B,,,,,,,,,,,,,,,, +P109,1,9,,,"TDO/ +TRACESWO",,GTOVUP,GTIOC1A_A,,TXD9/MOSI9/SDA9,MOSIB_B,,,CLKOUT,,,,,,,CTX1,,,,,, +P110,1,10,,IRQ3,TDI,,GTOVLO,GTIOC1B_A,CTS2_RTS2/SS2,RXD9/MISO9/SCL9,MISOB_B,,,VCOUT,,,,,,,CRX1,,,,,, +P111,1,11,,IRQ4,Hi-Z,,,GTIOC3A_A,SCK2,SCK9,RSPCKB_B,,,,,A05,,,,,,,,,,, +P112,1,12,,,,,,GTIOC3B_A,TXD2/MOSI2/SDA2,SCK1,SSLB0_B,,,,,A04,,,,,,,SSIBCK0,,,, +P113,1,13,,,,,,GTIOC2A,RXD2/MISO2/SCL2,,,,,,,A03,,,,,,,SSILRCK0/SSIFS0,,,, +P114,1,14,,,,,,GTIOC2B,,,,,,,,A02,,,,,,,SSIRXD0,,,, +P115,1,15,,,,,,GTIOC4A,,,,,,,,A01,,,,,,,SSITXD0,,,, +P200,2,0,,NMI,,,,,,,,,,,,,,,,,,,,,,, +P201,2,1,,,,,,,,,,,,,,,,,,,,,,,,, +-,2,2,,,,,,,,,,,,,,,,,,,,,,,,, +-,2,3,,,,,,,,,,,,,,,,,,,,,,,,, +-,2,4,,,,,,,,,,,,,,,,,,,,,,,,, +P205,2,5,,IRQ1-DS,,AGTO1,GTIV,GTIOC4A,TXD4/MOSI4/SDA4,CTS9_RTS9/SS9,,SCL1_A,,CLKOUT,,WAIT,TSCAP,,,,,,,USB_OVRCURA,,SD0DAT3_A, +P206,2,6,,IRQ0-DS,,,GTIU,,RXD4/MISO4/SCL4,,,SDA1_A,,,,,TS01,,,,,,,USB_VBUSEN,,SD0DAT2_A, +P207,2,7,,,,,,,,,,,,,,,,,,,,QSSL,,,,, +P208,2,8,,,,,GTOVL0,,,,,,,,,CS4,,,,,,QIO3,,,,SD0DAT0_B,TDATA3 +P209,2,9,,,,,GTOVUP,,,,,,,,,CS5,,,,,,QIO2,,,,SD0WP,TDATA2 +P210,2,10,,,,,GTIW,,,,,,,,,CS6,,,,,,QIO1,,,,SD0CD,TDATA1 +P211,2,11,,,,,GTIV,,,,,,,,,CS7,,,,,,QIO0,,,,SD0CMD_B,TDATA0 +P212,2,12,,IRQ3,,AGTEE1,GTETRGD,GTIOC0B,,RXD1/MISO1/SCL1,,,,,,,,,,,,,,,,, +P213,2,13,,IRQ2,,,GTETRGC,GTIOC0A,,TXD1/MOSI1/SDA1,,,,,,,,,,,,,,,,, +P214,2,14,,,,,GTIU,,,,,,,,,,,,,,,QSPCLK,,,,SD0CLK_B, TCLK +-,2,15,,,,,,,,,,,,,,,,,,,,,,,,, +P300,3,0,,,TCK/SWCLK,,,GTIOC0A_A,,,SSLB1_B,,,,,,,,,,,,,,,, +P301,3,1,,IRQ6,,AGTIO0,GTOULO,GTIOC4B,RXD2/MISO2/SCL2,CTS9_RTS9/SS9,SSLB2_B,,,,,A06,,,,,,,,,,, +P302,3,2,,IRQ5,,,GTOUUP,GTIOC4A,TXD2/MOSI2/SDA2,,SSLB3_B,,,,,A07,,,,,,,,,,, +P303,3,3,,,,,,GTIOC7B,,,,,,,,A08,,,,,,,,,,, +P304,3,4,,IRQ9,,,GTOWLO,GTIOC7A,,,,,,,,A09,,,,,,,,,,, +P305,3,5,,IRQ8,,,GTOWUP,,,,,,,,,A10,,,,,,QSPCLK,,,,, +P306,3,6,,,,,,,,,,,,,,A11,,,,,,QSSL,,,,, +P307,3,7,,,,,,,,,,,,,,A12,,,,,,QIO0,,,,, +-,3,8,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,9,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,10,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,13,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,14,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,15,,,,,,,,,,,,,,,,,,,,,,,,, +P400,4,0,,IRQ0,,AGTIO1,,GTIOC6A,SCK4,,,SCL0_A,,,ADTRG1,,,,,,,,AUDIO_CLK,,,, +P401,4,1,,IRQ5-DS,,,GTETRGA,GTIOC6B,CTS4_RTS4/SS4,,,SDA0_A,,,,,,,,,,,,,,, +P402,4,2,,IRQ4-DS,,,,,,,,,,,CACREF,,,,,,,,AUDIO_CLK,,,, +P403,4,3,,,,,,GTIOC3A,,,,,,,,,,,,,,,SSIBCK0_A,,,, +P404,4,4,,,,,,GTIOC3B,,,,,,,,,,,,,,,SSILRCK0/SSIFS0_A,,,, +P405,4,5,,,,,,GTIOC1A,,,,,,,,,,,,,,,SSITXD0_A,,,, +P406,4,6,,,,,,GTIOC1B,,,,,,,,,,,,,,,SSIRXD0_A,,,, +P407,4,7,,,,AGTIO0,,,CTS4_RTS4/SS4,,,SDA0_B,,RTCOUT,ADTRG0,,TS03,,,,,,,USB_VBUS,,, +P408,4,8,,IRQ7,,,GTOWLO,GTIOC10B,CTS1_RTS1/SS1,RXD3/MISO3/SCL3,,,,,,,TS04,,,,,,,USB_ID,,, +P409,4,9,,IRQ6,,,GTOWUP,GTIOC10A,,TXD3/MOSI3/SDA3,,,,,,,TS05,,,,,,,USB_EXICEN,,, +P410,4,10,,IRQ5,,AGTOB1,GTOVLO,GTIOC9B,RXD0/MISO0/SCL0,SCK3,MISOA_B,,,,,,TS06,,,,,,,,,SD0DAT1_A, +P411,4,11,,IRQ4,,AGTOA1,GTOVUP,GTIOC9A,TXD0/MOSI0/SDA0,CTS3_RTS3/SS3,MOSIA_B,,,,,,TS07,,,,,,,,,SD0DAT0_A, +P412,4,12,,,,AGTEE1,GTOULO,,SCK0,,RSPCKA_B,,,,,,TS08,,,,,,,,,SD0CMD_A, +P413,4,13,,,,,GTOUUP,,CTS0_RTS0/SS0,,SSLA0_B,,,,,,TS09,,,,,,,,,SD0CLK_A, +P414,4,14,,IRQ9,,,,GTIOC0B,,,SSLA1_B,,,,,,TS10,,,,,,,,,SD0WP, +P415,4,15,,IRQ8,,,,GTIOC0A,,,SSLA2_B,,,,,,TS11,,,,,,,USB_VBUSEN,,SD0CD, +P500,5,0,AN016,,,AGTOA0,GTIU,GTIOC11A,,,,,,,,,,,,,,QSPCLK,,USB_VBUSEN,,SD1CLK_A , +P501,5,1,AN116,IRQ11,,AGTOB0,GTIV,GTIOC11B,,,,,,,,,,,,,,QSSL,,USB_OVRCURA,,SD1CMD_A, +P502,5,2,AN017,IRQ12,,,GTIW, GTIOC12A,,,,,,,,,,,,,,QIO0,,USB_OVRCURB,,SD1DAT0_A, +P503,5,3,AN117,,,,GTETRGC,GTIOC12B,,,,,,,,,,,,,,QIO1,,USB_EXICEN,,SD1DAT1_A, +P504,5,4,AN018,,,,GTETRGD,,,,,,,,,,,,,,,QIO2,,USB_ID,,SD1DAT2_A, +-,5,5,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,6,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,7,,,,,,,,,,,,,,,,,,,,,,,,, +P508,5,8,AN020,,,,,,,,,,,,,,,,,,,,,,,SD1DAT3_A, +-,5,9,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,10,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,13,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,14,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,15,,,,,,,,,,,,,,,,,,,,,,,,, +P600,6,0,,,,,,GTIOC6B,,SCK9,,,,CLKOUT,CACREF,RD,,,,,,,,,,, +P601,6,1,,,,,,GTIOC6A,,RXD9,,,,,,WR0,,,,,,,,,,, +P602,6,2,,,,,,GTIOC7B,,TXD9,,,,,,EBCLK,,,,,,,,,,, +P603,6,3,,,,,,GTIOC7A,,,,,,,,,,,,,,,,,,, +-,6,4,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,5,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,6,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,7,,,,,,,,,,,,,,,,,,,,,,,,, +P608,6,8,,,,,,GTIOC4B,,,,,,,,A00,,,,,,,,,,, +P609,6,9,,,,,,GTIOC5A,,,,,,,,CS1,,,,,CTX1,,,,,, +P610,6,10,,,,,,GTIOC5B,,,,,,,,CS0,,,,,CRX1,,,,,, +-,6,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,13,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,14,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,15,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,0,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,1,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,2,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,3,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,4,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,5,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,6,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,7,,,,,,,,,,,,,,,,,,,,,,,,, +P708,7,8,,IRQ11,,,,,,RXD1/MISO1/SCL1,SSLA3_B,,,,CACREF,,TS12,,,,,,AUDIO_CLK,,,, +-,7,9,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,10,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,13,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,14,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,15,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,0,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,1,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,2,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,3,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,4,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,5,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,6,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,7,,,,,,,,,,,,,,,,,,,,,,,,, +P808,8,8,,,,,,,,,,,,,,,,,,,,,,,,, +P809,8,9,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,10,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,13,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,14,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,15,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,0,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,1,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,2,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,3,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,4,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,5,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,6,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,7,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,8,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,9,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,10,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,11,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,12,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,13,,,,,,,,,,,,,,,,,,,,,,,,, +P914,9,14,,,,,,,,,,,,,,,,,,,,,,(USB_DP),,, +P915,9,15,,,,,,,,,,,,,,,,,,,,,,(USB_DM),,, diff --git a/ports/renesas-ra/boards/ra6m2_af.csv b/ports/renesas-ra/boards/ra6m2_af.csv new file mode 100644 index 000000000..e956a4425 --- /dev/null +++ b/ports/renesas-ra/boards/ra6m2_af.csv @@ -0,0 +1,161 @@ +CPU_PIN,PORT_IDX,PORT_BIT,Analog,IRQ,AF0,AF1,AF2,AF3,AF4,AF5,AF6,AF7,AF8,AF9,AF10,AF11,AF12,AF13,AF14,AF15,AF16,AF17,AF18,AF19,AF20,AF21,AF22,,, +P000,0,0,AN000,IRQ6-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P001,0,1,AN001,IRQ7-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P002,0,2,AN002,IRQ8-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P003,0,3,AN007,,,,,,,,,,,,,,,,,,,,,,,,,,, +P004,0,4,AN100,IRQ9-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P005,0,5,AN101,RQ10-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P006,0,6,AN102,IRQ11-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P007,0,7,AN107,,,,,,,,,,,,,,,,,,,,,,,,,,, +P008,0,8,AN003,IRQ12-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +P009,0,9,AN004,IRQ13-DS,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,10,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,11,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,12,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,0,13,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P014,0,14,AN005,,,,,,,,,,,,,,,,,,,,,,,,,,, +P015,0,15,AN006,IRQ13,,,,,,,,,,,,,,,,,,,,,,,,,, +P100,1,0,AN022,IRQ2,,AGTIO0,GTETRGA,GTIOC5B,RXD0/MISO0/SCL0,SCK1,MISOA_A,SCL1_B,KR00,,,D00[A00/D00],,,,,,,,,,,,,, +P101,1,1,AN021,IRQ1,,AGTEE0,GTETRGB,GTIOC5A,TXD0/MOSI0/SDA0,CTS1_RTS1/SS1,MOSIA_A,SDA1_B,KR01,,,D01[A01/D01],,,,,,,,,,,,,, +P102,1,2,AN020,,,AGTO0,GTOWLO,GTIOC2B_A,SCK0,,RSPCKA_A,,KR02,,ADTRG0,D02[A02/D02],,,,,CRX0,,,,,,,,, +P103,1,3,AN019,,,,GTOWUP,GTIOC2A_A,CTS0_RTS0/SS0,,SSLA0_A,,KR03,,,D03[A03/D03],,,,,CTX0,,,,,,,,, +P104,1,4,,IRQ1,,,GTETRGB,GTIOC1B,RXD8/MISO8/SCL8,,SSLA1_A,,KR04,,,D04[A04/D04,,,,,,QIO0,,,,,,,, +P105,1,5,,IRQ0,,,GTETRGA,GTIOC1A,TXD8/MOSI8/SDA8,,SSLA2_A,,KR05,,,D05[A05/D05],,,,,,QIO1,,,,,,,, +P106,1,6,,,AGTOB0,,,GTIOC8B,SCK8,,SSLA3_A,,KR06,,,D06[A06/D06],,,,,,QIO2,,,,,,,, +P107,1,7,,,AGTOA0,,,GTIOC8A,CTS8_RTS8/SS8,,,,KR07,,,D07[A07/D07],,,,,,QIO3,,,,,,,, +P108,1,8,,,TMS/SWDIO,,GTOULO,GTIOC0B_A,,CTS9_RTS9/SS9,SSLB0_B,,,,,,,,,,,,,,,,,,, +P109,1,9,,,TDO/TRACESWO,,GTOVUP,GTIOC1A_A,,TXD9/MOSI9/SDA9,MOSIB_B,,,CLKOUT,,,,,,,CTX1,,,,,,,,, +P110,1,10,,IRQ3,TDI,,GTOVLO,GTIOC1B_A,CTS2_RTS2/SS2,RXD9/MISO9/SCL9,MISOB_B,,,VCOUT,,,,,,,CRX1,,,,,,,,, +P111,1,11,,IRQ4,Hi-Z,,,GTIOC3A_A,SCK2,SCK9,RSPCKB_B,,,,,A05,,,,,,,,,,,,,, +P112,1,12,,,,,,GTIOC3B_A,TXD2/MOSI2/SDA2,SCK1,SSLB0_B,,,,,A04,,,,,,,SSIBCK0_B,,,,,,, +P113,1,13,,,,,,GTIOC2A,RXD2/MISO2/SCL2,,,,,,,A03,,,,,,,SSILRCK0/SSIFS0_B,,,,,,, +P114,1,14,,,,,,GTIOC2B,,,,,,,,A02,,,,,,,SSIRXD0_B,,,,,,, +P115,1,15,,,,,,GTIOC4A,,,,,,,,A01,,,,,,,SSITXD0_B,,,,,,, +P200,2,0,,NMI,,,,,,,,,,,,,,,,,,,,,,,,,, +P201,2,1,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P202,2,2,,IRQ3-DS,,,,GTIOC5B,SCK2,RXD9/MISO9/SCL9,MISOB_A,,,,,WR1/BC1,,,,,,,,,,SD0DAT6_A,ET0_ERXD2,,, +P203,2,3,,IRQ2-DS,,,,GTIOC5A,CTS2_RTS2/SS2,TXD9/MOSI9/SDA9,MOSIB_A,,,,,A19,TSCAP,,,,,,,,,SD0DAT5_A,ET0_COL,,, +P204,2,4,,,,,,GTIOC4B,SCK4,SCK9,RSPCKB_A,SCL0_B,,,CACREF,A18,TS00,,,,,,SSIBCK0_C,USB_OVRCURB-DS,,SD0DAT4_A ,ET0_RX_DV,,, +P205,2,5,,IRQ1-DS,,AGTO1,GTIV,GTIOC4A,TXD4/MOSI4/SDA4,CTS9_RTS9/SS9,SSLB0_A,SCL1_A,,CLKOUT,,A16,TSCAP,,,,,,SSILRCK0/SSIFS0_C,URB-DSUSB_OVRCURA-DS,,SD0DAT3_A,ET0_WOL,ET0_WOL,, +P206,2,6,,IRQ0-DS,,,GTIU,,RXD4/MISO4/SCL4,,SSLB1_A,SDA1_A,,,,WAIT,TS01,,,,,,SSIDATA0_C,USB_VBUSEN,,SD0DAT2_A,ET0_LINKSTA,ET0_LINKSTA,, +P207,2,7,,,,,,,,,SSLB2_A,,,,,A17,TS02,,,,,QSSL,,,,,,,, +P208,2,8,,,,,GTOVL0,,,,,,,,,CS4,,,,,,QIO3,,,,SD0DAT0_B,ET0_LINKST,ET0_LINKST,,TDATA3 +P209,2,9,,,,,GTOVUP,,,,,,,,,CS5,,,,,,QIO2,,,,SD0WP,ET0_EXOUT,ET0_EXOUT,,TDATA2 +P210,2,10,,,,,GTIW,,,,,,,,,CS6,,,,,,QIO1,,,,SD0CD,ET0_WOL,ET0_WOL,,TDATA1 +P211,2,11,,,,,GTIV,,,,,,,,,CS7,,,,,,QIO0,,,,SD0CMD_B,ET0_MDIO,ET0_MDIO,,TDATA0 +P212,2,12,,IRQ3,,AGTEE1,GTETRGD,GTIOC0B,,RXD1/MISO1/SCL1,,,,,,,,,,,,,,,,,,,, +P213,2,13,,IRQ2,,,GTETRGC,GTIOC0A,,TXD1/MOSI1/SDA1,,,,,ADTRG1,,,,,,,,,,,,,,, +P214,2,14,,,,,GTIU,,,,,,,,,,,,,,,QSPCLK,,,,SD0CLK_B,ET0_MDC,ET0_MDC,, TCLK +-,2,15,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P300,3,0,,,TCK/SWCLK,,,GTIOC0A_A,,,SSLB1_B,,,,,,,,,,,,,,,,,,, +P301,3,1,,IRQ6,,AGTIO0,GTOULO,GTIOC4B,RXD2/MISO2/SCL2,CTS9_RTS9/SS9,SSLB2_B,,,,,A06,,,,,,,,,,,,,, +P302,3,2,,IRQ5,,,GTOUUP,GTIOC4A,TXD2/MOSI2/SDA2,,SSLB3_B,,,,,A07,,,,,,,,,,,,,, +P303,3,3,,,,,,GTIOC7B,,,,,,,,A08,,,,,,,,,,,,,, +P304,3,4,,IRQ9,,,GTOWLO,GTIOC7A,RXD6/MISO6/SCL6,,,,,,,A09,,,,,,,,,,,,,, +P305,3,5,,IRQ8,,,GTOWUP,,TXD6/MOSI6/SDA6,,,,,,,A10,,,,,,QSPCLK,,,,,,,, +P306,3,6,,,,,GTOULO,,SCK6,,,,,,,A11,,,,,,QSSL,,,,,,,, +P307,3,7,,,,,GTOUUP,,CTS6_RTS6/SS6,,,,,,,A12,,,,,,QIO0,,,,,,,, +P308,3,8,,,,,,,,,,,,,,A13,,,,,,QIO1,,,,,,,, +P309,3,9,,,,,,,,RXD3,,,,,,A14,,,,,,QIO2,,,,,,,, +P310,3,10,,,,AGTEE1,,,,TXD3,,,,,,A15,,,,,,QIO3,,,,,,,, +P311,3,11,,,,AGTOB1,,,,SCK3,,,,,,CS2/RAS,,,,,,,,,,,,,, +P312,3,12,,,,AGTOA1,,,,CTS3_RTS3/SS3,,,,,,CS3/CAS,,,,,,,,,,,,,, +P313,3,13,,,,,,,,,,,,,,A20,,,,,,,,,,SD0DAT7_A,ET0_ERXD3,,, +-,3,14,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,3,15,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P400,4,0,,IRQ0,,AGTIO1,,GTIOC6A,SCK4,SCK7,,SCL0_A,,,ADTRG1,,,,,,,,AUDIO_CLK,,,,ET0_WOL,ET0_WOL,, +P401,4,1,,IRQ5-DS,,,GTETRGA,GTIOC6B,CTS4_RTS4/SS4,TXD7/MOSI7/SDA7,,SDA0_A,,,,,,,,,CTX0,,,,,,ET0_MDC,ET0_MDC,, +P402,4,2,,IRQ4-DS,,,,,,RXD7/MISO7/SCL7,,,,,CACREF,,,,,,CRX0,,AUDIO_CLK,,,,ET0_MDIO,ET0_MDIO,VSYNC, +P403,4,3,,,,,,GTIOC3A,,CTS7_RTS7/SS7,,,,,,,,,,,,,SSIBCK0_A,,,SD1DAT7_B,ET0_LINKSTA,ET0_LINKSTA,PIXD7, +P404,4,4,,,,,,GTIOC3B,,,,,,,,,,,,,,,SSILRCK0/SSIFS0_A,,,SD1DAT6_B,ET0_EXOUT,ET0_EXOUT,PIXD6, +P405,4,5,,,,,,GTIOC1A,,,,,,,,,,,,,,,SSITXD0_A,,,SD1DAT5_B,ET0_TX_EN,RMII0_TXD_EN_B,PIXD5, +P406,4,6,,,,,,GTIOC1B,,,SSLB3_C,,,,,,,,,,,,SSIRXD0_A,,,SD1DAT4_B,ET0_RX_ER,RMII0_TXD1_B,PIXD4, +P407,4,7,,,,AGTIO0,,,CTS4_RTS4/SS4,,SSLB3_A,SDA0_B,,RTCOUT,ADTRG0,,TS03,,,,,,,USB_VBUS,,,ET0_EXOUT,ET0_EXOUT,, +P408,4,8,,IRQ7,,,GTOWLO,GTIOC10B,,RXD3/MISO3/SCL3,,SCL0_B,,,,,TS04,,,,,,,USB_ID,,,ET0_CRS,RMII0_CRS_DV_A,PIXCLK, +P409,4,9,,IRQ6,,,GTOWUP,GTIOC10A,,TXD3/MOSI3/SDA3,,,,,,,TS05,,,,,,,USB_EXICEN,,,ET0_RX_CLK,RMII0_RX_ER_A,HSYNC, +P410,4,10,,IRQ5,,AGTOB1,GTOVLO,GTIOC9B,RXD0/MISO0/SCL0,SCK3,MISOA_B,,,,,,TS06,,,,,,,,,SD0DAT1_A,ET0_ERXD0,RMII0_RXD1_A,PIXD0, +P411,4,11,,IRQ4,,AGTOA1,GTOVUP,GTIOC9A,TXD0/MOSI0/SDA0,CTS3_RTS3/SS3,MOSIA_B,,,,,,TS07,,,,,,,,,SD0DAT0_A,ET0_ERXD1,RMII0_RXD0_A,PIXD1, +P412,4,12,,,,AGTEE1,GTOULO,,SCK0,,RSPCKA_B,,,,,,TS08,,,,,,,,,SD0CMD_A,ET0_ETXD0,REF50CK0_A,PIXD2, +P413,4,13,,,,,GTOUUP,,CTS0_RTS0/SS0,,SSLA0_B,,,,,,TS09,,,,,,,,,SD0CLK_A,ET0_ETXD1,RMII0_TXD0_A,PIXD3, +P414,4,14,,IRQ9,,,,GTIOC0B,,,SSLA1_B,,,,,,TS10,,,,,,,,,SD0WP,,RMII0_TXD1_A,PIXD4, +P415,4,15,,IRQ8,,,,GTIOC0A,,,SSLA2_B,,,,,,TS11,,,,,,,USB_VBUSEN,,SD0CD,ET0_TX_EN,RMII0_TXD_EN_A,PIXD5, +P500,5,0, AN016,,,AGTOA0,GTIU,GTIOC11A,,,,,,,,,,,,,,QSPCLK,,USB_VBUSEN,,SD1CLK_A ,,,, +P501,5,1,AN116,IRQ11,,AGTOB0,GTIV,GTIOC11B,,TXD5/MOSI5/SDA5,,,,,,,,,,,,QSSL,,USB_OVRCURA,,SD1CMD_A,,,, +P502,5,2,AN017,IRQ12,,,GTIW, GTIOC12A,,RXD5/MISO5/SCL5,,,,,,,,,,,,QIO0,,USB_OVRCURB,,SD1DAT0_A,,,, +P503,5,3,AN117,,,,GTETRGC,GTIOC12B,CTS6_RTS6/SS6,SCK5,,,,,,,,,,,,QIO1,,USB_EXICEN,,SD1DAT1_A,,,, +P504,5,4,AN018,,,,GTETRGD,GTIOC13A,SCK6,CTS5_RTS5/SS5,,,,,,,,,,,,QIO2,,USB_ID,,SD1DAT2_A,,,, +P505,5,5,AN118,IRQ14,,,,GTIOC13B,RXD6/MISO6/SCL6,,,,,,,,,,,,,QIO3,,,,SD1DAT3_A,,,, +P506,5,6,AN019,IRQ15,,,,,TXD6/MOSI6/SDA6,,,,,,,,,,,,,,,,,SD1CD,,,, +-,5,7,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P508,5,8,AN020,,,,,GTIOC0B,SCK6,SCK5,,,,,,,,,,,,,,,,SD1DAT3_A,,,, +-,5,9,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,10,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P511,5,11,,IRQ15,,,,RXD4/MISO4/SCL4,RXD4/MISO4/SCL4,,,SDA2,,,,,,,,,CRX1,,,,,,,,PCKO, +P512,5,12,,IRQ14,,,,TXD4/MOSI4/SDA4,TXD4/MOSI4/SDA4,,,SCL2,,,,,,,,,CTX1,,,,,,,,VSYNC, +-,5,13,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,14,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,5,15,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P600,6,0,,,,,,GTIOC6B,,SCK9,,,,CLKOUT,CACREF,RD,,,,,,,,,,,,,, +P601,6,1,,,,,,GTIOC6A,,RXD9,,,,,,WR/WR0/DQM00,,,,,,,,,,,,,, +P602,6,2,,,,,,GTIOC7B,,TXD9,,,,,,EBCLK/SDCLK,,,,,,,,,,,,,, +P603,6,3,,,,,,GTIOC7A,,CTS9_RTS9/SS9,,,,,,D13[A13/D13]/DQ13,,,,,,,,,,,,,, +P604,6,4,,,,,,GTIOC8B,,,,,,,,D12[A12/D12]/DQ12,,,,,,,,,,,,,, +P605,6,5,,,,,,GTIOC8A,,,,,,,,D11[A11/D11]/DQ11,,,,,,,,,,,,,, +-,6,6,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,6,7,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P608,6,8,,,,,,GTIOC4B,,,,,,,,A00/BC0/DQM1,,,,,,,,,,,,,, +P609,6,9,,,,,,GTIOC5A,,,,,,,,CS1/CKE ,,,,,CTX1,,,,,,,,, +P610,6,10,,,,,,GTIOC5B,,,,,,,,CS0/WE,,,,,CRX1,,,,,,,,, +P611,6,11,,,,,,,CTS7_RTS7/SS7,,,,,,,SDCS,,,,,,,,,,,,,, +P612,6,12,,,,,,,SCK7,,,,,,,D08[A08/D08]/DQ08,,,,,,,,,,,,,, +P613,6,13,,,,,,,TXD7,,,,,,,D09[A09/D09]/DQ09,,,,,,,,,,,,,, +P614,6,14,,,,,,,RXD7,,,,,,,D10[A10/D10]/DQ10,,,,,,,,,,,,,, +-,6,15,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P700,7,0,,,,,,GTIOC5A,,,MISOB_C,,,,,,,,,,,,,,,SD1DAT3_B,ET0_ETXD1,RMII0_TXD0_B,PIXD3, +P701,7,1,,,,,,GTIOC5B,,,MOSIB_C,,,,,,,,,,,,,,,SD1DAT2_B,ET0_ETXD0,REF50CK0_B,PIXD2, +P702,7,2,,,,,,GTIOC6A,,,RSPCKB_C,,,,,,,,,,,,,,,SD1DAT1_B,ET0_ERXD1,RMII0_RXD0_B,PIXD1, +P703,7,3,,,,,,GTIOC6B,,,SSLB0_C,,,VCOUT,,,,,,,,,,,,SD1DAT0_B,ET0_ERXD0,RMII0_RXD1_B,PIXD0, +P704,7,4,,,,AGTO0,,,,,SSLB1_C,,,,,,,,,,CTX0,,,,,SD1CLK_B,ET0_RX_CLK,RMII0_RX_ER_B,HSYNC, +P705,7,5,,,,AGTIO0,,,,,SSLB2_C,,,,,,,,,,CRX0,,,,,SD1CMD_B,ET0_CRS,RMII0_CRS_DV_B,PIXCLK, +-,7,6,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,7,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P708,7,8,,IRQ11,,,,,,RXD1/MISO1/SCL1,SSLA3_B,,,,CACREF,,TS12,,,,,,AUDIO_CLK,,,,ET0_ETXD3,,PCKO, +P709,7,9,,IRQ10,,,,,,TXD1/MOSI1/SDA1,,,,,,,TS13,,,,,,,,,,ET0_ETXD2,,, +P710,7,10,,,,,,,,SCK1,,,,,,,TS14,,,,,,,,,,ET0_TX_ER,,, +P711,7,11,,,,AGTEE0,,,,CTS1_RTS1/SS1,,,,,,,TS15,,,,,,,,,,ET0_TX_CLK,,, +P712,7,12,,,,AGTOB0,,GTIOC2B,,,,,,,,,TS16,,,,,,,,,,,,, +P713,7,13,,,,AGTOA0,,GTIOC2A,,,,,,,,,TS17,,,,,,,,,,,,, +-,7,14,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,7,15,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P800,8,0,,,,,,,,,,,,,,D14[A14/D14]/DQ14,,,,,,,,,,,,,, +P801,8,1,,,,,,,,,,,,,,D15[A15/D15]/DQ15,,,,,,,,,,,,,, +-,8,2,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,3,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,4,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,5,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,6,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,7,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P808,8,8,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P809,8,9,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,10,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,11,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,12,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,13,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,14,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,8,15,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,0,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,1,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,2,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,3,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,4,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,5,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,6,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,7,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,8,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,9,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,10,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,11,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,12,,,,,,,,,,,,,,,,,,,,,,,,,,,, +-,9,13,,,,,,,,,,,,,,,,,,,,,,,,,,,, +P914,9,14,,,,,,,,,,,,,,,,,,,,,,(USB_DP),,,,,, +P915,9,15,,,,,,,,,,,,,,,,,,,,,,(USB_DM),,,,,, diff --git a/ports/renesas-ra/boards/ra_pin_prefix.c b/ports/renesas-ra/boards/ra_pin_prefix.c new file mode 100644 index 000000000..78b7878dd --- /dev/null +++ b/ports/renesas-ra/boards/ra_pin_prefix.c @@ -0,0 +1,37 @@ +// ra_pin_prefix.c becomes the initial portion of the generated pins file. + +#include <stdio.h> + +#include "py/obj.h" +#include "py/mphal.h" +#include "pin.h" + +#if 0 +#define AF(af_idx, af_fn, af_unit, af_type, af_ptr) \ + { \ + { &pin_af_type }, \ + .name = MP_QSTR_AF##af_idx##_##af_fn##af_unit, \ + .idx = (af_idx), \ + .fn = AF_FN_##af_fn, \ + .unit = (af_unit), \ + .type = AF_PIN_TYPE_##af_fn##_##af_type, \ + .af_fn = (af_ptr) \ + } +#endif + +#define PIN_AD(p_name, p_pin, ad_bit, ad_channel) \ + { \ + { &machine_pin_type }, \ + .name = MP_QSTR_##p_name, \ + .pin = p_pin, \ + .bit = ad_bit, \ + .channel = ad_channel \ + } + +#define PIN(p_name, p_pin, p_ad) \ + { \ + { &machine_pin_type }, \ + .name = MP_QSTR_##p_name, \ + .pin = p_pin, \ + .ad = p_ad, \ + } diff --git a/ports/renesas-ra/build_all_boards.sh b/ports/renesas-ra/build_all_boards.sh new file mode 100644 index 000000000..49b1cab85 --- /dev/null +++ b/ports/renesas-ra/build_all_boards.sh @@ -0,0 +1,26 @@ +#!/bin/bash +set -eu -o pipefail +export BOARD="RA4M1_CLICKER" +DT=`date +%Y%m%d%H%M` +make DEBUG=1 BOARD=${BOARD} clean 2>&1 | tee ${BOARD}_build_${DT}.log +make DEBUG=1 BOARD=${BOARD} 2>&1 | tee -a ${BOARD}_build_${DT}.log +# +export BOARD="RA6M2_EK" +DT=`date +%Y%m%d%H%M` +make DEBUG=1 BOARD=${BOARD} clean 2>&1 | tee ${BOARD}_build_${DT}.log +make DEBUG=1 BOARD=${BOARD} 2>&1 | tee -a ${BOARD}_build_${DT}.log +# +export BOARD="RA4M1_EK" +DT=`date +%Y%m%d%H%M` +make DEBUG=1 BOARD=${BOARD} clean 2>&1 | tee ${BOARD}_build_${DT}.log +make DEBUG=1 BOARD=${BOARD} 2>&1 | tee -a ${BOARD}_build_${DT}.log +# +export BOARD="RA4W1_EK" +DT=`date +%Y%m%d%H%M` +make DEBUG=1 BOARD=${BOARD} clean 2>&1 | tee ${BOARD}_build_${DT}.log +make DEBUG=1 BOARD=${BOARD} 2>&1 | tee -a ${BOARD}_build_${DT}.log +# +export BOARD="RA6M1_EK" +DT=`date +%Y%m%d%H%M` +make DEBUG=1 BOARD=${BOARD} clean 2>&1 | tee ${BOARD}_build_${DT}.log +make DEBUG=1 BOARD=${BOARD} 2>&1 | tee -a ${BOARD}_build_${DT}.log diff --git a/ports/renesas-ra/extint.c b/ports/renesas-ra/extint.c new file mode 100644 index 000000000..c3ad26ebe --- /dev/null +++ b/ports/renesas-ra/extint.c @@ -0,0 +1,402 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021, 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stddef.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/gc.h" +#include "py/mphal.h" +#include "pendsv.h" +#include "pin.h" +#include "extint.h" +#include "irq.h" +#if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) | defined(RA6M1) | defined(RA6M2) | defined(RA6M3) +#include "ra_icu.h" +#endif + +/// \moduleref pyb +/// \class ExtInt - configure I/O pins to interrupt on external events +/// +/// There are a total of 16 interrupt irq_nos. These can come from GPIO pins. +/// +/// For irq_nos 0 thru 15, a given irq_no can map to the corresponding irq_no from an +/// arbitrary port. +/// +/// def callback(irq_no): +/// print("irq_no =", irq_no) +/// +/// Note: ExtInt will automatically configure the gpio irq_no as an input. +/// +/// extint = pyb.ExtInt(pin, pyb.ExtInt.IRQ_FALLING, pyb.Pin.PULL_UP, callback) +/// +/// Now every time a falling edge is seen on the X1 pin, the callback will be +/// called. Caution: mechanical pushbuttons have "bounce" and pushing or +/// releasing a switch will often generate multiple edges. +/// See: http://www.eng.utah.edu/~cs5780/debouncing.pdf for a detailed +/// explanation, along with various techniques for debouncing. +/// +/// Trying to register 2 callbacks onto the same pin will throw an exception. +/// +/// If pin is passed as an integer, then it is assumed to map to one of the +/// internal interrupt sources, and must be in the range 16. +/// +/// All other pin objects go through the pin mapper to come up with one of the +/// gpio pins. +/// +/// extint = pyb.ExtInt(pin, mode, pull, callback) +/// +/// Valid modes are pyb.ExtInt.IRQ_RISING, pyb.ExtInt.IRQ_FALLING, +/// pyb.ExtInt.IRQ_RISING_FALLING, pyb.ExtInt.EVT_RISING, +/// pyb.ExtInt.EVT_FALLING, and pyb.ExtInt.EVT_RISING_FALLING. +/// +/// +/// Valid pull values are pyb.Pin.PULL_UP, pyb.Pin.PULL_NONE. +/// +/// There is also a C API, so that drivers which require EXTI interrupt irq_nos +/// can also use this code. See extint.h for the available functions and +/// usrsw.h for an example of using this. + +// TODO Add python method to change callback object. + + +typedef struct { + mp_obj_base_t base; + mp_int_t pin_idx; + mp_int_t irq_no; +} extint_obj_t; + +STATIC uint8_t pyb_extint_mode[EXTI_NUM_VECTORS]; +STATIC bool pyb_extint_hard_irq[EXTI_NUM_VECTORS]; + +// The callback arg is a small-int or a ROM Pin object, so no need to scan by GC +mp_obj_t pyb_extint_callback_arg[EXTI_NUM_VECTORS]; +uint extint_irq_no[EXTI_NUM_VECTORS]; + +void extint_callback(void *param) { + uint irq_no = *((uint *)param); + mp_obj_t *cb = &MP_STATE_PORT(pyb_extint_callback)[irq_no]; + if (*cb != mp_const_none) { + mp_sched_lock(); + // When executing code within a handler we must lock the GC to prevent + // any memory allocations. We must also catch any exceptions. + gc_lock(); + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + mp_call_function_1(*cb, pyb_extint_callback_arg[irq_no]); + nlr_pop(); + } else { + // Uncaught exception; disable the callback so it doesn't run again. + *cb = mp_const_none; + ra_icu_disable_irq_no(irq_no); + printf("Uncaught exception in ExtInt interrupt handler line %u\n", (unsigned int)irq_no); + mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val)); + } + gc_unlock(); + mp_sched_unlock(); + } +} + +// Set override_callback_obj to true if you want to unconditionally set the +// callback function. +uint extint_register(mp_obj_t pin_obj, uint32_t mode, uint32_t pull, mp_obj_t callback_obj, bool override_callback_obj) { + const machine_pin_obj_t *pin = NULL; + uint pin_idx; + uint8_t v_line = 0xff; + if (mp_obj_is_int(pin_obj)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin object is not specified")); + } else { + pin = machine_pin_find(pin_obj); + pin_idx = pin->pin; + bool find = ra_icu_find_irq_no((uint32_t)pin_idx, (uint8_t *)&v_line); + if (!find) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("The Pin object(%d) doesn't have EXTINT feature"), pin_idx); + } + } + if (pull != GPIO_NOPULL && + pull != GPIO_PULLUP) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid ExtInt Pull: %d"), pull); + } + mp_obj_t *cb = &MP_STATE_PORT(pyb_extint_callback)[v_line]; + if (!override_callback_obj && *cb != mp_const_none && callback_obj != mp_const_none) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("ExtInt vector %d is already in use"), v_line); + } + + // We need to update callback atomically, so we disable the line + // before we update anything. + + extint_disable(v_line); + + *cb = callback_obj; + // ToDo: mode should be handled + pyb_extint_mode[v_line] = mode; + pyb_extint_callback_arg[v_line] = MP_OBJ_NEW_SMALL_INT(v_line); + if (*cb != mp_const_none) { + pyb_extint_callback_arg[v_line] = MP_OBJ_NEW_SMALL_INT(v_line); + pyb_extint_hard_irq[v_line] = true; + + if (pin == NULL) { + // pin will be NULL for non GPIO EXTI lines + extint_trigger_mode(v_line, mode); + extint_enable(v_line); + } else { + extint_irq_no[v_line] = (uint)v_line; + ra_icu_set_callback((uint8_t)v_line, (ICU_CB)extint_callback, (void *)&extint_irq_no[v_line]); + ra_icu_set_pin(pin_idx, true, true); + ra_icu_enable_pin(pin_idx); + extint_trigger_mode(v_line, mode); + extint_enable(v_line); + } + } + return v_line; +} + +// This function is intended to be used by the Pin.irq() method +void extint_register_pin(const machine_pin_obj_t *pin, uint32_t mode, bool hard_irq, mp_obj_t callback_obj) { + uint32_t line = 0; + + bool find = ra_icu_find_irq_no((uint32_t)pin->pin, (uint8_t *)&line); + if (!find) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("The Pin object(%d) doesn't have EXTINT feature"), (uint32_t)pin->pin); + } + + // Check if the ExtInt line is already in use by another Pin/ExtInt + mp_obj_t *cb = &MP_STATE_PORT(pyb_extint_callback)[line]; + if (*cb != mp_const_none && MP_OBJ_FROM_PTR(pin) != pyb_extint_callback_arg[line]) { + if (mp_obj_is_small_int(pyb_extint_callback_arg[line])) { + mp_raise_msg_varg(&mp_type_OSError, MP_ERROR_TEXT("ExtInt vector %d is already in use"), line); + } else { + const machine_pin_obj_t *other_pin = MP_OBJ_TO_PTR(pyb_extint_callback_arg[line]); + mp_raise_msg_varg(&mp_type_OSError, + MP_ERROR_TEXT("IRQ resource already taken by Pin('%q')"), other_pin->name); + } + } + + extint_disable(line); + + *cb = callback_obj; + // ToDo: mode should be handled + pyb_extint_mode[line] = mode; + + if (*cb != mp_const_none) { + // Configure and enable the callback + + pyb_extint_hard_irq[line] = hard_irq; + pyb_extint_callback_arg[line] = MP_OBJ_FROM_PTR(pin); + + extint_trigger_mode(line, mode); + + // Configure the NVIC + ra_icu_priority_irq_no((uint8_t)line, (uint32_t)IRQ_PRI_EXTINT); + extint_irq_no[line] = (uint)line; + ra_icu_set_callback((uint8_t)line, (ICU_CB)extint_callback, (void *)&extint_irq_no[line]); + + // Enable the interrupt + extint_enable(line); + } +} + +void extint_enable(uint line) { + if (line >= EXTI_NUM_VECTORS) { + return; + } + mp_uint_t irq_state = disable_irq(); + ra_icu_enable_irq_no((uint8_t)line); + enable_irq(irq_state); +} + +void extint_disable(uint line) { + if (line >= EXTI_NUM_VECTORS) { + return; + } + mp_uint_t irq_state = disable_irq(); + ra_icu_disable_irq_no((uint8_t)line); + enable_irq(irq_state); +} + +void extint_swint(uint line) { + if (line >= EXTI_NUM_VECTORS) { + return; + } + ra_icu_swint((uint8_t)line); +} + +void extint_trigger_mode(uint line, uint32_t mode) { + if (line >= EXTI_NUM_VECTORS) { + return; + } + mp_uint_t irq_state = disable_irq(); + + // cond: 0: falling, 1: rising, 2: both edge, 3 low level + // Enable or disable the rising detector + uint32_t cond = 0; + if ((mode == GPIO_MODE_IT_RISING) || (mode == GPIO_MODE_EVT_RISING)) { + cond = 1; + } else if ((mode == GPIO_MODE_IT_FALLING) || (mode == GPIO_MODE_EVT_FALLING)) { + cond = 0; + } else if ((mode == GPIO_MODE_IT_RISING_FALLING) || (mode == GPIO_MODE_EVT_RISING_FALLING)) { + cond = 2; + } else if (mode == GPIO_IRQ_LOWLEVEL) { + cond = 3; + } else { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("The device doesn't have (%d) feature"), (uint32_t)mode); + } + ra_icu_trigger_irq_no((uint8_t)line, cond); + enable_irq(irq_state); +} + +/// \method irq_no() +/// Return the irq_no number that the pin is mapped to. +STATIC mp_obj_t extint_obj_irq_no(mp_obj_t self_in) { + extint_obj_t *self = MP_OBJ_TO_PTR(self_in); + uint8_t irq_no; + bool find = ra_icu_find_irq_no(self->pin_idx, &irq_no); + if (find) { + return MP_OBJ_NEW_SMALL_INT(self->irq_no); + } else { + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_irq_no_obj, extint_obj_irq_no); + +/// \method enable() +/// Enable a disabled interrupt. +STATIC mp_obj_t extint_obj_enable(mp_obj_t self_in) { + extint_obj_t *self = MP_OBJ_TO_PTR(self_in); + ra_icu_enable_pin(self->pin_idx); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_enable_obj, extint_obj_enable); + +/// \method disable() +/// Disable the interrupt associated with the ExtInt object. +/// This could be useful for debouncing. +STATIC mp_obj_t extint_obj_disable(mp_obj_t self_in) { + extint_obj_t *self = MP_OBJ_TO_PTR(self_in); + ra_icu_disable_pin(self->pin_idx); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_disable_obj, extint_obj_disable); + +/// \method swint() +/// Trigger the callback from software. +STATIC mp_obj_t extint_obj_swint(mp_obj_t self_in) { + extint_obj_t *self = MP_OBJ_TO_PTR(self_in); + ra_icu_swint(self->irq_no); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(extint_obj_swint_obj, extint_obj_swint); + +// TODO document as a staticmethod +/// \classmethod regs() +/// Dump the values of the EXTI registers. +STATIC mp_obj_t extint_regs(void) { + printf("Not Implemented\n"); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(extint_regs_fun_obj, extint_regs); +STATIC MP_DEFINE_CONST_STATICMETHOD_OBJ(extint_regs_obj, MP_ROM_PTR(&extint_regs_fun_obj)); + +/// \classmethod \constructor(pin, mode, pull, callback) +/// Create an ExtInt object: +/// +/// - `pin` is the pin on which to enable the interrupt (can be a pin object or any valid pin name). +/// - `mode` can be one of: +/// - `ExtInt.IRQ_RISING` - trigger on a rising edge; +/// - `ExtInt.IRQ_FALLING` - trigger on a falling edge; +/// - `ExtInt.IRQ_RISING_FALLING` - trigger on a rising or falling edge. +/// - `pull` can be one of: +/// - `pyb.Pin.PULL_NONE` - no pull up or down resistors; +/// - `pyb.Pin.PULL_UP` - enable the pull-up resistor; +/// - `pyb.Pin.PULL_DOWN` - enable the pull-down resistor. +/// - `callback` is the function to call when the interrupt triggers. The +/// callback function must accept exactly 1 argument, which is the irq_no that +/// triggered the interrupt. +STATIC const mp_arg_t pyb_extint_make_new_args[] = { + { MP_QSTR_pin, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_pull, MP_ARG_REQUIRED | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_callback, MP_ARG_REQUIRED | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, +}; +#define PYB_EXTINT_MAKE_NEW_NUM_ARGS MP_ARRAY_SIZE(pyb_extint_make_new_args) + +STATIC mp_obj_t extint_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // type_in == extint_obj_type + + // parse args + mp_arg_val_t vals[PYB_EXTINT_MAKE_NEW_NUM_ARGS]; + mp_arg_parse_all_kw_array(n_args, n_kw, args, PYB_EXTINT_MAKE_NEW_NUM_ARGS, pyb_extint_make_new_args, vals); + + extint_obj_t *self = m_new_obj(extint_obj_t); + machine_pin_obj_t *pin = vals[0].u_obj; + self->base.type = type; + self->pin_idx = pin->pin; + self->irq_no = extint_register(vals[0].u_obj, vals[1].u_int, vals[2].u_int, vals[3].u_obj, false); + + return MP_OBJ_FROM_PTR(self); +} + +STATIC void extint_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + extint_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "<ExtInt irq_no=%u>", self->irq_no); +} + +STATIC const mp_rom_map_elem_t extint_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_irq_no), MP_ROM_PTR(&extint_obj_irq_no_obj) }, + { MP_ROM_QSTR(MP_QSTR_line), MP_ROM_PTR(&extint_obj_irq_no_obj) }, + { MP_ROM_QSTR(MP_QSTR_enable), MP_ROM_PTR(&extint_obj_enable_obj) }, + { MP_ROM_QSTR(MP_QSTR_disable), MP_ROM_PTR(&extint_obj_disable_obj) }, + { MP_ROM_QSTR(MP_QSTR_swint), MP_ROM_PTR(&extint_obj_swint_obj) }, + { MP_ROM_QSTR(MP_QSTR_regs), MP_ROM_PTR(&extint_regs_obj) }, + + // class constants + /// \constant IRQ_RISING - interrupt on a rising edge + /// \constant IRQ_FALLING - interrupt on a falling edge + /// \constant IRQ_RISING_FALLING - interrupt on a rising or falling edge + { MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(GPIO_MODE_IT_RISING) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(GPIO_MODE_IT_FALLING) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_RISING_FALLING), MP_ROM_INT(GPIO_MODE_IT_RISING_FALLING) }, +}; + +STATIC MP_DEFINE_CONST_DICT(extint_locals_dict, extint_locals_dict_table); + +const mp_obj_type_t extint_type = { + { &mp_type_type }, + .name = MP_QSTR_ExtInt, + .print = extint_obj_print, + .make_new = extint_make_new, + .locals_dict = (mp_obj_dict_t *)&extint_locals_dict, +}; + +void extint_init0(void) { + ra_icu_init(); + ra_icu_deinit(); + for (int i = 0; i < PYB_EXTI_NUM_VECTORS; i++) { + MP_STATE_PORT(pyb_extint_callback)[i] = mp_const_none; + } +} diff --git a/ports/renesas-ra/extint.h b/ports/renesas-ra/extint.h new file mode 100644 index 000000000..a3e1ca15c --- /dev/null +++ b/ports/renesas-ra/extint.h @@ -0,0 +1,47 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RA_EXTINT_H +#define MICROPY_INCLUDED_RA_EXTINT_H + +#include "py/mphal.h" + +#define EXTI_RTC_WAKEUP (16) +#define EXTI_NUM_VECTORS (PYB_EXTI_NUM_VECTORS) +extern mp_obj_t pyb_extint_callback_arg[]; + +void extint_callback(void *param); +void extint_init0(void); +uint extint_register(mp_obj_t pin_obj, uint32_t mode, uint32_t pull, mp_obj_t callback_obj, bool override_callback_obj); +void extint_register_pin(const machine_pin_obj_t *pin, uint32_t mode, bool hard_irq, mp_obj_t callback_obj); +void extint_enable(uint line); +void extint_disable(uint line); +void extint_swint(uint line); +void extint_trigger_mode(uint line, uint32_t mode); + +extern const mp_obj_type_t extint_type; + +#endif // MICROPY_INCLUDED_RA_EXTINT_H diff --git a/ports/renesas-ra/factoryreset.c b/ports/renesas-ra/factoryreset.c new file mode 100644 index 000000000..9a44d3dc4 --- /dev/null +++ b/ports/renesas-ra/factoryreset.c @@ -0,0 +1,111 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2019 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mperrno.h" +#include "extmod/vfs_fat.h" +#include "systick.h" +#include "led.h" +#include "storage.h" +#include "factoryreset.h" + +#if MICROPY_HW_ENABLE_STORAGE + +#if MICROPY_VFS_FAT + +static const char fresh_boot_py[] = + "# boot.py -- run on boot-up\r\n" + "# can run arbitrary Python, but best to keep it minimal\r\n" +; + +static const char fresh_main_py[] = + "# main.py -- put your code here!\r\n" +; + +typedef struct _factory_file_t { + const char *name; + size_t len; + const char *data; +} factory_file_t; + +static const factory_file_t factory_files[] = { + {"boot.py", sizeof(fresh_boot_py) - 1, fresh_boot_py}, + {"main.py", sizeof(fresh_main_py) - 1, fresh_main_py}, +}; + +MP_WEAK void factory_reset_make_files(FATFS *fatfs) { + for (int i = 0; i < MP_ARRAY_SIZE(factory_files); ++i) { + const factory_file_t *f = &factory_files[i]; + FIL fp; + FRESULT res = f_open(fatfs, &fp, f->name, FA_WRITE | FA_CREATE_ALWAYS); + if (res == FR_OK) { + UINT n; + f_write(&fp, f->data, f->len, &n); + f_close(&fp); + } + } +} + +MP_WEAK int factory_reset_create_filesystem(void) { + // LED on to indicate creation of local filesystem + led_state(RA_LED1, 1); + uint32_t start_tick = HAL_GetTick(); + + fs_user_mount_t vfs; + pyb_flash_init_vfs(&vfs); + uint8_t working_buf[FF_MAX_SS]; + FRESULT res = f_mkfs(&vfs.fatfs, FM_FAT, 0, working_buf, sizeof(working_buf)); + if (res != FR_OK) { + mp_printf(&mp_plat_print, "MPY: can't create flash filesystem\n"); + return -MP_ENODEV; + } + + // Set label + f_setlabel(&vfs.fatfs, MICROPY_HW_FLASH_FS_LABEL); + + // Populate the filesystem with factory files + factory_reset_make_files(&vfs.fatfs); + + // Keep LED on for at least 200ms + systick_wait_at_least(start_tick, 200); + led_state(RA_LED1, 0); + + mp_printf(&mp_plat_print, "MPY: created flash filesystem\n"); + + return 0; // success +} + +#else + +// If FAT is not enabled then it's up to the board to create a fresh filesystem. +MP_WEAK int factory_reset_create_filesystem(void) { + return 0; // success +} + +#endif // MICROPY_VFS_FAT + +#endif // MICROPY_HW_ENABLE_STORAGE diff --git a/ports/renesas-ra/factoryreset.h b/ports/renesas-ra/factoryreset.h new file mode 100644 index 000000000..526f0b4ce --- /dev/null +++ b/ports/renesas-ra/factoryreset.h @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_FACTORYRESET_H +#define MICROPY_INCLUDED_RENESAS_RA_FACTORYRESET_H + +#include "lib/oofatfs/ff.h" + +void factory_reset_make_files(FATFS *fatfs); +int factory_reset_create_filesystem(void); + +#endif // MICROPY_INCLUDED_RENESAS_RA_FACTORYRESET_H diff --git a/ports/renesas-ra/fatfs_port.c b/ports/renesas-ra/fatfs_port.c new file mode 100644 index 000000000..1e4f3144e --- /dev/null +++ b/ports/renesas-ra/fatfs_port.c @@ -0,0 +1,50 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "lib/oofatfs/ff.h" +#if MICROPY_HW_ENABLE_RTC +#include "rtc.h" +#endif + +MP_WEAK DWORD get_fattime(void) { + #if MICROPY_HW_ENABLE_RTC + rtc_init_finalise(); + ra_rtc_t time; + ra_rtc_get_time(&time); + int year = time.year; + int month = time.month; + int date = time.date; + int hour = time.hour; + int minute = time.minute; + int second = time.second; + return ((year) << 25) | ((month) << 21) | ((date) << 16) | ((hour) << 11) | ((minute) << 5) | (second / 2); + #else + // Jan 1st, 2018 at midnight. Not sure what timezone. + return ((2018 - 1980) << 25) | ((1) << 21) | ((1) << 16) | ((0) << 11) | ((0) << 5) | (0 / 2); + #endif +} diff --git a/ports/renesas-ra/flash.c b/ports/renesas-ra/flash.c new file mode 100644 index 000000000..3501be13c --- /dev/null +++ b/ports/renesas-ra/flash.c @@ -0,0 +1,58 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mpconfig.h" +#include "py/misc.h" +#include "py/mphal.h" +#include "flash.h" + +typedef struct { + uint32_t base_address; + uint32_t sector_size; + uint32_t sector_count; +} flash_layout_t; + +uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size) { + *start_addr = sector_start(addr); + *size = sector_size(addr); + return sector_index(addr); +} + +bool flash_erase(uint32_t flash_dest, uint32_t num_word32) { + // check there is something to write + if (num_word32 == 0) { + return true; + } + bool ret = internal_flash_eraseblock((unsigned char *)flash_dest); + return ret; +} + +bool flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32) { + bool ret; + ret = internal_flash_write((unsigned char *)flash_dest, num_word32, (uint8_t *)src, false); + return ret; +} diff --git a/ports/renesas-ra/flash.h b/ports/renesas-ra/flash.h new file mode 100644 index 000000000..4b76b581e --- /dev/null +++ b/ports/renesas-ra/flash.h @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RA_FLASH_H +#define MICROPY_INCLUDED_RA_FLASH_H + +uint32_t flash_get_sector_info(uint32_t addr, uint32_t *start_addr, uint32_t *size); +bool flash_erase(uint32_t flash_dest, uint32_t num_word32); +bool flash_write(uint32_t flash_dest, const uint32_t *src, uint32_t num_word32); + +#endif // MICROPY_INCLUDED_RA_FLASH_H diff --git a/ports/renesas-ra/flashbdev.c b/ports/renesas-ra/flashbdev.c new file mode 100644 index 000000000..8fb20c66e --- /dev/null +++ b/ports/renesas-ra/flashbdev.c @@ -0,0 +1,321 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2018 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include <string.h> + +#include "py/obj.h" +#include "py/mperrno.h" +#include "irq.h" +#include "led.h" +#include "flash.h" +#include "storage.h" +#if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) | defined(RA6M1) | defined(RA6M2) | defined(RA6M3) +#include "ra_flash.h" +#endif + +#if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE + +// #define DEBUG_FLASH_BDEV + +// Here we try to automatically configure the location and size of the flash +// pages to use for the internal storage. We also configure the location of the +// cache used for writing. + +#if defined(RA4M1) + +STATIC byte flash_cache_mem[0x800] __attribute__((aligned(16))); // 2K +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x800) // 2k max +#define FLASH_MEM_SEG1_START_ADDR (0x37000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (72) // sectors 1,2,...,72 + +#elif defined(RA4M3) +STATIC byte flash_cache_mem[0x800] __attribute__((aligned(16))); // 2K +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x800) // 2k max +#define FLASH_MEM_SEG1_START_ADDR (0x37000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (72) // sectors 1,2,...,72 + +#elif defined(RA4W1) +STATIC byte flash_cache_mem[0x800] __attribute__((aligned(16))); // 2K +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x800) // 2k max +#define FLASH_MEM_SEG1_START_ADDR (0x70000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (128) // sectors 1,2,...,128 + +#elif defined(RA6M1) +STATIC byte flash_cache_mem[0x8000] __attribute__((aligned(16))); // 32K +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x8000) // 32k max +#define FLASH_MEM_SEG1_START_ADDR (0x60000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (256) // sectors 1,2,...,256 + +#elif defined(RA6M2) +STATIC byte flash_cache_mem[0x8000] __attribute__((aligned(16))); // 32K +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x8000) // 32k max +#define FLASH_MEM_SEG1_START_ADDR (0xe0000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (512) // sectors 1,2,...,512 + +#elif defined(RA6M3) +STATIC byte flash_cache_mem[0x8000] __attribute__((aligned(16))); // 32K +#define CACHE_MEM_START_ADDR (&flash_cache_mem[0]) +#define FLASH_SECTOR_SIZE_MAX (0x8000) // 32k max +#define FLASH_MEM_SEG1_START_ADDR (0x60000) // sector 1 +#define FLASH_MEM_SEG1_NUM_BLOCKS (256) // sectors 1,2,...,256 + +#else +#error "no internal flash storage support for this MCU" +#endif + +#if !defined(FLASH_MEM_SEG2_START_ADDR) +#define FLASH_MEM_SEG2_START_ADDR (0) // no second segment +#define FLASH_MEM_SEG2_NUM_BLOCKS (0) // no second segment +#endif + +#define FLASH_FLAG_DIRTY (1) +#define FLASH_FLAG_FORCE_WRITE (2) +#define FLASH_FLAG_ERASED (4) +static volatile uint8_t flash_flags = 0; +static uint32_t flash_cache_sector_id; +static uint32_t flash_cache_sector_start; +static uint32_t flash_cache_sector_size; +static long flash_tick_counter_last_write; + +void flash_bdev_irq_handler(void); + +int32_t flash_bdev_ioctl(uint32_t op, uint32_t arg) { + (void)arg; + switch (op) { + case BDEV_IOCTL_INIT: + flash_flags = 0; + flash_cache_sector_id = 0; + flash_tick_counter_last_write = 0L; + return 0; + + case BDEV_IOCTL_NUM_BLOCKS: + return FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS; + + case BDEV_IOCTL_IRQ_HANDLER: + flash_bdev_irq_handler(); + return 0; + + case BDEV_IOCTL_SYNC: + if (flash_flags & FLASH_FLAG_DIRTY) { + flash_flags |= FLASH_FLAG_FORCE_WRITE; + flash_bdev_irq_handler(); + // while (flash_flags & FLASH_FLAG_DIRTY) { + // NVIC->STIR = FLASH_IRQn; + // } + } + return 0; + } + // return -MP_EINVAL; + return -1; +} + +static uint8_t *flash_cache_get_addr_for_write(uint32_t flash_addr) { + uint32_t flash_sector_start; + uint32_t flash_sector_size; + uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); + if (flash_sector_size > FLASH_SECTOR_SIZE_MAX) { + flash_sector_size = FLASH_SECTOR_SIZE_MAX; + } + if (flash_cache_sector_id != flash_sector_id) { + flash_bdev_ioctl(BDEV_IOCTL_SYNC, 0); + memcpy((void *)CACHE_MEM_START_ADDR, (const void *)flash_sector_start, flash_sector_size); + flash_cache_sector_id = flash_sector_id; + flash_cache_sector_start = flash_sector_start; + flash_cache_sector_size = flash_sector_size; + } + flash_flags |= FLASH_FLAG_DIRTY; + led_state(RA_LED1, 1); // indicate a dirty cache with LED on + flash_tick_counter_last_write = (long)HAL_GetTick(); + return (uint8_t *)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; +} + +void flash_cache_commit(void) { + if (flash_flags & FLASH_FLAG_DIRTY) { + if (((long)HAL_GetTick() - flash_tick_counter_last_write) > 1000) { + flash_bdev_irq_handler(); + } + } +} + +static uint8_t *flash_cache_get_addr_for_read(uint32_t flash_addr) { + uint32_t flash_sector_start; + uint32_t flash_sector_size; + uint32_t flash_sector_id = flash_get_sector_info(flash_addr, &flash_sector_start, &flash_sector_size); + if (flash_cache_sector_id == flash_sector_id) { + // in cache, copy from there + return (uint8_t *)CACHE_MEM_START_ADDR + flash_addr - flash_sector_start; + } + // not in cache, copy straight from flash + return (uint8_t *)flash_addr; +} + +static uint32_t convert_block_to_flash_addr(uint32_t block) { + if (block < FLASH_MEM_SEG1_NUM_BLOCKS) { + return FLASH_MEM_SEG1_START_ADDR + block * FLASH_BLOCK_SIZE; + } + if (block < FLASH_MEM_SEG1_NUM_BLOCKS + FLASH_MEM_SEG2_NUM_BLOCKS) { + return FLASH_MEM_SEG2_START_ADDR + (block - FLASH_MEM_SEG1_NUM_BLOCKS) * FLASH_BLOCK_SIZE; + } + // can add more flash segments here if needed, following above pattern + + // bad block + return -1; +} + +void flash_bdev_irq_handler(void) { + if (!(flash_flags & FLASH_FLAG_DIRTY)) { + return; + } + + // This code uses interrupts to erase the flash + /* + if (flash_erase_state == 0) { + flash_erase_it(flash_cache_sector_start, flash_cache_sector_size / 4); + flash_erase_state = 1; + return; + } + + if (flash_erase_state == 1) { + // wait for erase + // TODO add timeout + #define flash_erase_done() (__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) == RESET) + if (!flash_erase_done()) { + return; + } + flash_erase_state = 2; + } + */ + + // This code erases the flash directly, waiting for it to finish + if (!(flash_flags & FLASH_FLAG_ERASED)) { + flash_erase(flash_cache_sector_start, flash_cache_sector_size); + flash_flags |= FLASH_FLAG_ERASED; + // return; + } + + // If not a forced write, wait at least 5 seconds after last write to flush + // On file close and flash unmount we get a forced write, so we can afford to wait a while + if ((flash_flags & FLASH_FLAG_FORCE_WRITE) || ((long)HAL_GetTick() - flash_tick_counter_last_write) >= 3000L) { + // sync the cache RAM buffer by writing it to the flash page + flash_tick_counter_last_write = 0x7fffffffL; + flash_write(flash_cache_sector_start, (const uint32_t *)CACHE_MEM_START_ADDR, flash_cache_sector_size); + // clear the flash flags now that we have a clean cache + flash_flags = 0; + // indicate a clean cache with LED off + led_state(RA_LED1, 0); + } +} + +bool flash_bdev_readblock(uint8_t *dest, uint32_t block) { + // non-MBR block, get data from flash memory, possibly via cache + uint32_t flash_addr = convert_block_to_flash_addr(block); + if (flash_addr == -1) { + // bad block number + return false; + } + uint8_t *src = flash_cache_get_addr_for_read(flash_addr); + memcpy(dest, src, FLASH_BLOCK_SIZE); + return true; +} + +bool flash_bdev_is_erased(uint32_t block) { + uint32_t *start; + uint32_t *end; + bool ret = true; + uint32_t flash_addr = convert_block_to_flash_addr(block); + start = (uint32_t *)flash_addr; + end = (uint32_t *)(flash_addr + FLASH_BLOCK_SIZE); + while (start < end) { + if (*start++ != 0xffffffff) { + ret = false; + break; + } + } + return ret; +} + +bool flash_bdev_writeblock(const uint8_t *src, uint32_t block) { + // non-MBR block, copy to cache + uint32_t flash_addr = convert_block_to_flash_addr(block); + if (flash_addr == -1) { + // bad block number + return false; + } + uint8_t *dest = flash_cache_get_addr_for_write(flash_addr); + memcpy(dest, src, FLASH_BLOCK_SIZE); + // flash_flags |= FLASH_FLAG_FORCE_WRITE; + // flash_bdev_irq_handler(); + return true; +} + +int flash_bdev_readblocks_ext(uint8_t *dest, uint32_t block, uint32_t offset, uint32_t len) { + // Get data from flash memory, possibly via cache + while (len) { + uint32_t l = MIN(len, FLASH_BLOCK_SIZE - offset); + uint32_t flash_addr = convert_block_to_flash_addr(block); + if (flash_addr == -1) { + // bad block number + return -1; + } + uint8_t *src = flash_cache_get_addr_for_read(flash_addr + offset); + memcpy(dest, src, l); + dest += l; + block += 1; + offset = 0; + len -= l; + } + return 0; +} + +int flash_bdev_writeblocks_ext(const uint8_t *src, uint32_t block, uint32_t offset, uint32_t len) { + // Copy to cache + while (len) { + uint32_t l = MIN(len, FLASH_BLOCK_SIZE - offset); + uint32_t flash_addr = convert_block_to_flash_addr(block); + if (flash_addr == -1) { + // bad block number + return -1; + } +// uint32_t basepri = raise_irq_pri(IRQ_PRI_FLASH); // prevent cache flushing and USB access + uint8_t *dest = flash_cache_get_addr_for_write(flash_addr + offset); + memcpy(dest, src, l); +// restore_irq_pri(basepri); + src += l; + block += 1; + offset = 0; + len -= l; + } + return 0; +} + +#endif // MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE diff --git a/ports/renesas-ra/gccollect.c b/ports/renesas-ra/gccollect.c new file mode 100644 index 000000000..bd697a2af --- /dev/null +++ b/ports/renesas-ra/gccollect.c @@ -0,0 +1,71 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> + +#include "py/mpstate.h" +#include "py/gc.h" +#include "py/mpthread.h" +#include "shared/runtime/gchelper.h" +#include "gccollect.h" +#include "softtimer.h" +#include "systick.h" + +void gc_collect(void) { + // get current time, in case we want to time the GC + #if 0 + uint32_t start = mp_hal_ticks_us(); + #endif + + // start the GC + gc_collect_start(); + + // trace the stack and registers + gc_helper_collect_regs_and_stack(); + + // trace root pointers from any threads + #if MICROPY_PY_THREAD + mp_thread_gc_others(); + #endif + + // trace soft timer nodes + soft_timer_gc_mark_all(); + + // end the GC + gc_collect_end(); + + #if 0 + // print GC info + uint32_t ticks = mp_hal_ticks_us() - start; + gc_info_t info; + gc_info(&info); + printf("GC@%lu %lums\n", start, ticks); + printf(" " UINT_FMT " total\n", info.total); + printf(" " UINT_FMT " : " UINT_FMT "\n", info.used, info.free); + printf(" 1=" UINT_FMT " 2=" UINT_FMT " m=" UINT_FMT "\n", info.num_1block, info.num_2block, info.max_block); + #endif +} diff --git a/ports/renesas-ra/gccollect.h b/ports/renesas-ra/gccollect.h new file mode 100644 index 000000000..c33c3513c --- /dev/null +++ b/ports/renesas-ra/gccollect.h @@ -0,0 +1,44 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_GCCOLLECT_H +#define MICROPY_INCLUDED_RENESAS_RA_GCCOLLECT_H + +// variables defining memory layout +// (these probably belong somewhere else...) +extern uint32_t _etext; +extern uint32_t _sidata; +extern uint32_t _ram_start; +extern uint32_t _sdata; +extern uint32_t _edata; +extern uint32_t _sbss; +extern uint32_t _ebss; +extern uint32_t _heap_start; +extern uint32_t _heap_end; +extern uint32_t _sstack; +extern uint32_t _estack; +extern uint32_t _ram_end; + +#endif // MICROPY_INCLUDED_RENESAS_RA_GCCOLLECT_H diff --git a/ports/renesas-ra/help.c b/ports/renesas-ra/help.c new file mode 100644 index 000000000..3bce504d9 --- /dev/null +++ b/ports/renesas-ra/help.c @@ -0,0 +1,61 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021, 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/builtin.h" + +const char ra_help_text[] = + "Welcome to MicroPython for Renesas RA!\n" + "\n" + "For online docs please visit http://docs.micropython.org/.\n" + "\n" + "For access to hardware please use machine module.\n" + "import machine\n" + "from machine import Pin\n" + "machine.info() -- print some general information\n" + "machine.freq() -- print some general information\n" + "p0 = Pin('P106',Pin.OUT) -- get a pin 'P106'\n" + "p0.value(1) -- Write 1 to pin 'P106'\n" + "p0.value() -- Read from pin 'P106'\n" + "Pin name: 'P000' - 'P915', Pin mode: Pin.IN, Pin.OUT\n" + "Pin pull: PULL_NONE, PULL_UP, PULL_DOWN\n" + "\n" + "For change boot mode by reset with pressing switch\n" + "Normal: release switch after LED1 flashes 4 times or more\n" + "Safe: release switch after LED1 flashes 2 times\n" + "Factory filesystem: release switch after LED1 flashes 3 times\n" + "*Note that Flash file system is erased and initialized.\n" + "\n" + "Control commands:\n" + " CTRL-A -- on a blank line, enter raw REPL mode\n" + " CTRL-B -- on a blank line, enter normal REPL mode\n" + " CTRL-C -- interrupt a running program\n" + " CTRL-D -- on a blank line, do a soft reset of the board\n" + " CTRL-E -- on a blank line, enter paste mode\n" + "\n" + "For further help on a specific object, type help(obj)\n" + "For a list of available modules, type help('modules')\n" +; diff --git a/ports/renesas-ra/irq.c b/ports/renesas-ra/irq.c new file mode 100644 index 000000000..fdaf2385c --- /dev/null +++ b/ports/renesas-ra/irq.c @@ -0,0 +1,59 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/obj.h" +#include "py/mphal.h" +#include "irq.h" +#include "modmachine.h" + +#if IRQ_ENABLE_STATS +uint32_t irq_stats[IRQ_STATS_MAX] = {0}; +#endif + +// disable_irq() +// Disable interrupt requests. +// Returns the previous IRQ state which can be passed to enable_irq. +STATIC mp_obj_t machine_disable_irq(void) { + return mp_obj_new_bool(disable_irq() == IRQ_STATE_ENABLED); +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_disable_irq_obj, machine_disable_irq); + +// enable_irq(state=True) +// Enable interrupt requests, based on the argument, which is usually the +// value returned by a previous call to disable_irq. +STATIC mp_obj_t machine_enable_irq(uint n_args, const mp_obj_t *arg) { + enable_irq((n_args == 0 || mp_obj_is_true(arg[0])) ? IRQ_STATE_ENABLED : IRQ_STATE_DISABLED); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_enable_irq_obj, 0, 1, machine_enable_irq); + +#if IRQ_ENABLE_STATS +// return a memoryview of the irq statistics array +STATIC mp_obj_t pyb_irq_stats(void) { + return mp_obj_new_memoryview(0x80 | 'I', MP_ARRAY_SIZE(irq_stats), &irq_stats[0]); +} +MP_DEFINE_CONST_FUN_OBJ_0(pyb_irq_stats_obj, pyb_irq_stats); +#endif diff --git a/ports/renesas-ra/irq.h b/ports/renesas-ra/irq.h new file mode 100644 index 000000000..f2d047822 --- /dev/null +++ b/ports/renesas-ra/irq.h @@ -0,0 +1,241 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_RA_IRQ_H +#define MICROPY_INCLUDED_RA_IRQ_H + +// Use this macro together with NVIC_SetPriority to indicate that an IRQn is non-negative, +// which helps the compiler optimise the resulting inline function. +#define IRQn_NONNEG(pri) ((pri) & 0x7f) + +// these states correspond to values from query_irq, enable_irq and disable_irq +#define IRQ_STATE_DISABLED (0x00000001) +#define IRQ_STATE_ENABLED (0x00000000) + +// Enable this to get a count for the number of times each irq handler is called, +// accessible via pyb.irq_stats(). +#define IRQ_ENABLE_STATS (0) + +#if IRQ_ENABLE_STATS +#if defined(RA4M1) | defined(RA4W1) +#define IRQ_STATS_MAX (48) +#else +#define IRQ_STATS_MAX (128) +#endif +extern uint32_t irq_stats[IRQ_STATS_MAX]; +#define IRQ_ENTER(irq) ++irq_stats[irq] +#define IRQ_EXIT(irq) +#else +#define IRQ_ENTER(irq) +#define IRQ_EXIT(irq) +#endif + +static inline uint32_t query_irq(void) { + return __get_PRIMASK(); +} + +// enable_irq and disable_irq are defined inline in mpconfigport.h + +#if __CORTEX_M >= 0x03 + +// irqs with a priority value greater or equal to "pri" will be disabled +// "pri" should be between 1 and 15 inclusive +static inline uint32_t raise_irq_pri(uint32_t pri) { + uint32_t basepri = __get_BASEPRI(); + // If non-zero, the processor does not process any exception with a + // priority value greater than or equal to BASEPRI. + // When writing to BASEPRI_MAX the write goes to BASEPRI only if either: + // - Rn is non-zero and the current BASEPRI value is 0 + // - Rn is non-zero and less than the current BASEPRI value + pri <<= (8 - __NVIC_PRIO_BITS); + __ASM volatile ("msr basepri_max, %0" : : "r" (pri) : "memory"); + return basepri; +} + +// "basepri" should be the value returned from raise_irq_pri +static inline void restore_irq_pri(uint32_t basepri) { + __set_BASEPRI(basepri); +} + +#else + +static inline uint32_t raise_irq_pri(uint32_t pri) { + return disable_irq(); +} + +// "state" should be the value returned from raise_irq_pri +static inline void restore_irq_pri(uint32_t state) { + enable_irq(state); +} + +#endif + +// IRQ priority definitions. +// +// Lower number implies higher interrupt priority. +// +// The default priority grouping is set to NVIC_PRIORITYGROUP_4 in the +// HAL_Init function. This corresponds to 4 bits for the priority field +// and 0 bits for the sub-priority field (which means that for all intensive +// purposes that the sub-priorities below are ignored). +// +// While a given interrupt is being processed, only higher priority (lower number) +// interrupts will preempt a given interrupt. If sub-priorities are active +// then the sub-priority determines the order that pending interrupts of +// a given priority are executed. This is only meaningful if 2 or more +// interrupts of the same priority are pending at the same time. +// +// The priority of the SysTick timer is determined from the TICK_INT_PRIORITY +// value which is normally set to 0 in the stm32f4xx_hal_conf.h file. +// +// The following interrupts are arranged from highest priority to lowest +// priority to make it a bit easier to figure out. + +#if __CORTEX_M == 0 + +#define IRQ_PRI_SYSTICK 0 +#define IRQ_PRI_UART 1 +#define IRQ_PRI_SDIO 1 +#define IRQ_PRI_DMA 1 +#define IRQ_PRI_FLASH 2 +#define IRQ_PRI_OTG_FS 2 +#define IRQ_PRI_OTG_HS 2 +#define IRQ_PRI_TIM5 2 +#define IRQ_PRI_CAN 2 +#define IRQ_PRI_TIMX 2 +#define IRQ_PRI_EXTINT 2 +#define IRQ_PRI_PENDSV 3 +#define IRQ_PRI_RTC_WKUP 3 + +#else + +#define NVIC_PRIORITYGROUP_0 0x00000007U /*!< 0 bits for pre-emption priority + 4 bits for subpriority */ +#define NVIC_PRIORITYGROUP_1 0x00000006U /*!< 1 bits for pre-emption priority + 3 bits for subpriority */ +#define NVIC_PRIORITYGROUP_2 0x00000005U /*!< 2 bits for pre-emption priority + 2 bits for subpriority */ +#define NVIC_PRIORITYGROUP_3 0x00000004U /*!< 3 bits for pre-emption priority + 1 bits for subpriority */ +#define NVIC_PRIORITYGROUP_4 0x00000003U /*!< 4 bits for pre-emption priority + 0 bits for subpriority */ + +#if defined(RA_PRI_SYSTICK) +#define IRQ_PRI_SYSTICK NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_SYSTICK, 0) +#else +#define IRQ_PRI_SYSTICK NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 0, 0) +#endif + +// The UARTs have no FIFOs, so if they don't get serviced quickly then characters +// get dropped. The handling for each character only consumes about 0.5 usec +#if defined(RA_PRI_UART) +#define IRQ_PRI_UART NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_UART, 0) +#else +#define IRQ_PRI_UART NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 1, 0) +#endif + +// SDIO must be higher priority than DMA for SDIO DMA transfers to work. +#if defined(RA_PRI_SDIO) +#define IRQ_PRI_SDIO NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_SDIO, 0) +#else +#define IRQ_PRI_SDIO NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 4, 0) +#endif + +// DMA should be higher priority than USB, since USB Mass Storage calls +// into the sdcard driver which waits for the DMA to complete. +#if defined(RA_PRI_DMA) +#define IRQ_PRI_DMA NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_DMA, 0) +#else +#define IRQ_PRI_DMA NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 5, 0) +#endif + +// Flash IRQ (used for flushing storage cache) must be at the same priority as +// the USB IRQs, so that the IRQ priority can be raised to this level to disable +// both the USB and cache flushing, when storage transfers are in progress. +#if defined(RA_PRI_FLASH) +#define IRQ_PRI_FLASH NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_FLASH, 0) +#else +#define IRQ_PRI_FLASH NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0) +#endif + +#if defined(RA_PRI_OTG_FS) +#define IRQ_PRI_OTG_FS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_OTG_FS, 0) +#else +#define IRQ_PRI_OTG_FS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0) +#endif +#if defined(RA_PRI_OTG_HS) +#define IRQ_PRI_OTG_HS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_OTG_HS, 0) +#else +#define IRQ_PRI_OTG_HS NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0) +#endif +#if defined(RA_PRI_TIM5) +#define IRQ_PRI_TIM5 NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_TIM5, 0) +#else +#define IRQ_PRI_TIM5 NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 6, 0) +#endif + +#if defined(RA_PRI_CAN) +#define IRQ_PRI_CAN NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_CAN, 0) +#else +#define IRQ_PRI_CAN NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 7, 0) +#endif + +#if defined(RA_PRI_SPI) +#define IRQ_PRI_SPI NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_SPI, 0) +#else +#define IRQ_PRI_SPI NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 8, 0) +#endif + +// Interrupt priority for non-special timers. +#if defined(RA_PRI_TIMX) +#define IRQ_PRI_TIMX NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_TIMX, 0) +#else +#define IRQ_PRI_TIMX NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 13, 0) +#endif + +#if defined(RA_PRI_EXTINT) +#define IRQ_PRI_EXTINT NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_EXTINT, 0) +#else +#define IRQ_PRI_EXTINT NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 14, 0) +#endif + +// PENDSV should be at the lowst priority so that other interrupts complete +// before exception is raised. +#if defined(RA_PRI_PENDSV) +#define IRQ_PRI_PENDSV NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_PENDSV, 0) +#else +#define IRQ_PRI_PENDSV NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0) +#endif +#if defined(RA_PRI_RTC_WKUP) +#define IRQ_PRI_RTC_WKUP NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, RA_PRI_RTC_WKUP, 0) +#else +#define IRQ_PRI_RTC_WKUP NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, 15, 0) +#endif + +#endif + +#endif // MICROPY_INCLUDED_RA_IRQ_H diff --git a/ports/renesas-ra/led.c b/ports/renesas-ra/led.c new file mode 100644 index 000000000..efc09d9de --- /dev/null +++ b/ports/renesas-ra/led.c @@ -0,0 +1,190 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2016 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> + +#include "py/runtime.h" +#include "py/mphal.h" +#include "timer.h" +#include "led.h" +#include "pin.h" + +#if defined(MICROPY_HW_LED1) + +/// \moduleref pyb +/// \class LED - LED object +/// +/// The LED object controls an individual LED (Light Emitting Diode). + +// the default is that LEDs are not inverted, and pin driven high turns them on +#ifndef MICROPY_HW_LED_INVERTED +#define MICROPY_HW_LED_INVERTED (0) +#endif + +typedef struct _ra_led_obj_t { + mp_obj_base_t base; + mp_uint_t led_id; + const machine_pin_obj_t *led_pin; +} ra_led_obj_t; + +STATIC const ra_led_obj_t ra_led_obj[] = { + {{&ra_led_type}, 1, MICROPY_HW_LED1}, + #if defined(MICROPY_HW_LED2) + {{&ra_led_type}, 2, MICROPY_HW_LED2}, + #if defined(MICROPY_HW_LED3) + {{&ra_led_type}, 3, MICROPY_HW_LED3}, + #if defined(MICROPY_HW_LED4) + {{&ra_led_type}, 4, MICROPY_HW_LED4}, + #endif + #endif + #endif +}; +#define NUM_LEDS MP_ARRAY_SIZE(ra_led_obj) + +void led_init(void) { + /* Turn off LEDs and initialize */ + for (int led = 0; led < NUM_LEDS; led++) { + const machine_pin_obj_t *led_pin = ra_led_obj[led].led_pin; + MICROPY_HW_LED_OFF(led_pin); + mp_hal_pin_output(led_pin); + } +} + +void led_state(ra_led_t led, int state) { + if (led < 1 || led > NUM_LEDS) { + return; + } + + const machine_pin_obj_t *led_pin = ra_led_obj[led - 1].led_pin; + // printf("led_state(%d,%d)\n", led, state); + if (state == 0) { + // turn LED off + MICROPY_HW_LED_OFF(led_pin); + } else { + // turn LED on + MICROPY_HW_LED_ON(led_pin); + } +} + +void led_toggle(ra_led_t led) { + if (led < 1 || led > NUM_LEDS) { + return; + } + const machine_pin_obj_t *led_pin = ra_led_obj[led - 1].led_pin; + MICROPY_HW_LED_TOGGLE(led_pin); +} + +void led_debug(int n, int delay) { + led_state(1, n & 1); + led_state(2, n & 2); + led_state(3, n & 4); + led_state(4, n & 8); + mp_hal_delay_ms(delay); +} + +/******************************************************************************/ +/* MicroPython bindings */ + +void led_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + ra_led_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "LED(%u)", self->led_id); +} + +/// \classmethod \constructor(id) +/// Create an LED object associated with the given LED: +/// +/// - `id` is the LED number, 1-4. +STATIC mp_obj_t led_obj_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 1, 1, false); + + // get led number + mp_int_t led_id = mp_obj_get_int(args[0]); + + // check led number + if (!(1 <= led_id && led_id <= NUM_LEDS)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("LED(%d) doesn't exist"), led_id); + } + + // return static led object + return MP_OBJ_FROM_PTR(&ra_led_obj[led_id - 1]); +} + +/// \method on() +/// Turn the LED on. +mp_obj_t led_obj_on(mp_obj_t self_in) { + ra_led_obj_t *self = MP_OBJ_TO_PTR(self_in); + led_state(self->led_id, 1); + return mp_const_none; +} + +/// \method off() +/// Turn the LED off. +mp_obj_t led_obj_off(mp_obj_t self_in) { + ra_led_obj_t *self = MP_OBJ_TO_PTR(self_in); + led_state(self->led_id, 0); + return mp_const_none; +} + +/// \method toggle() +/// Toggle the LED between on and off. +mp_obj_t led_obj_toggle(mp_obj_t self_in) { + ra_led_obj_t *self = MP_OBJ_TO_PTR(self_in); + led_toggle(self->led_id); + return mp_const_none; +} + +STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_on_obj, led_obj_on); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_off_obj, led_obj_off); +STATIC MP_DEFINE_CONST_FUN_OBJ_1(led_obj_toggle_obj, led_obj_toggle); + +STATIC const mp_rom_map_elem_t led_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&led_obj_on_obj) }, + { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&led_obj_off_obj) }, + { MP_ROM_QSTR(MP_QSTR_toggle), MP_ROM_PTR(&led_obj_toggle_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(led_locals_dict, led_locals_dict_table); + +const mp_obj_type_t ra_led_type = { + { &mp_type_type }, + .name = MP_QSTR_LED, + .print = led_obj_print, + .make_new = led_obj_make_new, + .locals_dict = (mp_obj_dict_t *)&led_locals_dict, +}; + +#else +// For boards with no LEDs, we leave an empty function here so that we don't +// have to put conditionals everywhere. +void led_init(void) { +} +void led_state(ra_led_t led, int state) { +} +void led_toggle(ra_led_t led) { +} +#endif // defined(MICROPY_HW_LED1) diff --git a/ports/renesas-ra/led.h b/ports/renesas-ra/led.h new file mode 100644 index 000000000..2689c7094 --- /dev/null +++ b/ports/renesas-ra/led.h @@ -0,0 +1,44 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_LED_H +#define MICROPY_INCLUDED_RENESAS_RA_LED_H + +typedef enum { + RA_LED1 = 1, + RA_LED2 = 2, + RA_LED3 = 3, + RA_LED4 = 4, +} ra_led_t; + +void led_init(void); +void led_state(ra_led_t led, int state); +void led_toggle(ra_led_t led); +void led_debug(int value, int delay); + +extern const mp_obj_type_t ra_led_type; + +#endif // MICROPY_INCLUDED_RENESAS_RA_LED_H diff --git a/ports/renesas-ra/machine_adc.c b/ports/renesas-ra/machine_adc.c new file mode 100644 index 000000000..29e50b8a3 --- /dev/null +++ b/ports/renesas-ra/machine_adc.c @@ -0,0 +1,136 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mphal.h" +#include "ra_adc.h" + +#define ADC_SAMPLETIME_DEFAULT 1 +#define ADC_CHANNEL_VREFINT (ADC_REF) +#define ADC_CHANNEL_TEMPSENSOR (ADC_TEMP) +#define ADC_SAMPLETIME_DEFAULT_INT 1 + +typedef struct { + uint8_t dummy; +} ADC_TypeDef; + +// Timeout for waiting for end-of-conversion +#define ADC_EOC_TIMEOUT_MS (10) + +// This is a synthesised channel representing the maximum ADC reading (useful to scale other channels) +#define ADC_CHANNEL_VREF (0xffff) + +/******************************************************************************/ +// MicroPython bindings for machine.ADC + +const mp_obj_type_t machine_adc_type; + +typedef struct _machine_adc_obj_t { + mp_obj_base_t base; + ADC_TypeDef *adc; + uint32_t channel; + uint32_t pin; + uint32_t sample_time; +} machine_adc_obj_t; + +STATIC void machine_adc_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + uint8_t resolution = (uint8_t)ra_adc_get_resolution(); + mp_printf(print, "<ADC%u channel=%u>", resolution, self->channel); +} + +// ADC(id) +STATIC mp_obj_t machine_adc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + // Check number of arguments + mp_arg_check_num(n_args, n_kw, 1, 1, false); + + mp_obj_t source = all_args[0]; + bool find = false; + uint8_t channel; + uint32_t pin; + uint32_t sample_time = ADC_SAMPLETIME_DEFAULT; + if (mp_obj_is_int(source)) { + channel = (uint8_t)mp_obj_get_int(source); + find = ra_adc_ch_to_pin((uint8_t)channel, (uint32_t *)&pin); + if (!find) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Channel(%q) does not have ADC capabilities"), channel); + } + } else { + const machine_pin_obj_t *pin_obj = machine_pin_find(source); + find = ra_adc_pin_to_ch((uint32_t)pin_obj->pin, (uint8_t *)&channel); + if (!find) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%q) does not have ADC capabilities"), pin_obj->name); + } + pin = pin_obj->pin; + } + ra_adc_init(); + machine_adc_obj_t *o = m_new_obj(machine_adc_obj_t); + o->base.type = &machine_adc_type; + o->adc = (ADC_TypeDef *)NULL; + o->channel = channel; + o->pin = pin; + o->sample_time = sample_time; + ra_adc_enable((uint8_t)pin); + return MP_OBJ_FROM_PTR(o); +} + +STATIC mp_obj_t machine_adc_read(mp_obj_t self_in) { + machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_SMALL_INT(ra_adc_read((uint32_t)(self->pin))); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_read_obj, machine_adc_read); + +STATIC mp_obj_t machine_adc_read_u16(mp_obj_t self_in) { + const machine_adc_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_uint_t raw = (mp_uint_t)ra_adc_read((uint32_t)(self->pin)); + mp_int_t bits = (mp_int_t)ra_adc_get_resolution(); + // Scale raw reading to 16 bit value using a Taylor expansion (for 8 <= bits <= 16) + mp_uint_t u16 = raw << (16 - bits) | raw >> (2 * bits - 16); + return MP_OBJ_NEW_SMALL_INT(u16); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_adc_read_u16_obj, machine_adc_read_u16); + +STATIC const mp_rom_map_elem_t machine_adc_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&machine_adc_read_obj) }, + { MP_ROM_QSTR(MP_QSTR_read_u16), MP_ROM_PTR(&machine_adc_read_u16_obj) }, + + { MP_ROM_QSTR(MP_QSTR_VREF), MP_ROM_INT(ADC_CHANNEL_VREF) }, + { MP_ROM_QSTR(MP_QSTR_CORE_VREF), MP_ROM_INT(ADC_CHANNEL_VREFINT) }, + { MP_ROM_QSTR(MP_QSTR_CORE_TEMP), MP_ROM_INT(ADC_CHANNEL_TEMPSENSOR) }, + #if defined(ADC_CHANNEL_VBAT) + { MP_ROM_QSTR(MP_QSTR_CORE_VBAT), MP_ROM_INT(ADC_CHANNEL_VBAT) }, + #endif +}; +STATIC MP_DEFINE_CONST_DICT(machine_adc_locals_dict, machine_adc_locals_dict_table); + +const mp_obj_type_t machine_adc_type = { + { &mp_type_type }, + .name = MP_QSTR_ADC, + .print = machine_adc_print, + .make_new = machine_adc_make_new, + .locals_dict = (mp_obj_dict_t *)&machine_adc_locals_dict, +}; diff --git a/ports/renesas-ra/machine_i2c.c b/ports/renesas-ra/machine_i2c.c new file mode 100644 index 000000000..5f385f363 --- /dev/null +++ b/ports/renesas-ra/machine_i2c.c @@ -0,0 +1,180 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016-2018 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/mphal.h" +#include "py/mperrno.h" +#include "extmod/machine_i2c.h" +#include "modmachine.h" + +#include "ra_i2c.h" + +#if MICROPY_HW_ENABLE_HW_I2C + +#define DEFAULT_I2C_FREQ (400000) +#define DEFAULT_I2C_TIMEOUT (1000) + +typedef struct _machine_i2c_obj_t { + mp_obj_base_t base; + R_IIC0_Type *i2c_inst; + uint8_t i2c_id; + mp_hal_pin_obj_t scl; + mp_hal_pin_obj_t sda; + uint32_t freq; +} machine_i2c_obj_t; + +STATIC machine_i2c_obj_t machine_i2c_obj[] = { + #if defined(MICROPY_HW_I2C0_SCL) + {{&machine_i2c_type}, R_IIC0, 0, MICROPY_HW_I2C0_SCL, MICROPY_HW_I2C0_SDA, 0}, + #endif + #if defined(MICROPY_HW_I2C1_SCL) + {{&machine_i2c_type}, R_IIC1, 1, MICROPY_HW_I2C1_SCL, MICROPY_HW_I2C1_SDA, 0}, + #endif + #if defined(MICROPY_HW_I2C2_SCL) + {{&machine_i2c_type}, R_IIC2, 2, MICROPY_HW_I2C2_SCL, MICROPY_HW_I2C2_SDA, 0}, + #endif +}; + +STATIC int i2c_read(machine_i2c_obj_t *self, uint16_t addr, uint8_t *dest, size_t len, bool stop); +STATIC int i2c_write(machine_i2c_obj_t *self, uint16_t addr, const uint8_t *src, size_t len, bool stop); + +STATIC int i2c_read(machine_i2c_obj_t *self, uint16_t addr, uint8_t *dest, size_t len, bool stop) { + bool flag; + xaction_t action; + xaction_unit_t unit; + ra_i2c_xunit_init(&unit, (uint8_t *)dest, (uint32_t)len, true, (void *)NULL); + ra_i2c_xaction_init(&action, (xaction_unit_t *)&unit, 1, (uint32_t)addr, stop); + flag = ra_i2c_action_execute(self->i2c_inst, &action, false, DEFAULT_I2C_TIMEOUT); + return flag? len:-1; +} + +STATIC int i2c_write(machine_i2c_obj_t *self, uint16_t addr, const uint8_t *src, size_t len, bool stop) { + bool flag; + xaction_t action; + xaction_unit_t unit; + ra_i2c_xunit_init(&unit, (uint8_t *)src, (uint32_t)len, false, (void *)NULL); + ra_i2c_xaction_init(&action, (xaction_unit_t *)&unit, 1, (uint32_t)addr, stop); + flag = ra_i2c_action_execute(self->i2c_inst, &action, false, DEFAULT_I2C_TIMEOUT); + return flag? len:-1; +} + +// MicroPython bindings for machine API + +STATIC void machine_i2c_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_i2c_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "I2C(%u, freq=%u, scl=%q, sda=%q)", + self->i2c_id, self->freq, self->scl->name, self->sda->name); +} + +STATIC void machine_i2c_init(mp_obj_base_t *obj, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + mp_raise_NotImplementedError(MP_ERROR_TEXT("init is not supported.")); + return; +} + +STATIC mp_obj_t machine_i2c_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + // parse args + enum { ARG_id, ARG_freq, ARG_scl, ARG_sda }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ }, + { MP_QSTR_freq, MP_ARG_INT, {.u_int = DEFAULT_I2C_FREQ} }, + { MP_QSTR_scl, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_sda, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // get static peripheral object + bool found = false; + int i2c_id = mp_obj_get_int(args[ARG_id].u_obj); + machine_i2c_obj_t *self = (machine_i2c_obj_t *)&machine_i2c_obj[0]; + for (int i = 0; i < MP_ARRAY_SIZE(machine_i2c_obj); i++) { + if (i2c_id == self->i2c_id) { + found = true; + break; + } + ++self; + } + if (found != true) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("I2C(%d) doesn't exist"), i2c_id); + } + + // here we would check the scl/sda pins and configure them, but it's not implemented + if (args[ARG_scl].u_obj != MP_OBJ_NULL || args[ARG_sda].u_obj != MP_OBJ_NULL) { + mp_raise_ValueError(MP_ERROR_TEXT("explicit choice of scl/sda is not implemented")); + } + + if (n_args > 1 || n_kw > 0 || self->freq == 0) { + self->freq = args[ARG_freq].u_int; + ra_i2c_init(self->i2c_inst, self->scl->pin, self->sda->pin, self->freq); + } + return MP_OBJ_FROM_PTR(self); +} + +STATIC int machine_i2c_transfer_single(mp_obj_base_t *self_in, uint16_t addr, size_t len, uint8_t *buf, unsigned int flags) { + machine_i2c_obj_t *self = MP_OBJ_TO_PTR(self_in); + int ret; + bool stop; + stop = (flags & MP_MACHINE_I2C_FLAG_STOP)? true : false; + if (flags & MP_MACHINE_I2C_FLAG_READ) { + ret = i2c_read(self, addr, buf, len, stop); + } else { + ret = i2c_write(self, addr, buf, len, stop); + } + return ret; +} + +STATIC int machine_i2c_start(mp_obj_base_t *self) { + mp_raise_NotImplementedError(MP_ERROR_TEXT("start is not supported.")); + return 0; +} + +STATIC int machine_i2c_stop(mp_obj_base_t *self) { + mp_raise_NotImplementedError(MP_ERROR_TEXT("start is not supported.")); + return 0; +} + +STATIC const mp_machine_i2c_p_t machine_i2c_p = { + .init = machine_i2c_init, + .transfer = mp_machine_i2c_transfer_adaptor, + .transfer_single = machine_i2c_transfer_single, + .start = machine_i2c_start, + .stop = machine_i2c_stop, +}; + +const mp_obj_type_t machine_i2c_type = { + { &mp_type_type }, + .name = MP_QSTR_I2C, + .print = machine_i2c_print, + .make_new = machine_i2c_make_new, + .protocol = &machine_i2c_p, + .locals_dict = (mp_obj_dict_t *)&mp_machine_i2c_locals_dict, +}; + +#endif // MICROPY_HW_ENABLE_HW_I2C diff --git a/ports/renesas-ra/machine_pin.c b/ports/renesas-ra/machine_pin.c new file mode 100644 index 000000000..e07794e4b --- /dev/null +++ b/ports/renesas-ra/machine_pin.c @@ -0,0 +1,642 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016-2021 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/mphal.h" +#include "shared/runtime/mpirq.h" +#include "modmachine.h" +#include "extmod/virtpin.h" + +#include "pin.h" +#include "extint.h" + +// Pin class variables +STATIC bool pin_class_debug; + +void machine_pin_init(void) { + MP_STATE_PORT(pin_class_mapper) = mp_const_none; + MP_STATE_PORT(pin_class_map_dict) = mp_const_none; + pin_class_debug = false; +} + +void machine_pin_deinit(void) { +} + +// C API used to convert a user-supplied pin name into an ordinal pin number. +const machine_pin_obj_t *machine_pin_find(mp_obj_t user_obj) { + const machine_pin_obj_t *pin_obj; + + // If a pin was provided, then use it + if (mp_obj_is_type(user_obj, &machine_pin_type)) { + pin_obj = MP_OBJ_TO_PTR(user_obj); + if (pin_class_debug) { + printf("Pin map passed pin "); + mp_obj_print(MP_OBJ_FROM_PTR(pin_obj), PRINT_STR); + printf("\n"); + } + return pin_obj; + } + + if (MP_STATE_PORT(pin_class_mapper) != mp_const_none) { + mp_obj_t o = mp_call_function_1(MP_STATE_PORT(pin_class_mapper), user_obj); + if (o != mp_const_none) { + if (!mp_obj_is_type(o, &machine_pin_type)) { + mp_raise_ValueError(MP_ERROR_TEXT("Pin.mapper didn't return a Pin object")); + } + if (pin_class_debug) { + printf("Pin.mapper maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print(o, PRINT_STR); + printf("\n"); + } + return MP_OBJ_TO_PTR(o); + } + // The pin mapping function returned mp_const_none, fall through to + // other lookup methods. + } + + if (MP_STATE_PORT(pin_class_map_dict) != mp_const_none) { + mp_map_t *pin_map_map = mp_obj_dict_get_map(MP_STATE_PORT(pin_class_map_dict)); + mp_map_elem_t *elem = mp_map_lookup(pin_map_map, user_obj, MP_MAP_LOOKUP); + if (elem != NULL && elem->value != MP_OBJ_NULL) { + mp_obj_t o = elem->value; + if (pin_class_debug) { + printf("Pin.map_dict maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print(o, PRINT_STR); + printf("\n"); + } + return MP_OBJ_TO_PTR(o); + } + } + + // See if the pin name matches a board pin + pin_obj = pin_find_named_pin(&pin_board_pins_locals_dict, user_obj); + if (pin_obj) { + if (pin_class_debug) { + printf("Pin.board maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print(MP_OBJ_FROM_PTR(pin_obj), PRINT_STR); + printf("\n"); + } + return pin_obj; + } + + // See if the pin name matches a cpu pin + pin_obj = pin_find_named_pin(&pin_cpu_pins_locals_dict, user_obj); + if (pin_obj) { + if (pin_class_debug) { + printf("Pin.cpu maps "); + mp_obj_print(user_obj, PRINT_REPR); + printf(" to "); + mp_obj_print(MP_OBJ_FROM_PTR(pin_obj), PRINT_STR); + printf("\n"); + } + return pin_obj; + } + + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Pin(%s) doesn't exist"), mp_obj_str_get_str(user_obj)); +} + +/// Return a string describing the pin object. +STATIC void machine_pin_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + + // pin name + mp_printf(print, "Pin(Pin.cpu.%q, mode=Pin.", self->name); + + uint32_t mode = pin_get_mode(self); + + if (mode == GPIO_MODE_ANALOG) { + // analog + mp_print_str(print, "ANALOG)"); + + } else { + // IO mode + bool af = false; + qstr mode_qst; + if (mode == GPIO_MODE_INPUT) { + mode_qst = MP_QSTR_IN; + } else if (mode == GPIO_MODE_OUTPUT_PP) { + mode_qst = MP_QSTR_OUT; + } else if (mode == GPIO_MODE_OUTPUT_OD) { + mode_qst = MP_QSTR_OPEN_DRAIN; + } else { + af = true; + if (mode == GPIO_MODE_AF_PP) { + mode_qst = MP_QSTR_ALT; + } else { + mode_qst = MP_QSTR_ALT_OPEN_DRAIN; + } + } + mp_print_str(print, qstr_str(mode_qst)); + + // pull mode + qstr pull_qst = MP_QSTRnull; + uint32_t pull = pin_get_pull(self); + if (pull == GPIO_PULLUP) { + pull_qst = MP_QSTR_PULL_UP; + } else if (pull == GPIO_NOPULL) { + pull_qst = MP_QSTR_PULL_NONE; + } + if (pull_qst != MP_QSTRnull) { + mp_printf(print, ", pull=Pin.%q", pull_qst); + } + + // drive + qstr drive_qst = MP_QSTRnull; + uint32_t drive = pin_get_drive(self); + if (drive == GPIO_HIGH_POWER) { + drive_qst = MP_QSTR_HIGH_POWER; + } else if (drive == GPIO_MED_POWER) { + drive_qst = MP_QSTR_MED_POWER; + } else if (drive == GPIO_LOW_POWER) { + drive_qst = MP_QSTR_LOW_POWER; + } + if (drive_qst != MP_QSTRnull) { + mp_printf(print, ", drive=Pin.%q", drive_qst); + } + + // AF mode + if (af) { + mp_uint_t af_idx = pin_get_af(self); + const pin_af_obj_t *af_obj = pin_find_af_by_index(self, af_idx); + if (af_obj == NULL) { + mp_printf(print, ", alt=%d)", af_idx); + } else { + mp_printf(print, ", alt=Pin.%q)", af_obj->name); + } + } else { + mp_print_str(print, ")"); + } + } +} + +// pin.init(mode, pull=None, *, value=None, driver=None, alt=FUNC_SIO) +STATIC mp_obj_t machine_pin_obj_init_helper(const machine_pin_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_mode, MP_ARG_REQUIRED | MP_ARG_INT }, + { MP_QSTR_pull, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE}}, + { MP_QSTR_af, MP_ARG_INT, {.u_int = -1}}, // legacy + { MP_QSTR_value, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL}}, + { MP_QSTR_drive, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = GPIO_LOW_POWER}}, + { MP_QSTR_alt, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1}}, + }; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // get io mode + uint mode = args[0].u_int; + if (!IS_GPIO_MODE(mode)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid pin mode: %d"), mode); + } + + // get pull mode + uint pull = 0; + if (args[1].u_obj != mp_const_none) { + pull = mp_obj_get_int(args[1].u_obj); + } + + // get drive + uint drive = args[4].u_int; + if (!IS_GPIO_DRIVE(drive)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid pin drive: %d"), drive); + } + + mp_hal_pin_config(self, mode, pull, drive, -1); + // if given, set the pin value before initialising to prevent glitches + if (args[3].u_obj != MP_OBJ_NULL) { + mp_hal_pin_write(self, mp_obj_is_true(args[3].u_obj)); + } + + return mp_const_none; +} + +// constructor(id, ...) +mp_obj_t mp_pin_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); + + // Run an argument through the mapper and return the result. + const machine_pin_obj_t *pin = machine_pin_find(args[0]); + + if (n_args > 1 || n_kw > 0) { + // pin mode given, so configure this GPIO + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + machine_pin_obj_init_helper(pin, n_args - 1, args + 1, &kw_args); + } + + return MP_OBJ_FROM_PTR(pin); +} + +// fast method for getting/setting pin value +STATIC mp_obj_t machine_pin_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) { + mp_arg_check_num(n_args, n_kw, 0, 1, false); + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (n_args == 0) { + // get pin + return MP_OBJ_NEW_SMALL_INT(mp_hal_pin_read(self)); + } else { + // set pin + mp_hal_pin_write(self, mp_obj_is_true(args[0])); + return mp_const_none; + } +} + +/// \classmethod mapper([fun]) +/// Get or set the pin mapper function. +STATIC mp_obj_t pin_mapper(size_t n_args, const mp_obj_t *args) { + if (n_args > 1) { + MP_STATE_PORT(pin_class_mapper) = args[1]; + return mp_const_none; + } + return MP_STATE_PORT(pin_class_mapper); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_mapper_fun_obj, 1, 2, pin_mapper); +STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_mapper_obj, MP_ROM_PTR(&pin_mapper_fun_obj)); + +/// \classmethod dict([dict]) +/// Get or set the pin mapper dictionary. +STATIC mp_obj_t pin_map_dict(size_t n_args, const mp_obj_t *args) { + if (n_args > 1) { + MP_STATE_PORT(pin_class_map_dict) = args[1]; + return mp_const_none; + } + return MP_STATE_PORT(pin_class_map_dict); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_map_dict_fun_obj, 1, 2, pin_map_dict); +STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_map_dict_obj, MP_ROM_PTR(&pin_map_dict_fun_obj)); + +#if 0 +/// \classmethod af_list() +/// Returns an array of alternate functions available for this pin. +STATIC mp_obj_t pin_af_list(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_obj_t result = mp_obj_new_list(0, NULL); + + const pin_af_obj_t *af = self->af; + for (mp_uint_t i = 0; i < self->num_af; i++, af++) { + mp_obj_list_append(result, MP_OBJ_FROM_PTR(af)); + } + return result; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_list_obj, pin_af_list); +#endif + +/// \classmethod debug([state]) +/// Get or set the debugging state (`True` or `False` for on or off). +STATIC mp_obj_t pin_debug(size_t n_args, const mp_obj_t *args) { + if (n_args > 1) { + pin_class_debug = mp_obj_is_true(args[1]); + return mp_const_none; + } + return mp_obj_new_bool(pin_class_debug); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pin_debug_fun_obj, 1, 2, pin_debug); +STATIC MP_DEFINE_CONST_CLASSMETHOD_OBJ(pin_debug_obj, MP_ROM_PTR(&pin_debug_fun_obj)); + +// pin.init(mode, pull) +STATIC mp_obj_t machine_pin_obj_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + return machine_pin_obj_init_helper(args[0], n_args - 1, args + 1, kw_args); +} +MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_init_obj, 1, machine_pin_obj_init); + +// pin.value([value]) +STATIC mp_obj_t machine_pin_value(size_t n_args, const mp_obj_t *args) { + return machine_pin_call(args[0], n_args - 1, 0, args + 1); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_pin_value_obj, 1, 2, machine_pin_value); + +// pin.low() +STATIC mp_obj_t machine_pin_low(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_hal_pin_write(self, false); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_low_obj, machine_pin_low); + +// pin.high() +STATIC mp_obj_t machine_pin_high(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_hal_pin_write(self, true); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_high_obj, machine_pin_high); + +// pin.mode() +STATIC mp_obj_t machine_pin_mode(mp_obj_t self_in) { + return MP_OBJ_NEW_SMALL_INT(pin_get_mode(MP_OBJ_TO_PTR(self_in))); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_mode_obj, machine_pin_mode); + +// pin.pull() +STATIC mp_obj_t machine_pin_pull(mp_obj_t self_in) { + return MP_OBJ_NEW_SMALL_INT(pin_get_pull(MP_OBJ_TO_PTR(self_in))); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_pull_obj, machine_pin_pull); + +// pin.drive() +STATIC mp_obj_t machine_pin_drive(mp_obj_t self_in) { + mp_raise_NotImplementedError(MP_ERROR_TEXT("Pin.drive() is not supported yet")); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_drive_obj, machine_pin_drive); + +// pin.toggle() +STATIC mp_obj_t machine_pin_toggle(mp_obj_t self_in) { + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_hal_pin_toggle(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_toggle_obj, machine_pin_toggle); + +// pin.irq(handler=None, trigger=IRQ_FALLING|IRQ_RISING, hard=False) +STATIC mp_obj_t machine_pin_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_handler, ARG_trigger, ARG_hard }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_handler, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_trigger, MP_ARG_INT, {.u_int = GPIO_MODE_IT_RISING | GPIO_MODE_IT_FALLING} }, + { MP_QSTR_hard, MP_ARG_BOOL, {.u_bool = false} }, + }; + machine_pin_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (n_args > 1 || kw_args->used != 0) { + // configure irq + extint_register_pin(self, args[ARG_trigger].u_int, + args[ARG_hard].u_bool, args[ARG_handler].u_obj); + } + + // TODO should return an IRQ object + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_pin_irq_obj, 1, machine_pin_irq); + +/// \method af() +/// Returns the currently configured alternate-function of the pin. The +/// integer returned will match one of the allowed constants for the af +/// argument to the init function. +STATIC mp_obj_t machine_pin_af(mp_obj_t self_in) { + return MP_OBJ_NEW_SMALL_INT(pin_get_af(MP_OBJ_TO_PTR(self_in))); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_pin_af_obj, machine_pin_af); + +STATIC const mp_rom_map_elem_t machine_pin_locals_dict_table[] = { + // instance methods + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_pin_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&machine_pin_value_obj) }, + { MP_ROM_QSTR(MP_QSTR_on), MP_ROM_PTR(&machine_pin_high_obj) }, + { MP_ROM_QSTR(MP_QSTR_off), MP_ROM_PTR(&machine_pin_low_obj) }, + { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&machine_pin_irq_obj) }, + { MP_ROM_QSTR(MP_QSTR_low), MP_ROM_PTR(&machine_pin_low_obj) }, + { MP_ROM_QSTR(MP_QSTR_high), MP_ROM_PTR(&machine_pin_high_obj) }, + { MP_ROM_QSTR(MP_QSTR_mode), MP_ROM_PTR(&machine_pin_mode_obj) }, + { MP_ROM_QSTR(MP_QSTR_pull), MP_ROM_PTR(&machine_pin_pull_obj) }, + { MP_ROM_QSTR(MP_QSTR_drive), MP_ROM_PTR(&machine_pin_drive_obj) }, + { MP_ROM_QSTR(MP_QSTR_toggle), MP_ROM_PTR(&machine_pin_toggle_obj) }, + #if 0 + { MP_ROM_QSTR(MP_QSTR_af_list), MP_ROM_PTR(&pin_af_list) }, + #endif + { MP_ROM_QSTR(MP_QSTR_af), MP_ROM_PTR(&machine_pin_af_obj) }, + + // class methods + { MP_ROM_QSTR(MP_QSTR_mapper), MP_ROM_PTR(&pin_mapper_obj) }, + { MP_ROM_QSTR(MP_QSTR_dict), MP_ROM_PTR(&pin_map_dict_obj) }, + { MP_ROM_QSTR(MP_QSTR_debug), MP_ROM_PTR(&pin_debug_obj) }, + + // class attributes + { MP_ROM_QSTR(MP_QSTR_board), MP_ROM_PTR(&pin_board_pins_obj_type) }, + { MP_ROM_QSTR(MP_QSTR_cpu), MP_ROM_PTR(&pin_cpu_pins_obj_type) }, + + + // class constants + { MP_ROM_QSTR(MP_QSTR_IN), MP_ROM_INT(GPIO_MODE_INPUT) }, + { MP_ROM_QSTR(MP_QSTR_OUT), MP_ROM_INT(GPIO_MODE_OUTPUT_PP) }, + { MP_ROM_QSTR(MP_QSTR_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_OUTPUT_OD) }, + { MP_ROM_QSTR(MP_QSTR_ALT), MP_ROM_INT(GPIO_MODE_AF_PP) }, + { MP_ROM_QSTR(MP_QSTR_ALT_OPEN_DRAIN), MP_ROM_INT(GPIO_MODE_AF_OD) }, + { MP_ROM_QSTR(MP_QSTR_ANALOG), MP_ROM_INT(GPIO_MODE_ANALOG) }, + { MP_ROM_QSTR(MP_QSTR_PULL_UP), MP_ROM_INT(GPIO_PULLUP) }, + { MP_ROM_QSTR(MP_QSTR_PULL_DOWN), MP_ROM_INT(GPIO_PULLDOWN) }, + { MP_ROM_QSTR(MP_QSTR_PULL_HOLD), MP_ROM_INT(GPIO_PULLHOLD) }, + { MP_ROM_QSTR(MP_QSTR_PULL_NONE), MP_ROM_INT(GPIO_NOPULL) }, + { MP_ROM_QSTR(MP_QSTR_LOW_POWER), MP_ROM_INT(GPIO_LOW_POWER) }, + { MP_ROM_QSTR(MP_QSTR_MED_POWER), MP_ROM_INT(GPIO_MED_POWER) }, + { MP_ROM_QSTR(MP_QSTR_HIGH_POWER), MP_ROM_INT(GPIO_HIGH_POWER) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_RISING), MP_ROM_INT(GPIO_MODE_IT_RISING) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_FALLING), MP_ROM_INT(GPIO_MODE_IT_FALLING) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_RISING_FALLING), MP_ROM_INT(GPIO_MODE_IT_RISING_FALLING) }, + { MP_ROM_QSTR(MP_QSTR_EVT_RISING), MP_ROM_INT(GPIO_MODE_EVT_RISING) }, + { MP_ROM_QSTR(MP_QSTR_EVT_FALLING), MP_ROM_INT(GPIO_MODE_EVT_FALLING) }, + { MP_ROM_QSTR(MP_QSTR_EVT_RISING_FALLING), MP_ROM_INT(GPIO_MODE_EVT_RISING_FALLING) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_LOWLEVEL), MP_ROM_INT(GPIO_IRQ_LOWLEVEL) }, + { MP_ROM_QSTR(MP_QSTR_IRQ_HIGHLEVEL), MP_ROM_INT(GPIO_IRQ_HIGHLEVEL) }, +}; +STATIC MP_DEFINE_CONST_DICT(machine_pin_locals_dict, machine_pin_locals_dict_table); + +STATIC mp_uint_t machine_pin_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { + (void)errcode; + machine_pin_obj_t *self = MP_OBJ_TO_PTR(self_in); + + switch (request) { + case MP_PIN_READ: { + return mp_hal_pin_read(self); + } + case MP_PIN_WRITE: { + mp_hal_pin_write(self, arg); + return 0; + } + } + return -1; +} + +STATIC const mp_pin_p_t machine_pin_pin_p = { + .ioctl = machine_pin_ioctl, +}; + +const mp_obj_type_t machine_pin_type = { + { &mp_type_type }, + .name = MP_QSTR_Pin, + .print = machine_pin_print, + .make_new = mp_pin_make_new, + .call = machine_pin_call, + .protocol = &machine_pin_pin_p, + .locals_dict = (mp_obj_t)&machine_pin_locals_dict, +}; + +// Returns the pin mode. This value returned by this macro should be one of: +// GPIO_MODE_INPUT, GPIO_MODE_OUTPUT_PP, GPIO_MODE_OUTPUT_OD, +// GPIO_MODE_AF_PP, GPIO_MODE_AF_OD, or GPIO_MODE_ANALOG. + +uint32_t pin_get_mode(const machine_pin_obj_t *pin) { + return ra_gpio_get_mode(pin->pin); +} + +// Returns the pin pullup/pulldown. The value returned by this macro should +// be one of GPIO_NOPULL, GPIO_PULLUP, or GPIO_PULLDOWN. + +uint32_t pin_get_pull(const machine_pin_obj_t *pin) { + return (uint32_t)ra_gpio_get_pull(pin->pin); +} + +// Returns the pin drive. The value returned by this macro should +// be one of GPIO_HIGH_POWER, GPIO_MED_POWER, or GPIO_LOW_POWER. + +uint32_t pin_get_drive(const machine_pin_obj_t *pin) { + return (uint32_t)ra_gpio_get_drive(pin->pin); +} + +// Returns the af (alternate function) index currently set for a pin. + +uint32_t pin_get_af(const machine_pin_obj_t *pin) { + return (uint32_t)ra_gpio_get_af(pin->pin); +} + +const mp_obj_type_t pin_cpu_pins_obj_type = { + { &mp_type_type }, + .name = MP_QSTR_cpu, + .locals_dict = (mp_obj_dict_t *)&pin_cpu_pins_locals_dict, +}; + +const mp_obj_type_t pin_board_pins_obj_type = { + { &mp_type_type }, + .name = MP_QSTR_board, + .locals_dict = (mp_obj_dict_t *)&pin_board_pins_locals_dict, +}; + +const machine_pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name) { + const mp_map_t *named_map = &named_pins->map; + mp_map_elem_t *named_elem = mp_map_lookup((mp_map_t *)named_map, name, MP_MAP_LOOKUP); + if (named_elem != NULL && named_elem->value != MP_OBJ_NULL) { + return MP_OBJ_TO_PTR(named_elem->value); + } + return NULL; +} + +const pin_af_obj_t *pin_find_af(const machine_pin_obj_t *pin, uint8_t fn, uint8_t unit) { + const pin_af_obj_t *af = pin->af; + for (mp_uint_t i = 0; i < pin->num_af; i++, af++) { + if (af->fn == fn && af->unit == unit) { + return af; + } + } + return NULL; +} + +const pin_af_obj_t *pin_find_af_by_index(const machine_pin_obj_t *pin, mp_uint_t af_idx) { + const pin_af_obj_t *af = pin->af; + for (mp_uint_t i = 0; i < pin->num_af; i++, af++) { + if (af->idx == af_idx) { + return af; + } + } + return NULL; +} + +// ==================================================================== +// PinAF +// ==================================================================== + +/// \moduleref pyb +/// \class PinAF - Pin Alternate Functions +/// +/// A Pin represents a physical pin on the microcprocessor. Each pin +/// can have a variety of functions (GPIO, I2C SDA, etc). Each PinAF +/// object represents a particular function for a pin. +/// +/// Usage Model: +/// +/// x3 = pyb.Pin.board.X3 +/// x3_af = x3.af_list() +/// +/// x3_af will now contain an array of PinAF objects which are availble on +/// pin X3. +/// +/// For the pyboard, x3_af would contain: +/// [Pin.AF1_TIM2, Pin.AF2_TIM5, Pin.AF3_TIM9, Pin.AF7_USART2] +/// +/// Normally, each peripheral would configure the af automatically, but sometimes +/// the same function is available on multiple pins, and having more control +/// is desired. +/// +/// To configure X3 to expose TIM2_CH3, you could use: +/// pin = pyb.Pin(pyb.Pin.board.X3, mode=pyb.Pin.AF_PP, af=pyb.Pin.AF1_TIM2) +/// or: +/// pin = pyb.Pin(pyb.Pin.board.X3, mode=pyb.Pin.AF_PP, af=1) + +/// \method __str__() +/// Return a string describing the alternate function. +STATIC void pin_af_obj_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pin_af_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "Pin.%q", self->name); +} + +/// \method index() +/// Return the alternate function index. +STATIC mp_obj_t pin_af_index(mp_obj_t self_in) { + pin_af_obj_t *af = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_SMALL_INT(af->idx); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_index_obj, pin_af_index); + +/// \method name() +/// Return the name of the alternate function. +STATIC mp_obj_t pin_af_name(mp_obj_t self_in) { + pin_af_obj_t *af = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_QSTR(af->name); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_name_obj, pin_af_name); + +STATIC mp_obj_t pin_af_reg(mp_obj_t self_in) { + pin_af_obj_t *af = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_SMALL_INT((uintptr_t)af->reg); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pin_af_reg_obj, pin_af_reg); + +STATIC const mp_rom_map_elem_t pin_af_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_index), MP_ROM_PTR(&pin_af_index_obj) }, + { MP_ROM_QSTR(MP_QSTR_name), MP_ROM_PTR(&pin_af_name_obj) }, + { MP_ROM_QSTR(MP_QSTR_reg), MP_ROM_PTR(&pin_af_reg_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(pin_af_locals_dict, pin_af_locals_dict_table); + +const mp_obj_type_t pin_af_type = { + { &mp_type_type }, + .name = MP_QSTR_PinAF, + .print = pin_af_obj_print, + .locals_dict = (mp_obj_dict_t *)&pin_af_locals_dict, +}; diff --git a/ports/renesas-ra/machine_rtc.c b/ports/renesas-ra/machine_rtc.c new file mode 100644 index 000000000..9f698b6bc --- /dev/null +++ b/ports/renesas-ra/machine_rtc.c @@ -0,0 +1,349 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> + +#include "py/runtime.h" +#include "shared/timeutils/timeutils.h" +#include "extint.h" +#include "rtc.h" +#include "irq.h" +#if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) | defined(RA6M1) | defined(RA6M2) | defined(RA6M3) +#include "ra_rtc.h" +#endif + +#define RTC_INIT_YEAR 2019 +#define RTC_INIT_MONTH 1 +#define RTC_INIT_DATE 1 +#define RTC_INIT_WEEKDAY 2 /* Tuesday */ +#define RTC_INIT_HOUR 0 +#define RTC_INIT_MINUTE 0 +#define RTC_INIT_SECOND 0 + +/// \moduleref pyb +/// \class RTC - real time clock +/// +/// The RTC is and independent clock that keeps track of the date +/// and time. +/// +/// Example usage: +/// +/// rtc = pyb.RTC() +/// rtc.datetime((2014, 5, 1, 4, 13, 0, 0, 0)) +/// print(rtc.datetime()) + +#define HAL_StatusTypeDef void +// rtc_info indicates various things about RTC startup +// it's a bit of a hack at the moment +static mp_uint_t rtc_info; + +STATIC uint32_t rtc_startup_tick; +STATIC bool rtc_need_init_finalise = false; +STATIC uint32_t rtc_wakeup_param; + +STATIC void rtc_calendar_config(void) { + ra_rtc_t tm; + tm.year = RTC_INIT_YEAR - 2000; + tm.month = RTC_INIT_MONTH; + tm.date = RTC_INIT_DATE; + tm.weekday = RTC_INIT_WEEKDAY; + tm.hour = RTC_INIT_HOUR; + tm.minute = RTC_INIT_MINUTE; + tm.second = RTC_INIT_SECOND; + ra_rtc_set_time(&tm); +} + +void rtc_get_time(RTC_TimeTypeDef *time) { + ra_rtc_t dt; + ra_rtc_get_time(&dt); + time->DayLightSaving = 0; + time->Hours = dt.hour; + time->Minutes = dt.minute; + time->SecondFraction = 0; + time->Seconds = dt.second; + // time->StoreOperation; + time->SubSeconds = 0; + time->TimeFormat = 0; +} + +void rtc_get_date(RTC_DateTypeDef *date) { + ra_rtc_t dt; + ra_rtc_get_time(&dt); + date->Date = dt.date; + date->Month = dt.month; + date->WeekDay = dt.weekday; + date->Year = (uint8_t)(dt.year - 2000); +} + +void rtc_init_start(bool force_init) { + /* Configure RTC prescaler and RTC data registers */ + #if (MICROPY_HW_RTC_SOURCE == 1) + // clock source is LOCO + ra_rtc_init(1); + #else + // clock source is subclock + ra_rtc_init(0); + #endif + rtc_need_init_finalise = false; + + if (!force_init) { + // So far, this case (force_init == false) is not called. + rtc_info |= 0x40000; + // or rtc_info |= 0x80000; + return; + } + + rtc_startup_tick = HAL_GetTick(); + rtc_info = 0x3f000000 | (rtc_startup_tick & 0xffffff); + rtc_need_init_finalise = true; +} + +void rtc_init_finalise(void) { + if (!rtc_need_init_finalise) { + return; + } + rtc_info = 0x20000000; + rtc_info |= (HAL_GetTick() - rtc_startup_tick) & 0xffff; + rtc_calendar_config(); + rtc_need_init_finalise = false; +} + +uint64_t mp_hal_time_ns(void) { + uint64_t ns = 0; + #if MICROPY_HW_ENABLE_RTC + // Get current according to the RTC. + rtc_init_finalise(); + RTC_TimeTypeDef time; + RTC_DateTypeDef date; + rtc_get_time(&time); + rtc_get_date(&date); + ns = timeutils_seconds_since_epoch(2000 + date.Year, date.Month, date.Date, time.Hours, time.Minutes, time.Seconds); + ns *= 1000000000ULL; + #endif + return ns; +} + +/******************************************************************************/ +// MicroPython bindings + +typedef struct _pyb_rtc_obj_t { + mp_obj_base_t base; +} pyb_rtc_obj_t; + +STATIC const pyb_rtc_obj_t pyb_rtc_obj = {{&pyb_rtc_type}}; + +/// \classmethod \constructor() +/// Create an RTC object. +STATIC mp_obj_t pyb_rtc_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 0, 0, false); + + // return constant object + return MP_OBJ_FROM_PTR(&pyb_rtc_obj); +} + +// force rtc to re-initialise +mp_obj_t pyb_rtc_init(mp_obj_t self_in) { + rtc_init_start(true); + rtc_init_finalise(); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_1(pyb_rtc_init_obj, pyb_rtc_init); + +/// \method info() +/// Get information about the startup time and reset source. +/// +/// - The lower 0xffff are the number of milliseconds the RTC took to +/// start up. +/// - Bit 0x10000 is set if a power-on reset occurred. +/// - Bit 0x20000 is set if an external reset occurred +mp_obj_t pyb_rtc_info(mp_obj_t self_in) { + return mp_obj_new_int(rtc_info); +} +MP_DEFINE_CONST_FUN_OBJ_1(pyb_rtc_info_obj, pyb_rtc_info); + +/// \method datetime([datetimetuple]) +/// Get or set the date and time of the RTC. +/// +/// With no arguments, this method returns an 8-tuple with the current +/// date and time. With 1 argument (being an 8-tuple) it sets the date +/// and time. +/// +/// The 8-tuple has the following format: +/// +/// (year, month, day, weekday, hours, minutes, seconds, subseconds) +/// +/// `weekday` is 1-7 for Monday through Sunday. +/// +/// `subseconds` counts down from 255 to 0 + +#define MEG_DIV_64 (1000000 / 64) +#define MEG_DIV_SCALE ((RTC_SYNCH_PREDIV + 1) / 64) + +#if defined(MICROPY_HW_RTC_USE_US) && MICROPY_HW_RTC_USE_US +uint32_t rtc_subsec_to_us(uint32_t ss) { + return ((RTC_SYNCH_PREDIV - ss) * MEG_DIV_64) / MEG_DIV_SCALE; +} + +uint32_t rtc_us_to_subsec(uint32_t us) { + return RTC_SYNCH_PREDIV - (us * MEG_DIV_SCALE / MEG_DIV_64); +} +#else +#define rtc_us_to_subsec +#define rtc_subsec_to_us +#endif + +mp_obj_t pyb_rtc_datetime(size_t n_args, const mp_obj_t *args) { + rtc_init_finalise(); + if (n_args == 1) { + ra_rtc_t time; + ra_rtc_get_time(&time); + mp_obj_t tuple[8] = { + mp_obj_new_int(time.year), + mp_obj_new_int(time.month), + mp_obj_new_int(time.date), + mp_obj_new_int(time.weekday), + mp_obj_new_int(time.hour), + mp_obj_new_int(time.minute), + mp_obj_new_int(time.second), + mp_obj_new_int(0), + }; + return mp_obj_new_tuple(8, tuple); + } else { + // set date and time + mp_obj_t *items; + mp_obj_get_array_fixed_n(args[1], 8, &items); + ra_rtc_t tm; + tm.year = mp_obj_get_int(items[0]); + tm.month = mp_obj_get_int(items[1]); + tm.date = mp_obj_get_int(items[2]); + tm.weekday = mp_obj_get_int(items[3]); + tm.hour = mp_obj_get_int(items[4]); + tm.minute = mp_obj_get_int(items[5]); + tm.second = mp_obj_get_int(items[6]); + ra_rtc_set_time(&tm); + return mp_const_none; + } +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_datetime_obj, 1, 2, pyb_rtc_datetime); + +// wakeup(None) +// wakeup(ms, callback=None) - ms should be between 4ms - 2000ms +// wakeup(wucksel, wut, callback) - not implemented +mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) { + bool enable = false; + mp_int_t ms; + mp_obj_t callback = mp_const_none; + uint32_t period = 0; + if (args[1] == mp_const_none) { + // disable wakeup + } else { + // time given in ms + ms = mp_obj_get_int(args[1]); + if (ms <= 4) { + period = 6; + } else if (ms <= 8) { + period = 7; + } else if (ms <= 16) { + period = 8; + } else if (ms <= 32) { + period = 9; + } else if (ms <= 63) { + period = 10; + } else if (ms <= 125) { + period = 11; + } else if (ms <= 250) { + period = 12; + } else if (ms <= 500) { + period = 13; + } else if (ms <= 1000) { + period = 14; + } else if (ms <= 2000) { + period = 15; + } + enable = true; + } + if (n_args >= 2) { + callback = args[2]; + } + // set the callback + MP_STATE_PORT(pyb_extint_callback)[EXTI_RTC_WAKEUP] = callback; + pyb_extint_callback_arg[EXTI_RTC_WAKEUP] = MP_OBJ_NEW_SMALL_INT(EXTI_RTC_WAKEUP); + rtc_wakeup_param = EXTI_RTC_WAKEUP; + if (enable) { + if (callback != mp_const_none) { + ra_rtc_set_period_func((void *)extint_callback, (void *)&rtc_wakeup_param); + } else { + ra_rtc_set_period_func((void *)NULL, (void *)NULL); + } + ra_rtc_set_period_time(period); + ra_rtc_period_on(); + } else { + ra_rtc_period_off(); + } + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_wakeup_obj, 2, 3, pyb_rtc_wakeup); + +// calibration(None) +// calibration(cal) +// When an integer argument is provided, check that it falls in the range [-63(s) to 63(s)] +// and set the calibration value; otherwise return calibration value +mp_obj_t pyb_rtc_calibration(size_t n_args, const mp_obj_t *args) { + rtc_init_finalise(); + mp_int_t cal; + if (n_args == 2) { + cal = mp_obj_get_int(args[1]); + if (cal < -63 || cal > 63) { + mp_raise_ValueError(MP_ERROR_TEXT("calibration value out of range")); + } else { + ra_rtc_set_adjustment(cal, 0); // calibration for second + } + return mp_const_none; + } else { + // get calibration register + cal = (mp_int_t)ra_rtc_get_adjustment(); + return mp_obj_new_int(cal); + } +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_calibration_obj, 1, 2, pyb_rtc_calibration); + +STATIC const mp_rom_map_elem_t pyb_rtc_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_rtc_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_info), MP_ROM_PTR(&pyb_rtc_info_obj) }, + { MP_ROM_QSTR(MP_QSTR_datetime), MP_ROM_PTR(&pyb_rtc_datetime_obj) }, + { MP_ROM_QSTR(MP_QSTR_wakeup), MP_ROM_PTR(&pyb_rtc_wakeup_obj) }, + { MP_ROM_QSTR(MP_QSTR_calibration), MP_ROM_PTR(&pyb_rtc_calibration_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(pyb_rtc_locals_dict, pyb_rtc_locals_dict_table); + +const mp_obj_type_t pyb_rtc_type = { + { &mp_type_type }, + .name = MP_QSTR_RTC, + .make_new = pyb_rtc_make_new, + .locals_dict = (mp_obj_dict_t *)&pyb_rtc_locals_dict, +}; diff --git a/ports/renesas-ra/machine_spi.c b/ports/renesas-ra/machine_spi.c new file mode 100644 index 000000000..01972ad45 --- /dev/null +++ b/ports/renesas-ra/machine_spi.c @@ -0,0 +1,379 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2018 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/mphal.h" +#include "py/mperrno.h" +#include "extmod/machine_spi.h" +#include "pin.h" +#include "spi.h" +#include "ra/ra_spi.h" +#include "modmachine.h" + +typedef struct _machine_hard_spi_obj_t { + mp_obj_base_t base; + uint8_t spi_id; + uint8_t polarity; + uint8_t phase; + uint8_t bits; + uint8_t firstbit; + uint32_t baudrate; + mp_hal_pin_obj_t sck; + mp_hal_pin_obj_t mosi; + mp_hal_pin_obj_t miso; +} machine_hard_spi_obj_t; + +#define DEFAULT_SPI_BAUDRATE (500000) +#define DEFAULT_SPI_POLARITY (0) +#define DEFAULT_SPI_PHASE (0) +#define DEFAULT_SPI_BITS (8) +#define DEFAULT_SPI_FIRSTBIT (MICROPY_PY_MACHINE_SPI_MSB) + +#define IS_VALID_SCK(obj_pin, arg_pin) ((obj_pin) == (arg_pin)) +#define IS_VALID_MOSI(obj_pin, arg_pin) ((obj_pin) == (arg_pin)) +#define IS_VALID_MISO(obj_pin, arg_pin) ((obj_pin) == (arg_pin)) +#define IS_VALID_POLARITY(n) (((n) == 0) || ((n) == 1)) +#define IS_VALID_PHASE(n) (((n) == 0) || ((n) == 1)) +#define IS_VALID_BITS(n) (((n) == 8) || ((n) == 16) || ((n) == 32)) +#define IS_VALID_FIRSTBIT(n) ((n) == MICROPY_PY_MACHINE_SPI_LSB) + +/******************************************************************************/ +// Implementation of hard SPI for machine module + +STATIC machine_hard_spi_obj_t machine_hard_spi_obj[] = { + #if defined(MICROPY_HW_SPI0_RSPCK) + { + {&machine_hard_spi_type}, 0, + DEFAULT_SPI_POLARITY, DEFAULT_SPI_PHASE, DEFAULT_SPI_BITS, + DEFAULT_SPI_FIRSTBIT, DEFAULT_SPI_BAUDRATE, + MICROPY_HW_SPI0_RSPCK, MICROPY_HW_SPI0_MOSI, MICROPY_HW_SPI0_MISO, + }, + #endif + #if defined(MICROPY_HW_SPI1_RSPCK) + { + {&machine_hard_spi_type}, 1, + DEFAULT_SPI_POLARITY, DEFAULT_SPI_PHASE, DEFAULT_SPI_BITS, + DEFAULT_SPI_FIRSTBIT, DEFAULT_SPI_BAUDRATE, + MICROPY_HW_SPI1_RSPCK, MICROPY_HW_SPI1_MOSI, MICROPY_HW_SPI1_MISO, + }, + #endif +}; + +STATIC void machine_hard_spi_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_hard_spi_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "SPI(%u, baudrate=%u, polarity=%u, phase=%u, bits=%u, firstbit=%u, sck=%q, mosi=%q, miso=%q)", + self->spi_id, self->baudrate, self->polarity, self->phase, self->bits, + self->firstbit, self->sck->name, self->mosi->name, self->miso->name); +} + +mp_obj_t machine_hard_spi_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + MP_MACHINE_SPI_CHECK_FOR_LEGACY_SOFTSPI_CONSTRUCTION(n_args, n_kw, all_args); + + enum { ARG_id, ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits, ARG_firstbit, ARG_sck, ARG_mosi, ARG_miso }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_id, MP_ARG_REQUIRED | MP_ARG_OBJ }, + { MP_QSTR_baudrate, MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_sck, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_mosi, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_miso, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // get the SPI bus id. + bool found = false; + int spi_id = mp_obj_get_int(args[ARG_id].u_obj); + machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t *)&machine_hard_spi_obj[0]; + for (int i = 0; i < MP_ARRAY_SIZE(machine_hard_spi_obj); i++) { + if (spi_id == self->spi_id) { + found = true; + break; + } + ++self; + } + if (found != true) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("SPI(%d) doesno't exist"), spi_id); + } + + if (args[ARG_baudrate].u_int != -1) { + self->baudrate = args[ARG_baudrate].u_int; + } + if (args[ARG_polarity].u_int != -1) { + if (IS_VALID_POLARITY(args[ARG_polarity].u_int)) { + self->polarity = args[ARG_polarity].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad polarity")); + } + } + if (args[ARG_phase].u_int != -1) { + if (IS_VALID_PHASE(args[ARG_phase].u_int)) { + self->phase = args[ARG_phase].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad phase")); + } + } + if (args[ARG_bits].u_int != -1) { + if (IS_VALID_BITS(args[ARG_bits].u_int)) { + self->bits = args[ARG_bits].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad bits")); + } + } + if (args[ARG_firstbit].u_int != -1) { + if (IS_VALID_FIRSTBIT(args[ARG_firstbit].u_int)) { + self->firstbit = args[ARG_firstbit].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad firstbit")); + } + } + // Set SCK/MOSI/MISO pins if configured. + // currently pins are fixed, can not be changed. + uint8_t sck, mosi, miso; + + if (args[ARG_sck].u_obj == MP_OBJ_NULL) { + sck = self->sck->pin; + } else { + const machine_pin_obj_t *arg_sck = mp_hal_get_pin_obj(args[ARG_sck].u_obj); + sck = arg_sck->pin; + if (!IS_VALID_SCK(self->sck->pin, sck)) { + mp_raise_ValueError(MP_ERROR_TEXT("bad SCK pin")); + } + } + if (args[ARG_mosi].u_obj == MP_OBJ_NULL) { + mosi = self->mosi->pin; + } else { + const machine_pin_obj_t *arg_mosi = mp_hal_get_pin_obj(args[ARG_mosi].u_obj); + mosi = arg_mosi->pin; + if (!IS_VALID_MOSI(self->mosi->pin, mosi)) { + mp_raise_ValueError(MP_ERROR_TEXT("bad MOSI pin")); + } + } + if (args[ARG_miso].u_obj == MP_OBJ_NULL) { + miso = self->miso->pin; + } else { + const machine_pin_obj_t *arg_miso = mp_hal_get_pin_obj(args[ARG_miso].u_obj); + miso = arg_miso->pin; + if (!IS_VALID_MISO(self->miso->pin, miso)) { + mp_raise_ValueError(MP_ERROR_TEXT("bad MISO pin")); + } + } + // init the SPI bus + spi_init(self->spi_id); + // set configurable paramaters + spi_set_params(self->spi_id, self->baudrate, self->polarity, + self->phase, self->bits, self->firstbit); + return MP_OBJ_FROM_PTR(self); +} + +STATIC void machine_hard_spi_init(mp_obj_base_t *self_in, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t *)self_in; + + enum { ARG_baudrate, ARG_polarity, ARG_phase, ARG_bits, ARG_firstbit, ARG_sck, ARG_mosi, ARG_miso }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_baudrate, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_polarity, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_phase, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_bits, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_firstbit, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_sck, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_mosi, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_miso, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + }; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // Set SCK/MOSI/MISO pins if configured. + // currently pins are fixed, can not be changed. + uint8_t sck, mosi, miso; + + if (args[ARG_baudrate].u_int != -1) { + self->baudrate = args[ARG_baudrate].u_int; + } + if (args[ARG_polarity].u_int != -1) { + if (IS_VALID_POLARITY(args[ARG_polarity].u_int)) { + self->polarity = args[ARG_polarity].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad polarity")); + } + } + if (args[ARG_phase].u_int != -1) { + if (IS_VALID_PHASE(args[ARG_phase].u_int)) { + self->phase = args[ARG_phase].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad phase")); + } + } + if (args[ARG_bits].u_int != -1) { + if (IS_VALID_BITS(args[ARG_bits].u_int)) { + self->bits = args[ARG_bits].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad bits")); + } + } + if (args[ARG_firstbit].u_int != -1) { + if (IS_VALID_FIRSTBIT(args[ARG_firstbit].u_int)) { + self->firstbit = args[ARG_firstbit].u_int; + } else { + mp_raise_ValueError(MP_ERROR_TEXT("bad firstbit")); + } + } + if (args[ARG_sck].u_obj != MP_OBJ_NULL) { + const machine_pin_obj_t *arg_sck = mp_hal_get_pin_obj(args[ARG_sck].u_obj); + sck = arg_sck->pin; + if (!IS_VALID_SCK(self->sck->pin, sck)) { + mp_raise_ValueError(MP_ERROR_TEXT("bad SCK pin")); + } + } + if (args[ARG_mosi].u_obj != MP_OBJ_NULL) { + const machine_pin_obj_t *arg_mosi = mp_hal_get_pin_obj(args[ARG_mosi].u_obj); + mosi = arg_mosi->pin; + if (!IS_VALID_MOSI(self->mosi->pin, mosi)) { + mp_raise_ValueError(MP_ERROR_TEXT("bad MOSI pin")); + } + } + if (args[ARG_miso].u_obj != MP_OBJ_NULL) { + const machine_pin_obj_t *arg_miso = mp_hal_get_pin_obj(args[ARG_miso].u_obj); + miso = arg_miso->pin; + if (!IS_VALID_MISO(self->miso->pin, miso)) { + mp_raise_ValueError(MP_ERROR_TEXT("bad MISO pin")); + } + } + + if (self->firstbit == MICROPY_PY_MACHINE_SPI_LSB) { + mp_raise_NotImplementedError(MP_ERROR_TEXT("LSB")); + } + + // init the SPI bus + spi_init(self->spi_id); + // set configurable paramaters + spi_set_params(self->spi_id, self->baudrate, self->polarity, + self->phase, self->bits, self->firstbit); +} + +STATIC void machine_hard_spi_deinit(mp_obj_base_t *self_in) { + machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t *)self_in; + spi_deinit(self->spi_id); +} + +STATIC void machine_hard_spi_transfer(mp_obj_base_t *self_in, size_t len, const uint8_t *src, uint8_t *dest) { + machine_hard_spi_obj_t *self = (machine_hard_spi_obj_t *)self_in; + spi_transfer(self->spi_id, self->bits, len, src, dest, SPI_TRANSFER_TIMEOUT(len)); +} + +STATIC const mp_machine_spi_p_t machine_hard_spi_p = { + .init = machine_hard_spi_init, + .deinit = machine_hard_spi_deinit, + .transfer = machine_hard_spi_transfer, +}; + +const mp_obj_type_t machine_hard_spi_type = { + { &mp_type_type }, + .name = MP_QSTR_SPI, + .print = machine_hard_spi_print, + .make_new = machine_hard_spi_make_new, + .protocol = &machine_hard_spi_p, + .locals_dict = (mp_obj_dict_t *)&mp_machine_spi_locals_dict, +}; + +void spi_init0(void) { +} + +// sets the parameters in the SPI_InitTypeDef struct +// if an argument is -1 then the corresponding parameter is not changed +void spi_set_params(uint32_t ch, int32_t baudrate, + int32_t polarity, int32_t phase, int32_t bits, int32_t firstbit) { + ra_spi_set_mode(ch, polarity, phase); + ra_spi_set_clk(ch, baudrate); + ra_spi_set_bits(ch, bits); + ra_spi_set_lsb_first(ch, firstbit); +} + +void spi_init(uint32_t ch) { + const machine_pin_obj_t *pins[4] = { NULL, NULL, NULL, NULL }; + + if (0) { + #if defined(MICROPY_HW_SPI0_RSPCK) + } else if (ch == 0) { + #if defined(MICROPY_HW_SPI0_SSL) + pins[0] = MICROPY_HW_SPI0_SSL; + #endif + #if defined(MICROPY_HW_SPI0_RSPCK) + pins[1] = MICROPY_HW_SPI0_RSPCK; + #endif + #if defined(MICROPY_HW_SPI0_MISO) + pins[2] = MICROPY_HW_SPI0_MISO; + #endif + #if defined(MICROPY_HW_SPI0_MOSI) + pins[3] = MICROPY_HW_SPI0_MOSI; + #endif + ra_spi_init(ch, pins[3]->pin, pins[2]->pin, pins[1]->pin, pins[0]->pin, DEFAULT_SPI_BAUDRATE, DEFAULT_SPI_BITS, DEFAULT_SPI_POLARITY, DEFAULT_SPI_PHASE); + #endif + #if defined(MICROPY_HW_SPI1_RSPCK) + } else if (ch == 1) { + #if defined(MICROPY_HW_SPI1_SSL) + pins[0] = MICROPY_HW_SPI1_SSL; + #endif + #if defined(MICROPY_HW_SPI1_RSPCK) + pins[1] = MICROPY_HW_SPI1_RSPCK; + #endif + #if defined(MICROPY_HW_SPI1_MISO) + pins[2] = MICROPY_HW_SPI1_MISO; + #endif + #if defined(MICROPY_HW_SPI1_MOSI) + pins[3] = MICROPY_HW_SPI1_MOSI; + #endif + ra_spi_init(ch, pins[3]->pin, pins[2]->pin, pins[1]->pin, pins[0]->pin, DEFAULT_SPI_BAUDRATE, DEFAULT_SPI_BITS, DEFAULT_SPI_POLARITY, DEFAULT_SPI_PHASE); + #endif + } else { + // SPI does not exist for this board (shouldn't get here, should be checked by caller) + return; + } +} + +void spi_deinit(uint32_t ch) { + if (0) { + #if defined(MICROPY_HW_SPI0_RSPCK) + } else if (ch == 0) { + ra_spi_deinit(ch, 0); + #endif + #if defined(MICROPY_HW_SPI1_RSPCK) + } else if (ch == 1) { + ra_spi_deinit(ch, 0); + #endif + } +} + +void spi_transfer(uint32_t ch, uint32_t bits, size_t len, const uint8_t *src, uint8_t *dest, uint32_t timeout) { + ra_spi_transfer(ch, bits, dest, (uint8_t *)src, (uint32_t)len, timeout); +} diff --git a/ports/renesas-ra/machine_timer.c b/ports/renesas-ra/machine_timer.c new file mode 100644 index 000000000..c94532218 --- /dev/null +++ b/ports/renesas-ra/machine_timer.c @@ -0,0 +1,145 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mphal.h" +#include "softtimer.h" + +typedef soft_timer_entry_t machine_timer_obj_t; + +const mp_obj_type_t machine_timer_type; + +STATIC void machine_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + machine_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + qstr mode = self->mode == SOFT_TIMER_MODE_ONE_SHOT ? MP_QSTR_ONE_SHOT : MP_QSTR_PERIODIC; + mp_printf(print, "Timer(mode=%q, period=%u)", mode, self->delta_ms); +} + +STATIC mp_obj_t machine_timer_init_helper(machine_timer_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + enum { ARG_mode, ARG_callback, ARG_period, ARG_tick_hz, ARG_freq, }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_mode, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = SOFT_TIMER_MODE_PERIODIC} }, + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_obj = MP_OBJ_NULL} }, + { MP_QSTR_period, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0xffffffff} }, + { MP_QSTR_tick_hz, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 1000} }, + { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + }; + + // Parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + self->mode = args[ARG_mode].u_int; + + uint64_t delta_ms = self->delta_ms; + if (args[ARG_freq].u_obj != mp_const_none) { + // Frequency specified in Hz + #if MICROPY_PY_BUILTINS_FLOAT + delta_ms = (uint32_t)(MICROPY_FLOAT_CONST(1000.0) / mp_obj_get_float(args[ARG_freq].u_obj)); + #else + delta_ms = 1000 / mp_obj_get_int(args[ARG_freq].u_obj); + #endif + } else if (args[ARG_period].u_int != 0xffffffff) { + // Period specified + delta_ms = (uint64_t)args[ARG_period].u_int * 1000 / args[ARG_tick_hz].u_int; + } + + if (delta_ms < 1) { + delta_ms = 1; + } else if (delta_ms >= 0x40000000) { + mp_raise_ValueError(MP_ERROR_TEXT("period too large")); + } + self->delta_ms = (uint32_t)delta_ms; + + if (args[ARG_callback].u_obj != MP_OBJ_NULL) { + self->py_callback = args[ARG_callback].u_obj; + } + + if (self->py_callback != mp_const_none) { + soft_timer_insert(self, self->delta_ms); + } + + return mp_const_none; +} + +STATIC mp_obj_t machine_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + machine_timer_obj_t *self = m_new_obj(machine_timer_obj_t); + self->pairheap.base.type = &machine_timer_type; + self->flags = SOFT_TIMER_FLAG_PY_CALLBACK | SOFT_TIMER_FLAG_GC_ALLOCATED; + self->delta_ms = 1000; + self->py_callback = mp_const_none; + + // Get timer id (only soft timer (-1) supported at the moment) + mp_int_t id = -1; + if (n_args > 0) { + id = mp_obj_get_int(args[0]); + --n_args; + ++args; + } + if (id != -1) { + mp_raise_ValueError(MP_ERROR_TEXT("Timer doesn't exist")); + } + + if (n_args > 0 || n_kw > 0) { + // Start the timer + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + machine_timer_init_helper(self, n_args, args, &kw_args); + } + + return MP_OBJ_FROM_PTR(self); +} + +STATIC mp_obj_t machine_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + machine_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]); + soft_timer_remove(self); + return machine_timer_init_helper(self, n_args - 1, args + 1, kw_args); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(machine_timer_init_obj, 1, machine_timer_init); + +STATIC mp_obj_t machine_timer_deinit(mp_obj_t self_in) { + machine_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + soft_timer_remove(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(machine_timer_deinit_obj, machine_timer_deinit); + +STATIC const mp_rom_map_elem_t machine_timer_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&machine_timer_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&machine_timer_deinit_obj) }, + + { MP_ROM_QSTR(MP_QSTR_ONE_SHOT), MP_ROM_INT(SOFT_TIMER_MODE_ONE_SHOT) }, + { MP_ROM_QSTR(MP_QSTR_PERIODIC), MP_ROM_INT(SOFT_TIMER_MODE_PERIODIC) }, +}; +STATIC MP_DEFINE_CONST_DICT(machine_timer_locals_dict, machine_timer_locals_dict_table); + +const mp_obj_type_t machine_timer_type = { + { &mp_type_type }, + .name = MP_QSTR_Timer, + .print = machine_timer_print, + .make_new = machine_timer_make_new, + .locals_dict = (mp_obj_dict_t *)&machine_timer_locals_dict, +}; diff --git a/ports/renesas-ra/machine_uart.c b/ports/renesas-ra/machine_uart.c new file mode 100644 index 000000000..59fa469c3 --- /dev/null +++ b/ports/renesas-ra/machine_uart.c @@ -0,0 +1,583 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2018 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> +#include <stdarg.h> + +#include "py/runtime.h" +#include "py/stream.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "shared/runtime/interrupt_char.h" +#include "shared/runtime/mpirq.h" +#include "uart.h" +#include "irq.h" +#include "pendsv.h" + +#define DEFAULT_UART_BAUDRATE (115200) + +STATIC const char *_parity_name[] = {"None", "ODD", "EVEN"}; + +/// \moduleref pyb +/// \class UART - duplex serial communication bus +/// +/// UART implements the standard UART/USART duplex serial communications protocol. At +/// the physical level it consists of 2 lines: RX and TX. The unit of communication +/// is a character (not to be confused with a string character) which can be 8 or 9 +/// bits wide. +/// +/// UART objects can be created and initialised using: +/// +/// from pyb import UART +/// +/// uart = UART(1, 9600) # init with given baudrate +/// uart.init(9600, bits=8, parity=None, stop=1) # init with given parameters +/// +/// Bits can be 8 or 9. Parity can be None, 0 (even) or 1 (odd). Stop can be 1 or 2. +/// +/// A UART object acts like a stream object and reading and writing is done +/// using the standard stream methods: +/// +/// uart.read(10) # read 10 characters, returns a bytes object +/// uart.read() # read all available characters +/// uart.readline() # read a line +/// uart.readinto(buf) # read and store into the given buffer +/// uart.write('abc') # write the 3 characters +/// +/// Individual characters can be read/written using: +/// +/// uart.readchar() # read 1 character and returns it as an integer +/// uart.writechar(42) # write 1 character +/// +/// To check if there is anything to be read, use: +/// +/// uart.any() # returns True if any characters waiting + +STATIC void pyb_uart_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (!self->is_enabled) { + mp_printf(print, "UART(%u)", self->uart_id); + } else { + mp_printf(print, "UART(%u, baudrate=%u, bits=%u, parity=%s, stop=%u", + self->uart_id, self->baudrate, self->bits, + _parity_name[self->parity], self->stop); + mp_printf(print, ", tx=%q, rx=%q", self->tx->name, self->rx->name); + if (self->rts) { + mp_printf(print, ", rts=%q", self->rts->name); + } + if (self->cts) { + mp_printf(print, ", cts=%q", self->cts->name); + } + mp_printf(print, ", flow=%d, rxbuf=%d, timeout=%u, timeout_char=%u", + self->flow, + self->read_buf_len == 0 ? 0 : self->read_buf_len - 1, // -1 to adjust for usable length of buffer + self->timeout, self->timeout_char); + if (self->mp_irq_trigger != 0) { + mp_printf(print, ", irq=0x%x", self->mp_irq_trigger); + } + mp_print_str(print, ")"); + } +} + +/// \method init(baudrate, bits=8, parity=None, stop=1, *, timeout=1000, timeout_char=0, flow=0, read_buf_len=64) +/// +/// Initialise the UART bus with the given parameters: +/// +/// - `baudrate` is the clock rate. +/// - `bits` is the number of bits per byte, 7, 8 or 9. +/// - `parity` is the parity, `None`, 0 (even) or 1 (odd). +/// - `stop` is the number of stop bits, 1 or 2. +/// - `timeout` is the timeout in milliseconds to wait for the first character. +/// - `timeout_char` is the timeout in milliseconds to wait between characters. +/// - `flow` is RTS | CTS where RTS == 256, CTS == 512 +/// - `read_buf_len` is the character length of the read buffer (0 to disable). +STATIC mp_obj_t pyb_uart_init_helper(pyb_uart_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_baudrate, MP_ARG_INT | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_bits, MP_ARG_INT, {.u_int = 8} }, + { MP_QSTR_parity, MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_stop, MP_ARG_INT, {.u_int = 1} }, + { MP_QSTR_flow, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_timeout, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_timeout_char, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + { MP_QSTR_rxbuf, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_read_buf_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 512} }, // legacy + }; + + // parse args + struct { + mp_arg_val_t baudrate, bits, parity, stop, flow, timeout, timeout_char, rxbuf, read_buf_len; + } args; + mp_arg_parse_all(n_args, pos_args, kw_args, + MP_ARRAY_SIZE(allowed_args), allowed_args, (mp_arg_val_t *)&args); + + // baudrate + uint32_t baudrate = args.baudrate.u_int; + if (baudrate == 0) { + baudrate = DEFAULT_UART_BAUDRATE; + } + + // parity + uint32_t bits = args.bits.u_int; + uint32_t parity; + if (args.parity.u_obj == mp_const_none) { + parity = UART_PARITY_NONE; + } else { + mp_int_t p = mp_obj_get_int(args.parity.u_obj); + parity = (p & 1) ? UART_PARITY_ODD : UART_PARITY_EVEN; + bits += 1; // STs convention has bits including parity + } + + // number of bits + if (!((bits == 7) | (bits == 8) | (bits == 9))) { + mp_raise_ValueError(MP_ERROR_TEXT("unsupported combination of bits and parity")); + } + + // stop bits + uint32_t stop; + switch (args.stop.u_int) { + case 1: + stop = UART_STOPBITS_1; + break; + default: + stop = UART_STOPBITS_2; + break; + } + + // flow control + uint32_t flow = args.flow.u_int; + + // Save attach_to_repl setting because uart_init will disable it. + bool attach_to_repl = self->attached_to_repl; + + // uint32_t irq_state = disable_irq(); + + // init UART (if it fails, it's because the port doesn't exist) + if (!uart_init(self, baudrate, bits, parity, stop, flow)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%d) doesn't exist"), self->uart_id); + } + + // Restore attach_to_repl setting so UART still works if attached to dupterm. + uart_attach_to_repl(self, attach_to_repl); + + // set timeout + self->timeout = args.timeout.u_int; + + // set timeout_char + // make sure it is at least as long as a whole character (13 bits to be safe) + // minimum value is 2ms because sys-tick has a resolution of only 1ms + self->timeout_char = args.timeout_char.u_int; + uint32_t min_timeout_char = 13000 / baudrate + 2; + if (self->timeout_char < min_timeout_char) { + self->timeout_char = min_timeout_char; + } + + if (self->is_static) { + // Static UARTs have fixed memory for the rxbuf and can't be reconfigured. + if (args.rxbuf.u_int >= 0) { + mp_raise_ValueError(MP_ERROR_TEXT("UART is static and rxbuf can't be changed")); + } + uart_set_rxbuf(self, self->read_buf_len, self->read_buf); + } else { + // setup the read buffer + m_del(byte, self->read_buf, self->read_buf_len << self->char_width); + if (args.rxbuf.u_int >= 0) { + // rxbuf overrides legacy read_buf_len + args.read_buf_len.u_int = args.rxbuf.u_int; + } + if (args.read_buf_len.u_int <= 0) { + // no read buffer + uart_set_rxbuf(self, 0, NULL); + } else { + // read buffer using interrupts + size_t len = args.read_buf_len.u_int + 1; // +1 to adjust for usable length of buffer + uint8_t *buf = m_new(byte, len << self->char_width); + uart_set_rxbuf(self, len, buf); + } + } + + #if RA_TODO + // compute actual baudrate that was configured + uint32_t actual_baudrate = uart_get_baudrate(self); + + // check we could set the baudrate within 5% + uint32_t baudrate_diff; + if (actual_baudrate > baudrate) { + baudrate_diff = actual_baudrate - baudrate; + } else { + baudrate_diff = baudrate - actual_baudrate; + } + if (20 * baudrate_diff > actual_baudrate) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("set baudrate %d is not within 5%% of desired value"), actual_baudrate); + } + #endif + + // enable_irq(irq_state); + return mp_const_none; +} + +/// \classmethod \constructor(bus, ...) +/// +/// Construct a UART object on the given bus. `bus` can be 1-6, or 'XA', 'XB', 'YA', or 'YB'. +/// With no additional parameters, the UART object is created but not +/// initialised (it has the settings from the last initialisation of +/// the bus, if any). If extra arguments are given, the bus is initialised. +/// See `init` for parameters of initialisation. +/// +/// The physical pins of the UART buses are: +/// +/// - `UART(4)` is on `XA`: `(TX, RX) = (X1, X2) = (PA0, PA1)` +/// - `UART(1)` is on `XB`: `(TX, RX) = (X9, X10) = (PB6, PB7)` +/// - `UART(6)` is on `YA`: `(TX, RX) = (Y1, Y2) = (PC6, PC7)` +/// - `UART(3)` is on `YB`: `(TX, RX) = (Y9, Y10) = (PB10, PB11)` +/// - `UART(2)` is on: `(TX, RX) = (X3, X4) = (PA2, PA3)` +STATIC mp_obj_t pyb_uart_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); + + // work out port + int uart_id = 0; + if (mp_obj_is_str(args[0])) { + const char *port = mp_obj_str_get_str(args[0]); + if (0) { + #ifdef MICROPY_HW_UART0_NAME + } else if (strcmp(port, MICROPY_HW_UART0_NAME) == 0) { + uart_id = HW_UART_0; + #endif + #ifdef MICROPY_HW_UART1_NAME + } else if (strcmp(port, MICROPY_HW_UART1_NAME) == 0) { + uart_id = HW_UART_1; + #endif + #ifdef MICROPY_HW_UART2_NAME + } else if (strcmp(port, MICROPY_HW_UART2_NAME) == 0) { + uart_id = HW_UART_2; + #endif + #ifdef MICROPY_HW_UART3_NAME + } else if (strcmp(port, MICROPY_HW_UART3_NAME) == 0) { + uart_id = HW_UART_3; + #endif + #ifdef MICROPY_HW_UART4_NAME + } else if (strcmp(port, MICROPY_HW_UART4_NAME) == 0) { + uart_id = HW_UART_4; + #endif + #ifdef MICROPY_HW_UART5_NAME + } else if (strcmp(port, MICROPY_HW_UART5_NAME) == 0) { + uart_id = HW_UART_5; + #endif + #ifdef MICROPY_HW_UART6_NAME + } else if (strcmp(port, MICROPY_HW_UART6_NAME) == 0) { + uart_id = HW_UART_6; + #endif + #ifdef MICROPY_HW_UART7_NAME + } else if (strcmp(port, MICROPY_HW_UART7_NAME) == 0) { + uart_id = HW_UART_7; + #endif + #ifdef MICROPY_HW_UART8_NAME + } else if (strcmp(port, MICROPY_HW_UART8_NAME) == 0) { + uart_id = HW_UART_8; + #endif + #ifdef MICROPY_HW_UART9_NAME + } else if (strcmp(port, MICROPY_HW_UART9_NAME) == 0) { + uart_id = HW_UART_9; + #endif + } else { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%s) doesn't exist"), port); + } + } else { + uart_id = mp_obj_get_int(args[0]); + if (!uart_exists(uart_id)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%d) doesn't exist"), uart_id); + } + } + + // check if the UART is reserved for system use or not + if (MICROPY_HW_UART_IS_RESERVED(uart_id)) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("UART(%d) is reserved"), uart_id); + } + + pyb_uart_obj_t *self; + if (MP_STATE_PORT(pyb_uart_obj_all)[uart_id] == NULL) { + // create new UART object + self = m_new0(pyb_uart_obj_t, 1); + self->base.type = &pyb_uart_type; + self->uart_id = uart_id; + MP_STATE_PORT(pyb_uart_obj_all)[uart_id] = self; + } else { + // reference existing UART object + self = MP_STATE_PORT(pyb_uart_obj_all)[uart_id]; + } + + // start the peripheral + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + pyb_uart_init_helper(self, n_args - 1, args + 1, &kw_args); + + return MP_OBJ_FROM_PTR(self); +} + +STATIC mp_obj_t pyb_uart_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + return pyb_uart_init_helper(MP_OBJ_TO_PTR(args[0]), n_args - 1, args + 1, kw_args); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_init_obj, 1, pyb_uart_init); + +/// \method deinit() +/// Turn off the UART bus. +STATIC mp_obj_t pyb_uart_deinit(mp_obj_t self_in) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + uart_deinit(self); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_deinit_obj, pyb_uart_deinit); + +/// \method any() +/// Return `True` if any characters waiting, else `False`. +STATIC mp_obj_t pyb_uart_any(mp_obj_t self_in) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + return MP_OBJ_NEW_SMALL_INT(uart_rx_any(self)); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_any_obj, pyb_uart_any); + +/// \method writechar(char) +/// Write a single character on the bus. `char` is an integer to write. +/// Return value: `None`. +STATIC mp_obj_t pyb_uart_writechar(mp_obj_t self_in, mp_obj_t char_in) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + + // get the character to write (might be 9 bits) + uint16_t data = mp_obj_get_int(char_in); + + // write the character + int errcode; + if (uart_tx_wait(self, self->timeout)) { + uart_tx_data(self, &data, 1, &errcode); + } else { + errcode = MP_ETIMEDOUT; + } + + if (errcode != 0) { + mp_raise_OSError(errcode); + } + + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_uart_writechar_obj, pyb_uart_writechar); + +/// \method readchar() +/// Receive a single character on the bus. +/// Return value: The character read, as an integer. Returns -1 on timeout. +STATIC mp_obj_t pyb_uart_readchar(mp_obj_t self_in) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (uart_rx_wait(self, self->timeout)) { + return MP_OBJ_NEW_SMALL_INT(uart_rx_char(self)); + } else { + // return -1 on timeout + return MP_OBJ_NEW_SMALL_INT(-1); + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_readchar_obj, pyb_uart_readchar); + +// uart.sendbreak() +STATIC mp_obj_t pyb_uart_sendbreak(mp_obj_t self_in) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + ra_sci_tx_break((uint32_t)self->uart_id); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_uart_sendbreak_obj, pyb_uart_sendbreak); + +// irq(handler, trigger, hard) +STATIC mp_obj_t pyb_uart_irq(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + mp_arg_val_t args[MP_IRQ_ARG_INIT_NUM_ARGS]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_IRQ_ARG_INIT_NUM_ARGS, mp_irq_init_args, args); + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + + if (self->mp_irq_obj == NULL) { + self->mp_irq_trigger = 0; + self->mp_irq_obj = mp_irq_new(&uart_irq_methods, MP_OBJ_FROM_PTR(self)); + } + + if (n_args > 1 || kw_args->used != 0) { + // Check the handler + mp_obj_t handler = args[MP_IRQ_ARG_INIT_handler].u_obj; + if (handler != mp_const_none && !mp_obj_is_callable(handler)) { + mp_raise_ValueError(MP_ERROR_TEXT("handler must be None or callable")); + } + + // Check the trigger + mp_uint_t trigger = args[MP_IRQ_ARG_INIT_trigger].u_int; + mp_uint_t not_supported = trigger & ~MP_UART_ALLOWED_FLAGS; + if (trigger != 0 && not_supported) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("trigger 0x%08x unsupported"), not_supported); + } + + // Reconfigure user IRQs + uart_irq_config(self, false); + self->mp_irq_obj->handler = handler; + self->mp_irq_obj->ishard = args[MP_IRQ_ARG_INIT_hard].u_bool; + self->mp_irq_trigger = trigger; + uart_irq_config(self, true); + } + + return MP_OBJ_FROM_PTR(self->mp_irq_obj); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_uart_irq_obj, 1, pyb_uart_irq); + +STATIC const mp_rom_map_elem_t pyb_uart_locals_dict_table[] = { + // instance methods + + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_uart_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&pyb_uart_deinit_obj) }, + { MP_ROM_QSTR(MP_QSTR_any), MP_ROM_PTR(&pyb_uart_any_obj) }, + + /// \method read([nbytes]) + { MP_ROM_QSTR(MP_QSTR_read), MP_ROM_PTR(&mp_stream_read_obj) }, + /// \method readline() + { MP_ROM_QSTR(MP_QSTR_readline), MP_ROM_PTR(&mp_stream_unbuffered_readline_obj)}, + /// \method readinto(buf[, nbytes]) + { MP_ROM_QSTR(MP_QSTR_readinto), MP_ROM_PTR(&mp_stream_readinto_obj) }, + /// \method write(buf) + { MP_ROM_QSTR(MP_QSTR_write), MP_ROM_PTR(&mp_stream_write_obj) }, + { MP_ROM_QSTR(MP_QSTR_irq), MP_ROM_PTR(&pyb_uart_irq_obj) }, + + { MP_ROM_QSTR(MP_QSTR_writechar), MP_ROM_PTR(&pyb_uart_writechar_obj) }, + { MP_ROM_QSTR(MP_QSTR_readchar), MP_ROM_PTR(&pyb_uart_readchar_obj) }, + { MP_ROM_QSTR(MP_QSTR_sendbreak), MP_ROM_PTR(&pyb_uart_sendbreak_obj) }, + + // class constants + { MP_ROM_QSTR(MP_QSTR_RTS), MP_ROM_INT(UART_HWCONTROL_RTS) }, + { MP_ROM_QSTR(MP_QSTR_CTS), MP_ROM_INT(UART_HWCONTROL_CTS) }, +}; + +STATIC MP_DEFINE_CONST_DICT(pyb_uart_locals_dict, pyb_uart_locals_dict_table); + +STATIC mp_uint_t pyb_uart_read(mp_obj_t self_in, void *buf_in, mp_uint_t size, int *errcode) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + byte *buf = buf_in; + + // check that size is a multiple of character width + if (size & self->char_width) { + *errcode = MP_EIO; + return MP_STREAM_ERROR; + } + + // convert byte size to char size + size >>= self->char_width; + + // make sure we want at least 1 char + if (size == 0) { + return 0; + } + + // wait for first char to become available + if (!uart_rx_wait(self, self->timeout)) { + // return EAGAIN error to indicate non-blocking (then read() method returns None) + *errcode = MP_EAGAIN; + return MP_STREAM_ERROR; + } + + // read the data + byte *orig_buf = buf; + for (;;) { + int data = uart_rx_char(self); + if (self->char_width == CHAR_WIDTH_9BIT) { + *(uint16_t *)buf = data; + buf += 2; + } else { + *buf++ = data; + } + if (--size == 0 || !uart_rx_wait(self, self->timeout_char)) { + // return number of bytes read + return buf - orig_buf; + } + } +} + +STATIC mp_uint_t pyb_uart_write(mp_obj_t self_in, const void *buf_in, mp_uint_t size, int *errcode) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + const byte *buf = buf_in; + + // check that size is a multiple of character width + if (size & self->char_width) { + *errcode = MP_EIO; + return MP_STREAM_ERROR; + } + + // wait to be able to write the first character. EAGAIN causes write to return None + if (self->timeout != 0) { + if (!uart_tx_wait(self, self->timeout)) { + *errcode = MP_EAGAIN; + return MP_STREAM_ERROR; + } + } + + // write the data + size_t num_tx = uart_tx_data(self, buf, size >> self->char_width, errcode); + + if (*errcode == 0 || *errcode == MP_ETIMEDOUT) { + // return number of bytes written, even if there was a timeout + return num_tx << self->char_width; + } else { + return MP_STREAM_ERROR; + } +} + +STATIC mp_uint_t pyb_uart_ioctl(mp_obj_t self_in, mp_uint_t request, uintptr_t arg, int *errcode) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_uint_t ret; + if (request == MP_STREAM_POLL) { + uintptr_t flags = arg; + ret = 0; + if ((flags & MP_STREAM_POLL_RD) && uart_rx_any(self)) { + ret |= MP_STREAM_POLL_RD; + } + if ((flags & MP_STREAM_POLL_WR) && uart_tx_avail(self)) { + ret |= MP_STREAM_POLL_WR; + } + } else { + *errcode = MP_EINVAL; + ret = MP_STREAM_ERROR; + } + return ret; +} + +STATIC const mp_stream_p_t uart_stream_p = { + .read = pyb_uart_read, + .write = pyb_uart_write, + .ioctl = pyb_uart_ioctl, + .is_text = false, +}; + +const mp_obj_type_t pyb_uart_type = { + { &mp_type_type }, + .name = MP_QSTR_UART, + .print = pyb_uart_print, + .make_new = pyb_uart_make_new, + .getiter = mp_identity_getiter, + .iternext = mp_stream_unbuffered_iter, + .protocol = &uart_stream_p, + .locals_dict = (mp_obj_dict_t *)&pyb_uart_locals_dict, +}; diff --git a/ports/renesas-ra/main.c b/ports/renesas-ra/main.c new file mode 100644 index 000000000..82aa6be89 --- /dev/null +++ b/ports/renesas-ra/main.c @@ -0,0 +1,399 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2020 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/stackctrl.h" +#include "py/gc.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "shared/readline/readline.h" +#include "shared/runtime/pyexec.h" +#include "lib/oofatfs/ff.h" +#include "lib/littlefs/lfs1.h" +#include "lib/littlefs/lfs1_util.h" +#include "lib/littlefs/lfs2.h" +#include "lib/littlefs/lfs2_util.h" +#include "extmod/vfs.h" +#include "extmod/vfs_fat.h" +#include "extmod/vfs_lfs.h" + +#include "boardctrl.h" +#include "systick.h" +#include "pendsv.h" +#include "powerctrl.h" +#include "pybthread.h" +#include "gccollect.h" +#include "factoryreset.h" +#include "modmachine.h" +#include "softtimer.h" +#include "spi.h" +#include "uart.h" +#include "timer.h" +#include "led.h" +#include "pin.h" +#include "extint.h" +#include "usrsw.h" +#include "rtc.h" +#include "storage.h" + +#define RA_EARLY_PRINT 1 /* for enabling mp_print in boardctrl. */ + +#if MICROPY_PY_THREAD +STATIC pyb_thread_t pyb_thread_main; +#endif + +#if defined(MICROPY_HW_UART_REPL) +#ifndef MICROPY_HW_UART_REPL_RXBUF +#define MICROPY_HW_UART_REPL_RXBUF (260) +#endif +STATIC pyb_uart_obj_t pyb_uart_repl_obj; +STATIC uint8_t pyb_uart_repl_rxbuf[MICROPY_HW_UART_REPL_RXBUF]; +#endif + +void NORETURN __fatal_error(const char *msg) { + for (volatile uint delay = 0; delay < 1000000; delay++) { + } + led_state(1, 1); + led_state(2, 1); + led_state(3, 1); + led_state(4, 1); + mp_hal_stdout_tx_strn("\nFATAL ERROR:\n", 14); + mp_hal_stdout_tx_strn(msg, strlen(msg)); + for (uint i = 0;;) { + led_toggle(((i++) & 3) + 1); + for (volatile uint delay = 0; delay < 1000000; delay++) { + } + if (i >= 16) { + // to conserve power + __WFI(); + } + } +} + +void nlr_jump_fail(void *val) { + printf("FATAL: uncaught exception %p\n", val); + mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(val)); + __fatal_error(""); +} + +void abort(void) { + __fatal_error("abort"); +} + +#ifndef NDEBUG +void MP_WEAK __assert_func(const char *file, int line, const char *func, const char *expr) { + (void)func; + printf("Assertion '%s' failed, at file %s:%d\n", expr, file, line); + __fatal_error(""); +} +#endif + +STATIC mp_obj_t pyb_main(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_opt, MP_ARG_INT, {.u_int = 0} } + }; + + if (mp_obj_is_str(pos_args[0])) { + MP_STATE_PORT(pyb_config_main) = pos_args[0]; + + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 1, pos_args + 1, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + #if MICROPY_ENABLE_COMPILER + MP_STATE_VM(mp_optimise_value) = args[0].u_int; + #endif + } + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_KW(pyb_main_obj, 1, pyb_main); + +#if MICROPY_HW_FLASH_MOUNT_AT_BOOT +// avoid inlining to avoid stack usage within main() +MP_NOINLINE STATIC bool init_flash_fs(uint reset_mode) { + if (reset_mode == BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM) { + // Asked by user to reset filesystem + factory_reset_create_filesystem(); + } + + // Default block device to entire flash storage + mp_obj_t bdev = MP_OBJ_FROM_PTR(&pyb_flash_obj); + + int ret; + + #if MICROPY_VFS_LFS1 || MICROPY_VFS_LFS2 + + // Try to detect the block device used for the main filesystem based on the + // contents of the superblock, which can be the first or second block. + mp_int_t len = -1; + uint8_t buf[64]; + for (size_t block_num = 0; block_num <= 1; ++block_num) { + ret = storage_readblocks_ext(buf, block_num, 0, sizeof(buf)); + + #if MICROPY_VFS_LFS1 + if (ret == 0 && memcmp(&buf[40], "littlefs", 8) == 0) { + // LFS1 + lfs1_superblock_t *superblock = (void *)&buf[12]; + uint32_t block_size = lfs1_fromle32(superblock->d.block_size); + uint32_t block_count = lfs1_fromle32(superblock->d.block_count); + len = block_count * block_size; + break; + } + #endif + + #if MICROPY_VFS_LFS2 + if (ret == 0 && memcmp(&buf[8], "littlefs", 8) == 0) { + // LFS2 + lfs2_superblock_t *superblock = (void *)&buf[20]; + uint32_t block_size = lfs2_fromle32(superblock->block_size); + uint32_t block_count = lfs2_fromle32(superblock->block_count); + len = block_count * block_size; + break; + } + #endif + } + + if (len != -1) { + // Detected a littlefs filesystem so create correct block device for it + mp_obj_t args[] = { MP_OBJ_NEW_QSTR(MP_QSTR_len), MP_OBJ_NEW_SMALL_INT(len) }; + bdev = pyb_flash_type.make_new(&pyb_flash_type, 0, 1, args); + } + + #endif + + // Try to mount the flash on "/flash" and chdir to it for the boot-up directory. + mp_obj_t mount_point = MP_OBJ_NEW_QSTR(MP_QSTR__slash_flash); + ret = mp_vfs_mount_and_chdir_protected(bdev, mount_point); + + if (ret == -MP_ENODEV && bdev == MP_OBJ_FROM_PTR(&pyb_flash_obj) + && reset_mode != BOARDCTRL_RESET_MODE_FACTORY_FILESYSTEM) { + // No filesystem, bdev is still the default (so didn't detect a possibly corrupt littlefs), + // and didn't already create a filesystem, so try to create a fresh one now. + ret = factory_reset_create_filesystem(); + if (ret == 0) { + ret = mp_vfs_mount_and_chdir_protected(bdev, mount_point); + } + } + + if (ret != 0) { + printf("MPY: can't mount flash\n"); + return false; + } + + return true; +} +#endif + +void ra_main(uint32_t reset_mode) { + // Hook for a board to run code at start up, for example check if a + // bootloader should be entered instead of the main application. + MICROPY_BOARD_STARTUP(); + + // Initialize interrupt, systick and internal flash for RA. + ra_init(); + + MICROPY_BOARD_EARLY_INIT(); + + // basic sub-system init + #if MICROPY_PY_THREAD + pyb_thread_init(&pyb_thread_main); + #endif + pendsv_init(); + led_init(); + #if MICROPY_HW_HAS_SWITCH + switch_init0(); + #endif + machine_init(); + #if MICROPY_HW_ENABLE_RTC + rtc_init_start(false); + #endif + uart_init0(); + spi_init0(); + #if MICROPY_HW_ENABLE_STORAGE + storage_init(); + #endif + + #if defined(MICROPY_HW_UART_REPL) + // Set up a UART REPL using a statically allocated object + pyb_uart_repl_obj.base.type = &pyb_uart_type; + pyb_uart_repl_obj.uart_id = MICROPY_HW_UART_REPL; + pyb_uart_repl_obj.is_static = true; + pyb_uart_repl_obj.timeout = 0; + pyb_uart_repl_obj.timeout_char = 2; + uart_init(&pyb_uart_repl_obj, MICROPY_HW_UART_REPL_BAUD, UART_WORDLENGTH_8B, UART_PARITY_NONE, UART_STOPBITS_1, 0); + uart_set_rxbuf(&pyb_uart_repl_obj, sizeof(pyb_uart_repl_rxbuf), pyb_uart_repl_rxbuf); + uart_attach_to_repl(&pyb_uart_repl_obj, true); + MP_STATE_PORT(pyb_uart_obj_all)[MICROPY_HW_UART_REPL] = &pyb_uart_repl_obj; + #if RA_EARLY_PRINT + MP_STATE_PORT(pyb_stdio_uart) = &pyb_uart_repl_obj; + #endif + #endif + + boardctrl_state_t state; + state.reset_mode = reset_mode; + state.log_soft_reset = false; + + MICROPY_BOARD_BEFORE_SOFT_RESET_LOOP(&state); + +soft_reset: + + MICROPY_BOARD_TOP_SOFT_RESET_LOOP(&state); + + // Python threading init + #if MICROPY_PY_THREAD + mp_thread_init(); + #endif + + // Stack limit should be less than real stack size, so we have a chance + // to recover from limit hit. (Limit is measured in bytes.) + // Note: stack control relies on main thread being initialised above + mp_stack_set_top(&_estack); + mp_stack_set_limit((char *)&_estack - (char *)&_sstack - 1024); + + // GC init + gc_init(MICROPY_HEAP_START, MICROPY_HEAP_END); + + #if MICROPY_ENABLE_PYSTACK + static mp_obj_t pystack[384]; + mp_pystack_init(pystack, &pystack[384]); + #endif + + // MicroPython init + mp_init(); + + // Initialise low-level sub-systems. Here we need to very basic things like + // zeroing out memory and resetting any of the sub-systems. Following this + // we can run Python scripts (eg boot.py), but anything that is configurable + // by boot.py must be set after boot.py is run. + + #if defined(MICROPY_HW_UART_REPL) + MP_STATE_PORT(pyb_stdio_uart) = &pyb_uart_repl_obj; + #else + MP_STATE_PORT(pyb_stdio_uart) = NULL; + #endif + + readline_init0(); + machine_pin_init(); + extint_init0(); + timer_init0(); + + #if MICROPY_HW_ENABLE_I2S + machine_i2s_init0(); + #endif + + // Initialise the local flash filesystem. + // Create it if needed, mount in on /flash, and set it as current dir. + bool mounted_flash = false; + #if MICROPY_HW_FLASH_MOUNT_AT_BOOT + mounted_flash = init_flash_fs(state.reset_mode); + #endif + + // set sys.path based on mounted filesystems + if (mounted_flash) { + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_flash)); + mp_obj_list_append(mp_sys_path, MP_OBJ_NEW_QSTR(MP_QSTR__slash_flash_slash_lib)); + } + + // reset config variables; they should be set by boot.py + MP_STATE_PORT(pyb_config_main) = MP_OBJ_NULL; + + // Run optional frozen boot code. + #ifdef MICROPY_BOARD_FROZEN_BOOT_FILE + pyexec_frozen_module(MICROPY_BOARD_FROZEN_BOOT_FILE); + #endif + + // Run boot.py (or whatever else a board configures at this stage). + if (MICROPY_BOARD_RUN_BOOT_PY(&state) == BOARDCTRL_GOTO_SOFT_RESET_EXIT) { + goto soft_reset_exit; + } + + // Now we initialise sub-systems that need configuration from boot.py, + // or whose initialisation can be safely deferred until after running + // boot.py. + + // At this point everything is fully configured and initialised. + + // Run main.py (or whatever else a board configures at this stage). + if (MICROPY_BOARD_RUN_MAIN_PY(&state) == BOARDCTRL_GOTO_SOFT_RESET_EXIT) { + goto soft_reset_exit; + } + + #if MICROPY_ENABLE_COMPILER + // Main script is finished, so now go into REPL mode. + // The REPL mode can change, or it can request a soft reset. + for (;;) { + if (pyexec_mode_kind == PYEXEC_MODE_RAW_REPL) { + if (pyexec_raw_repl() != 0) { + break; + } + } else { + if (pyexec_friendly_repl() != 0) { + break; + } + } + } + #endif + +soft_reset_exit: + + // soft reset + + MICROPY_BOARD_START_SOFT_RESET(&state); + + #if MICROPY_HW_ENABLE_STORAGE + if (state.log_soft_reset) { + mp_printf(&mp_plat_print, "MPY: sync filesystems\n"); + } + storage_flush(); + #endif + + if (state.log_soft_reset) { + mp_printf(&mp_plat_print, "MPY: soft reboot\n"); + } + + soft_timer_deinit(); + timer_deinit(); + uart_deinit_all(); + #if MICROPY_HW_ENABLE_DAC + dac_deinit_all(); + #endif + machine_pin_deinit(); + machine_deinit(); + + #if MICROPY_PY_THREAD + pyb_thread_deinit(); + #endif + + MICROPY_BOARD_END_SOFT_RESET(&state); + + gc_sweep_all(); + mp_deinit(); + + goto soft_reset; +} diff --git a/ports/renesas-ra/modmachine.c b/ports/renesas-ra/modmachine.c new file mode 100644 index 000000000..7aea7c218 --- /dev/null +++ b/ports/renesas-ra/modmachine.c @@ -0,0 +1,304 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2015 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> + +#include "modmachine.h" +#include "py/gc.h" +#include "py/runtime.h" +#include "py/objstr.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "extmod/machine_mem.h" +#include "extmod/machine_signal.h" +#include "extmod/machine_pulse.h" +#include "extmod/machine_i2c.h" +#include "extmod/machine_spi.h" +#include "shared/runtime/pyexec.h" +#include "lib/oofatfs/ff.h" +#include "extmod/vfs.h" +#include "extmod/vfs_fat.h" +#include "drivers/dht/dht.h" +#include "gccollect.h" +#include "irq.h" +#include "powerctrl.h" +#include "pybthread.h" +#include "storage.h" +#include "pin.h" +#include "timer.h" +#include "rtc.h" +#include "spi.h" +#include "uart.h" + + +#define PYB_RESET_SOFT (0) +#define PYB_RESET_POWER_ON (1) +#define PYB_RESET_HARD (2) +#define PYB_RESET_WDT (3) +#define PYB_RESET_DEEPSLEEP (4) + +STATIC uint32_t reset_cause; + +void get_unique_id(uint8_t *id) { + uint32_t *p = (uint32_t *)id; + uint32_t *uniqueid = (uint32_t *)R_BSP_UniqueIdGet(); + p[0] = uniqueid[0]; + p[1] = uniqueid[1]; + p[2] = uniqueid[2]; + p[3] = uniqueid[3]; +} + +void machine_init(void) { +} + +void machine_deinit(void) { + // we are doing a soft-reset so change the reset_cause + reset_cause = PYB_RESET_SOFT; +} + +// machine.info([dump_alloc_table]) +// Print out lots of information about the board. +STATIC mp_obj_t machine_info(size_t n_args, const mp_obj_t *args) { + // get and print unique id; 128 bits + { + uint8_t id[16]; + get_unique_id((uint8_t *)&id); + printf("ID=%02x%02x%02x%02x:%02x%02x%02x%02x:%02x%02x%02x%02x:%02x%02x%02x%02x\n", + id[0], id[1], id[2], id[3], id[4], id[5], id[6], id[7], + id[8], id[9], id[10], id[11], id[12], id[13], id[14], id[15]); + } + // get and print clock speeds + // SystemCoreClock is an external variable in FSP + printf("S=%u\nP=%u\n", + (unsigned int)SystemCoreClock, + (unsigned int)MICROPY_HW_MCU_PCLK); + // to print info about memory + { + printf("_etext=%p\n", &_etext); + printf("_sidata=%p\n", &_sidata); + printf("_sdata=%p\n", &_sdata); + printf("_edata=%p\n", &_edata); + printf("_sbss=%p\n", &_sbss); + printf("_ebss=%p\n", &_ebss); + printf("_sstack=%p\n", &_sstack); + printf("_estack=%p\n", &_estack); + printf("_ram_start=%p\n", &_ram_start); + printf("_heap_start=%p\n", &_heap_start); + printf("_heap_end=%p\n", &_heap_end); + printf("_ram_end=%p\n", &_ram_end); + } + + // qstr info + { + size_t n_pool, n_qstr, n_str_data_bytes, n_total_bytes; + qstr_pool_info(&n_pool, &n_qstr, &n_str_data_bytes, &n_total_bytes); + printf("qstr:\n n_pool=%u\n n_qstr=%u\n n_str_data_bytes=%u\n n_total_bytes=%u\n", n_pool, n_qstr, n_str_data_bytes, n_total_bytes); + } + + // GC info + { + gc_info_t info; + gc_info(&info); + printf("GC:\n"); + printf(" %u total\n", info.total); + printf(" %u : %u\n", info.used, info.free); + printf(" 1=%u 2=%u m=%u\n", info.num_1block, info.num_2block, info.max_block); + } + + // free space on flash + { + #if MICROPY_VFS_FAT + for (mp_vfs_mount_t *vfs = MP_STATE_VM(vfs_mount_table); vfs != NULL; vfs = vfs->next) { + if (strncmp("/flash", vfs->str, vfs->len) == 0) { + // assumes that it's a FatFs filesystem + fs_user_mount_t *vfs_fat = MP_OBJ_TO_PTR(vfs->obj); + DWORD nclst; + f_getfree(&vfs_fat->fatfs, &nclst); + printf("LFS free: %u bytes\n", (uint)(nclst * vfs_fat->fatfs.csize * 512)); + break; + } + } + #endif + } + + #if MICROPY_PY_THREAD + pyb_thread_dump(); + #endif + + if (n_args == 1) { + // arg given means dump gc allocation table + gc_dump_alloc_table(); + } + + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj, 0, 1, machine_info); + +// Returns a string of 16 bytes (128 bits), which is the unique ID for the MCU. +STATIC mp_obj_t machine_unique_id(void) { + uint8_t id[16]; + get_unique_id((uint8_t *)&id); + return mp_obj_new_bytes(id, 16); +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_unique_id_obj, machine_unique_id); + +// Resets the pyboard in a manner similar to pushing the external RESET button. +STATIC mp_obj_t machine_reset(void) { + powerctrl_mcu_reset(); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_obj, machine_reset); + +STATIC mp_obj_t machine_soft_reset(void) { + pyexec_system_exit = PYEXEC_FORCED_EXIT; + mp_raise_type(&mp_type_SystemExit); +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_soft_reset_obj, machine_soft_reset); + +// Activate the bootloader without BOOT* pins. +STATIC NORETURN mp_obj_t machine_bootloader(size_t n_args, const mp_obj_t *args) { + #if MICROPY_HW_ENABLE_STORAGE + storage_flush(); + #endif + + __disable_irq(); + + #if MICROPY_HW_USES_BOOTLOADER + // ToDo: need to review how to implement + + #endif + + while (1) { + ; + } +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_bootloader_obj, 0, 1, machine_bootloader); + +// get or set the MCU frequencies +STATIC mp_obj_t machine_freq(size_t n_args, const mp_obj_t *args) { + if (n_args == 0) { + // get + return mp_obj_new_int(SystemCoreClock); + } else { + // set + mp_raise_NotImplementedError(MP_ERROR_TEXT("machine.freq set not supported yet")); + return mp_const_none; + } +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_freq_obj, 0, 4, machine_freq); + +// idle() +// This executies a wfi machine instruction which reduces power consumption +// of the MCU until an interrupt occurs, at which point execution continues. +STATIC mp_obj_t machine_idle(void) { + __WFI(); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(machine_idle_obj, machine_idle); + +STATIC mp_obj_t machine_lightsleep(size_t n_args, const mp_obj_t *args) { + if (n_args != 0) { + mp_obj_t args2[2] = {MP_OBJ_NULL, args[0]}; + pyb_rtc_wakeup(2, args2); + } + powerctrl_enter_stop_mode(); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_lightsleep_obj, 0, 1, machine_lightsleep); + +STATIC mp_obj_t machine_deepsleep(size_t n_args, const mp_obj_t *args) { + if (n_args != 0) { + mp_obj_t args2[2] = {MP_OBJ_NULL, args[0]}; + pyb_rtc_wakeup(2, args2); + } + powerctrl_enter_standby_mode(); + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(machine_deepsleep_obj, 0, 1, machine_deepsleep); + +STATIC mp_obj_t machine_reset_cause(void) { + return MP_OBJ_NEW_SMALL_INT(reset_cause); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_0(machine_reset_cause_obj, machine_reset_cause); + +STATIC const mp_rom_map_elem_t machine_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_umachine) }, + { MP_ROM_QSTR(MP_QSTR_info), MP_ROM_PTR(&machine_info_obj) }, + { MP_ROM_QSTR(MP_QSTR_unique_id), MP_ROM_PTR(&machine_unique_id_obj) }, + { MP_ROM_QSTR(MP_QSTR_reset), MP_ROM_PTR(&machine_reset_obj) }, + { MP_ROM_QSTR(MP_QSTR_soft_reset), MP_ROM_PTR(&machine_soft_reset_obj) }, + { MP_ROM_QSTR(MP_QSTR_bootloader), MP_ROM_PTR(&machine_bootloader_obj) }, + { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&machine_freq_obj) }, + { MP_ROM_QSTR(MP_QSTR_idle), MP_ROM_PTR(&machine_idle_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&machine_lightsleep_obj) }, + { MP_ROM_QSTR(MP_QSTR_lightsleep), MP_ROM_PTR(&machine_lightsleep_obj) }, + { MP_ROM_QSTR(MP_QSTR_deepsleep), MP_ROM_PTR(&machine_deepsleep_obj) }, + { MP_ROM_QSTR(MP_QSTR_reset_cause), MP_ROM_PTR(&machine_reset_cause_obj) }, + { MP_ROM_QSTR(MP_QSTR_disable_irq), MP_ROM_PTR(&machine_disable_irq_obj) }, + { MP_ROM_QSTR(MP_QSTR_enable_irq), MP_ROM_PTR(&machine_enable_irq_obj) }, + + #if MICROPY_PY_MACHINE_PULSE + { MP_ROM_QSTR(MP_QSTR_time_pulse_us), MP_ROM_PTR(&machine_time_pulse_us_obj) }, + #endif + + { MP_ROM_QSTR(MP_QSTR_mem8), MP_ROM_PTR(&machine_mem8_obj) }, + { MP_ROM_QSTR(MP_QSTR_mem16), MP_ROM_PTR(&machine_mem16_obj) }, + { MP_ROM_QSTR(MP_QSTR_mem32), MP_ROM_PTR(&machine_mem32_obj) }, + + { MP_ROM_QSTR(MP_QSTR_Pin), MP_ROM_PTR(&machine_pin_type) }, + { MP_ROM_QSTR(MP_QSTR_Signal), MP_ROM_PTR(&machine_signal_type) }, + + { MP_ROM_QSTR(MP_QSTR_RTC), MP_ROM_PTR(&pyb_rtc_type) }, + { MP_ROM_QSTR(MP_QSTR_ADC), MP_ROM_PTR(&machine_adc_type) }, + #if MICROPY_PY_MACHINE_I2C + #if MICROPY_HW_ENABLE_HW_I2C + { MP_ROM_QSTR(MP_QSTR_I2C), MP_ROM_PTR(&machine_i2c_type) }, + #endif + { MP_ROM_QSTR(MP_QSTR_SoftI2C), MP_ROM_PTR(&mp_machine_soft_i2c_type) }, + #endif + #if MICROPY_PY_MACHINE_SPI + { MP_ROM_QSTR(MP_QSTR_SPI), MP_ROM_PTR(&machine_hard_spi_type) }, + { MP_ROM_QSTR(MP_QSTR_SoftSPI), MP_ROM_PTR(&mp_machine_soft_spi_type) }, + #endif + { MP_ROM_QSTR(MP_QSTR_UART), MP_ROM_PTR(&pyb_uart_type) }, + { MP_ROM_QSTR(MP_QSTR_Timer), MP_ROM_PTR(&machine_timer_type) }, + { MP_ROM_QSTR(MP_QSTR_PWRON_RESET), MP_ROM_INT(PYB_RESET_POWER_ON) }, + { MP_ROM_QSTR(MP_QSTR_HARD_RESET), MP_ROM_INT(PYB_RESET_HARD) }, + { MP_ROM_QSTR(MP_QSTR_WDT_RESET), MP_ROM_INT(PYB_RESET_WDT) }, + { MP_ROM_QSTR(MP_QSTR_DEEPSLEEP_RESET), MP_ROM_INT(PYB_RESET_DEEPSLEEP) }, + { MP_ROM_QSTR(MP_QSTR_SOFT_RESET), MP_ROM_INT(PYB_RESET_SOFT) }, + + { MP_ROM_QSTR(MP_QSTR_dht_readinto), MP_ROM_PTR(&dht_readinto_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(machine_module_globals, machine_module_globals_table); + +const mp_obj_module_t mp_module_machine = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t *)&machine_module_globals, +}; diff --git a/ports/renesas-ra/modmachine.h b/ports/renesas-ra/modmachine.h new file mode 100644 index 000000000..65077220d --- /dev/null +++ b/ports/renesas-ra/modmachine.h @@ -0,0 +1,68 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2015 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_MODMACHINE_H +#define MICROPY_INCLUDED_RENESAS_RA_MODMACHINE_H + +#include "py/obj.h" + +extern const mp_obj_type_t machine_timer_type; +extern const mp_obj_type_t machine_wdt_type; +extern const mp_obj_type_t machine_pin_type; +extern const mp_obj_type_t machine_touchpad_type; +extern const mp_obj_type_t machine_adc_type; +extern const mp_obj_type_t machine_adcblock_type; +extern const mp_obj_type_t machine_dac_type; +extern const mp_obj_type_t machine_i2c_type; +extern const mp_obj_type_t machine_hard_spi_type; +extern const mp_obj_type_t machine_i2s_type; +extern const mp_obj_type_t machine_uart_type; +extern const mp_obj_type_t machine_rtc_type; +extern const mp_obj_type_t machine_sdcard_type; + + +void machine_init(void); +void machine_deinit(void); +void machine_pin_init(void); +void machine_pin_deinit(void); +void machine_i2s_init0(void); + +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_info_obj); +MP_DECLARE_CONST_FUN_OBJ_0(machine_unique_id_obj); +MP_DECLARE_CONST_FUN_OBJ_0(machine_reset_obj); +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_bootloader_obj); +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_freq_obj); + +MP_DECLARE_CONST_FUN_OBJ_0(machine_idle_obj); +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_lightsleep_obj); +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_deepsleep_obj); + +MP_DECLARE_CONST_FUN_OBJ_0(machine_disable_irq_obj); +MP_DECLARE_CONST_FUN_OBJ_VAR_BETWEEN(machine_enable_irq_obj); + +MP_DECLARE_CONST_FUN_OBJ_0(pyb_irq_stats_obj); + +#endif // MICROPY_INCLUDED_RENESAS_RA_MODMACHINE_H diff --git a/ports/renesas-ra/moduos.c b/ports/renesas-ra/moduos.c new file mode 100644 index 000000000..218c44a29 --- /dev/null +++ b/ports/renesas-ra/moduos.c @@ -0,0 +1,62 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "uart.h" + +#if MICROPY_VFS_FAT +#include "lib/oofatfs/ff.h" +#include "lib/oofatfs/diskio.h" +#endif + +// sync() +// Sync all filesystems. +STATIC mp_obj_t mp_uos_sync(void) { + #if MICROPY_VFS_FAT + for (mp_vfs_mount_t *vfs = MP_STATE_VM(vfs_mount_table); vfs != NULL; vfs = vfs->next) { + // this assumes that vfs->obj is fs_user_mount_t with block device functions + disk_ioctl(MP_OBJ_TO_PTR(vfs->obj), CTRL_SYNC, NULL); + } + #endif + return mp_const_none; +} +MP_DEFINE_CONST_FUN_OBJ_0(mp_uos_sync_obj, mp_uos_sync); + +bool mp_uos_dupterm_is_builtin_stream(mp_const_obj_t stream) { + const mp_obj_type_t *type = mp_obj_get_type(stream); + return type == &pyb_uart_type; +} + +void mp_uos_dupterm_stream_detached_attached(mp_obj_t stream_detached, mp_obj_t stream_attached) { + if (mp_obj_get_type(stream_detached) == &pyb_uart_type) { + uart_attach_to_repl(MP_OBJ_TO_PTR(stream_detached), false); + } + + if (mp_obj_get_type(stream_attached) == &pyb_uart_type) { + uart_attach_to_repl(MP_OBJ_TO_PTR(stream_attached), true); + } +} diff --git a/ports/renesas-ra/modutime.c b/ports/renesas-ra/modutime.c new file mode 100644 index 000000000..bff76035e --- /dev/null +++ b/ports/renesas-ra/modutime.c @@ -0,0 +1,158 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/smallint.h" +#include "py/obj.h" +#include "shared/timeutils/timeutils.h" +#include "extmod/utime_mphal.h" +#include "systick.h" +#include "rtc.h" + +/// \module time - time related functions +/// +/// The `time` module provides functions for getting the current time and date, +/// and for sleeping. + +/// \function localtime([secs]) +/// Convert a time expressed in seconds since Jan 1, 2000 into an 8-tuple which +/// contains: (year, month, mday, hour, minute, second, weekday, yearday) +/// If secs is not provided or None, then the current time from the RTC is used. +/// year includes the century (for example 2014) +/// month is 1-12 +/// mday is 1-31 +/// hour is 0-23 +/// minute is 0-59 +/// second is 0-59 +/// weekday is 0-6 for Mon-Sun. +/// yearday is 1-366 +STATIC mp_obj_t time_localtime(size_t n_args, const mp_obj_t *args) { + if (n_args == 0 || args[0] == mp_const_none) { + // get current date and time + // note: need to call get time then get date to correctly access the registers + rtc_init_finalise(); + // RTC_DateTypeDef date; + // RTC_TimeTypeDef time; + // HAL_RTC_GetTime(&RTCHandle, &time, RTC_FORMAT_BIN); + // HAL_RTC_GetDate(&RTCHandle, &date, RTC_FORMAT_BIN); + ra_rtc_t time; + ra_rtc_get_time(&time); + mp_obj_t tuple[8] = { + mp_obj_new_int(time.year), + mp_obj_new_int(time.month), + mp_obj_new_int(time.date), + mp_obj_new_int(time.hour), + mp_obj_new_int(time.minute), + mp_obj_new_int(time.second), + mp_obj_new_int(time.weekday - 1), + mp_obj_new_int(timeutils_year_day(time.year, time.month, time.date)), + }; + return mp_obj_new_tuple(8, tuple); + } else { + mp_int_t seconds = mp_obj_get_int(args[0]); + timeutils_struct_time_t tm; + timeutils_seconds_since_epoch_to_struct_time(seconds, &tm); + mp_obj_t tuple[8] = { + tuple[0] = mp_obj_new_int(tm.tm_year), + tuple[1] = mp_obj_new_int(tm.tm_mon), + tuple[2] = mp_obj_new_int(tm.tm_mday), + tuple[3] = mp_obj_new_int(tm.tm_hour), + tuple[4] = mp_obj_new_int(tm.tm_min), + tuple[5] = mp_obj_new_int(tm.tm_sec), + tuple[6] = mp_obj_new_int(tm.tm_wday), + tuple[7] = mp_obj_new_int(tm.tm_yday), + }; + return mp_obj_new_tuple(8, tuple); + } +} +MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(time_localtime_obj, 0, 1, time_localtime); + + +/// \function mktime() +/// This is inverse function of localtime. It's argument is a full 8-tuple +/// which expresses a time as per localtime. It returns an integer which is +/// the number of seconds since Jan 1, 2000. +STATIC mp_obj_t time_mktime(mp_obj_t tuple) { + + size_t len; + mp_obj_t *elem; + + mp_obj_get_array(tuple, &len, &elem); + + // localtime generates a tuple of len 8. CPython uses 9, so we accept both. + if (len < 8 || len > 9) { + mp_raise_msg_varg(&mp_type_TypeError, MP_ERROR_TEXT("mktime needs a tuple of length 8 or 9 (%d given)"), len); + } + + return mp_obj_new_int_from_uint(timeutils_mktime(mp_obj_get_int(elem[0]), + mp_obj_get_int(elem[1]), mp_obj_get_int(elem[2]), mp_obj_get_int(elem[3]), + mp_obj_get_int(elem[4]), mp_obj_get_int(elem[5]))); +} +MP_DEFINE_CONST_FUN_OBJ_1(time_mktime_obj, time_mktime); + +/// \function time() +/// Returns the number of seconds, as an integer, since 1/1/2000. +STATIC mp_obj_t time_time(void) { + // get date and time + // note: need to call get time then get date to correctly access the registers + rtc_init_finalise(); + // RTC_DateTypeDef date; + // RTC_TimeTypeDef time; + // HAL_RTC_GetTime(&RTCHandle, &time, RTC_FORMAT_BIN); + // HAL_RTC_GetDate(&RTCHandle, &date, RTC_FORMAT_BIN); + ra_rtc_t time; + ra_rtc_get_time(&time); + return mp_obj_new_int(timeutils_seconds_since_epoch(time.year, time.month, time.date, time.hour, time.minute, time.second)); +} +MP_DEFINE_CONST_FUN_OBJ_0(time_time_obj, time_time); + +STATIC const mp_rom_map_elem_t time_module_globals_table[] = { + { MP_ROM_QSTR(MP_QSTR___name__), MP_ROM_QSTR(MP_QSTR_utime) }, + + { MP_ROM_QSTR(MP_QSTR_gmtime), MP_ROM_PTR(&time_localtime_obj) }, + { MP_ROM_QSTR(MP_QSTR_localtime), MP_ROM_PTR(&time_localtime_obj) }, + { MP_ROM_QSTR(MP_QSTR_mktime), MP_ROM_PTR(&time_mktime_obj) }, + { MP_ROM_QSTR(MP_QSTR_time), MP_ROM_PTR(&time_time_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep), MP_ROM_PTR(&mp_utime_sleep_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep_ms), MP_ROM_PTR(&mp_utime_sleep_ms_obj) }, + { MP_ROM_QSTR(MP_QSTR_sleep_us), MP_ROM_PTR(&mp_utime_sleep_us_obj) }, + { MP_ROM_QSTR(MP_QSTR_ticks_ms), MP_ROM_PTR(&mp_utime_ticks_ms_obj) }, + { MP_ROM_QSTR(MP_QSTR_ticks_us), MP_ROM_PTR(&mp_utime_ticks_us_obj) }, + { MP_ROM_QSTR(MP_QSTR_ticks_cpu), MP_ROM_PTR(&mp_utime_ticks_cpu_obj) }, + { MP_ROM_QSTR(MP_QSTR_ticks_add), MP_ROM_PTR(&mp_utime_ticks_add_obj) }, + { MP_ROM_QSTR(MP_QSTR_ticks_diff), MP_ROM_PTR(&mp_utime_ticks_diff_obj) }, + { MP_ROM_QSTR(MP_QSTR_time_ns), MP_ROM_PTR(&mp_utime_time_ns_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(time_module_globals, time_module_globals_table); + +const mp_obj_module_t mp_module_utime = { + .base = { &mp_type_module }, + .globals = (mp_obj_dict_t *)&time_module_globals, +}; diff --git a/ports/renesas-ra/mpconfigboard_common.h b/ports/renesas-ra/mpconfigboard_common.h new file mode 100644 index 000000000..f63a924ad --- /dev/null +++ b/ports/renesas-ra/mpconfigboard_common.h @@ -0,0 +1,244 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// Common settings and defaults for board configuration. +// The defaults here should be overridden in mpconfigboard.h. + +#include RA_HAL_H + +/*****************************************************************************/ +// Feature settings with defaults + +// Whether to include the ra module, with peripheral register constants +#ifndef MICROPY_PY_RA +#define MICROPY_PY_RA (1) +#endif + +// Whether to include the pyb module +#ifndef MICROPY_PY_PYB +#define MICROPY_PY_PYB (1) +#endif + +// Whether to include legacy functions and classes in the pyb module +#ifndef MICROPY_PY_PYB_LEGACY +#define MICROPY_PY_PYB_LEGACY (1) +#endif + +// Whether machine.bootloader() will enter the bootloader via reset, or direct jump. +#ifndef MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET +#define MICROPY_HW_ENTER_BOOTLOADER_VIA_RESET (1) +#endif + +// Whether to enable storage on the internal flash of the MCU +#ifndef MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) +#endif + +// If internal flash storage is enabled, whether to use a second segment of flash. +#ifndef MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE +#define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE_SEGMENT2 (0) +#endif + +// Whether to enable the RTC, exposed as pyb.RTC +#ifndef MICROPY_HW_ENABLE_RTC +#define MICROPY_HW_ENABLE_RTC (0) +#endif + +// Whether to enable the hardware RNG peripheral, exposed as pyb.rng() +#ifndef MICROPY_HW_ENABLE_RNG +#define MICROPY_HW_ENABLE_RNG (0) +#endif + +// Whether to enable the ADC peripheral, exposed as pyb.ADC and pyb.ADCAll +#ifndef MICROPY_HW_ENABLE_ADC +#define MICROPY_HW_ENABLE_ADC (1) +#endif + +// Whether to enable the DAC peripheral, exposed as pyb.DAC +#ifndef MICROPY_HW_ENABLE_DAC +#define MICROPY_HW_ENABLE_DAC (0) +#endif + +// Whether to enable the DCMI peripheral +#ifndef MICROPY_HW_ENABLE_DCMI +#define MICROPY_HW_ENABLE_DCMI (0) +#endif + +// Whether to enable the PA0-PA3 servo driver, exposed as pyb.Servo +#ifndef MICROPY_HW_ENABLE_SERVO +#define MICROPY_HW_ENABLE_SERVO (0) +#endif + +// Whether to enable a USR switch, exposed as pyb.Switch +#ifndef MICROPY_HW_HAS_SWITCH +#define MICROPY_HW_HAS_SWITCH (0) +#endif + +// Whether to expose internal flash storage as pyb.Flash +#ifndef MICROPY_HW_HAS_FLASH +#define MICROPY_HW_HAS_FLASH (0) +#endif + +// Whether to enable the MMA7660 driver, exposed as pyb.Accel +#ifndef MICROPY_HW_HAS_MMA7660 +#define MICROPY_HW_HAS_MMA7660 (0) +#endif + +// Whether to enable the LCD32MK driver, exposed as pyb.LCD +#ifndef MICROPY_HW_HAS_LCD +#define MICROPY_HW_HAS_LCD (0) +#endif + +// Whether to automatically mount (and boot from) the flash filesystem +#ifndef MICROPY_HW_FLASH_MOUNT_AT_BOOT +#define MICROPY_HW_FLASH_MOUNT_AT_BOOT (MICROPY_HW_ENABLE_STORAGE) +#endif + +// The volume label used when creating the flash filesystem +#ifndef MICROPY_HW_FLASH_FS_LABEL +#define MICROPY_HW_FLASH_FS_LABEL "raflash" +#endif + +// Function to determine if the given i2c_id is reserved for system use or not. +#ifndef MICROPY_HW_I2C_IS_RESERVED +#define MICROPY_HW_I2C_IS_RESERVED(i2c_id) (false) +#endif + +// Function to determine if the given spi_id is reserved for system use or not. +#ifndef MICROPY_HW_SPI_IS_RESERVED +#define MICROPY_HW_SPI_IS_RESERVED(spi_id) (false) +#endif + +// Function to determine if the given tim_id is reserved for system use or not. +#ifndef MICROPY_HW_TIM_IS_RESERVED +#define MICROPY_HW_TIM_IS_RESERVED(tim_id) (false) +#endif + +// Function to determine if the given uart_id is reserved for system use or not. +#ifndef MICROPY_HW_UART_IS_RESERVED +#define MICROPY_HW_UART_IS_RESERVED(uart_id) (false) +#endif + +/*****************************************************************************/ +// General configuration + +// Heap start / end definitions +#ifndef MICROPY_HEAP_START +#define MICROPY_HEAP_START &_heap_start +#endif +#ifndef MICROPY_HEAP_END +#define MICROPY_HEAP_END &_heap_end +#endif + +// Configuration for RA series +#if defined(RA4M1) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x1ffff7ac) +// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h +#define PYB_EXTI_NUM_VECTORS (17) +#define MICROPY_HW_MAX_TIMER (2) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (0) + +#elif defined(RA4M3) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x1ffff7ac) /* To be fixed */ +// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h +#define PYB_EXTI_NUM_VECTORS (17) +#define MICROPY_HW_MAX_TIMER (2) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (0) + +#elif defined(RA4W1) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x1ffff7ac) /* To be fixed */ +// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h +#define PYB_EXTI_NUM_VECTORS (17) +#define MICROPY_HW_MAX_TIMER (2) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (0) + +#elif defined(RA6M1) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x0100A150) /* To be fixed */ +// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h +#define PYB_EXTI_NUM_VECTORS (17) +#define MICROPY_HW_MAX_TIMER (2) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (0) + +#elif defined(RA6M2) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x1ffff7ac) /* To be fixed */ +// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h +#define PYB_EXTI_NUM_VECTORS (17) +#define MICROPY_HW_MAX_TIMER (2) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (0) + +#elif defined(RA6M3) + +#define MP_HAL_UNIQUE_ID_ADDRESS (0x1ffff7ac) /* To be fixed */ +// 16 IRQ + 1 EXTI_RTC_WAKEUP defined in exti.h +#define PYB_EXTI_NUM_VECTORS (17) +#define MICROPY_HW_MAX_TIMER (2) +#define MICROPY_HW_MAX_UART (10) +#define MICROPY_HW_MAX_LPUART (0) + +#error Unsupported MCU series +#endif + +// If disabled then try normal (non-bypass) LSE first, with fallback to LSI. +// If enabled first try LSE in bypass mode. If that fails to start, try non-bypass mode, with fallback to LSI. +#ifndef MICROPY_HW_RTC_USE_BYPASS +#define MICROPY_HW_RTC_USE_BYPASS (0) +#endif + +#if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE +// Provide block device macros if internal flash storage is enabled +#define MICROPY_HW_BDEV_IOCTL flash_bdev_ioctl +#define MICROPY_HW_BDEV_READBLOCK flash_bdev_readblock +#define MICROPY_HW_BDEV_WRITEBLOCK flash_bdev_writeblock +#endif + +// Enable the storage sub-system if a block device is defined +#if defined(MICROPY_HW_BDEV_IOCTL) +#define MICROPY_HW_ENABLE_STORAGE (1) +#else +#define MICROPY_HW_ENABLE_STORAGE (0) +#endif + +// Enable hardware I2C if there are any peripherals defined +#if defined(MICROPY_HW_I2C0_SCL) || defined(MICROPY_HW_I2C1_SCL) \ + || defined(MICROPY_HW_I2C2_SCL) +#define MICROPY_HW_ENABLE_HW_I2C (1) +#else +#define MICROPY_HW_ENABLE_HW_I2C (0) +#endif + +// Pin definition header file +#define MICROPY_PIN_DEFS_PORT_H "pin_defs_ra.h" diff --git a/ports/renesas-ra/mpconfigport.h b/ports/renesas-ra/mpconfigport.h new file mode 100644 index 000000000..0301a41d3 --- /dev/null +++ b/ports/renesas-ra/mpconfigport.h @@ -0,0 +1,303 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2017 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// Options to control how MicroPython is built for this port, +// overriding defaults in py/mpconfig.h. + +// board specific definitions +#include "mpconfigboard.h" +#include "mpconfigboard_common.h" + +#ifndef MICROPY_CONFIG_ROM_LEVEL +#define MICROPY_CONFIG_ROM_LEVEL (MICROPY_CONFIG_ROM_LEVEL_EXTRA_FEATURES) +#endif + +// memory allocation policies +#ifndef MICROPY_GC_STACK_ENTRY_TYPE +#if MICROPY_HW_SDRAM_SIZE +#define MICROPY_GC_STACK_ENTRY_TYPE uint32_t +#else +#define MICROPY_GC_STACK_ENTRY_TYPE uint16_t +#endif +#endif +#define MICROPY_ALLOC_PATH_MAX (128) + +// optimisations +#ifndef MICROPY_OPT_COMPUTED_GOTO +#define MICROPY_OPT_COMPUTED_GOTO (1) +#endif + +// Don't enable lookup cache on M0 (low RAM) +#ifndef MICROPY_OPT_MAP_LOOKUP_CACHE +#define MICROPY_OPT_MAP_LOOKUP_CACHE (__CORTEX_M > 0) +#endif + +// emitters +#define MICROPY_PERSISTENT_CODE_LOAD (1) +#ifndef MICROPY_EMIT_THUMB +#define MICROPY_EMIT_THUMB (1) +#endif +#ifndef MICROPY_EMIT_INLINE_THUMB +#define MICROPY_EMIT_INLINE_THUMB (1) +#endif + +// Python internal features +#define MICROPY_READER_VFS (1) +#define MICROPY_ENABLE_GC (1) +#define MICROPY_ENABLE_EMERGENCY_EXCEPTION_BUF (1) +#define MICROPY_EMERGENCY_EXCEPTION_BUF_SIZE (0) +#define MICROPY_REPL_INFO (1) +#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ) +#ifndef MICROPY_FLOAT_IMPL // can be configured by each board via mpconfigboard.mk +#define MICROPY_FLOAT_IMPL (MICROPY_FLOAT_IMPL_FLOAT) +#endif +#define MICROPY_USE_INTERNAL_ERRNO (1) +#define MICROPY_SCHEDULER_DEPTH (8) +#define MICROPY_VFS (1) + +// control over Python builtins +#ifndef MICROPY_PY_BUILTINS_HELP_TEXT +#define MICROPY_PY_BUILTINS_HELP_TEXT ra_help_text +#endif +#define MICROPY_PY_IO_FILEIO (MICROPY_VFS_FAT || MICROPY_VFS_LFS1 || MICROPY_VFS_LFS2) +#ifndef MICROPY_PY_SYS_PLATFORM // let boards override it if they want +#define MICROPY_PY_SYS_PLATFORM "renesas-ra" +#endif +#ifndef MICROPY_PY_THREAD +#define MICROPY_PY_THREAD (0) +#endif + +// extended modules +#define MICROPY_PY_UOS_INCLUDEFILE "ports/renesas-ra/moduos.c" +#define MICROPY_PY_OS_DUPTERM (3) +#define MICROPY_PY_UOS_DUPTERM_BUILTIN_STREAM (1) +#define MICROPY_PY_UOS_DUPTERM_STREAM_DETACHED_ATTACHED (1) +#define MICROPY_PY_UOS_SEP (1) +#define MICROPY_PY_UOS_SYNC (1) +#define MICROPY_PY_UOS_UNAME (1) +#define MICROPY_PY_UOS_URANDOM (MICROPY_HW_ENABLE_RNG) +#ifndef MICROPY_PY_UTIME +#define MICROPY_PY_UTIME (1) +#endif +#define MICROPY_PY_UTIME_MP_HAL (MICROPY_PY_UTIME) +#ifndef MICROPY_PY_UTIMEQ +#define MICROPY_PY_UTIMEQ (1) +#endif +#ifndef MICROPY_PY_MACHINE +#define MICROPY_PY_MACHINE (1) +#ifndef MICROPY_PY_MACHINE_BITSTREAM +#define MICROPY_PY_MACHINE_BITSTREAM (1) +#endif +#define MICROPY_PY_MACHINE_PULSE (1) +#define MICROPY_PY_MACHINE_PIN_MAKE_NEW mp_pin_make_new +#define MICROPY_PY_MACHINE_I2C (1) +#define MICROPY_PY_MACHINE_SOFTI2C (1) +#define MICROPY_PY_MACHINE_SPI (1) +#define MICROPY_PY_MACHINE_SPI_MSB (SPI_FIRSTBIT_MSB) +#define MICROPY_PY_MACHINE_SPI_LSB (SPI_FIRSTBIT_LSB) +#define MICROPY_PY_MACHINE_SOFTSPI (1) +#endif +#define MICROPY_HW_SOFTSPI_MIN_DELAY (0) +#define MICROPY_HW_SOFTSPI_MAX_BAUDRATE (48000000 / 48) +#ifndef MICROPY_PY_ONEWIRE +#define MICROPY_PY_ONEWIRE (1) +#endif +#ifndef MICROPY_PY_UPLATFORM +#define MICROPY_PY_UPLATFORM (1) +#endif + +// fatfs configuration used in ffconf.h +#define MICROPY_FATFS_ENABLE_LFN (1) +#define MICROPY_FATFS_LFN_CODE_PAGE 437 /* 1=SFN/ANSI 437=LFN/U.S.(OEM) */ +#define MICROPY_FATFS_USE_LABEL (1) +#define MICROPY_FATFS_RPATH (2) +#define MICROPY_FATFS_MULTI_PARTITION (1) + +// TODO these should be generic, not bound to a particular FS implementation +#if MICROPY_VFS_FAT +#define mp_type_fileio mp_type_vfs_fat_fileio +#define mp_type_textio mp_type_vfs_fat_textio +#elif MICROPY_VFS_LFS1 +#define mp_type_fileio mp_type_vfs_lfs1_fileio +#define mp_type_textio mp_type_vfs_lfs1_textio +#elif MICROPY_VFS_LFS2 +#define mp_type_fileio mp_type_vfs_lfs2_fileio +#define mp_type_textio mp_type_vfs_lfs2_textio +#endif + +// use vfs's functions for import stat and builtin open +#define mp_import_stat mp_vfs_import_stat +#define mp_builtin_open mp_vfs_open +#define mp_builtin_open_obj mp_vfs_open_obj + +// extra built in names to add to the global namespace +#define MICROPY_PORT_BUILTINS \ + { MP_ROM_QSTR(MP_QSTR_open), MP_ROM_PTR(&mp_builtin_open_obj) }, + +// extra built in modules to add to the list of known ones +extern const struct _mp_obj_module_t mp_module_ubinascii; +extern const struct _mp_obj_module_t mp_module_ure; +extern const struct _mp_obj_module_t mp_module_uzlib; +extern const struct _mp_obj_module_t mp_module_ujson; +extern const struct _mp_obj_module_t mp_module_uheapq; +extern const struct _mp_obj_module_t mp_module_uhashlib; +extern const struct _mp_obj_module_t mp_module_utime; +extern const struct _mp_obj_module_t mp_module_onewire; + +#if MICROPY_PY_MACHINE +#define MACHINE_BUILTIN_MODULE_CONSTANTS \ + { MP_ROM_QSTR(MP_QSTR_umachine), MP_ROM_PTR(&mp_module_machine) }, \ + { MP_ROM_QSTR(MP_QSTR_machine), MP_ROM_PTR(&mp_module_machine) }, +#else +#define MACHINE_BUILTIN_MODULE_CONSTANTS +#endif + +#if MICROPY_PY_UTIME +#define UTIME_BUILTIN_MODULE { MP_ROM_QSTR(MP_QSTR_utime), MP_ROM_PTR(&mp_module_utime) }, +#else +#define UTIME_BUILTIN_MODULE +#endif + +#if MICROPY_PY_ONEWIRE +#define ONEWIRE_BUILTIN_MODULE { MP_ROM_QSTR(MP_QSTR__onewire), MP_ROM_PTR(&mp_module_onewire) }, +#else +#define ONEWIRE_BUILTIN_MODULE +#endif + +#define MICROPY_PORT_BUILTIN_MODULES \ + UTIME_BUILTIN_MODULE \ + ONEWIRE_BUILTIN_MODULE \ + +// extra constants +#define MICROPY_PORT_CONSTANTS \ + MACHINE_BUILTIN_MODULE_CONSTANTS \ + +#define MP_STATE_PORT MP_STATE_VM + +#ifndef MICROPY_BOARD_ROOT_POINTERS +#define MICROPY_BOARD_ROOT_POINTERS +#endif + +#define MICROPY_PORT_ROOT_POINTERS \ + const char *readline_hist[8]; \ + \ + mp_obj_t pyb_hid_report_desc; \ + \ + mp_obj_t pyb_config_main; \ + \ + mp_obj_t pyb_switch_callback; \ + \ + mp_obj_t pin_class_mapper; \ + mp_obj_t pin_class_map_dict; \ + \ + mp_obj_t pyb_extint_callback[PYB_EXTI_NUM_VECTORS]; \ + \ + /* pointers to all Timer objects (if they have been created) */ \ + struct _pyb_timer_obj_t *pyb_timer_obj_all[MICROPY_HW_MAX_TIMER]; \ + \ + /* stdio is repeated on this UART object if it's not null */ \ + struct _pyb_uart_obj_t *pyb_stdio_uart; \ + \ + /* pointers to all UART objects (if they have been created) */ \ + struct _pyb_uart_obj_t *pyb_uart_obj_all[MICROPY_HW_MAX_UART + MICROPY_HW_MAX_LPUART]; \ + \ + /* list of registered NICs */ \ + /* mp_obj_list_t mod_network_nic_list; */ \ + \ + /* root pointers for sub-systems */ \ + \ + /* root pointers defined by a board */ \ + MICROPY_BOARD_ROOT_POINTERS \ + +// type definitions for the specific machine + +#define MICROPY_MAKE_POINTER_CALLABLE(p) ((void *)((uint32_t)(p) | 1)) + +#define MP_SSIZE_MAX (0x7fffffff) + +// Assume that if we already defined the obj repr then we also defined these items +#ifndef MICROPY_OBJ_REPR +#define UINT_FMT "%u" +#define INT_FMT "%d" +typedef int mp_int_t; // must be pointer size +typedef unsigned int mp_uint_t; // must be pointer size +#endif + +typedef long mp_off_t; + +// We have inlined IRQ functions for efficiency (they are generally +// 1 machine instruction). +// +// Note on IRQ state: you should not need to know the specific +// value of the state variable, but rather just pass the return +// value from disable_irq back to enable_irq. If you really need +// to know the machine-specific values, see irq.h. + +static inline void enable_irq(mp_uint_t state) { + __set_PRIMASK(state); +} + +static inline mp_uint_t disable_irq(void) { + mp_uint_t state = __get_PRIMASK(); + __disable_irq(); + return state; +} + +#define MICROPY_BEGIN_ATOMIC_SECTION() disable_irq() +#define MICROPY_END_ATOMIC_SECTION(state) enable_irq(state) + +#if MICROPY_PY_THREAD +#define MICROPY_EVENT_POLL_HOOK \ + do { \ + extern void mp_handle_pending(bool); \ + mp_handle_pending(true); \ + if (pyb_thread_enabled) { \ + MP_THREAD_GIL_EXIT(); \ + pyb_thread_yield(); \ + MP_THREAD_GIL_ENTER(); \ + } else { \ + __WFI(); \ + } \ + } while (0); + +#define MICROPY_THREAD_YIELD() pyb_thread_yield() +#else +#define MICROPY_EVENT_POLL_HOOK \ + do { \ + extern void mp_handle_pending(bool); \ + mp_handle_pending(true); \ + __WFI(); \ + } while (0); + +#define MICROPY_THREAD_YIELD() +#endif + +// We need an implementation of the log2 function which is not a macro +#define MP_NEED_LOG2 (1) + +// We need to provide a declaration/definition of alloca() +#include <alloca.h> diff --git a/ports/renesas-ra/mpconfigport.mk b/ports/renesas-ra/mpconfigport.mk new file mode 100644 index 000000000..adf2b8f4a --- /dev/null +++ b/ports/renesas-ra/mpconfigport.mk @@ -0,0 +1,4 @@ +# Enable/disable extra modules + +# VFS FAT FS support +MICROPY_VFS_FAT ?= 1 diff --git a/ports/renesas-ra/mphalport.c b/ports/renesas-ra/mphalport.c new file mode 100644 index 000000000..6a416f431 --- /dev/null +++ b/ports/renesas-ra/mphalport.c @@ -0,0 +1,120 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <string.h> + +#include "py/runtime.h" +#include "py/stream.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "extmod/misc.h" +#include "uart.h" + +// this table converts from HAL_StatusTypeDef to POSIX errno +const byte mp_hal_status_to_errno_table[4] = { + [HAL_OK] = 0, + [HAL_ERROR] = MP_EIO, + [HAL_BUSY] = MP_EBUSY, + [HAL_TIMEOUT] = MP_ETIMEDOUT, +}; + +NORETURN void mp_hal_raise(HAL_StatusTypeDef status) { + mp_raise_OSError(mp_hal_status_to_errno_table[status]); +} + +MP_WEAK uintptr_t mp_hal_stdio_poll(uintptr_t poll_flags) { + uintptr_t ret = 0; + if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { + mp_obj_t pyb_stdio_uart = MP_OBJ_FROM_PTR(MP_STATE_PORT(pyb_stdio_uart)); + int errcode; + const mp_stream_p_t *stream_p = mp_get_stream(pyb_stdio_uart); + ret = stream_p->ioctl(pyb_stdio_uart, MP_STREAM_POLL, poll_flags, &errcode); + } + return ret | mp_uos_dupterm_poll(poll_flags); +} + +#if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE +void flash_cache_commit(void); +#endif + +MP_WEAK int mp_hal_stdin_rx_chr(void) { + for (;;) { + #if MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE + flash_cache_commit(); + #endif + if (MP_STATE_PORT(pyb_stdio_uart) != NULL && uart_rx_any(MP_STATE_PORT(pyb_stdio_uart))) { + return uart_rx_char(MP_STATE_PORT(pyb_stdio_uart)); + } + int dupterm_c = mp_uos_dupterm_rx_chr(); + if (dupterm_c >= 0) { + return dupterm_c; + } + MICROPY_EVENT_POLL_HOOK + } +} + +MP_WEAK void mp_hal_stdout_tx_strn(const char *str, size_t len) { + if (MP_STATE_PORT(pyb_stdio_uart) != NULL) { + uart_tx_strn(MP_STATE_PORT(pyb_stdio_uart), str, len); + } + mp_uos_dupterm_tx_strn(str, len); +} + +void mp_hal_ticks_cpu_enable(void) { +} + +void mp_hal_pin_config(mp_hal_pin_obj_t pin_obj, uint32_t mode, uint32_t pull, uint32_t drive, uint32_t alt) { + ra_gpio_config(pin_obj->pin, mode, pull, drive, alt); +} + +/*******************************************************************************/ +// MAC address + +// Generate a random locally administered MAC address (LAA) +void mp_hal_generate_laa_mac(int idx, uint8_t buf[6]) { + uint8_t *id = (uint8_t *)MP_HAL_UNIQUE_ID_ADDRESS; + buf[0] = 0x02; // LAA range + buf[1] = (id[11] << 4) | (id[10] & 0xf); + buf[2] = (id[9] << 4) | (id[8] & 0xf); + buf[3] = (id[7] << 4) | (id[6] & 0xf); + buf[4] = id[2]; + buf[5] = (id[0] << 2) | idx; +} + +// A board can override this if needed +MP_WEAK void mp_hal_get_mac(int idx, uint8_t buf[6]) { + mp_hal_generate_laa_mac(idx, buf); +} + +void mp_hal_get_mac_ascii(int idx, size_t chr_off, size_t chr_len, char *dest) { + static const char hexchr[16] = "0123456789ABCDEF"; + uint8_t mac[6]; + mp_hal_get_mac(idx, mac); + for (; chr_len; ++chr_off, --chr_len) { + *dest++ = hexchr[mac[chr_off >> 1] >> (4 * (1 - (chr_off & 1))) & 0xf]; + } +} diff --git a/ports/renesas-ra/mphalport.h b/ports/renesas-ra/mphalport.h new file mode 100644 index 000000000..c489d1b96 --- /dev/null +++ b/ports/renesas-ra/mphalport.h @@ -0,0 +1,98 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include RA_HAL_H +#include "pin.h" + +extern const unsigned char mp_hal_status_to_errno_table[4]; + +static inline int mp_hal_status_to_neg_errno(HAL_StatusTypeDef status) { + return -mp_hal_status_to_errno_table[status]; +} + +NORETURN void mp_hal_raise(HAL_StatusTypeDef status); +void mp_hal_set_interrupt_char(int c); // -1 to disable + +// timing functions + +#include "irq.h" + +#if __CORTEX_M == 0 +// Don't have raise_irq_pri on Cortex-M0 so keep IRQs enabled to have SysTick timing +#define mp_hal_quiet_timing_enter() (1) +#define mp_hal_quiet_timing_exit(irq_state) (void)(irq_state) +#else +#define mp_hal_quiet_timing_enter() raise_irq_pri(1) +#define mp_hal_quiet_timing_exit(irq_state) restore_irq_pri(irq_state) +#endif +#define mp_hal_delay_us_fast(us) mp_hal_delay_us(us) + +void mp_hal_ticks_cpu_enable(void); +static inline mp_uint_t mp_hal_ticks_cpu(void) { + return 0; +} +#define SPI_FIRSTBIT_MSB (0x00000000U) +#define SPI_FIRSTBIT_LSB (0x00000001U) + +#define MP_HAL_PIN_FMT "%q" +#define MP_HAL_PIN_MODE_INPUT (GPIO_MODE_INPUT) +#define MP_HAL_PIN_MODE_OUTPUT (GPIO_MODE_OUTPUT_PP) +#define MP_HAL_PIN_MODE_ALT (GPIO_MODE_AF_PP) +#define MP_HAL_PIN_MODE_ANALOG (GPIO_MODE_ANALOG) +#define MP_HAL_PIN_MODE_ADC (GPIO_MODE_ANALOG) +#define MP_HAL_PIN_MODE_OPEN_DRAIN (GPIO_MODE_OUTPUT_OD) +#define MP_HAL_PIN_MODE_ALT_OPEN_DRAIN (GPIO_MODE_AF_OD) +#define MP_HAL_PIN_PULL_NONE (GPIO_NOPULL) +#define MP_HAL_PIN_PULL_UP (GPIO_PULLUP) +#define MP_HAL_PIN_PULL_DOWN (GPIO_PULLDOWN) + +#define mp_hal_pin_obj_t const machine_pin_obj_t * +#define mp_hal_get_pin_obj(o) machine_pin_find(o) +#define mp_hal_pin_name(p) ((p)->name) +#define mp_hal_pin_input(p) ra_gpio_mode_input((p)->pin) +#define mp_hal_pin_output(p) ra_gpio_mode_output((p)->pin) +#define mp_hal_pin_open_drain(p) ra_gpio_config((p)->pin, GPIO_MODE_OUTPUT_OD, 0, 0, 0) +#define mp_hal_pin_high(p) ra_gpio_write((p)->pin, 1) +#define mp_hal_pin_low(p) ra_gpio_write((p)->pin, 0) +#define mp_hal_pin_toggle(p) ra_gpio_toggle((p)->pin) +#define mp_hal_pin_od_low(p) mp_hal_pin_low(p) +#define mp_hal_pin_od_high(p) mp_hal_pin_high(p) +#define mp_hal_pin_read(p) ra_gpio_read((p)->pin) +#define mp_hal_pin_write(p, v) do { if (v) { mp_hal_pin_high(p); } else { mp_hal_pin_low(p); } } while (0) + +void mp_hal_pin_config(mp_hal_pin_obj_t pin, uint32_t mode, uint32_t pull, uint32_t drive, uint32_t alt); + +enum { + MP_HAL_MAC_WLAN0 = 0, + MP_HAL_MAC_WLAN1, + MP_HAL_MAC_BDADDR, + MP_HAL_MAC_ETH0, +}; + +void mp_hal_get_mac(int idx, uint8_t buf[6]); + +void mp_hal_set_interrupt_char(int c); // -1 to disable diff --git a/ports/renesas-ra/mpthreadport.c b/ports/renesas-ra/mpthreadport.c new file mode 100644 index 000000000..ecdb26846 --- /dev/null +++ b/ports/renesas-ra/mpthreadport.c @@ -0,0 +1,93 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> + +#include "py/runtime.h" +#include "py/gc.h" +#include "py/mpthread.h" +#include "gccollect.h" + +#if MICROPY_PY_THREAD + +// the mutex controls access to the linked list +STATIC mp_thread_mutex_t thread_mutex; + +void mp_thread_init(void) { + mp_thread_mutex_init(&thread_mutex); + mp_thread_set_state(&mp_state_ctx.thread); +} + +void mp_thread_gc_others(void) { + mp_thread_mutex_lock(&thread_mutex, 1); + for (pyb_thread_t *th = pyb_thread_all; th != NULL; th = th->all_next) { + gc_collect_root((void **)&th, 1); + gc_collect_root(&th->arg, 1); + gc_collect_root(&th->stack, 1); + if (th != pyb_thread_cur) { + gc_collect_root(th->stack, th->stack_len); + } + } + mp_thread_mutex_unlock(&thread_mutex); +} + +void mp_thread_create(void *(*entry)(void *), void *arg, size_t *stack_size) { + if (*stack_size == 0) { + *stack_size = 4096; // default stack size + } else if (*stack_size < 2048) { + *stack_size = 2048; // minimum stack size + } + + // round stack size to a multiple of the word size + size_t stack_len = *stack_size / sizeof(uint32_t); + *stack_size = stack_len * sizeof(uint32_t); + + // allocate stack and linked-list node (must be done outside thread_mutex lock) + uint32_t *stack = m_new(uint32_t, stack_len); + pyb_thread_t *th = m_new_obj(pyb_thread_t); + + mp_thread_mutex_lock(&thread_mutex, 1); + + // create thread + uint32_t id = pyb_thread_new(th, stack, stack_len, entry, arg); + if (id == 0) { + mp_thread_mutex_unlock(&thread_mutex); + mp_raise_msg(&mp_type_OSError, MP_ERROR_TEXT("can't create thread")); + } + + mp_thread_mutex_unlock(&thread_mutex); + + // adjust stack_size to provide room to recover from hitting the limit + *stack_size -= 1024; +} + +void mp_thread_start(void) { +} + +void mp_thread_finish(void) { +} + +#endif // MICROPY_PY_THREAD diff --git a/ports/renesas-ra/mpthreadport.h b/ports/renesas-ra/mpthreadport.h new file mode 100644 index 000000000..e2b39979f --- /dev/null +++ b/ports/renesas-ra/mpthreadport.h @@ -0,0 +1,53 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2016 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mpthread.h" +#include "pybthread.h" + +typedef pyb_mutex_t mp_thread_mutex_t; + +void mp_thread_init(void); +void mp_thread_gc_others(void); + +static inline void mp_thread_set_state(struct _mp_state_thread_t *state) { + pyb_thread_set_local(state); +} + +static inline struct _mp_state_thread_t *mp_thread_get_state(void) { + return pyb_thread_get_local(); +} + +static inline void mp_thread_mutex_init(mp_thread_mutex_t *m) { + pyb_mutex_init(m); +} + +static inline int mp_thread_mutex_lock(mp_thread_mutex_t *m, int wait) { + return pyb_mutex_lock(m, wait); +} + +static inline void mp_thread_mutex_unlock(mp_thread_mutex_t *m) { + pyb_mutex_unlock(m); +} diff --git a/ports/renesas-ra/pendsv.c b/ports/renesas-ra/pendsv.c new file mode 100644 index 000000000..d4c4496f1 --- /dev/null +++ b/ports/renesas-ra/pendsv.c @@ -0,0 +1,184 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdlib.h> + +#include "py/runtime.h" +#include "shared/runtime/interrupt_char.h" +#include "pendsv.h" +#include "irq.h" + +// This variable is used to save the exception object between a ctrl-C and the +// PENDSV call that actually raises the exception. It must be non-static +// otherwise gcc-5 optimises it away. It can point to the heap but is not +// traced by GC. This is okay because we only ever set it to +// mp_kbd_exception which is in the root-pointer set. +void *pendsv_object; + +#if defined(PENDSV_DISPATCH_NUM_SLOTS) +uint32_t pendsv_dispatch_active; +pendsv_dispatch_t pendsv_dispatch_table[PENDSV_DISPATCH_NUM_SLOTS]; +#endif + +void pendsv_init(void) { + #if defined(PENDSV_DISPATCH_NUM_SLOTS) + pendsv_dispatch_active = false; + #endif + // set PendSV interrupt at lowest priority + NVIC_SetPriority(PendSV_IRQn, IRQ_PRI_PENDSV); +} + +// Call this function to raise a pending exception during an interrupt. +// It will first try to raise the exception "softly" by setting the +// mp_pending_exception variable and hoping that the VM will notice it. +// If this function is called a second time (ie with the mp_pending_exception +// variable already set) then it will force the exception by using the hardware +// PENDSV feature. This will wait until all interrupts are finished then raise +// the given exception object using nlr_jump in the context of the top-level +// thread. +void pendsv_kbd_intr(void) { + if (MP_STATE_MAIN_THREAD(mp_pending_exception) == MP_OBJ_NULL) { + mp_sched_keyboard_interrupt(); + } else { + MP_STATE_MAIN_THREAD(mp_pending_exception) = MP_OBJ_NULL; + pendsv_object = &MP_STATE_VM(mp_kbd_exception); + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; + } +} + +#if defined(PENDSV_DISPATCH_NUM_SLOTS) +void pendsv_schedule_dispatch(size_t slot, pendsv_dispatch_t f) { + pendsv_dispatch_table[slot] = f; + pendsv_dispatch_active = true; + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; +} + +void pendsv_dispatch_handler(void) { + for (size_t i = 0; i < PENDSV_DISPATCH_NUM_SLOTS; ++i) { + if (pendsv_dispatch_table[i] != NULL) { + pendsv_dispatch_t f = pendsv_dispatch_table[i]; + pendsv_dispatch_table[i] = NULL; + f(); + } + } +} +#endif + +__attribute__((naked)) void PendSV_Handler(void) { + // Handle a PendSV interrupt + // + // For the case of an asynchronous exception, re-jig the + // stack so that when we return from this interrupt handler + // it returns instead to nlr_jump with argument pendsv_object + // note that stack has a different layout if DEBUG is enabled + // + // For the case of a thread switch, swap stacks. + // + // on entry to this (naked) function, stack has the following layout: + // + // stack layout with DEBUG disabled: + // sp[6]: pc=r15 + // sp[5]: lr=r14 + // sp[4]: r12 + // sp[3]: r3 + // sp[2]: r2 + // sp[1]: r1 + // sp[0]: r0 + // + // stack layout with DEBUG enabled: + // sp[8]: pc=r15 + // sp[7]: lr=r14 + // sp[6]: r12 + // sp[5]: r3 + // sp[4]: r2 + // sp[3]: r1 + // sp[2]: r0 + // sp[1]: 0xfffffff9 + // sp[0]: ? + + __asm volatile ( + #if defined(PENDSV_DISPATCH_NUM_SLOTS) + // Check if there are any pending calls to dispatch to + "ldr r1, pendsv_dispatch_active_ptr\n" + "ldr r0, [r1]\n" + "cmp r0, #0\n" + "beq .no_dispatch\n" + "mov r2, #0\n" + "str r2, [r1]\n" // clear pendsv_dispatch_active + "b pendsv_dispatch_handler\n" // jump to the handler + ".no_dispatch:\n" + #endif + + // Check if there is an active object to throw via nlr_jump + "ldr r1, pendsv_object_ptr\n" + "ldr r0, [r1]\n" + "cmp r0, #0\n" + "beq .no_obj\n" + #if defined(PENDSV_DEBUG) + "str r0, [sp, #8]\n" // store to r0 on stack + #else + "str r0, [sp, #0]\n" // store to r0 on stack + #endif + "mov r0, #0\n" + "str r0, [r1]\n" // clear pendsv_object + "ldr r0, nlr_jump_ptr\n" + #if defined(PENDSV_DEBUG) + "str r0, [sp, #32]\n" // store to pc on stack + #else + "str r0, [sp, #24]\n" // store to pc on stack + #endif + "bx lr\n" // return from interrupt; will return to nlr_jump + ".no_obj:\n" // pendsv_object==NULL + + #if MICROPY_PY_THREAD + // Do a thread context switch + "push {r4-r11, lr}\n" + "vpush {s16-s31}\n" + "mrs r5, primask\n" // save PRIMASK in r5 + "cpsid i\n" // disable interrupts while we change stacks + "mov r0, sp\n" // pass sp to save + "mov r4, lr\n" // save lr because we are making a call + "bl pyb_thread_next\n" // get next thread to execute + "mov lr, r4\n" // restore lr + "mov sp, r0\n" // switch stacks + "msr primask, r5\n" // reenable interrupts + "vpop {s16-s31}\n" + "pop {r4-r11, lr}\n" + "bx lr\n" // return from interrupt; will return to new thread + #else + // Spurious pendsv, just return + "bx lr\n" + #endif + + // Data + ".align 2\n" + #if defined(PENDSV_DISPATCH_NUM_SLOTS) + "pendsv_dispatch_active_ptr: .word pendsv_dispatch_active\n" + #endif + "pendsv_object_ptr: .word pendsv_object\n" + "nlr_jump_ptr: .word nlr_jump\n" + ); +} diff --git a/ports/renesas-ra/pendsv.h b/ports/renesas-ra/pendsv.h new file mode 100644 index 000000000..9d7c3d941 --- /dev/null +++ b/ports/renesas-ra/pendsv.h @@ -0,0 +1,54 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_PENDSV_H +#define MICROPY_INCLUDED_RENESAS_RA_PENDSV_H + +#include "boardctrl.h" + +enum { + PENDSV_DISPATCH_SOFT_TIMER, + #if MICROPY_PY_NETWORK && MICROPY_PY_LWIP + PENDSV_DISPATCH_LWIP, + #if MICROPY_PY_NETWORK_CYW43 + PENDSV_DISPATCH_CYW43, + #endif + #endif + #if MICROPY_PY_BLUETOOTH && !MICROPY_PY_BLUETOOTH_USE_SYNC_EVENTS + PENDSV_DISPATCH_BLUETOOTH_HCI, + #endif + MICROPY_BOARD_PENDSV_ENTRIES + PENDSV_DISPATCH_MAX +}; + +#define PENDSV_DISPATCH_NUM_SLOTS PENDSV_DISPATCH_MAX + +typedef void (*pendsv_dispatch_t)(void); + +void pendsv_init(void); +void pendsv_kbd_intr(void); +void pendsv_schedule_dispatch(size_t slot, pendsv_dispatch_t f); + +#endif // MICROPY_INCLUDED_RENESAS_RA_PENDSV_H diff --git a/ports/renesas-ra/pin.h b/ports/renesas-ra/pin.h new file mode 100644 index 000000000..32aa96075 --- /dev/null +++ b/ports/renesas-ra/pin.h @@ -0,0 +1,98 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021, 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_RA_PIN_H +#define MICROPY_INCLUDED_RA_PIN_H + +#include "shared/runtime/mpirq.h" +#include "py/obj.h" + +typedef struct { + mp_obj_base_t base; + qstr name; + uint8_t idx; + uint8_t fn; + uint8_t unit; + uint8_t type; + void *reg; // The peripheral associated with this AF +} pin_af_obj_t; + +typedef struct { + mp_obj_base_t base; + qstr name; + uint8_t pin; + uint8_t bit; + uint8_t channel; +} pin_ad_obj_t; + +typedef struct { + mp_obj_base_t base; + qstr name; + uint8_t pin; + uint8_t num_af; + const pin_af_obj_t *af; + const pin_ad_obj_t *ad; +} machine_pin_obj_t; + +extern const mp_obj_type_t machine_pin_type; +extern const mp_obj_type_t pin_af_type; + +// Include all of the individual pin objects +#include "genhdr/pins.h" + +typedef struct { + const char *name; + const machine_pin_obj_t *pin; +} pin_named_pin_t; + +extern const pin_named_pin_t pin_board_pins[]; +extern const pin_named_pin_t pin_cpu_pins[]; + +typedef struct { + mp_obj_base_t base; + qstr name; + const pin_named_pin_t *named_pins; +} pin_named_pins_obj_t; + +extern const mp_obj_type_t pin_board_pins_obj_type; +extern const mp_obj_type_t pin_cpu_pins_obj_type; + +extern const mp_obj_dict_t pin_cpu_pins_locals_dict; +extern const mp_obj_dict_t pin_board_pins_locals_dict; + +void machine_pin_init(void); +uint32_t pin_get_mode(const machine_pin_obj_t *pin); +uint32_t pin_get_pull(const machine_pin_obj_t *pin); +uint32_t pin_get_drive(const machine_pin_obj_t *pin); +uint32_t pin_get_af(const machine_pin_obj_t *pin); +const machine_pin_obj_t *machine_pin_find(mp_obj_t user_obj); +const machine_pin_obj_t *pin_find_named_pin(const mp_obj_dict_t *named_pins, mp_obj_t name); +const pin_af_obj_t *pin_find_af(const machine_pin_obj_t *pin, uint8_t fn, uint8_t unit); +const pin_af_obj_t *pin_find_af_by_index(const machine_pin_obj_t *pin, mp_uint_t af_idx); +const pin_af_obj_t *pin_find_af_by_name(const machine_pin_obj_t *pin, const char *name); + +#endif // MICROPY_INCLUDED_RA_PIN_H diff --git a/ports/renesas-ra/powerctrl.c b/ports/renesas-ra/powerctrl.c new file mode 100644 index 000000000..8f9e25b72 --- /dev/null +++ b/ports/renesas-ra/powerctrl.c @@ -0,0 +1,304 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2018 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "hal_data.h" +#include "rtc.h" +#include "powerctrl.h" + +#if 0 + +// Sleep Mode +// At power on, by default sleep is set as the low-power mode. Sleep +// mode is the most convenient low-power mode available, as it does +// not require any special configuration (other than configuring and +// enabling a suitable interrupt or event to wake the MCU from sleep) +// to return to normal program-execution mode. +// The states of the SRAM, the processor registers, and the hardware +// peripherals are all maintained in sleep mode, and the time needed +// to enter and wake from sleep is minimal. Any interrupt causes the +// MCU device to wake from sleep mode, including the Systick interrupt +// used by the RTOS scheduler. + +// Software Standby Mode +// In software-standby mode, the CPU, as well as most of the on-chip +// peripheral functions and all of the internal oscillators, are +// stopped. +// The contents of the CPU internal registers and SRAM data, the states +// of on-chip peripheral functions, and I/O Ports are all retained. +// Software-standby mode allows significant reduction in power +// consumption, because most of the oscillators are stopped in this mode. +// Like sleep mode, standby mode requires an interrupt or event be +// configured and enabled to wake up. + +// Snooze Mode +// Snooze mode can be used with some MCU peripherals to execute basic +// tasks while keeping the MCU in a low-power state. +// Many core peripherals and all clocks can be selected to run during +// Snooze, allowing for more flexible low-power configuration than +// Software Standby mode. To enable Snooze, select "Software Standby +// mode with Snooze mode enabled" for the "Low Power Mode" configuration +// option. +// Snooze mode settings (including entry/exit sources) are available +// under "Standby Options". + +// Deep Software Standby Mode +// Deep Software Standby Mode is only available on some MCU devices. +// The MCU always wakes from Deep Software Standby Mode by going +// through reset, either by the negation of the reset pin or by one of +// the wakeup sources configurable in the "Deep Standby Options" +// configuration group. + +#endif + +#if defined(USE_FSP_LPM) + +// LPM_MODE_SLEEP: Sleep mode +// LPM_MODE_STANDBY: Software Standby mode +// LPM_MODE_STANDBY_SNOOZE: Software Standby mode with Snooze mode enabled +// LPM_MODE_DEEP: Deep Software Standby mode + +lpm_instance_ctrl_t g_lpm_sleep_ctrl; + +const lpm_cfg_t g_lpm_sleep_cfg = { + .low_power_mode = LPM_MODE_SLEEP, + .snooze_cancel_sources = LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RTC_PERIOD, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = 0, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = 0, + .power_supply_state = 0, + .deep_standby_cancel_source = (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm_sleep = { + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm_sleep_ctrl, + .p_cfg = &g_lpm_sleep_cfg +}; + +lpm_instance_ctrl_t g_lpm_deep_ctrl; + +const lpm_cfg_t g_lpm_deep_cfg = { + .low_power_mode = LPM_MODE_DEEP, + .snooze_cancel_sources = + LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = + (lpm_standby_wake_source_t)0, + .snooze_request_source = + LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = + (lpm_snooze_end_t)0, + .dtc_state_in_snooze = + LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_INTERVAL | LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_ALARM | (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm_deep = { + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm_deep_ctrl, + .p_cfg = &g_lpm_deep_cfg +}; + +lpm_instance_ctrl_t g_lpm_standby_ctrl; + +const lpm_cfg_t g_lpm_standby_cfg = { + .low_power_mode = LPM_MODE_STANDBY, + .snooze_cancel_sources = + LPM_SNOOZE_CANCEL_SOURCE_NONE, + .standby_wake_sources = + LPM_STANDBY_WAKE_SOURCE_RTCALM | LPM_STANDBY_WAKE_SOURCE_RTCPRD | (lpm_standby_wake_source_t)0, + .snooze_request_source = LPM_SNOOZE_REQUEST_RXD0_FALLING, + .snooze_end_sources = (lpm_snooze_end_t)0, + .dtc_state_in_snooze = LPM_SNOOZE_DTC_DISABLE, + #if BSP_FEATURE_LPM_HAS_SBYCR_OPE + .output_port_enable = LPM_OUTPUT_PORT_ENABLE_RETAIN, + #endif + #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY + .io_port_state = LPM_IO_PORT_NO_CHANGE, + .power_supply_state = LPM_POWER_SUPPLY_DEEPCUT0, + .deep_standby_cancel_source = LPM_DEEP_STANDBY_CANCEL_SOURCE_RTC_INTERVAL | (lpm_deep_standby_cancel_source_t)0, + .deep_standby_cancel_edge = (lpm_deep_standby_cancel_edge_t)0, + #endif + .p_extend = NULL, +}; + +const lpm_instance_t g_lpm_standby = { + .p_api = &g_lpm_on_lpm, + .p_ctrl = &g_lpm_standby_ctrl, + .p_cfg = &g_lpm_standby_cfg +}; + +#endif + +NORETURN void powerctrl_mcu_reset(void) { + #if BSP_FEATURE_TZ_HAS_TRUSTZONE + R_BSP_NonSecureEnter(); + #else + NVIC_SystemReset(); + #endif + while (1) { + ; + } +} + +NORETURN void powerctrl_enter_bootloader(uint32_t r0, uint32_t bl_addr) { + while (1) { + ; + } +} + +// static __attribute__((naked)) void branch_to_bootloader(uint32_t r0, uint32_t +// bl_addr) { +// } + +void powerctrl_check_enter_bootloader(void) { +} + +void powerctrl_enter_sleep_mode(void) { + // start trandition to RA MCU sleep mode + #if defined(USE_FSP_LPM) + fsp_err_t err; + err = R_LPM_Open(&g_lpm_sleep_ctrl, &g_lpm_sleep_cfg); + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter sleep mode")); + } + err = R_LPM_LowPowerModeEnter(&g_lpm_sleep_ctrl); + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter sleep mode")); + } + #endif +} + +void powerctrl_enter_stop_mode(void) { + // Disable IRQs so that the IRQ that wakes the device from stop mode is not + // executed until after the clocks are reconfigured + uint32_t irq_state = disable_irq(); + + #if defined(MICROPY_BOARD_ENTER_STOP) + MICROPY_BOARD_ENTER_STOP + #endif + + // start trandition to RA MCU sleep mode + #if defined(USE_FSP_LPM) + fsp_err_t err; + err = R_LPM_Open(&g_lpm_standby_ctrl, &g_lpm_standby_cfg); + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter stop mode")); + } + err = R_LPM_LowPowerModeEnter(&g_lpm_standby_ctrl); + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter stop mode")); + } + #endif + + // reconfigure the system clock after waking up + + #if defined(MICROPY_BOARD_LEAVE_STOP) + MICROPY_BOARD_LEAVE_STOP + #endif + + // Enable IRQs now that all clocks are reconfigured + enable_irq(irq_state); +} + +void powerctrl_enter_standby_mode(void) { + rtc_init_finalise(); + + #if defined(MICROPY_BOARD_ENTER_STANDBY) + MICROPY_BOARD_ENTER_STANDBY + #endif + + // start trandition to RA MCU deep software standby mode via software standby mode + #if defined(USE_FSP_LPM) + + fsp_err_t err; + err = R_LPM_Open(&g_lpm_deep_ctrl, &g_lpm_deep_cfg); + /* Handle any errors. This function should be defined by the user. */ + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter stop mode")); + } + /* Check the Deep Software Standby Reset Flag. */ + if (1U == R_SYSTEM->RSTSR0_b.DPSRSTF) { + /* Clear the IOKEEP bit to allow I/O Port use. */ + err = R_LPM_IoKeepClear(&g_lpm_deep_ctrl); + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter stop mode")); + } + } + /* Add user code here. */ + /* Reconfigure the module to set the IOKEEP bit before entering deep software standby. */ + err = R_LPM_LowPowerReconfigure(&g_lpm_deep_ctrl, &g_lpm_deep_cfg); + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter stop mode")); + } + err = R_LPM_LowPowerModeEnter(&g_lpm_deep_ctrl); + /* Code after R_LPM_LowPowerModeEnter when using Deep Software Standby never be executed. + * Deep software standby exits by resetting the MCU. */ + if (err != FSP_SUCCESS) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("Can't enter stop mode")); + } + + #endif + + // We need to clear the PWR wake-up-flag before entering standby, since + // the flag may have been set by a previous wake-up event. Furthermore, + // we need to disable the wake-up sources while clearing this flag, so + // that if a source is active it does actually wake the device. + // See section 5.3.7 of RM0090. + + // save RTC interrupts + // disable register write protection + // disable RTC interrupts + // clear RTC wake-up flags + + // enable previously-enabled RTC interrupts + // enable register write protection + + // enter standby mode + + // we never return; MCU is reset on exit from standby +} diff --git a/ports/renesas-ra/powerctrl.h b/ports/renesas-ra/powerctrl.h new file mode 100644 index 000000000..1743150b3 --- /dev/null +++ b/ports/renesas-ra/powerctrl.h @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2018 Damien P. George + * Copyright (c) 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RA_POWERCTRL_H +#define MICROPY_INCLUDED_RA_POWERCTRL_H + +#include <stdbool.h> +#include <stdint.h> + +void SystemClock_Config(void); + +NORETURN void powerctrl_mcu_reset(void); +NORETURN void powerctrl_enter_bootloader(uint32_t r0, uint32_t bl_addr); +void powerctrl_check_enter_bootloader(void); + +void powerctrl_enter_stop_mode(void); +void powerctrl_enter_standby_mode(void); + +#endif // MICROPY_INCLUDED_RA_POWERCTRL_H diff --git a/ports/renesas-ra/powerctrlboot.c b/ports/renesas-ra/powerctrlboot.c new file mode 100644 index 000000000..541eb6a9d --- /dev/null +++ b/ports/renesas-ra/powerctrlboot.c @@ -0,0 +1,36 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/mphal.h" +#include "irq.h" +#include "powerctrl.h" + +static inline void powerctrl_config_systick(void) { + // Configure SYSTICK to run at 1kHz (1ms interval) + SysTick->CTRL |= 0x00000004U; + SysTick_Config(MICROPY_HW_MCU_SYSCLK / 1000); + NVIC_SetPriority(SysTick_IRQn, IRQ_PRI_SYSTICK); +} diff --git a/ports/renesas-ra/pybthread.c b/ports/renesas-ra/pybthread.c new file mode 100644 index 000000000..603bc2e4e --- /dev/null +++ b/ports/renesas-ra/pybthread.c @@ -0,0 +1,237 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <string.h> +#include <stdio.h> + +#include "py/obj.h" +#include "gccollect.h" +#include "irq.h" +#include "pybthread.h" + +#if MICROPY_PY_THREAD + +#define PYB_MUTEX_UNLOCKED ((void *)0) +#define PYB_MUTEX_LOCKED ((void *)1) + +// These macros are used when we only need to protect against a thread +// switch; other interrupts are still allowed to proceed. +#define RAISE_IRQ_PRI() raise_irq_pri(IRQ_PRI_PENDSV) +#define RESTORE_IRQ_PRI(state) restore_irq_pri(state) + +extern void __fatal_error(const char *); + +volatile int pyb_thread_enabled; +pyb_thread_t *volatile pyb_thread_all; +pyb_thread_t *volatile pyb_thread_cur; + +static inline void pyb_thread_add_to_runable(pyb_thread_t *thread) { + thread->run_prev = pyb_thread_cur->run_prev; + thread->run_next = pyb_thread_cur; + pyb_thread_cur->run_prev->run_next = thread; + pyb_thread_cur->run_prev = thread; +} + +static inline void pyb_thread_remove_from_runable(pyb_thread_t *thread) { + if (thread->run_next == thread) { + __fatal_error("deadlock"); + } + thread->run_prev->run_next = thread->run_next; + thread->run_next->run_prev = thread->run_prev; +} + +void pyb_thread_init(pyb_thread_t *thread) { + pyb_thread_enabled = 0; + pyb_thread_all = thread; + pyb_thread_cur = thread; + thread->sp = NULL; // will be set when this thread switches out + thread->local_state = 0; // will be set by mp_thread_init + thread->arg = NULL; + thread->stack = &_sstack; + thread->stack_len = ((uint32_t)&_estack - (uint32_t)&_sstack) / sizeof(uint32_t); + thread->all_next = NULL; + thread->run_prev = thread; + thread->run_next = thread; + thread->queue_next = NULL; +} + +void pyb_thread_deinit() { + uint32_t irq_state = disable_irq(); + pyb_thread_enabled = 0; + pyb_thread_all = pyb_thread_cur; + pyb_thread_cur->all_next = NULL; + pyb_thread_cur->run_prev = pyb_thread_cur; + pyb_thread_cur->run_next = pyb_thread_cur; + enable_irq(irq_state); +} + +STATIC void pyb_thread_terminate(void) { + uint32_t irq_state = disable_irq(); + pyb_thread_t *thread = pyb_thread_cur; + // take current thread off the run list + pyb_thread_remove_from_runable(thread); + // take current thread off the list of all threads + for (pyb_thread_t **n = (pyb_thread_t **)&pyb_thread_all;; n = &(*n)->all_next) { + if (*n == thread) { + *n = thread->all_next; + break; + } + } + // clean pointers as much as possible to help GC + thread->all_next = NULL; + thread->queue_next = NULL; + thread->stack = NULL; + if (pyb_thread_all->all_next == NULL) { + // only 1 thread left + pyb_thread_enabled = 0; + } + // thread switch will occur after we enable irqs + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; + enable_irq(irq_state); + // should not return + __fatal_error("could not terminate"); +} + +uint32_t pyb_thread_new(pyb_thread_t *thread, void *stack, size_t stack_len, void *entry, void *arg) { + uint32_t *stack_top = (uint32_t *)stack + stack_len; // stack is full descending + *--stack_top = 0x01000000; // xPSR (thumb bit set) + *--stack_top = (uint32_t)entry & 0xfffffffe; // pc (must have bit 0 cleared, even for thumb code) + *--stack_top = (uint32_t)pyb_thread_terminate; // lr + *--stack_top = 0; // r12 + *--stack_top = 0; // r3 + *--stack_top = 0; // r2 + *--stack_top = 0; // r1 + *--stack_top = (uint32_t)arg; // r0 + *--stack_top = 0xfffffff9; // lr (return to thread mode, non-FP, use MSP) + stack_top -= 8; // r4-r11 + stack_top -= 16; // s16-s31 (we assume all threads use FP registers) + thread->sp = stack_top; + thread->local_state = 0; + thread->arg = arg; + thread->stack = stack; + thread->stack_len = stack_len; + thread->queue_next = NULL; + uint32_t irq_state = disable_irq(); + pyb_thread_enabled = 1; + thread->all_next = pyb_thread_all; + pyb_thread_all = thread; + pyb_thread_add_to_runable(thread); + enable_irq(irq_state); + return (uint32_t)thread; // success +} + +void pyb_thread_dump(void) { + if (!pyb_thread_enabled) { + printf("THREAD: only main thread\n"); + } else { + printf("THREAD:\n"); + for (pyb_thread_t *th = pyb_thread_all; th != NULL; th = th->all_next) { + bool runable = false; + for (pyb_thread_t *th2 = pyb_thread_cur;; th2 = th2->run_next) { + if (th == th2) { + runable = true; + break; + } + if (th2->run_next == pyb_thread_cur) { + break; + } + } + printf(" id=%p sp=%p sz=%u", th, th->stack, th->stack_len); + if (runable) { + printf(" (runable)"); + } + printf("\n"); + } + } +} + +// should only be called from pendsv_isr_handler +void *pyb_thread_next(void *sp) { + pyb_thread_cur->sp = sp; + pyb_thread_cur = pyb_thread_cur->run_next; + pyb_thread_cur->timeslice = 4; // in milliseconds + return pyb_thread_cur->sp; +} + +void pyb_mutex_init(pyb_mutex_t *m) { + *m = PYB_MUTEX_UNLOCKED; +} + +int pyb_mutex_lock(pyb_mutex_t *m, int wait) { + uint32_t irq_state = RAISE_IRQ_PRI(); + if (*m == PYB_MUTEX_UNLOCKED) { + // mutex is available + *m = PYB_MUTEX_LOCKED; + RESTORE_IRQ_PRI(irq_state); + } else { + // mutex is locked + if (!wait) { + RESTORE_IRQ_PRI(irq_state); + return 0; // failed to lock mutex + } + if (*m == PYB_MUTEX_LOCKED) { + *m = pyb_thread_cur; + } else { + for (pyb_thread_t *n = *m;; n = n->queue_next) { + if (n->queue_next == NULL) { + n->queue_next = pyb_thread_cur; + break; + } + } + } + pyb_thread_cur->queue_next = NULL; + // take current thread off the run list + pyb_thread_remove_from_runable(pyb_thread_cur); + // thread switch will occur after we enable irqs + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; + RESTORE_IRQ_PRI(irq_state); + // when we come back we have the mutex + } + return 1; // have mutex +} + +void pyb_mutex_unlock(pyb_mutex_t *m) { + uint32_t irq_state = RAISE_IRQ_PRI(); + if (*m == PYB_MUTEX_LOCKED) { + // no threads are blocked on the mutex + *m = PYB_MUTEX_UNLOCKED; + } else { + // at least one thread is blocked on this mutex + pyb_thread_t *th = *m; + if (th->queue_next == NULL) { + // no other threads are blocked + *m = PYB_MUTEX_LOCKED; + } else { + // at least one other thread is still blocked + *m = th->queue_next; + } + // put unblocked thread on runable list + pyb_thread_add_to_runable(th); + } + RESTORE_IRQ_PRI(irq_state); +} + +#endif // MICROPY_PY_THREAD diff --git a/ports/renesas-ra/pybthread.h b/ports/renesas-ra/pybthread.h new file mode 100644 index 000000000..91eeeb6d9 --- /dev/null +++ b/ports/renesas-ra/pybthread.h @@ -0,0 +1,77 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2017 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_PYBTHREAD_H +#define MICROPY_INCLUDED_RENESAS_RA_PYBTHREAD_H + +typedef struct _pyb_thread_t { + void *sp; + uint32_t local_state; + void *arg; // thread Python args, a GC root pointer + void *stack; // pointer to the stack + size_t stack_len; // number of words in the stack + uint32_t timeslice; + struct _pyb_thread_t *all_next; + struct _pyb_thread_t *run_prev; + struct _pyb_thread_t *run_next; + struct _pyb_thread_t *queue_next; +} pyb_thread_t; + +typedef pyb_thread_t *pyb_mutex_t; + +extern volatile int pyb_thread_enabled; +extern pyb_thread_t *volatile pyb_thread_all; +extern pyb_thread_t *volatile pyb_thread_cur; + +void pyb_thread_init(pyb_thread_t *th); +void pyb_thread_deinit(); +uint32_t pyb_thread_new(pyb_thread_t *th, void *stack, size_t stack_len, void *entry, void *arg); +void pyb_thread_dump(void); + +static inline uint32_t pyb_thread_get_id(void) { + return (uint32_t)pyb_thread_cur; +} + +static inline void pyb_thread_set_local(void *value) { + pyb_thread_cur->local_state = (uint32_t)value; +} + +static inline void *pyb_thread_get_local(void) { + return (void *)pyb_thread_cur->local_state; +} + +static inline void pyb_thread_yield(void) { + if (pyb_thread_cur->run_next == pyb_thread_cur) { + __WFI(); + } else { + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; + } +} + +void pyb_mutex_init(pyb_mutex_t *m); +int pyb_mutex_lock(pyb_mutex_t *m, int wait); +void pyb_mutex_unlock(pyb_mutex_t *m); + +#endif // MICROPY_INCLUDED_RENESAS_RA_PYBTHREAD_H diff --git a/ports/renesas-ra/qstrdefsport.h b/ports/renesas-ra/qstrdefsport.h new file mode 100644 index 000000000..bc07f2752 --- /dev/null +++ b/ports/renesas-ra/qstrdefsport.h @@ -0,0 +1,44 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +// qstrs specific to this port +// *FORMAT-OFF* + +// Entries for sys.path +Q(/flash) +Q(/flash/lib) +Q(/sd) +Q(/sd/lib) + +// For uos.sep +Q(/) + +#if MICROPY_HW_ENABLE_USB +// for usb modes +Q(MSC+HID) +Q(VCP+MSC) +Q(VCP+HID) +#endif diff --git a/ports/renesas-ra/ra/ra_adc.c b/ports/renesas-ra/ra/ra_adc.c new file mode 100644 index 000000000..e7a270a19 --- /dev/null +++ b/ports/renesas-ra/ra/ra_adc.c @@ -0,0 +1,556 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_gpio.h" +#include "ra_utils.h" +#include "ra_adc.h" + +static R_ADC0_Type *adc_reg = (R_ADC0_Type *)0x4005c000; +#if defined(RA4M1) | defined(RA4W1) +static R_TSN_Type *tsn_reg = (R_TSN_Type *)0x407ec000; +#endif +#if defined(RA6M1) | defined(RA6M2) +static R_TSN_CTRL_Type *tsn_ctrl_reg = (R_TSN_CTRL_Type *)0x4005D000; +static R_TSN_CAL_Type *tsn_cal_reg = (R_TSN_CAL_Type *)0x407FB17C; +#endif +static uint8_t resolution = RA_ADC_DEF_RESOLUTION; + +typedef struct adc_pin_to_ch { + uint32_t pin; + uint8_t ch; +} adc_pin_to_ch_t; + +static const adc_pin_to_ch_t pin_to_ch[] = { + #if defined(RA4M1) + + { P000, AN000 }, + { P001, AN001 }, + { P002, AN002 }, + { P003, AN003 }, + { P004, AN004 }, + { P005, AN011 }, + { P006, AN012 }, + { P007, AN013 }, + { P008, AN014 }, + { P010, AN005 }, + { P011, AN006 }, + { P012, AN007 }, + { P013, AN008 }, + { P014, AN009 }, + { P015, AN010 }, + { P100, AN022 }, + { P101, AN021 }, + { P102, AN020 }, + { P103, AN019 }, + { P500, AN016 }, + { P501, AN017 }, + { P502, AN018 }, + { P503, AN023 }, + { P504, AN024 }, + { P505, AN025 }, + + #elif defined(RA4W1) + + { P004, AN004 }, + { P010, AN005 }, + { P011, AN006 }, + { P014, AN009 }, + { P015, AN010 }, + { P102, AN020 }, + { P103, AN019 }, + { P501, AN017 }, + + #elif defined(RA6M2) + { P000, AN000 }, + { P001, AN001 }, + { P002, AN002 }, + { P003, AN007 }, + { P004, AN100 }, + { P005, AN101 }, + { P006, AN102 }, + { P007, AN107 }, + { P008, AN003 }, + { P009, AN004 }, + { P014, AN005 }, + { P014, AN105 }, + { P015, AN006 }, + { P015, AN106 }, + { P500, AN016 }, + { P501, AN116 }, + { P502, AN017 }, + { P503, AN117 }, + { P504, AN018 }, + { P505, AN118 }, + { P506, AN019 }, + { P509, AN020 }, + + #elif defined(RA6M1) + { P000, AN000 }, + { P001, AN001 }, + { P002, AN002 }, + { P003, AN007 }, + { P004, AN100 }, + { P005, AN101 }, + { P006, AN102 }, + { P007, AN107 }, + { P008, AN003 }, + { P014, AN005 }, + { P014, AN105 }, + { P015, AN006 }, + { P015, AN106 }, + { P500, AN016 }, + { P501, AN116 }, + { P502, AN017 }, + { P503, AN117 }, + { P504, AN018 }, + { P508, AN020 }, + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define ADC_PIN_TO_CH_SIZE (sizeof(pin_to_ch) / sizeof(adc_pin_to_ch_t)) + +#define ADC_CH_MAX (32) +#define ADC_UNIT0_SCAN_MAX (28) +static uint16_t adc_values[ADC_CH_MAX]; + +bool ra_adc_pin_to_ch(uint32_t pin, uint8_t *ch) { + uint32_t i; + *ch = (uint8_t)ADC_NON; + for (i = 0; i < ADC_PIN_TO_CH_SIZE; i++) { + if (pin == pin_to_ch[i].pin) { + *ch = pin_to_ch[i].ch; + break; + } + } + if (*ch == (uint8_t)ADC_NON) { + return false; + } else { + return true; + } +} + +bool ra_adc_ch_to_pin(uint8_t ch, uint32_t *pin) { + uint32_t i; + *pin = (uint32_t)PIN_END; + for (i = 0; i < ADC_PIN_TO_CH_SIZE; i++) { + if (ch == pin_to_ch[i].ch) { + *pin = pin_to_ch[i].pin; + break; + } + } + if (*pin == (uint32_t)PIN_END) { + return false; + } else { + return true; + } +} + +uint8_t ra_adc_get_channel(uint32_t pin) { + bool flag; + uint8_t ch; + flag = ra_adc_pin_to_ch(pin, &ch); + if (!flag) { + ch = 0; + } + return ch; +} + +static void ra_adc0_module_start(void) { + ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD16_Msk); +} + +static void ra_adc0_module_stop(void) { + ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD16_Msk); +} + +#if defined(RA6M1) | defined(RA6M2) +static void ra_adc1_module_start(void) { + ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD15_Msk); +} + +static void ra_adc1_module_stop(void) { + ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD15_Msk); +} +#endif + +// For RA4M1 and RA4W1, there is no TSN configuration +#if defined(RA6M1) | defined(RA6M2) +static void ra_tsn_module_start(void) { + ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD22_Msk); +} + +static void ra_tsn_module_stop(void) { + ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD22_Msk); +} +#endif + +void ra_adc_set_pin(uint32_t pin, bool adc_enable) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + uint32_t pfs = _PXXPFS(port, bit); + pwpr_unprotect(); + if (adc_enable) { + pfs &= ~PMR_MASK; /* GPIO */ + pfs &= ~PDR_MASK; /* input */ + pfs |= ASEL_MASK; /* set adc bit */ + } else { + pfs |= PMR_MASK; /* GPIO */ + pfs &= ~PDR_MASK; /* input */ + pfs &= ~ASEL_MASK; /* clear adc bit */ + } + _PXXPFS(port, bit) = pfs; + pwpr_protect(); +} + +void ra_adc_enable(uint32_t pin) { + ra_adc_set_pin(pin, true); +} + +void ra_adc_disable(uint32_t pin) { + ra_adc_set_pin(pin, false); +} + +__attribute__((naked)) static void min_delay(__attribute__((unused)) uint32_t loop_cnt) { + __asm volatile ( + "sw_delay_loop: \n" + #if defined(__ICCARM__) || defined(__ARMCC_VERSION) + " subs r0, #1 \n" ///< 1 cycle + #elif defined(__GNUC__) + " sub r0, r0, #1 \n" ///< 1 cycle + #endif + " cmp r0, #0 \n" ///< 1 cycle + /* CM0 and CM23 have a different instruction set */ + #if defined(__CORE_CM0PLUS_H_GENERIC) || defined(__CORE_CM23_H_GENERIC) + " bne sw_delay_loop \n" ///< 2 cycles + #else + " bne.n sw_delay_loop \n" ///< 2 cycles + #endif + " bx lr \n"); ///< 2 cycles +} + +static void udelay(uint32_t us) { + while (us-- > 0) { + min_delay(PCLK / 1000000 / 4); + } +} + +void ra_adc_set_resolution(uint8_t res) { + uint16_t adcer; + uint16_t adprc; + #if defined(RA4M1) | defined(RA4W1) + if ((res == 14) | (res == 12)) { + if (res == 14) { + adprc = 0x0006; + } else { + adprc = 0x0000; + } + adcer = adc_reg->ADCER; + adcer &= (uint16_t) ~0x0006; + adcer |= (uint16_t)adprc; + adc_reg->ADCER; + resolution = res; + } + #else + if ((res == 12) | (res == 10) | (res == 8)) { + if (res == 12) { + adprc = 0x0000; + } else if (res == 10) { + adprc = 0x0002; + } else { + adprc = 0x0004; + } + adcer = adc_reg->ADCER; + adcer &= (uint16_t) ~0x0006; + adcer |= (uint16_t)adprc; + adc_reg->ADCER; + resolution = res; + } + #endif +} + +uint8_t ra_adc_get_resolution(void) { + uint8_t res = 0; + uint16_t adcer; + adcer = adc_reg->ADCER; + adcer &= 0x0006; + #if defined(RA4M1) | defined(RA4W1) + if (adcer == 0x0006) { + res = 14; + } else if (adcer == 0x0000) { + res = 12; + } + #else + if (adcer == 0x0000) { + res = 12; + } else if (adcer == 0x0002) { + res = 10; + } else if (adcer == 0x0004) { + res = 8; + } + #endif + return res; +} + +// assumption +// AVCC0 is used. Neither VREFH0 nor internal reference voltage is not used. +uint16_t ra_adc_read_ch(uint8_t ch) { + uint16_t value16 = 0; + if ((ch == ADC_TEMP) | (ch == ADC_REF)) { + #if defined(RA6M1) | defined(RA6M2) + if (ch == ADC_TEMP) { + adc_reg->ADEXICR_b.TSSA = 1; + tsn_ctrl_reg->TSCR_b.TSEN = 1; + while (!tsn_ctrl_reg->TSCR_b.TSEN) { + ; + } + tsn_ctrl_reg->TSCR_b.TSOE = 1; + while (!tsn_ctrl_reg->TSCR_b.TSOE) { + ; + } + udelay(300); + } else if (ch == ADC_REF) { + adc_reg->ADEXICR_b.OCSA = 1; + udelay(300); + } + #endif + adc_reg->ADANSA[0] = 0; + adc_reg->ADANSA[1] = 0; + } else if (ch < 16) { + adc_reg->ADANSA[0] |= (uint16_t)(1 << ch); + } else { + adc_reg->ADANSA[1] |= (uint16_t)(1 << (ch - 16)); + } + adc_reg->ADCSR_b.ADCS = 0; /* single scan mode */ + adc_reg->ADCSR_b.ADST = 1; /* start a/d conversion */ + while (adc_reg->ADCSR_b.ADST) { + ; /* ADC in progress*/ + } + if (ch == ADC_TEMP) { + value16 = (uint16_t)adc_reg->ADTSDR; + } else if (ch == ADC_REF) { + value16 = (uint16_t)adc_reg->ADOCDR; + } else { + value16 = (uint16_t)adc_reg->ADDR[ch]; + } + #if defined(RA6M1) | defined(RA6M2) + if (ch == ADC_TEMP) { + tsn_ctrl_reg->TSCR_b.TSOE = 0; + while (tsn_ctrl_reg->TSCR_b.TSOE) { + ; + } + tsn_ctrl_reg->TSCR_b.TSEN = 0; + while (tsn_ctrl_reg->TSCR_b.TSEN) { + ; + } + } else if (ch == ADC_REF) { + adc_reg->ADEXICR_b.OCSA = 0; + } + #endif + return value16; +} + +uint16_t ra_adc_read(uint32_t pin) { + uint8_t ch = ra_adc_get_channel(pin); + if (ch == ADC_NON) { + return 0; + } + return ra_adc_read_ch(ch); +} + +int16_t ra_adc_read_itemp(void) { + int16_t temp = 0; + int16_t vmax = (int16_t)(1 << resolution); + #if defined(RA4M1) | defined(RA4W1) + uint16_t cal125 = ((uint16_t)tsn_reg->TSCDRH << 8) + (uint16_t)tsn_reg->TSCDRL; + uint16_t val = ra_adc_read_ch(ADC_TEMP); + int16_t v125 = (int16_t)(33 * cal125 / vmax / 10); + int16_t vtemp = (int16_t)(33 * val / vmax / 10); + temp = (int16_t)(125 + ((vtemp - v125) * 1000000 / (int16_t)BSP_FEATURE_ADC_TSN_SLOPE)); + #elif defined(RA6M1) | defined(RA6M2) + uint16_t cal127 = (uint16_t)tsn_cal_reg->TSCDR; + uint16_t val = ra_adc_read_ch(ADC_TEMP); + int16_t v127 = (int16_t)(33 * cal127 / vmax / 10); + int16_t vtemp = (int16_t)(33 * val / vmax / 10); + temp = (int16_t)(127 + ((vtemp - v127) * 1000000 / (int16_t)BSP_FEATURE_ADC_TSN_SLOPE)); + #else + #error "CMSIS MCU Series is not specified." + #endif + return temp; +} + +float ra_adc_read_ftemp(void) { + float temp; + float vmax = (float)(1 << resolution); + #if defined(RA4M1) | defined(RA4W1) + uint16_t cal125 = ((uint16_t)tsn_reg->TSCDRH << 8) + (uint16_t)tsn_reg->TSCDRL; + uint16_t val = ra_adc_read_ch(ADC_TEMP); + float v125 = (float)(3.3f * (float)cal125 / vmax); + float vtemp = (float)(3.3f * (float)val / vmax); + temp = (float)(125.0f + ((vtemp - v125) * 1000000.0f / (float)BSP_FEATURE_ADC_TSN_SLOPE)); + #endif + #if defined(RA6M1) | defined(RA6M2) + uint16_t cal127 = (uint16_t)tsn_cal_reg->TSCDR; + uint16_t val = ra_adc_read_ch(ADC_TEMP); + float v127 = (float)(3.3f * (float)cal127 / vmax); + float vtemp = (float)(3.3f * (float)val / vmax); + temp = (float)(127.0f + ((vtemp - v127) * 1000000.0f / (float)BSP_FEATURE_ADC_TSN_SLOPE)); + #endif + return temp; +} + +float ra_adc_read_fref(void) { + uint16_t val = ra_adc_read_ch(ADC_REF); + float vmax = (float)(1 << resolution); + float vref = (float)(3.3f * (float)val / vmax); + return vref; +} + +uint16_t ra_adc_all_read_ch(uint32_t ch) { + if (ch < ADC_CH_MAX) { + return adc_values[ch]; + } else { + return 0; + } +} + +void ra_adc_all(__attribute__((unused)) uint32_t resolution, uint32_t mask) { + uint32_t i; + uint32_t pin; + uint32_t bit; + uint16_t value16 = 0; + bool badc = ((mask & 0x1fffffff) != 0); + bool btemp = ((mask & (1 << ADC_TEMP)) != 0); + bool bref = ((mask & (1 << ADC_REF)) != 0); + for (i = 0; i < ADC_CH_MAX; i++) { + adc_values[i] = 0; + } + if (badc) { + bit = 1; + adc_reg->ADANSA[0] = 0; + adc_reg->ADANSA[1] = 0; + for (i = 0; i < ADC_UNIT0_SCAN_MAX; i++) { + if (mask & bit) { + if (ra_adc_ch_to_pin((uint8_t)i, &pin)) { + ra_adc_enable(pin); + if (i < 16) { + adc_reg->ADANSA[0] |= (uint16_t)(1 << i); + } else { + adc_reg->ADANSA[1] |= (uint16_t)(1 << (i - 16)); + } + } + } + bit <<= 1; + } + adc_reg->ADCSR_b.ADCS = 0; /* single scan mode */ + adc_reg->ADCSR_b.ADST = 1; /* start a/d conversion */ + while (adc_reg->ADCSR_b.ADST) { + ; /* ADC in progress*/ + } + bit = 1; + for (i = 0; i < ADC_UNIT0_SCAN_MAX; i++) { + if (mask & bit) { + value16 = (uint16_t)adc_reg->ADDR[i]; + adc_values[i] = value16; + } + bit <<= 1; + } + } + if (btemp) { + adc_reg->ADANSA[0] = 0; + adc_reg->ADANSA[1] = 0; + adc_reg->ADEXICR_b.TSSA = 1; + #if defined(RA6M1) | defined(RA6M2) + tsn_ctrl_reg->TSCR_b.TSEN = 1; + while (!tsn_ctrl_reg->TSCR_b.TSEN) { + ; + } + tsn_ctrl_reg->TSCR_b.TSOE = 1; + while (!tsn_ctrl_reg->TSCR_b.TSOE) { + ; + } + udelay(30); + #endif + adc_reg->ADCSR_b.ADCS = 0; /* single scan mode */ + adc_reg->ADCSR_b.ADST = 1; /* start a/d conversion */ + while (adc_reg->ADCSR_b.ADST) { + ; /* ADC in progress*/ + } + value16 = (uint16_t)adc_reg->ADTSDR; + adc_values[ADC_TEMP] = value16; + #if defined(RA6M1) | defined(RA6M2) + tsn_ctrl_reg->TSCR_b.TSOE = 0; + while (tsn_ctrl_reg->TSCR_b.TSOE) { + ; + } + tsn_ctrl_reg->TSCR_b.TSEN = 0; + while (tsn_ctrl_reg->TSCR_b.TSEN) { + ; + } + #endif + } + if (bref) { + adc_reg->ADANSA[0] = 0; + adc_reg->ADANSA[1] = 0; + adc_reg->ADEXICR_b.OCSA = 1; + udelay(30); + adc_reg->ADCSR_b.ADCS = 0; /* single scan mode */ + adc_reg->ADCSR_b.ADST = 1; /* start a/d conversion */ + while (adc_reg->ADCSR_b.ADST) { + ; /* ADC in progress*/ + } + value16 = (uint16_t)adc_reg->ADOCDR; + adc_values[ADC_REF] = value16; + } +} + +bool ra_adc_init(void) { + ra_adc0_module_start(); + #if defined(RA6M1) | defined(RA6M2) + ra_adc1_module_start(); + ra_tsn_module_start(); + #endif + resolution = RA_ADC_DEF_RESOLUTION; + ra_adc_set_resolution(resolution); + return true; +} + +bool ra_adc_deinit(void) { + ra_adc0_module_stop(); + #if defined(RA6M1) | defined(RA6M2) + ra_adc1_module_stop(); + ra_tsn_module_stop(); + #endif + return true; +} + +__WEAK void adc_scan_end_isr(void) { + // dummy +} diff --git a/ports/renesas-ra/ra/ra_adc.h b/ports/renesas-ra/ra/ra_adc.h new file mode 100644 index 000000000..4d56243d1 --- /dev/null +++ b/ports/renesas-ra/ra/ra_adc.h @@ -0,0 +1,186 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_ADC_H_ +#define RA_ADC_H_ + +#include <stdint.h> +#include <stdbool.h> + +#if defined(RA4M1) | defined(RA4W1) +#define ADC_RESOLUTION (14) +#else +#define ADC_RESOLUTION (12) +#endif + +enum ADC14_PIN +{ + #if defined(RA4M1) + + AN000 = 0, + AN001 = 1, + AN002 = 2, + AN003 = 3, + AN004 = 4, + AN005 = 5, + AN006 = 6, + AN007 = 7, + AN008 = 8, + AN009 = 9, + AN010 = 10, + AN011 = 11, + AN012 = 12, + AN013 = 13, + AN014 = 14, + AN016 = 16, + AN017 = 17, + AN018 = 18, + AN019 = 19, + AN020 = 20, + AN021 = 21, + AN022 = 22, + AN023 = 23, + AN024 = 24, + AN025 = 25, + + #elif defined(RA4W1) + + AN004 = 4, + AN005 = 5, + AN006 = 6, + AN009 = 9, + AN010 = 10, + AN017 = 17, + AN019 = 19, + AN020 = 20, + + #elif defined(RA6M1) + + AN000 = 0, + AN001 = 1, + AN002 = 2, + AN003 = 3, + AN004 = 4, + AN005 = 5, + AN006 = 6, + AN007 = 7, + AN008 = 8, + AN009 = 9, + AN010 = 10, + AN011 = 11, + AN012 = 12, + AN013 = 13, + AN014 = 14, + AN015 = 15, + AN016 = 16, + AN017 = 17, + AN018 = 18, + AN019 = 19, + AN020 = 20, + AN021 = 21, + AN022 = 22, + AN100 = 32, + AN101 = 33, + AN102 = 34, + AN103 = 35, + AN104 = 36, + AN105 = 37, + AN106 = 38, + AN107 = 39, + AN108 = 40, + AN109 = 41, + AN110 = 42, + AN111 = 43, + AN112 = 44, + AN113 = 45, + AN114 = 46, + AN115 = 47, + AN116 = 48, + AN117 = 49, + AN118 = 50, + AN119 = 51, + AN120 = 52, + + #elif defined(RA6M2) + // Unit 0 + AN000 = 0, + AN001 = 1, + AN002 = 2, + AN003 = 3, + AN004 = 4, + AN005 = 5, + AN006 = 6, + AN007 = 7, + AN016 = 16, + AN017 = 17, + AN018 = 18, + AN019 = 19, + AN020 = 20, + // Unit 1 + AN100 = 32, + AN101 = 33, + AN102 = 34, + AN105 = 37, + AN106 = 38, + AN107 = 39, + AN116 = 48, + AN117 = 49, + AN118 = 50, + + #else + #error "CMSIS MCU Series is not specified." + #endif + ADC_TEMP = 29, + ADC_REF = 30, + ADC_NON = 255, +}; + +#if defined(RA4M1) | defined(RA4W1) +#define RA_ADC_DEF_RESOLUTION 14 +#else +#define RA_ADC_DEF_RESOLUTION 12 +#endif + +bool ra_adc_pin_to_ch(uint32_t pin, uint8_t *ch); +bool ra_adc_ch_to_pin(uint8_t ch, uint32_t *pin); +uint8_t ra_adc_get_channel(uint32_t pin); +// static void ra_adc_module_start(void); +// static void ra_adc_module_stop(void); +void ra_adc_set_pin(uint32_t pin, bool adc_enable); +void ra_adc_enable(uint32_t pin); +void ra_adc_disable(uint32_t pin); +void ra_adc_set_resolution_set(uint8_t res); +uint8_t ra_adc_get_resolution(void); +uint16_t ra_adc_read_ch(uint8_t ch); +uint16_t ra_adc_read(uint32_t pin); +int16_t ra_adc_read_itemp(void); +float ra_adc_read_ftemp(void); +float ra_adc_read_fref(void); +void ra_adc_all(uint32_t resolution, uint32_t mask); +uint16_t ra_adc_all_read_ch(uint32_t ch); +bool ra_adc_init(void); +bool ra_adc_deinit(void); +__attribute__((weak)) void adc_scan_end_isr(void); + +#endif /* RA_ADC_H_ */ diff --git a/ports/renesas-ra/ra/ra_config.h b/ports/renesas-ra/ra/ra_config.h new file mode 100644 index 000000000..c02947a47 --- /dev/null +++ b/ports/renesas-ra/ra/ra_config.h @@ -0,0 +1,103 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_CONFIG_H_ +#define RA_RA_CONFIG_H_ + +#include <stdint.h> + +#if defined(RA4M1) | defined(RA4W1) +#define SCI_CH_MAX 10 +#define SCI_CH_NUM 4 +#define SCI_TX_BUF_SIZE 128 +#define SCI_RX_BUF_SIZE 256 +#define PCLK 48000000 +#elif defined(RA6M1) | defined(RA6M2) +#define SCI_CH_MAX 10 +#define SCI_CH_NUM 4 +#define SCI_TX_BUF_SIZE 128 +#define SCI_RX_BUF_SIZE 256 +#define PCLK 120000000 +#else +#error "CMSIS MCU Series is not specified." +#endif + +#if defined(MICROPY_HW_MCU_PCLK) +#undef PCLK +#define PCLK MICROPY_HW_MCU_PCLK +#endif + +#define SCI_DEF_BAUD (115200) + +#if !defined(RA_PRI_SYSTICK) +#define RA_PRI_SYSTICK (0) +#endif +#if !defined(RA_PRI_UART) +#define RA_PRI_UART (1) +#endif +#if !defined(RA_PRI_SDIO) +#define RA_PRI_SDIO (4) +#endif +#if !defined(RA_PRI_DMA) +#define RA_PRI_DMA (5) +#endif +#if !defined(RA_PRI_FLASH) +#define RA_PRI_FLASH (6) +#endif +#if !defined(RA_PRI_OTG_FS) +#define RA_PRI_OTG_FS (6) +#endif +#if !defined(RA_PRI_OTG_HS) +#define RA_PRI_OTG_HS (6) +#endif +#if !defined(RA_PRI_TIM5) +#define RA_PRI_TIM5 (6) +#endif +#if !defined(RA_PRI_CAN) +#define RA_PRI_CAN (7) +#endif +#if !defined(RA_PRI_SPI) +#define RA_PRI_SPI (8) +#endif +#if !defined(RA_PRI_I2C) +#define RA_PRI_I2C (8) +#endif +#if !defined(RA_PRI_TIMX) +#define RA_PRI_TIMX (13) +#endif +#if !defined(RA_PRI_EXTINT) +#define RA_PRI_EXTINT (14) +#endif +#if !defined(RA_PRI_PENDSV) +#define RA_PRI_PENDSV (15) +#endif +#if !defined(RA_PRI_RTC_WKUP) +#define RA_PRI_RTC_WKUP (15) +#endif + +#if !defined(__WEAK) +#define __WEAK __attribute__((weak)) +#endif + +#endif /* RA_RA_CONFIG_H_ */ diff --git a/ports/renesas-ra/ra/ra_flash.c b/ports/renesas-ra/ra/ra_flash.c new file mode 100644 index 000000000..e289f5f92 --- /dev/null +++ b/ports/renesas-ra/ra/ra_flash.c @@ -0,0 +1,298 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdbool.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_utils.h" +#include "ra_flash.h" + +#if !defined(USE_FSP_FLASH) +#define USE_FSP_FLASH +#endif + +#if defined(USE_FSP_FLASH) + +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wmissing-declarations" +#endif + +/* Flags, set from Callback function */ +static volatile _Bool g_b_flash_event_not_blank = false; +static volatile _Bool g_b_flash_event_blank = false; +static volatile _Bool g_b_flash_event_erase_complete = false; +static volatile _Bool g_b_flash_event_write_complete = false; + +static uint8_t flash_buf[FLASH_BUF_SIZE] __attribute__((aligned(2))); + +void *FLASH_SECTION lmemset(void *dst, int c, size_t len) { + char *p; + for (p = (char *)dst; len > 0; len--) { + *(p++) = (char)c; + } + return (void *)dst; +} + +void *FLASH_SECTION lmemcpy(void *dst, const void *src, size_t len) { + char *d = (char *)dst; + const char *s = (const char *)src; + for (; len > 0; len--) { + *(d++) = *(s++); + } + return (void *)dst; +} + +int FLASH_SECTION lmemcmp(const void *p1, const void *p2, size_t len) { + unsigned char *a, *b; + size_t i; + + a = (unsigned char *)p1; + b = (unsigned char *)p2; + for (i = 0; i < len; i++) { + if (*a != *b) { + return (*a < *b) ? -1 : 1; + } + a++; + b++; + } + return (int)0; +} + +#if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) + +uint32_t FLASH_SECTION sector_size(uint32_t addr) { + return FLASH_SECTOR_SIZE; +} + +uint32_t FLASH_SECTION sector_start(uint32_t addr) { + return addr & ~(FLASH_SECTOR_SIZE - 1); +} + +uint32_t FLASH_SECTION sector_index(uint32_t addr) { + return (addr - 0x00000000) / FLASH_SECTOR_SIZE; +} + +#elif defined(RA6M1) | defined(RA6M2) + +#define REGION1_SECTOR_SIZE 0x8000 // 32K +#define REGION1_SECTOR_MAX 14 +#define REGION0_SECTOR_SIZE 0x2000 // 8K +#define REGION0_SECTOR_MAX 8 + +uint32_t FLASH_SECTION sector_size(uint32_t addr) { + if (addr <= 0x00010000) { + return REGION0_SECTOR_SIZE; + } else { + return REGION1_SECTOR_SIZE; + } +} + +uint32_t FLASH_SECTION sector_start(uint32_t addr) { + if (addr <= 0x00010000) { + return addr & ~(REGION0_SECTOR_SIZE - 1); + } else { + return addr & ~(REGION1_SECTOR_SIZE - 1); + } +} + +uint32_t FLASH_SECTION sector_index(uint32_t addr) { + if (addr <= 0x00010000) { + return (addr - 0x00010000) / REGION0_SECTOR_SIZE; + } else { + return (addr - 0x000100000) / REGION1_SECTOR_SIZE; + } +} + +#else +#error "CMSIS MCU Series is not specified." +#endif + +bool internal_flash_read(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuff) { + CHIP_WORD *startaddr = (CHIP_WORD *)addr; + CHIP_WORD *endaddr = (CHIP_WORD *)(addr + NumBytes); + while (startaddr < endaddr) { + *pSectorBuff++ = *startaddr++; + } + return true; +} + +bool internal_flash_write(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuff, bool ReadModifyWrite) { + return internal_flash_writex(addr, NumBytes, pSectorBuff, ReadModifyWrite, true); +} + +bool internal_flash_writex(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuff, bool ReadModifyWrite, bool fIncrementDataPtr) { + fsp_err_t err = FSP_SUCCESS; + bool flag; + uint32_t count; + uint8_t *buf_addr = (uint8_t *)&flash_buf[0]; + uint32_t startaddr = (uint32_t)addr & FLASH_BUF_ADDR_MASK; + uint32_t offset = (uint32_t)addr & FLASH_BUF_OFF_MASK; + uint32_t endaddr = (uint32_t)addr + NumBytes; + uint32_t error_code = 0; + while (startaddr < endaddr) { + // copy from dst rom addr to flash buffer to keep current data + lmemcpy(flash_buf, (void *)startaddr, FLASH_BUF_SIZE); + // memset(flash_buf, 0xff, FLASH_BUF_SIZE); + if (NumBytes + offset > FLASH_BUF_SIZE) { + count = FLASH_BUF_SIZE - offset; + NumBytes -= count; + } else { + count = NumBytes; + } + // overwrite data from src addr to flash buffer + if (fIncrementDataPtr) { + lmemcpy(flash_buf + offset, pSectorBuff, count); + } else { + lmemset(flash_buf + offset, (int)*pSectorBuff, count); + } + g_b_flash_event_write_complete = false; + uint8_t *flash_addr = (uint8_t *)((uint32_t)startaddr & FLASH_BUF_ADDR_MASK); + uint32_t state = ra_disable_irq(); + #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) + err = R_FLASH_LP_Write(&g_flash0_ctrl, (uint32_t const)buf_addr, (uint32_t)flash_addr, FLASH_SECTOR_SIZE); + #elif defined(RA6M1) | defined(RA6M2) + err = R_FLASH_HP_Write(&g_flash0_ctrl, (uint32_t const)buf_addr, (uint32_t)flash_addr, FLASH_SECTOR_SIZE); + #else + #error "CMSIS MCU Series is not specified." + #endif + ra_enable_irq(state); + if (FSP_SUCCESS != err) { + error_code = 1; + goto WriteX_exit; + } + if (fIncrementDataPtr) { + flag = (lmemcmp((void *)(startaddr + offset), flash_buf + offset, count) == 0); + if (!flag) { + error_code = 2; + break; + } + } + offset = 0; + startaddr += FLASH_BUF_SIZE; + pSectorBuff += count; + } +WriteX_exit: + if (error_code == 0) { + return true; + } + return false; +} + +bool internal_flash_memset(uint8_t *addr, uint8_t Data, uint32_t NumBytes) { + return true; +} + +bool internal_flash_isblockerased(uint8_t *addr, uint32_t BlockLength) { + fsp_err_t err = FSP_SUCCESS; + flash_result_t blankCheck = FLASH_RESULT_BLANK; + g_b_flash_event_not_blank = false; + g_b_flash_event_blank = false; + uint32_t state = ra_disable_irq(); + #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) + err = R_FLASH_LP_BlankCheck(&g_flash0_ctrl, (uint32_t const)((uint32_t)addr & FLASH_BUF_ADDR_MASK), FLASH_SECTOR_SIZE, &blankCheck); + #elif defined(RA6M1) | defined(RA6M2) + err = R_FLASH_HP_BlankCheck(&g_flash0_ctrl, (uint32_t const)((uint32_t)addr & FLASH_BUF_ADDR_MASK), FLASH_SECTOR_SIZE, &blankCheck); + #else + #error "CMSIS MCU Series is not specified." + #endif + ra_enable_irq(state); + if (err == FSP_SUCCESS) { + if (FLASH_RESULT_BLANK == blankCheck) { + return true; + } else { + return false; + } + } else { + return false; + } +} + +bool internal_flash_eraseblock(uint8_t *addr) { + uint32_t error_code = 0; + fsp_err_t err = FSP_SUCCESS; + g_b_flash_event_erase_complete = false; + uint32_t state = ra_disable_irq(); + #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) + err = R_FLASH_LP_Erase(&g_flash0_ctrl, (uint32_t const)addr, 1); + #elif defined(RA6M1) | defined(RA6M2) + err = R_FLASH_HP_Erase(&g_flash0_ctrl, (uint32_t const)addr, 1); + #else + #error "CMSIS MCU Series is not specified." + #endif + ra_enable_irq(state); + if (err == FSP_SUCCESS) { + error_code = 0; + } else { + error_code = 1; + } + if (error_code == 0) { + return true; + } + return false; +} + +/* Callback function */ +void callback_flash(flash_callback_args_t *p_args) { + /* TODO: add your own code here */ + switch (p_args->event) { + case FLASH_EVENT_NOT_BLANK: + g_b_flash_event_not_blank = true; + break; + case FLASH_EVENT_BLANK: + g_b_flash_event_blank = true; + break; + case FLASH_EVENT_ERASE_COMPLETE: + g_b_flash_event_erase_complete = true; + break; + case FLASH_EVENT_WRITE_COMPLETE: + g_b_flash_event_write_complete = true; + break; + default: + /* Do nothing */ + break; + } +} + +bool internal_flash_init(void) { + fsp_err_t err = FSP_SUCCESS; + #if defined(RA4M1) | defined(RA4M3) | defined(RA4W1) + err = R_FLASH_LP_Open(&g_flash0_ctrl, &g_flash0_cfg); + #elif defined(RA6M1) | defined(RA6M2) + err = R_FLASH_HP_Open(&g_flash0_ctrl, &g_flash0_cfg); + #else + #error "CMSIS MCU Series is not specified." + #endif + if (err == FSP_SUCCESS) { + return true; + } else { + return false; + } +} + +#else + +// ToDo: implementation + +#endif diff --git a/ports/renesas-ra/ra/ra_flash.h b/ports/renesas-ra/ra/ra_flash.h new file mode 100644 index 000000000..f9afef2a9 --- /dev/null +++ b/ports/renesas-ra/ra/ra_flash.h @@ -0,0 +1,57 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_FLASH_H_ +#define RA_FLASH_H_ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> + +#define FLASH_SECTOR_SIZE ((uint32_t)2048) +#define FLASH_NUM_BLOCKS ((uint32_t)128) +#define FLASH_BUF_OFF_MASK (FLASH_SECTOR_SIZE - 1) +#define FLASH_BUF_ADDR_MASK (~FLASH_BUF_OFF_MASK) +#define FLASH_BUF_SIZE FLASH_SECTOR_SIZE + +#define FLASH_SECTION __attribute__((section("FLASH_OP"))) + +typedef uint8_t CHIP_WORD; + +void FLASH_SECTION *lmemset(void *dst, int c, size_t len); +void FLASH_SECTION *lmemcpy(void *dst, const void *src, size_t len); +int FLASH_SECTION lmemcmp(const void *p1, const void *p2, size_t len); + +uint32_t FLASH_SECTION sector_size(uint32_t addr); +uint32_t FLASH_SECTION sector_start(uint32_t addr); +uint32_t FLASH_SECTION sector_index(uint32_t addr); +bool FLASH_SECTION internal_flash_read(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuff); +bool FLASH_SECTION internal_flash_write(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuff, bool ReadModifyWrite); +bool FLASH_SECTION internal_flash_writex(uint8_t *addr, uint32_t NumBytes, uint8_t *pSectorBuff, bool ReadModifyWrite, bool fIncrementDataPtr); +bool FLASH_SECTION internal_flash_memset(uint8_t *addr, uint8_t Data, uint32_t NumBytes); +bool FLASH_SECTION internal_flash_isblockerased(uint8_t *addr, uint32_t BlockLength); +bool FLASH_SECTION internal_flash_eraseblock(uint8_t *addr); +bool FLASH_SECTION internal_flash_init(void); + +#endif /* RA_FLASH_H_ */ diff --git a/ports/renesas-ra/ra/ra_gpio.c b/ports/renesas-ra/ra/ra_gpio.c new file mode 100644 index 000000000..598546cb9 --- /dev/null +++ b/ports/renesas-ra/ra/ra_gpio.c @@ -0,0 +1,176 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_gpio.h" + +void ra_gpio_config(uint32_t pin, uint32_t mode, uint32_t pull, uint32_t drive, uint32_t alt) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + pwpr_unprotect(); + switch (mode) { + case GPIO_MODE_INPUT: + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO + _PXXPFS(port, bit) &= ~PDR_MASK; // input + if (pull != 0) { + _PXXPFS(port, bit) |= PCR_MASK; // set pullup + } else { + _PXXPFS(port, bit) &= ~PCR_MASK; // clear pullup + } + break; + case GPIO_MODE_OUTPUT_PP: + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO + _PXXPFS(port, bit) |= PDR_MASK; // output + _PXXPFS(port, bit) &= ~PCR_MASK; // pullup clear + break; + case GPIO_MODE_OUTPUT_OD: + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO + _PXXPFS(port, bit) |= (PDR_MASK | NCODR_MASK); + break; + case GPIO_MODE_AF_PP: + _PXXPFS(port, bit) |= (PMR_MASK | PDR_MASK); + break; + case GPIO_MODE_AF_OD: + _PXXPFS(port, bit) |= (PMR_MASK | PDR_MASK | NCODR_MASK); + break; + } + switch (drive) { + case GPIO_HIGH_POWER: + _PXXPFS(port, bit) |= (DSCR1_MASK | DSCR_MASK); + break; + case GPIO_MED_POWER: + _PXXPFS(port, bit) &= ~DSCR1_MASK; + _PXXPFS(port, bit) |= DSCR_MASK; + break; + case GPIO_LOW_POWER: + _PXXPFS(port, bit) &= ~(DSCR1_MASK | DSCR_MASK); + break; + default: /* GPIO_NOTOUCH_POWER */ + /* do not modify */ + break; + } + _PXXPFS(port, bit) &= ~(uint32_t)(0x1f000000); + if (alt != 0) { + _PXXPFS(port, bit) |= (alt << 24); // Must set PSEL when PMR is 0 + _PXXPFS(port, bit) |= PMR_MASK; + } + pwpr_protect(); +} + +void ra_gpio_mode_output(uint32_t pin) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + pwpr_unprotect(); + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK | PCR_MASK); // GPIO + _PXXPFS(port, bit) |= PDR_MASK; // output + pwpr_protect(); +} + +void ra_gpio_mode_input(uint32_t pin) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + pwpr_unprotect(); + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO + _PXXPFS(port, bit) &= ~PDR_MASK; // input + pwpr_protect(); +} + +void ra_gpio_toggle(uint32_t pin) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + pwpr_unprotect(); + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO + _PXXPFS(port, bit) ^= 1; + pwpr_protect(); +} + +void ra_gpio_write(uint32_t pin, uint32_t value) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + pwpr_unprotect(); + _PXXPFS(port, bit) &= ~(PMR_MASK | ASEL_MASK); // GPIO + if (value != 0) { + _PXXPFS(port, bit) |= 1; + } else { + _PXXPFS(port, bit) &= ~(uint32_t)1; + } + pwpr_protect(); +} + +uint32_t ra_gpio_read(uint32_t pin) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + return ((_PXXPFS(port, bit) &= PIDR_MASK) != 0) ? 1 : 0; +} + +uint32_t ra_gpio_get_mode(uint32_t pin) { + uint8_t mode = 0; + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + if ((_PXXPFS(port, bit) &= PDR_MASK) != 0) { + mode = GPIO_MODE_OUTPUT_PP; + } else { + mode = GPIO_MODE_INPUT; + } + return mode; +} + +uint32_t ra_gpio_get_pull(uint32_t pin) { + uint8_t pull = 0; + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + if ((_PXXPFS(port, bit) &= PCR_MASK) != 0) { + pull = GPIO_PULLUP; + } else { + pull = GPIO_NOPULL; + } + return pull; +} + +uint32_t ra_gpio_get_af(uint32_t pin) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + return (_PXXPFS(port, bit) &= PMR_MASK) != 0; +} + +uint32_t ra_gpio_get_drive(uint32_t pin) { + uint8_t drive = 0; + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + switch (_PXXPFS(port, bit) &= (DSCR1_MASK | DSCR_MASK)) { + case (DSCR1_MASK | DSCR_MASK): + drive = GPIO_HIGH_POWER; + break; + case DSCR_MASK: + drive = GPIO_MED_POWER; + break; + case 0: + default: + drive = GPIO_LOW_POWER; + break; + } + return drive; +} diff --git a/ports/renesas-ra/ra/ra_gpio.h b/ports/renesas-ra/ra/ra_gpio.h new file mode 100644 index 000000000..7b7601663 --- /dev/null +++ b/ports/renesas-ra/ra/ra_gpio.h @@ -0,0 +1,187 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_GPIO_H_ +#define RA_RA_GPIO_H_ + +// clang-format off + +#include <stdint.h> + +typedef struct ra_af_pin { + uint8_t af; + uint8_t ch; + uint32_t pin; +} ra_af_pin_t; + +enum CPU_PIN { + P000 = 0x00, P001, P002, P003, P004, P005, P006, P007, P008, P009, P010, P011, P012, P013, P014, P015, + P100 = 0x10, P101, P102, P103, P104, P105, P106, P107, P108, P109, P110, P111, P112, P113, P114, P115, + P200 = 0x20, P201, P202, P203, P204, P205, P206, P207, P208, P209, P210, P211, P212, P213, P214, P215, + P300 = 0x30, P301, P302, P303, P304, P305, P306, P307, P308, P309, P310, P311, P312, P313, P314, P315, + P400 = 0x40, P401, P402, P403, P404, P405, P406, P407, P408, P409, P410, P411, P412, P413, P414, P415, + P500 = 0x50, P501, P502, P503, P504, P505, P506, P507, P508, P509, P510, P511, P512, P513, P514, P515, + P600 = 0x90, P601, P602, P603, P604, P605, P606, P607, P608, P609, P610, P611, P612, P613, P614, P615, + P700 = 0x70, P701, P702, P703, P704, P705, P706, P707, P708, P709, P710, P711, P712, P713, P714, P715, + P800 = 0x80, P801, P802, P803, P804, P805, P806, P807, P808, P809, P810, P811, P812, P813, P814, P815, + P900 = 0x90, P901, P902, P903, P904, P905, P906, P907, P908, P909, P910, P911, P912, P913, P914, P915, + PIN_END = 0xff, +}; + +enum AF_INDEX { + AF_GPIO = 0, + AF_AGT = 1, + AF_GPT1 = 2, + AF_GPT2 = 3, + AF_SCI1 = 4, + AF_SCI2 = 5, + AF_SPI = 6, + AF_I2C = 7, + AF_KINT = 8, + AF_RTC = 9, + AF_CAC = 10, + AF_CTSU = 12, + AF_SLCDC = 13, + AF_CAN = 16, + AF_SSIE = 18, + AF_USBFS = 19, + AF_END = 0xff, +}; + +#define GPIO_MODE_INPUT 1 +#define GPIO_MODE_OUTPUT_PP 2 +#define GPIO_MODE_OUTPUT_OD 3 +#define GPIO_MODE_AF_PP 4 +#define GPIO_MODE_AF_OD 5 +#define GPIO_MODE_ANALOG 6 +#define GPIO_MODE_IT_RISING 7 +#define GPIO_MODE_IT_FALLING 8 +#define GPIO_MODE_IT_RISING_FALLING 9 +#define GPIO_MODE_EVT_RISING 10 +#define GPIO_MODE_EVT_FALLING 11 +#define GPIO_MODE_EVT_RISING_FALLING 12 +#define GPIO_NOPULL 13 +#define GPIO_PULLUP 14 +#define GPIO_PULLDOWN 15 +#define GPIO_PULLHOLD 16 +#define GPIO_LOW_POWER 17 +#define GPIO_MED_POWER 18 +#define GPIO_HIGH_POWER 19 +#define GPIO_NOTOUCH_POWER 20 +#define GPIO_IRQ_LOWLEVEL 21 +#define GPIO_IRQ_HIGHLEVEL 22 + +#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT) || \ + ((MODE) == GPIO_MODE_OUTPUT_PP) || \ + ((MODE) == GPIO_MODE_OUTPUT_OD) || \ + ((MODE) == GPIO_MODE_AF_PP) || \ + ((MODE) == GPIO_MODE_AF_OD) || \ + ((MODE) == GPIO_MODE_IT_RISING) || \ + ((MODE) == GPIO_MODE_IT_FALLING) || \ + ((MODE) == GPIO_MODE_IT_RISING_FALLING) || \ + ((MODE) == GPIO_MODE_EVT_RISING) || \ + ((MODE) == GPIO_MODE_EVT_FALLING) || \ + ((MODE) == GPIO_MODE_EVT_RISING_FALLING) || \ + ((MODE) == GPIO_MODE_ANALOG)) + +#define IS_GPIO_DRIVE(DRIVE) (((DRIVE) == GPIO_LOW_POWER) || \ + ((DRIVE) == GPIO_MED_POWER) || \ + ((DRIVE) == GPIO_HIGH_POWER)) + +#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP)) + +#define IS_GPIO_AF(AF) ((AF) <= (uint8_t)0x1F) + +#define GPIO_PORT(pin) ((pin) >> 4) +#define GPIO_MASK(pin) (1 << ((pin) & 0xf)) +#define GPIO_BIT(pin) ((pin) & 0xf) + +#define PODR_MASK (uint32_t)0x00000001 +#define PIDR_MASK (uint32_t)0x00000002 +#define PDR_MASK (uint32_t)0x00000004 +#define PCR_MASK (uint32_t)0x00000010 +#define NCODR_MASK (uint32_t)0x00000040 +#define DSCR_MASK (uint32_t)0x00000400 +#define DSCR1_MASK (uint32_t)0x00000800 +#define EOR_MASK (uint32_t)0x00001000 +#define EOF_MASK (uint32_t)0x00002000 +#define ISEL_MASK (uint32_t)0x00004000 +#define ASEL_MASK (uint32_t)0x00008000 +#define PMR_MASK (uint32_t)0x00010000 +#define PSEL_MASK (uint32_t)0x1f000000 + +#define _PWPR (*(volatile uint8_t *)(0x40040D03)) + +#define _PXXPFS(port, bit) (*(volatile uint32_t *)(0x40040800 + (0x40 * ((uint32_t)port)) + (0x4 * ((uint32_t)bit)))) +#define _PCNTR1(port) (*(volatile uint32_t *)(0x40040000 + (0x20 * (port)))) +#define _PODR(port) (*(volatile uint16_t *)(0x40040000 + (0x20 * (port)))) +#define _PDR(port) (*(volatile uint16_t *)(0x40040002 + (0x20 * (port)))) +#define _PCNTR2(port) (*(volatile uint32_t *)(0x40040004 + (0x20 * (port)))) +#define _EIDR(port) (*(volatile uint16_t *)(0x40040004 + (0x20 * (port)))) +#define _PIDR(port) (*(volatile uint16_t *)(0x40040006 + (0x20 * (port)))) +#define _PCNTR3(port) (*(volatile uint32_t *)(0x40040008 + (0x20 * (port)))) +#define _PORR(port) (*(volatile uint16_t *)(0x40040008 + (0x20 * (port)))) +#define _POSR(port) (*(volatile uint16_t *)(0x4004000a + (0x20 * (port)))) +#define _PCNTR4(port) (*(volatile uint32_t *)(0x4004000c + (0x20 * (port)))) +#define _EORR(port) (*(volatile uint16_t *)(0x4004000c + (0x20 * (port)))) +#define _EOSR(port) (*(volatile uint16_t *)(0x4004000e + (0x20 * (port)))) + +#define _PPXXPFS(port, bit) ((volatile uint32_t *)(0x40040800 + (0x40 * (port)) + (0x4 * (bit)))) +#define _PPCNTR1(port) ((volatile uint32_t *)(0x40040000 + (0x20 * (port)))) +#define _PPODR(port) ((volatile uint16_t *)(0x40040000 + (0x20 * (port)))) +#define _PPDR(port) ((volatile uint16_t *)(0x40040002 + (0x20 * (port)))) +#define _PPCNTR2(port) ((volatile uint32_t *)(0x40040004 + (0x20 * (port)))) +#define _PEIDR(port) ((volatile uint16_t *)(0x40040004 + (0x20 * (port)))) +#define _PPIDR(port) ((volatile uint16_t *)(0x40040006 + (0x20 * (port)))) +#define _PPCNTR3(port) ((volatile uint32_t *)(0x40040008 + (0x20 * (port)))) +#define _PPORR(port) ((volatile uint16_t *)(0x40040008 + (0x20 * (port)))) +#define _PPOSR(port) ((volatile uint16_t *)(0x4004000a + (0x20 * (port)))) +#define _PPCNTR4(port) ((volatile uint32_t *)(0x4004000c + (0x20 * (port)))) +#define _PEORR(port) ((volatile uint16_t *)(0x4004000c + (0x20 * (port)))) +#define _PEOSR(port) ((volatile uint16_t *)(0x4004000e + (0x20 * (port)))) + +void ra_gpio_config(uint32_t pin, uint32_t mode, uint32_t pull, uint32_t drive, uint32_t alt); +void ra_gpio_mode_output(uint32_t pin); +void ra_gpio_mode_input(uint32_t pin); +void ra_gpio_set(uint32_t pin, uint32_t value); +uint32_t ra_gpio_get(uint32_t pin); +void ra_gpio_toggle(uint32_t pin); +void ra_gpio_write(uint32_t pin, uint32_t value); +uint32_t ra_gpio_read(uint32_t pin); +uint32_t ra_gpio_get_mode(uint32_t pin); +uint32_t ra_gpio_get_pull(uint32_t pin); +uint32_t ra_gpio_get_af(uint32_t pin); +uint32_t ra_gpio_get_drive(uint32_t pin); + +inline static void pwpr_unprotect(void) { + _PWPR &= (uint8_t) ~0x80; + _PWPR |= (uint8_t)0x40; +} + +inline static void pwpr_protect(void) { + _PWPR &= (uint8_t) ~0x40; + _PWPR |= (uint8_t)0x80; +} + +#endif /* RA_RA_GPIO_H_ */ diff --git a/ports/renesas-ra/ra/ra_i2c.c b/ports/renesas-ra/ra/ra_i2c.c new file mode 100644 index 000000000..64bbd6f50 --- /dev/null +++ b/ports/renesas-ra/ra/ra_i2c.c @@ -0,0 +1,603 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_gpio.h" +#include "ra_icu.h" +#include "ra_int.h" +#include "ra_timer.h" +#include "ra_utils.h" +#include "ra_i2c.h" + +#if !defined(RA_PRI_I2C) +#define RA_PRI_I2C (8) +#endif + +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wimplicit-function-declaration" +#pragma GCC diagnostic ignored "-Wunused-variable" +#endif + +extern volatile uint32_t uwTick; + +static const ra_af_pin_t scl_pins[] = { + #if defined(RA4M1) + + { AF_I2C, 0, P204 }, + { AF_I2C, 0, P400 }, + { AF_I2C, 0, P408 }, + { AF_I2C, 1, P100 }, + { AF_I2C, 1, P205 }, + + #elif defined(RA4W1) + + { AF_I2C, 0, P204 }, + { AF_I2C, 1, P100 }, + { AF_I2C, 1, P205 }, + + #elif defined(RA6M1) + + { AF_I2C, 0, P400 }, + { AF_I2C, 0, P408 }, + { AF_I2C, 1, P100 }, + { AF_I2C, 1, P205 }, + + #elif defined(RA6M2) + + { AF_I2C, 0, P204 }, + { AF_I2C, 0, P400 }, + { AF_I2C, 0, P408 }, + { AF_I2C, 1, P100 }, + { AF_I2C, 1, P205 }, + { AF_I2C, 2, P512 }, + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define SCL_PINS_SIZE sizeof(scl_pins) / sizeof(ra_af_pin_t) + +static const ra_af_pin_t sda_pins[] = { + #if defined(RA4M1) + + { AF_I2C, 0, P401 }, + { AF_I2C, 0, P407 }, + { AF_I2C, 1, P101 }, + { AF_I2C, 1, P206 }, + + #elif defined(RA4W1) + + { AF_I2C, 0, P407 }, + { AF_I2C, 1, P101 }, + { AF_I2C, 1, P206 }, + + #elif defined(RA6M1) + + { AF_I2C, 0, P401 }, + { AF_I2C, 0, P407 }, + { AF_I2C, 1, P101 }, + { AF_I2C, 1, P206 }, + + #elif defined(RA6M2) + + { AF_I2C, 0, P401 }, + { AF_I2C, 0, P407 }, + { AF_I2C, 1, P101 }, + { AF_I2C, 1, P206 }, + { AF_I2C, 2, P511 }, + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define SDA_PINS_SIZE sizeof(sda_pins) / sizeof(ra_af_pin_t) + +static const uint8_t ra_i2c_ch_to_rxirq[] = { + #if defined(VECTOR_NUMBER_IIC0_RXI) + VECTOR_NUMBER_IIC0_RXI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC1_RXI) + VECTOR_NUMBER_IIC1_RXI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC2_RXI) + VECTOR_NUMBER_IIC2_RXI, + #else + VECTOR_NUMBER_NONE, + #endif +}; +static const uint8_t ra_i2c_ch_to_txirq[] = { + #if defined(VECTOR_NUMBER_IIC0_TXI) + VECTOR_NUMBER_IIC0_TXI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC1_TXI) + VECTOR_NUMBER_IIC1_TXI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC2_TXI) + VECTOR_NUMBER_IIC2_TXI, + #else + VECTOR_NUMBER_NONE, + #endif +}; +static const uint8_t ra_i2c_ch_to_teirq[] = { + #if defined(VECTOR_NUMBER_IIC0_TEI) + VECTOR_NUMBER_IIC0_TEI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC1_TEI) + VECTOR_NUMBER_IIC1_TEI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC2_TEI) + VECTOR_NUMBER_IIC2_TEI, + #else + VECTOR_NUMBER_NONE, + #endif +}; +static const uint8_t ra_i2c_ch_to_erirq[] = { + #if defined(VECTOR_NUMBER_IIC0_ERI) + VECTOR_NUMBER_IIC0_ERI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC1_ERI) + VECTOR_NUMBER_IIC1_ERI, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_IIC2_ERI) + VECTOR_NUMBER_IIC2_ERI, + #else + VECTOR_NUMBER_NONE, + #endif +}; + +static xaction_t *current_xaction; +static xaction_unit_t *current_xaction_unit; +static bool last_stop; +static uint8_t pclk_div[8] = { + 1, 2, 4, 8, 16, 32, 64, 128 +}; + +static uint32_t R_IIC0_Type_to_ch(R_IIC0_Type *i2c_inst) { + if (i2c_inst == R_IIC2) { + return 2; /* channel 2 */ + } else if (i2c_inst == R_IIC1) { + return 1; /* channel 1 */ + } else { + return 0; /* channel 0 */ + } +} + +static R_IIC0_Type *ch_to_R_IIC0_Type(uint32_t ch) { + if (ch == 2) { + return R_IIC2; + } else if (ch == 1) { + return R_IIC1; + } else { + return R_IIC0; + } +} + +bool ra_i2c_find_af_ch(uint32_t scl, uint32_t sda, uint8_t *ch) { + bool find = false; + uint8_t scl_ch; + uint8_t sda_ch; + find = ra_af_find_ch((ra_af_pin_t *)&scl_pins, SCL_PINS_SIZE, scl, &scl_ch); + if (find) { + find = ra_af_find_ch((ra_af_pin_t *)&sda_pins, SDA_PINS_SIZE, sda, &sda_ch); + if (find) { + find = (scl_ch == sda_ch); + if (find) { + *ch = scl_ch; + } else { + *ch = 0; + } + } + } + return find; +} + +static void ra_i2c_module_start(R_IIC0_Type *i2c_inst) { + if (i2c_inst == R_IIC0) { + ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB9_Msk); + } else if (i2c_inst == R_IIC1) { + ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB8_Msk); + } else if (i2c_inst == R_IIC2) { + ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB7_Msk); + } +} + +static void ra_i2c_module_stop(R_IIC0_Type *i2c_inst) { + if (i2c_inst == R_IIC0) { + ra_mstpcrb_stop(R_MSTP_MSTPCRB_MSTPB9_Msk); + } else if (i2c_inst == R_IIC1) { + ra_mstpcrb_stop(R_MSTP_MSTPCRB_MSTPB8_Msk); + } else if (i2c_inst == R_IIC2) { + ra_mstpcrb_stop(R_MSTP_MSTPCRB_MSTPB7_Msk); + } +} + +void ra_i2c_irq_enable(R_IIC0_Type *i2c_inst) { + uint32_t ch = R_IIC0_Type_to_ch(i2c_inst); + R_BSP_IrqEnable((IRQn_Type const)ra_i2c_ch_to_rxirq[ch]); + R_BSP_IrqEnable((IRQn_Type const)ra_i2c_ch_to_txirq[ch]); + R_BSP_IrqEnable((IRQn_Type const)ra_i2c_ch_to_teirq[ch]); + R_BSP_IrqEnable((IRQn_Type const)ra_i2c_ch_to_erirq[ch]); +} + +void ra_i2c_irq_disable(R_IIC0_Type *i2c_inst) { + uint32_t ch = R_IIC0_Type_to_ch(i2c_inst); + R_BSP_IrqDisable((IRQn_Type const)ra_i2c_ch_to_rxirq[ch]); + R_BSP_IrqDisable((IRQn_Type const)ra_i2c_ch_to_txirq[ch]); + R_BSP_IrqDisable((IRQn_Type const)ra_i2c_ch_to_teirq[ch]); + R_BSP_IrqDisable((IRQn_Type const)ra_i2c_ch_to_erirq[ch]); +} + +void ra_i2c_priority(R_IIC0_Type *i2c_inst, uint32_t ipl) { + uint32_t ch = R_IIC0_Type_to_ch(i2c_inst); + R_BSP_IrqCfg((IRQn_Type const)ra_i2c_ch_to_rxirq[ch], ipl, (void *)NULL); + R_BSP_IrqCfg((IRQn_Type const)ra_i2c_ch_to_txirq[ch], ipl, (void *)NULL); + R_BSP_IrqCfg((IRQn_Type const)ra_i2c_ch_to_teirq[ch], ipl, (void *)NULL); + R_BSP_IrqCfg((IRQn_Type const)ra_i2c_ch_to_erirq[ch], ipl, (void *)NULL); +} + +void ra_i2c_clear_IR(R_IIC0_Type *i2c_inst) { + uint32_t ch = R_IIC0_Type_to_ch(i2c_inst); + R_BSP_IrqStatusClear((IRQn_Type const)ra_i2c_ch_to_rxirq[ch]); + R_BSP_IrqStatusClear((IRQn_Type const)ra_i2c_ch_to_txirq[ch]); + R_BSP_IrqStatusClear((IRQn_Type const)ra_i2c_ch_to_teirq[ch]); + R_BSP_IrqStatusClear((IRQn_Type const)ra_i2c_ch_to_erirq[ch]); +} + +// ToDo: need to properly implement +static void ra_i2c_clock_calc(uint32_t baudrate, uint8_t *cks, uint8_t *brh, uint8_t *brl); +static void ra_i2c_clock_calc(uint32_t baudrate, uint8_t *cks, uint8_t *brh, uint8_t *brl) { + #if defined(RA4M1) + if (baudrate >= 400000) { + // assume clock is 400000Hz (PCLKB 32MHz) + *cks = 1; + *brh = 9; + *brl = 20; + } else { + // assume clock is 100000Hz (PCLKB 32MHz) + *cks = 3; + *brh = 15; + *brl = 18; + } + #elif defined(RA4W1) + if (baudrate >= 400000) { + // assume clock is 400000Hz (PCLKB 32MHz) + *cks = 1; + *brh = 9; + *brl = 20; + } else { + // assume clock is 100000Hz (PCLKB 32MHz) + *cks = 3; + *brh = 15; + *brl = 18; + } + #elif defined(RA6M1) + // PCLKB 60MHz SCLE=0 + if (baudrate >= 1000000) { + *cks = 0; + *brh = 15; + *brl = 29; + } else if (baudrate >= 400000) { + // assume clock is 400000Hz (PCLKB 32MHz) + *cks = 2; + *brh = 8; + *brl = 19; + } else { + // assume clock is 100000Hz (PCLKB 32MHz) + *cks = 4; + *brh = 14; + *brl = 17; + } + #elif defined(RA6M2) + // PCLKB 60MHz SCLE=0 + if (baudrate >= RA_I2C_CLOCK_MAX) { + *cks = 0; + *brh = 15; + *brl = 29; + } else if (baudrate >= 400000) { + // assume clock is 400000Hz + *cks = 2; + *brh = 8; + *brl = 19; + } else { + // assume clock is 100000Hz + *cks = 4; + *brh = 14; + *brl = 17; + } + #else + #error "CMSIS MCU Series is not specified." + #endif +} + +void ra_i2c_set_baudrate(R_IIC0_Type *i2c_inst, uint32_t baudrate) { + uint8_t cks; + uint8_t brh; + uint8_t brl; + ra_i2c_clock_calc(baudrate, &cks, &brh, &brl); + i2c_inst->ICMR1_b.CKS = cks; + i2c_inst->ICBRH_b.BRH = brh; + i2c_inst->ICBRL_b.BRL = brl; +} + +void ra_i2c_init(R_IIC0_Type *i2c_inst, uint32_t scl, uint32_t sda, uint32_t baudrate) { + ra_i2c_module_start(i2c_inst); + ra_gpio_config(scl, GPIO_MODE_AF_OD, 0, GPIO_NOTOUCH_POWER, AF_I2C); + ra_gpio_config(sda, GPIO_MODE_AF_OD, 0, GPIO_NOTOUCH_POWER, AF_I2C); + ra_i2c_priority(i2c_inst, RA_PRI_I2C); + i2c_inst->ICCR1_b.ICE = 0; // I2C disable + i2c_inst->ICCR1_b.IICRST = 1; // I2C internal reset + i2c_inst->ICIER = 0x00; // I2C disable all interrupts + while (i2c_inst->ICIER != 0) { + ; + } + ra_i2c_clear_IR(i2c_inst); // clear IR + i2c_inst->ICCR1_b.ICE = 1; // I2C enable + ra_i2c_set_baudrate(i2c_inst, baudrate); + i2c_inst->ICSER = 0x00; // I2C reset bus status enable register + i2c_inst->ICMR3_b.ACKWP = 0x01; // I2C allow to write ACKBT (transfer acknowledge bit) + i2c_inst->ICIER = 0xFF; // Enable all interrupts + i2c_inst->ICCR1_b.IICRST = 0; // I2C internal reset + ra_i2c_irq_enable(i2c_inst); + last_stop = true; + return; +} + +void ra_i2c_deinit(R_IIC0_Type *i2c_inst) { + i2c_inst->ICIER = 0; // I2C interrupt disable + i2c_inst->ICCR1_b.ICE = 0; // I2C disable + ra_i2c_module_stop(i2c_inst); + return; +} + +void ra_i2c_xaction_start(R_IIC0_Type *i2c_inst, xaction_t *action, bool repeated_start) { + uint32_t timeout; + + if (last_stop == false) { + i2c_inst->ICSR2_b.START = 0; + i2c_inst->ICCR2_b.RS = 1; + return; /* We still keep I2C bus */ + } + timeout = RA_I2C_TIMEOUT_BUS_BUSY; + while (i2c_inst->ICCR2_b.BBSY) { + if (timeout-- == 0) { + action->m_status = RA_I2C_STATUS_Stopped; + action->m_error = RA_I2C_ERROR_BUSY; + return; + } + } + i2c_inst->ICCR2_b.ST = 1; // I2C start condition +} + +void ra_i2c_xaction_stop() { + last_stop = current_xaction->m_stop; +} + +void ra_i2c_xunit_write_byte(R_IIC0_Type *i2c_inst, xaction_unit_t *unit) { + i2c_inst->ICDRT = unit->buf[unit->m_bytes_transferred]; + ++unit->m_bytes_transferred; + --unit->m_bytes_transfer; +} + +void ra_i2c_xunit_read_byte(R_IIC0_Type *i2c_inst, xaction_unit_t *unit) { + uint8_t data = i2c_inst->ICDRR; + unit->buf[unit->m_bytes_transferred] = data; + ++unit->m_bytes_transferred; + --unit->m_bytes_transfer; +} + +void ra_i2c_xunit_init(xaction_unit_t *unit, uint8_t *buf, uint32_t size, bool fread, void *next) { + unit->m_bytes_transferred = 0; + unit->m_bytes_transfer = size; + unit->m_fread = fread; + unit->buf = buf; + unit->next = (void *)next; +} + +void ra_i2c_xaction_init(xaction_t *action, xaction_unit_t *units, uint32_t size, uint32_t address, bool stop) { + action->units = units; + action->m_num_of_units = size; + action->m_current = 0; + action->m_address = (((address << 1) & 0xFE) | (units->m_fread ? 0x1 : 0x0)); + action->m_status = RA_I2C_STATUS_Idle; + action->m_error = RA_I2C_ERROR_OK; + action->m_stop = stop; +} + +static void ra_i2c_iceri_isr(R_IIC0_Type *i2c_inst) { + xaction_t *action = current_xaction; + if (i2c_inst->ICSR2_b.TMOF != 0) { + action->m_error = RA_I2C_ERROR_TMOF; + i2c_inst->ICSR2_b.TMOF = 0; + i2c_inst->ICCR2_b.SP = 1; // request stop condition + } + if (i2c_inst->ICSR2_b.AL != 0) { + action->m_error = RA_I2C_ERROR_AL; + i2c_inst->ICSR2_b.AL = 0; + i2c_inst->ICCR2_b.SP = 1; // request stop condition + } + // Check Start + if (i2c_inst->ICSR2_b.START != 0) { + action->m_status = RA_I2C_STATUS_Started; + i2c_inst->ICSR2_b.START = 0; + } + // Check Stop + if (i2c_inst->ICSR2_b.STOP != 0) { + action->m_status = RA_I2C_STATUS_Stopped; + i2c_inst->ICSR2_b.STOP = 0; + i2c_inst->ICSR2_b.NACKF = 0; // clear for next transaction + } + // Check NACK reception + if (i2c_inst->ICSR2_b.NACKF != 0) { + action->m_error = RA_I2C_ERROR_NACK; + i2c_inst->ICSR2_b.NACKF = 0; + i2c_inst->ICCR2_b.SP = 1; // request stop condition + } +} + +static void ra_i2c_icrxi_isr(R_IIC0_Type *i2c_inst) { + xaction_unit_t *unit = current_xaction_unit; + xaction_t *action = current_xaction; + if (action->m_status == RA_I2C_STATUS_AddrWriteCompleted) { + (void)i2c_inst->ICDRR; // dummy read + action->m_status = RA_I2C_STATUS_FirstReceiveCompleted; + return; + } + if (unit->m_bytes_transfer > 2) { + if (unit->m_bytes_transfer == 3) { + i2c_inst->ICMR3_b.WAIT = 1; + } + ra_i2c_xunit_read_byte(i2c_inst, unit); + } else if (unit->m_bytes_transfer == 2) { + i2c_inst->ICMR3_b.ACKBT = 1; + ra_i2c_xunit_read_byte(i2c_inst, unit); + } else { + // last data + action->m_status = RA_I2C_STATUS_LastReceiveCompleted; + if (action->m_stop == true) { + i2c_inst->ICCR2_b.SP = 1; // request top condition + } + ra_i2c_xunit_read_byte(i2c_inst, unit); + } +} + +static void ra_i2c_ictxi_isr(R_IIC0_Type *i2c_inst) { + xaction_t *action = current_xaction; + xaction_unit_t *unit = current_xaction_unit; + + if (action->m_status == RA_I2C_STATUS_Started) { + i2c_inst->ICDRT = action->m_address; // I2C send slave address + action->m_status = RA_I2C_STATUS_AddrWriteCompleted; + return; + } + if (action->m_status == RA_I2C_STATUS_AddrWriteCompleted && + unit->m_fread == false) { + if (unit->m_bytes_transfer != 0) { + ra_i2c_xunit_write_byte(i2c_inst, unit); + } else { + if (unit->next == (void *)NULL) { + action->m_status = RA_I2C_STATUS_DataWriteCompleted; + } else { + current_xaction_unit = (xaction_unit_t *)unit->next; + if (current_xaction_unit->m_bytes_transfer == 0) { + action->m_status = RA_I2C_STATUS_DataWriteCompleted; + } + } + } + return; + } +} + +static void ra_i2c_ictei_isr(R_IIC0_Type *i2c_inst) { + xaction_t *action = current_xaction; + i2c_inst->ICSR2_b.TEND = 0; + action->m_current++; + if (action->m_current == action->m_num_of_units) { + // We wrote all data and received transfer end, so request stop condition + if (action->m_stop == true) { + action->m_status = RA_I2C_STATUS_DataSendCompleted; + i2c_inst->ICCR2_b.SP = 1; + } else { + action->m_status = RA_I2C_STATUS_Stopped; // set Stopped status insted STOP condition + } + } else { + ra_i2c_xaction_start(i2c_inst, action, true); + } +} + +void iic_master_rxi_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint8_t ch = irq_to_ch[(uint32_t)irq]; + ra_i2c_icrxi_isr(ch_to_R_IIC0_Type(ch)); + R_BSP_IrqStatusClear(irq); +} + +void iic_master_txi_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint8_t ch = irq_to_ch[(uint32_t)irq]; + ra_i2c_ictxi_isr(ch_to_R_IIC0_Type(ch)); + R_BSP_IrqStatusClear(irq); +} + +void iic_master_tei_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint8_t ch = irq_to_ch[(uint32_t)irq]; + ra_i2c_ictei_isr(ch_to_R_IIC0_Type(ch)); + R_BSP_IrqStatusClear(irq); +} + +void iic_master_eri_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint8_t ch = irq_to_ch[(uint32_t)irq]; + ra_i2c_iceri_isr(ch_to_R_IIC0_Type(ch)); + R_BSP_IrqStatusClear(irq); +} + +bool ra_i2c_action_execute(R_IIC0_Type *i2c_inst, xaction_t *action, bool repeated_start, uint32_t timeout_ms) { + bool flag = false; + uint32_t start = uwTick; + + current_xaction = action; + current_xaction_unit = action->units; + + ra_i2c_xaction_start(i2c_inst, action, repeated_start); + while (true) { + if (action->m_status == RA_I2C_STATUS_Stopped) { + if (action->m_error == RA_I2C_ERROR_OK) { + flag = true; + } + break; + } + if (uwTick - start > timeout_ms) { + break; + } + } + ra_i2c_xaction_stop(); + if (last_stop == true) { + mp_hal_delay_ms(3); // avoid device busy of next access. + } + current_xaction = (xaction_t *)NULL; + current_xaction_unit = (xaction_unit_t *)NULL; + + return flag; +} diff --git a/ports/renesas-ra/ra/ra_i2c.h b/ports/renesas-ra/ra/ra_i2c.h new file mode 100644 index 000000000..93a170ab8 --- /dev/null +++ b/ports/renesas-ra/ra/ra_i2c.h @@ -0,0 +1,99 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_I2C_H_ +#define RA_RA_I2C_H_ + +#include <stdint.h> +#include <stdbool.h> + +#define RA_I2C_DEF_TIMEOUT 1000 // 1000 ms +#define RA_I2C_TIMEOUT_STOP_CONDITION 100000 // counts +#define RA_I2C_TIMEOUT_BUS_BUSY 100000 // counts +#define RA_I2C_CLOCK_MAX 1000000 // counts + +typedef enum +{ + RA_I2C_STATUS_Idle = 1, + RA_I2C_STATUS_Started = 2, + RA_I2C_STATUS_AddrWriteCompleted = 3, + RA_I2C_STATUS_DataWriteCompleted = 4, + RA_I2C_STATUS_DataSendCompleted = 5, + RA_I2C_STATUS_FirstReceiveCompleted = 5, + RA_I2C_STATUS_LastReceiveCompleted = 6, + RA_I2C_STATUS_Stopped = 7, +} xaction_status_t; + +typedef enum +{ + RA_I2C_ERROR_OK = 0, + RA_I2C_ERROR_TMOF = 1, + RA_I2C_ERROR_AL = 2, + RA_I2C_ERROR_NACK = 3, + RA_I2C_ERROR_BUSY = 4, +} xaction_error_t; + +typedef struct { + volatile uint32_t m_bytes_transferred; + volatile uint32_t m_bytes_transfer; + bool m_fread; + uint8_t *buf; + void *next; +} xaction_unit_t; + +typedef struct { + xaction_unit_t *units; + uint32_t m_num_of_units; + uint32_t m_current; + uint32_t m_address; + volatile xaction_status_t m_status; + xaction_error_t m_error; + bool m_stop; +} xaction_t; + +bool ra_i2c_find_af_ch(uint32_t scl, uint32_t sda, uint8_t *ch); +void ra_i2c_irq_enable(R_IIC0_Type *i2c_inst); +void ra_i2c_irq_disable(R_IIC0_Type *i2c_inst); +void ra_i2c_priority(R_IIC0_Type *i2c_inst, uint32_t ipl); +void ra_i2c_set_baudrate(R_IIC0_Type *i2c_inst, uint32_t baudrate); +void ra_i2c_clear_IR(R_IIC0_Type *i2c_inst); +void ra_i2c_init(R_IIC0_Type *i2c_inst, uint32_t scl, uint32_t sda, uint32_t baudrate); +void ra_i2c_deinit(R_IIC0_Type *i2c_inst); +void ra_i2c_read_last_byte(R_IIC0_Type *i2c_inst); +void ra_i2c_stop_condition(R_IIC0_Type *i2c_inst); +void ra_i2c_abort(R_IIC0_Type *i2c_inst); +void ra_i2c_xaction_start(R_IIC0_Type *i2c_inst, xaction_t *xaction, bool repeated_start); +void ra_i2c_xaction_stop(void); +void ra_i2c_get_clock(uint32_t rateKhz, uint8_t *clockRate, uint8_t *clockRate2); +void ra_i2c_xunit_write_byte(R_IIC0_Type *i2c_inst, xaction_unit_t *unit); +void ra_i2c_xunit_read_byte(R_IIC0_Type *i2c_inst, xaction_unit_t *unit); +void ra_i2c_xunit_init(xaction_unit_t *unit, uint8_t *buf, uint32_t size, bool fread, void *next); +void ra_i2c_xaction_init(xaction_t *action, xaction_unit_t *units, uint32_t size, uint32_t address, bool stop); +void iic_master_rxi_isr(void); +void iic_master_txi_isr(void); +void iic_master_tei_isr(void); +void iic_master_eri_isr(void); +bool ra_i2c_action_execute(R_IIC0_Type *i2c_inst, xaction_t *action, bool repeated_start, uint32_t timeout_ms); + +#endif /* RA_RA_I2C_H_ */ diff --git a/ports/renesas-ra/ra/ra_icu.c b/ports/renesas-ra/ra/ra_icu.c new file mode 100644 index 000000000..000667b4c --- /dev/null +++ b/ports/renesas-ra/ra/ra_icu.c @@ -0,0 +1,750 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_gpio.h" +#include "ra_int.h" +#include "ra_timer.h" +#include "ra_icu.h" + +#define DEFAULT_BOUNCE_PERIOD (200) /* 200ms */ + +#if !defined(RA_PRI_EXTIT) +#define RA_PRI_EXTINT (14) +#endif + +static R_ICU_Type *icu_reg = (R_ICU_Type *)0x40006000; + +enum +{ + #if defined(VECTOR_NUMBER_ICU_IRQ0) + IRQ0_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + IRQ1_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + IRQ2_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + IRQ3_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + IRQ4_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + IRQ5_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + IRQ6_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + IRQ7_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + IRQ8_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + IRQ9_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + IRQ10_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + IRQ11_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + IRQ12_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + IRQ13_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + IRQ14_IDX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + IRQ15_IDX, + #endif + IRQ_IDX_MAX, +}; + +static const ra_icu_pin_t ra_irq_pins[] = { + #if defined(RA4W1) + + #if defined(VECTOR_NUMBER_ICU_IRQ0) + { 0, P105 }, + { 0, P206 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + { 1, P101 }, + { 1, P104 }, + { 1, P205 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + { 2, P100 }, + { 2, P213 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + { 3, P004 }, + { 3, P110 }, + { 3, P212 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + { 4, P111 }, + { 4, P402 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + { 6, P409 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + { 7, P015 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + { 9, P414 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + { 11, P501 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + { 14, P010 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + { 15, P011 }, + #endif + + #elif defined(RA4M1) + + #if defined(VECTOR_NUMBER_ICU_IRQ0) + { 0, P105 }, + { 0, P206 }, + { 0, P400 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + { 1, P101 }, + { 1, P104 }, + { 1, P205 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + { 2, P002 }, + { 2, P100 }, + { 2, P213 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + { 3, P004 }, + { 3, P110 }, + { 3, P212 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + { 4, P111 }, + { 4, P411 }, + { 4, P402 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + { 5, P302 }, + { 5, P410 }, + { 5, P401 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + { 6, P000 }, + { 6, P301 }, + { 6, P409 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + { 7, P001 }, + { 7, P015 }, + { 7, P408 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + { 8, P305 }, + { 8, P415 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + { 9, P304 }, + { 9, P414 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + { 10, P005 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + { 11, P501 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + { 12, P502 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + { 14, P505 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + { 15, P011 }, + #endif + + #elif defined(RA6M1) + + #if defined(VECTOR_NUMBER_ICU_IRQ0) + { 0, P105 }, + { 0, P206 }, /* DS */ + { 0, P400 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + { 1, P101 }, + { 1, P104 }, + { 1, P205 }, /* DS */ + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + { 2, P100 }, + { 2, P213 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + { 3, P110 }, + { 3, P212 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + { 4, P111 }, + { 4, P402 }, /* DS */ + { 4, P411 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + { 5, P302 }, + { 5, P401 }, /* DS */ + { 5, P410 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + { 6, P000 }, /* DS */ + { 6, P301 }, + { 6, P409 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + { 7, P001 }, /* DS */ + { 7, P408 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + { 8, P002 }, /* DS */ + { 8, P305 }, + { 8, P415 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + { 9, P004 }, /* DS */ + { 9, P304 }, + { 9, P414 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + { 10, P005 }, /* DS */ + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + { 11, P006 }, /* DS */ + { 11, P501 }, + { 11, P708 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + { 12, P008 }, /* DS */ + { 12, P502 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + { 13, P015 }, + #endif + + #elif defined(RA6M2) + + #if defined(VECTOR_NUMBER_ICU_IRQ0) + { 0, P105 }, + { 0, P206 }, /* DS */ + { 0, P400 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + { 1, P101 }, + { 1, P104 }, + { 1, P205 }, /* DS */ + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + { 2, P100 }, + { 2, P213 }, + { 2, P203 }, /* DS */ + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + { 3, P110 }, + { 3, P212 }, + { 3, P202 }, /* DS */ + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + { 4, P111 }, + { 4, P402 }, /* DS */ + { 4, P411 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + { 5, P302 }, + { 5, P401 }, /* DS */ + { 5, P410 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + { 6, P000 }, /* DS */ + { 6, P301 }, + { 6, P409 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + { 7, P001 }, /* DS */ + { 7, P408 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + { 8, P002 }, /* DS */ + { 8, P305 }, + { 8, P415 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + { 9, P004 }, /* DS */ + { 9, P304 }, + { 9, P414 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + { 10, P005 }, /* DS */ + { 10, P709 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + { 11, P006 }, /* DS */ + { 11, P501 }, + { 11, P708 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + { 12, P008 }, /* DS */ + { 12, P502 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + { 13, P009 }, /* DS */ + { 13, P015 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + { 14, P505 }, + { 14, P512 }, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + { 15, P506 }, + { 15, P511 }, + #endif + + #else + #error "CMSIS MCU Series is not speficied." + #endif +}; +#define ICU_PINS_SIZE (sizeof(ra_irq_pins) / sizeof(ra_icu_pin_t)) + +static const uint32_t idx_to_irq_vec[] = { + #if defined(VECTOR_NUMBER_ICU_IRQ0) + VECTOR_NUMBER_ICU_IRQ0, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + VECTOR_NUMBER_ICU_IRQ1, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + VECTOR_NUMBER_ICU_IRQ2, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + VECTOR_NUMBER_ICU_IRQ3, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + VECTOR_NUMBER_ICU_IRQ4, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + VECTOR_NUMBER_ICU_IRQ5, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + VECTOR_NUMBER_ICU_IRQ6, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + VECTOR_NUMBER_ICU_IRQ7, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + VECTOR_NUMBER_ICU_IRQ8, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + VECTOR_NUMBER_ICU_IRQ9, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + VECTOR_NUMBER_ICU_IRQ10, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + VECTOR_NUMBER_ICU_IRQ11, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + VECTOR_NUMBER_ICU_IRQ12, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + VECTOR_NUMBER_ICU_IRQ13, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + VECTOR_NUMBER_ICU_IRQ14, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + VECTOR_NUMBER_ICU_IRQ15, + #endif +}; + +static const uint8_t irq_no_to_idx[] = { + #if defined(VECTOR_NUMBER_ICU_IRQ0) + IRQ0_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + IRQ1_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + IRQ2_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + IRQ3_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + IRQ4_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + IRQ5_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + IRQ6_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + IRQ7_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + IRQ8_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + IRQ9_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + IRQ10_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + IRQ11_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + IRQ12_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + IRQ13_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + IRQ14_IDX, + #else + IRQ_IDX_MAX, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + IRQ15_IDX, + #else + IRQ_IDX_MAX, + #endif +}; + +static const uint8_t irq_no_to_irq_vec[] = { + #if defined(VECTOR_NUMBER_ICU_IRQ0) + VECTOR_NUMBER_ICU_IRQ0, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + VECTOR_NUMBER_ICU_IRQ1, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + VECTOR_NUMBER_ICU_IRQ2, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + VECTOR_NUMBER_ICU_IRQ3, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + VECTOR_NUMBER_ICU_IRQ4, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + VECTOR_NUMBER_ICU_IRQ5, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + VECTOR_NUMBER_ICU_IRQ6, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + VECTOR_NUMBER_ICU_IRQ7, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + VECTOR_NUMBER_ICU_IRQ8, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + VECTOR_NUMBER_ICU_IRQ9, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + VECTOR_NUMBER_ICU_IRQ10, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + VECTOR_NUMBER_ICU_IRQ11, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + VECTOR_NUMBER_ICU_IRQ12, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + VECTOR_NUMBER_ICU_IRQ13, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + VECTOR_NUMBER_ICU_IRQ14, + #else + VECTOR_NUMBER_NONE, + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + VECTOR_NUMBER_ICU_IRQ15, + #else + VECTOR_NUMBER_NONE, + #endif +}; +static ICU_CB icu_cbs[IRQ_IDX_MAX]; +static void *icu_params[IRQ_IDX_MAX]; +static bool bounce_flag[IRQ_IDX_MAX]; +static uint32_t bounce_period[IRQ_IDX_MAX]; +static uint32_t bounce_start[IRQ_IDX_MAX]; + +bool ra_icu_find_irq_no(uint32_t pin, uint8_t *irq_no) { + ra_icu_pin_t *icu_pin = (ra_icu_pin_t *)&ra_irq_pins; + uint32_t size = (uint32_t)ICU_PINS_SIZE; + bool find = false; + uint32_t i; + for (i = 0; i < size; i++) { + if (icu_pin->pin == pin) { + find = true; + *irq_no = icu_pin->irq_no; + break; + } + icu_pin++; + } + return find; +} + +static void ra_icu_irq_no(uint8_t irq_no, bool enable) { + uint8_t irq_vec = irq_no_to_irq_vec[irq_no]; + if (irq_vec != VECTOR_NUMBER_NONE) { + if (enable) { + R_BSP_IrqCfg((IRQn_Type const)irq_vec, (uint32_t)RA_PRI_EXTINT, (void *)NULL); + R_BSP_IrqEnable((IRQn_Type const)irq_vec); + } else { + R_BSP_IrqDisable((IRQn_Type const)irq_vec); + } + } +} + +void ra_icu_set_pin(uint32_t pin, bool irq_enable, bool pullup) { + uint32_t port = GPIO_PORT(pin); + uint32_t bit = GPIO_BIT(pin); + uint32_t pfs = _PXXPFS(port, bit); + pwpr_unprotect(); + pfs &= ~PMR_MASK; /* GPIO */ + pfs &= ~PDR_MASK; /* input */ + if (irq_enable) { + pfs |= ISEL_MASK; /* set pullup */ + } else { + pfs &= ~ISEL_MASK; /* clear pullup */ + } + if (pullup) { + pfs |= PCR_MASK; /* set pullup */ + } else { + pfs &= ~PCR_MASK; /* clear pullup */ + } + _PXXPFS(port, bit) = pfs; + pwpr_protect(); +} + +static void ra_icu_pin(uint32_t pin, bool enable) { + bool find = false; + uint8_t irq_no; + find = ra_icu_find_irq_no(pin, &irq_no); + if (find) { + ra_icu_irq_no(irq_no, enable); + } +} + +void ra_icu_enable_irq_no(uint8_t irq_no) { + ra_icu_irq_no(irq_no, true); +} + +void ra_icu_disable_irq_no(uint8_t irq_no) { + ra_icu_irq_no(irq_no, false); +} + +void ra_icu_enable_pin(uint32_t pin) { + ra_icu_pin(pin, true); +} + +void ra_icu_disable_pin(uint32_t pin) { + ra_icu_pin(pin, false); +} + +void ra_icu_priority_irq_no(uint8_t irq_no, uint32_t ipl) { + uint8_t irq_vec = (uint8_t)idx_to_irq_vec[irq_no]; + R_BSP_IrqCfg((IRQn_Type const)irq_vec, ipl, (void *)NULL); +} + +void ra_icu_priority_pin(uint32_t pin, uint32_t ipl) { + bool find = false; + uint8_t irq_no; + find = ra_icu_find_irq_no(pin, &irq_no); + if (find) { + ra_icu_priority_irq_no(irq_no, ipl); + } +} + +void ra_icu_set_callback(uint8_t irq_no, ICU_CB func, void *param) { + uint8_t idx = irq_no_to_idx[irq_no]; + if (idx != IRQ_IDX_MAX) { + icu_cbs[idx] = func; + icu_params[idx] = param; + } +} + +static void ra_icu_callback(uint8_t irq_no) { + uint8_t idx = irq_no_to_idx[irq_no]; + if (idx != IRQ_IDX_MAX) { + if (bounce_flag[idx]) { + if ((mtick() - bounce_start[idx]) > bounce_period[idx]) { + bounce_flag[idx] = false; + } else { + return; + } + } + if (icu_cbs[idx] != NULL) { + if (!bounce_flag[idx]) { + bounce_start[idx] = mtick(); + bounce_flag[idx] = true; + (*icu_cbs[idx])(icu_params[idx]); + } + } + } +} + +/* + * pin: cpu pin + * irq_no: IRQ number + * cond: 0: falling, 1: rising, 2: both edge, 3 low level + */ +void ra_icu_trigger_irq_no(uint8_t irq_no, uint32_t cond) { + icu_reg->IRQCR_b[irq_no].IRQMD = (uint8_t)cond; +} + +void ra_icu_trigger_pin(uint32_t pin, uint32_t cond) { + bool find = false; + uint8_t irq_no; + find = ra_icu_find_irq_no(pin, &irq_no); + if (find) { + ra_icu_trigger_irq_no(irq_no, cond); + } +} + +void ra_icu_set_bounce(uint8_t irq_no, uint32_t bounce) { + uint8_t idx = irq_no_to_idx[irq_no]; + if (idx != IRQ_IDX_MAX) { + bounce_period[idx] = bounce; + } +} + +static void ra_icu_bounce_init(void) { + uint32_t idx; + for (idx = 0; idx < IRQ_IDX_MAX; idx++) { + bounce_flag[idx] = false; + bounce_period[idx] = DEFAULT_BOUNCE_PERIOD; + } +} + +void ra_icu_init(void) { + ra_icu_bounce_init(); +} + +void ra_icu_deinit(void) { + uint32_t idx; + for (idx = 0; idx < IRQ_IDX_MAX; idx++) { + R_BSP_IrqDisable(idx_to_irq_vec[idx]); + } +} + +void ra_icu_swint(uint8_t irq_no) { + // RA MCU doesn't support STM32 EXTINT SWINT + // just call callback function + uint8_t idx = irq_no_to_idx[irq_no]; + if (icu_cbs[idx] != NULL) { + (*icu_cbs[idx])(icu_params[idx]); + } +} + +__WEAK void r_icu_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t irq_no = (uint32_t)irq_to_ch[(uint32_t)irq]; + R_BSP_IrqStatusClear(irq); + ra_icu_callback(irq_no); +} diff --git a/ports/renesas-ra/ra/ra_icu.h b/ports/renesas-ra/ra/ra_icu.h new file mode 100644 index 000000000..589e55c37 --- /dev/null +++ b/ports/renesas-ra/ra/ra_icu.h @@ -0,0 +1,58 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_ICU_H_ +#define RA_RA_ICU_H_ + +#include <stdint.h> +#include <stdbool.h> + +// #define IRQ_MAX (16) +#define VECTOR_NUMBER_NONE (0xff) + +typedef struct ra_irq_pin { + uint8_t irq_no; + uint32_t pin; +} ra_icu_pin_t; + +typedef void (*ICU_CB)(void *); + +bool ra_icu_find_irq_no(uint32_t pin, uint8_t *irq_no); +void ra_icu_set_pin(uint32_t pin, bool irq_enable, bool pullup); +void ra_icu_enable_irq_no(uint8_t irq_no); +void ra_icu_disable_irq_no(uint8_t irq_no); +void ra_icu_enable_pin(uint32_t pin); +void ra_icu_disable_pin(uint32_t pin); +void ra_icu_priority_irq_no(uint8_t irq_no, uint32_t ipl); +void ra_icu_priority_pin(uint32_t pin, uint32_t ipl); +void ra_icu_set_callback(uint8_t irq_no, ICU_CB func, void *param); +void ra_icu_trigger_irq_no(uint8_t irq_no, uint32_t cond); +void ra_icu_trigger_pin(uint32_t pin, uint32_t cond); +void ra_icu_set_bounce(uint8_t irq_no, uint32_t bounce); +void ra_icu_init(void); +void ra_icu_deinit(void); +void ra_icu_swint(uint8_t irq_no); +void r_icu_isr(void); + +#endif /* RA_RA_ICU_H_ */ diff --git a/ports/renesas-ra/ra/ra_init.c b/ports/renesas-ra/ra/ra_init.c new file mode 100644 index 000000000..c9b78e0dd --- /dev/null +++ b/ports/renesas-ra/ra/ra_init.c @@ -0,0 +1,39 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_data.h" +#include "ra_config.h" +#include "ra_flash.h" +#include "ra_int.h" +#include "ra_init.h" + +void ra_init(void) { + ra_int_init(); + SysTick_Config(PCLK / 1000); + internal_flash_init(); +} + +void ra_deinit(void) { + ra_int_init(); +} diff --git a/ports/renesas-ra/ra/ra_init.h b/ports/renesas-ra/ra/ra_init.h new file mode 100644 index 000000000..cb90e7f23 --- /dev/null +++ b/ports/renesas-ra/ra/ra_init.h @@ -0,0 +1,31 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA_RA_INIT_H_ +#define PORTS_RA_RA_RA_INIT_H_ + +void ra_init(void); +void ra_deinit(void); + +#endif /* PORTS_RA_RA_RA_INIT_H_ */ diff --git a/ports/renesas-ra/ra/ra_int.c b/ports/renesas-ra/ra/ra_int.c new file mode 100644 index 000000000..2f6449d14 --- /dev/null +++ b/ports/renesas-ra/ra/ra_int.c @@ -0,0 +1,273 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_data.h" +#include "ra_config.h" +#include "ra_int.h" + +/* + * store channel no or irq_no for specified irq_type(irq index) + */ +uint8_t irq_to_ch[IRQ_MAX]; + +void ra_int_init(void) { + uint32_t i; + for (i = 0; i < IRQ_MAX; i++) { + irq_to_ch[i] = 0; + } + #if defined(VECTOR_NUMBER_AGT0_INT) + irq_to_ch[VECTOR_NUMBER_AGT0_INT] = 0; + #endif + #if defined(VECTOR_NUMBER_AGT1_INT) + irq_to_ch[VECTOR_NUMBER_AGT1_INT] = 1; + #endif + #if defined(VECTOR_NUMBER_IIC0_RXI) + irq_to_ch[VECTOR_NUMBER_IIC0_RXI] = 0; + #endif + #if defined(VECTOR_NUMBER_IIC0_TXI) + irq_to_ch[VECTOR_NUMBER_IIC0_TXI] = 0; + #endif + #if defined(VECTOR_NUMBER_IIC0_TEI) + irq_to_ch[VECTOR_NUMBER_IIC0_TEI] = 0; + #endif + #if defined(VECTOR_NUMBER_IIC0_ERI) + irq_to_ch[VECTOR_NUMBER_IIC0_ERI] = 0; + #endif + #if defined(VECTOR_NUMBER_IIC1_RXI) + irq_to_ch[VECTOR_NUMBER_IIC1_RXI] = 1; + #endif + #if defined(VECTOR_NUMBER_IIC1_TXI) + irq_to_ch[VECTOR_NUMBER_IIC1_TXI] = 1; + #endif + #if defined(VECTOR_NUMBER_IIC1_TEI) + irq_to_ch[VECTOR_NUMBER_IIC1_TEI] = 1; + #endif + #if defined(VECTOR_NUMBER_IIC1_ERI) + irq_to_ch[VECTOR_NUMBER_IIC1_ERI] = 1; + #endif + #if defined(VECTOR_NUMBER_IIC2_RXI) + irq_to_ch[VECTOR_NUMBER_IIC2_RXI] = 2; + #endif + #if defined(VECTOR_NUMBER_IIC2_TXI) + irq_to_ch[VECTOR_NUMBER_IIC2_TXI] = 2; + #endif + #if defined(VECTOR_NUMBER_IIC2_TEI) + irq_to_ch[VECTOR_NUMBER_IIC2_TEI] = 2; + #endif + #if defined(VECTOR_NUMBER_IIC2_ERI) + irq_to_ch[VECTOR_NUMBER_IIC2_ERI] = 2; + #endif + #if defined(VECTOR_NUMBER_SPI0_RXI) + irq_to_ch[VECTOR_NUMBER_SPI0_RXI] = 0; + #endif + #if defined(VECTOR_NUMBER_SPI0_TXI) + irq_to_ch[VECTOR_NUMBER_SPI0_TXI] = 0; + #endif + #if defined(VECTOR_NUMBER_SPI0_TEI) + irq_to_ch[VECTOR_NUMBER_SPI0_TEI] = 0; + #endif + #if defined(VECTOR_NUMBER_SPI0_ERI) + irq_to_ch[VECTOR_NUMBER_SPI0_ERI] = 0; + #endif + #if defined(VECTOR_NUMBER_SPI1_RXI) + irq_to_ch[VECTOR_NUMBER_SPI1_RXI] = 1; + #endif + #if defined(VECTOR_NUMBER_SPI1_TXI) + irq_to_ch[VECTOR_NUMBER_SPI1_TXI] = 1; + #endif + #if defined(VECTOR_NUMBER_SPI1_TEI) + irq_to_ch[VECTOR_NUMBER_SPI1_TEI] = 1; + #endif + #if defined(VECTOR_NUMBER_SPI1_ERI) + irq_to_ch[VECTOR_NUMBER_SPI1_ERI] = 1; + #endif + #if defined(VECTOR_NUMBER_SCI0_RXI) + irq_to_ch[VECTOR_NUMBER_SCI0_RXI] = 0; + #endif + #if defined(VECTOR_NUMBER_SCI0_TXI) + irq_to_ch[VECTOR_NUMBER_SCI0_TXI] = 0; + #endif + #if defined(VECTOR_NUMBER_SCI0_TEI) + irq_to_ch[VECTOR_NUMBER_SCI0_TEI] = 0; + #endif + #if defined(VECTOR_NUMBER_SCI0_ERI) + irq_to_ch[VECTOR_NUMBER_SCI0_ERI] = 0; + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + irq_to_ch[VECTOR_NUMBER_SCI1_RXI] = 1; + #endif + #if defined(VECTOR_NUMBER_SCI1_TXI) + irq_to_ch[VECTOR_NUMBER_SCI1_TXI] = 1; + #endif + #if defined(VECTOR_NUMBER_SCI1_TEI) + irq_to_ch[VECTOR_NUMBER_SCI1_TEI] = 1; + #endif + #if defined(VECTOR_NUMBER_SCI1_ERI) + irq_to_ch[VECTOR_NUMBER_SCI1_ERI] = 1; + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + irq_to_ch[VECTOR_NUMBER_SCI2_RXI] = 2; + #endif + #if defined(VECTOR_NUMBER_SCI2_TXI) + irq_to_ch[VECTOR_NUMBER_SCI2_TXI] = 2; + #endif + #if defined(VECTOR_NUMBER_SCI2_TEI) + irq_to_ch[VECTOR_NUMBER_SCI2_TEI] = 2; + #endif + #if defined(VECTOR_NUMBER_SCI2_ERI) + irq_to_ch[VECTOR_NUMBER_SCI2_ERI] = 2; + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + irq_to_ch[VECTOR_NUMBER_SCI3_RXI] = 3; + #endif + #if defined(VECTOR_NUMBER_SCI3_TXI) + irq_to_ch[VECTOR_NUMBER_SCI3_TXI] = 3; + #endif + #if defined(VECTOR_NUMBER_SCI3_TEI) + irq_to_ch[VECTOR_NUMBER_SCI3_TEI] = 3; + #endif + #if defined(VECTOR_NUMBER_SCI3_ERI) + irq_to_ch[VECTOR_NUMBER_SCI3_ERI] = 3; + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + irq_to_ch[VECTOR_NUMBER_SCI4_RXI] = 4; + #endif + #if defined(VECTOR_NUMBER_SCI4_TXI) + irq_to_ch[VECTOR_NUMBER_SCI4_TXI] = 4; + #endif + #if defined(VECTOR_NUMBER_SCI4_TEI) + irq_to_ch[VECTOR_NUMBER_SCI4_TEI] = 4; + #endif + #if defined(VECTOR_NUMBER_SCI4_ERI) + irq_to_ch[VECTOR_NUMBER_SCI4_ERI] = 4; + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + irq_to_ch[VECTOR_NUMBER_SCI5_RXI] = 5; + #endif + #if defined(VECTOR_NUMBER_SCI5_TXI) + irq_to_ch[VECTOR_NUMBER_SCI5_TXI] = 5; + #endif + #if defined(VECTOR_NUMBER_SCI5_TEI) + irq_to_ch[VECTOR_NUMBER_SCI5_TEI] = 5; + #endif + #if defined(VECTOR_NUMBER_SCI5_ERI) + irq_to_ch[VECTOR_NUMBER_SCI5_ERI] = 5; + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + irq_to_ch[VECTOR_NUMBER_SCI6_RXI] = 6; + #endif + #if defined(VECTOR_NUMBER_SCI6_TXI) + irq_to_ch[VECTOR_NUMBER_SCI6_TXI] = 6; + #endif + #if defined(VECTOR_NUMBER_SCI6_TEI) + irq_to_ch[VECTOR_NUMBER_SCI6_TEI] = 6; + #endif + #if defined(VECTOR_NUMBER_SCI6_ERI) + irq_to_ch[VECTOR_NUMBER_SCI6_ERI] = 6; + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + irq_to_ch[VECTOR_NUMBER_SCI7_RXI] = 7; + #endif + #if defined(VECTOR_NUMBER_SCI7_TXI) + irq_to_ch[VECTOR_NUMBER_SCI7_TXI] = 7; + #endif + #if defined(VECTOR_NUMBER_SCI7_TEI) + irq_to_ch[VECTOR_NUMBER_SCI7_TEI] = 7; + #endif + #if defined(VECTOR_NUMBER_SCI7_ERI) + irq_to_ch[VECTOR_NUMBER_SCI7_ERI] = 7; + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + irq_to_ch[VECTOR_NUMBER_SCI8_RXI] = 8; + #endif + #if defined(VECTOR_NUMBER_SCI8_TXI) + irq_to_ch[VECTOR_NUMBER_SCI8_TXI] = 8; + #endif + #if defined(VECTOR_NUMBER_SCI8_TEI) + irq_to_ch[VECTOR_NUMBER_SCI8_TEI] = 8; + #endif + #if defined(VECTOR_NUMBER_SCI8_ERI) + irq_to_ch[VECTOR_NUMBER_SCI8_ERI] = 8; + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + irq_to_ch[VECTOR_NUMBER_SCI9_RXI] = 9; + #endif + #if defined(VECTOR_NUMBER_SCI9_TXI) + irq_to_ch[VECTOR_NUMBER_SCI9_TXI] = 9; + #endif + #if defined(VECTOR_NUMBER_SCI9_TEI) + irq_to_ch[VECTOR_NUMBER_SCI9_TEI] = 9; + #endif + #if defined(VECTOR_NUMBER_SCI9_ERI) + irq_to_ch[VECTOR_NUMBER_SCI9_ERI] = 9; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ0) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ0] = 0; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ1) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ1] = 1; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ2) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ2] = 2; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ3) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ3] = 3; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ4) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ4] = 4; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ5) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ5] = 5; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ6) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ6] = 6; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ7) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ7] = 7; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ8) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ8] = 8; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ9) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ9] = 9; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ10) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ10] = 10; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ11) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ11] = 11; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ12) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ12] = 12; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ13) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ13] = 13; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ14) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ14] = 14; + #endif + #if defined(VECTOR_NUMBER_ICU_IRQ15) + irq_to_ch[VECTOR_NUMBER_ICU_IRQ15] = 15; + #endif +} diff --git a/ports/renesas-ra/ra/ra_int.h b/ports/renesas-ra/ra/ra_int.h new file mode 100644 index 000000000..cd12908bc --- /dev/null +++ b/ports/renesas-ra/ra/ra_int.h @@ -0,0 +1,42 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_INT_H_ +#define RA_RA_INT_H_ + +#include <stdint.h> + +#if defined(RA4M1) | defined(RA4W1) +#define IRQ_MAX 48 +#elif defined(RA6M1) | defined(RA6M2) +#define IRQ_MAX 128 +#else +#error "CMSIS MCU Series is not specified." +#endif + +extern uint8_t irq_to_ch[IRQ_MAX]; + +void ra_int_init(void); + +#endif /* RA_RA_INT_H_ */ diff --git a/ports/renesas-ra/ra/ra_rtc.c b/ports/renesas-ra/ra/ra_rtc.c new file mode 100644 index 000000000..f108de568 --- /dev/null +++ b/ports/renesas-ra/ra/ra_rtc.c @@ -0,0 +1,430 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_rtc.h" + +#include <stdio.h> +#include <stdlib.h> +#include "hal_data.h" +#include "ra_rtc.h" + +static R_RTC_Type *rtc_reg = (R_RTC_Type *)0x40044000; +static R_SYSTEM_Type *system_reg = (R_SYSTEM_Type *)0x4001E000; + +#if defined(VECTOR_NUMBER_RTC_ALARM) +ra_rtc_cb_t ra_rtc_func_alarm = NULL; +void *ra_rtc_param_alarm = NULL; +#endif +#if defined(VECTOR_NUMBER_RTC_PERIOD) +ra_rtc_cb_t ra_rtc_func_period = NULL; +void *ra_rtc_param_period = NULL; +#endif + +static inline uint8_t int_to_bcd(int num) { + return (uint8_t)(((num / 10) << 4) | (num % 10)); +} + +static inline int bcd_to_int(uint8_t bcd) { + return (int)(((bcd >> 4) * 10) + (bcd & 0x0F)); +} + +int ra_rtc_get_year(void) { + return bcd_to_int((uint8_t)rtc_reg->RYRCNT) + 2000; +} + +int ra_rtc_get_month(void) { + return bcd_to_int((uint8_t)rtc_reg->RMONCNT); +} + +int ra_rtc_get_date(void) { + return bcd_to_int((uint8_t)rtc_reg->RDAYCNT); +} + +int ra_rtc_get_hour(void) { + return bcd_to_int((uint8_t)(0x3f & rtc_reg->RHRCNT)); +} + +int ra_rtc_get_minute(void) { + return bcd_to_int((uint8_t)rtc_reg->RMINCNT); +} + +int ra_rtc_get_second(void) { + return bcd_to_int((uint8_t)rtc_reg->RSECCNT); +} + +int ra_rtc_get_weekday(void) { + return bcd_to_int((uint8_t)rtc_reg->RWKCNT); +} + +#if defined(VECTOR_NUMBER_RTC_PERIOD) + +void ra_rtc_period_on() { + // Enable periodic interrupt + rtc_reg->RCR1_b.PIE = 1; + while (!rtc_reg->RCR1_b.PIE) { + ; + } + // Enable NVIC RTC Alarm interrupt + R_BSP_IrqCfg((IRQn_Type const)RTC_PERIOD_IRQn, (uint32_t)RA_PRI_RTC_WKUP, (void *)NULL); + R_BSP_IrqEnable((IRQn_Type const)RTC_PERIOD_IRQn); +} + +void ra_rtc_period_off() { + // Disable NVIC RTC Alarm interrupt + R_BSP_IrqDisable((IRQn_Type const)RTC_PERIOD_IRQn); + // Disable periodic interrupt + rtc_reg->RCR1_b.PIE = 0; + while (rtc_reg->RCR1_b.PIE) { + ; + } +} + +// period +// 6 : every 1/256(s) +// 7 : every 1/128(s) +// 8 : every 1/64(s) +// 9 : every 1/32(s) +// 10 : every 1/16(s) +// 11 : every 1/8(s) +// 12 : every 1/4(s) +// 13 : every 1/2(s) +// 14 : every 1(s) +// 15 : every 2(s) +void ra_rtc_set_period_time(uint32_t period) { + if ((period < 6) | (period > 15)) { + return; + } + ra_rtc_period_off(); + uint8_t rcr1 = rtc_reg->RCR1; + rcr1 &= (uint8_t) ~R_RTC_RCR1_PES_Msk; + rcr1 |= (uint8_t)(period << R_RTC_RCR1_PES_Pos); + rtc_reg->RCR1 = rcr1; + while (rtc_reg->RCR1 != rcr1) { + ; + } + ra_rtc_period_on(); +} + +void ra_rtc_set_period_func(void *cb, void *param) { + ra_rtc_period_off(); + ra_rtc_func_period = (ra_rtc_cb_t)cb; + ra_rtc_param_period = param; + ra_rtc_period_on(); +} + +#endif + +#if defined(VECTOR_NUMBER_RTC_ALARM) + +void ra_rtc_alarm_on() { + // Enable alarm interrupt + rtc_reg->RCR1_b.AIE = 1; + while (!rtc_reg->RCR1_b.AIE) { + ; + } + // Enable NVIC RTC Alarm interrupt + R_BSP_IrqCfg((IRQn_Type const)RTC_ALARM_IRQn, (uint32_t)RA_PRI_RTC_WKUP, (void *)NULL); + R_BSP_IrqEnable((IRQn_Type const)RTC_ALARM_IRQn); +} + +void ra_rtc_alarm_off() { + // Disable NVIC RTC Alarm interrupt + R_BSP_IrqDisable((IRQn_Type const)RTC_ALARM_IRQn); + // Disable alarm interrupt + rtc_reg->RCR1_b.AIE = 0; + while (rtc_reg->RCR1_b.AIE) { + ; + } +} + +void ra_rtc_set_alarm_time(int hour, int min, int week_flag) { + ra_rtc_alarm_off(); + // Configure the alarm + rtc_reg->RMINAR = (uint8_t)int_to_bcd(min); + rtc_reg->RHRAR = (uint8_t)int_to_bcd(hour); + if (week_flag <= 0x06) { + rtc_reg->RWKAR = (uint8_t)week_flag; + } + rtc_reg->RMINAR_b.ENB = 1; + rtc_reg->RHRAR_b.ENB = 1; + if (week_flag <= 0x06) { + rtc_reg->RWKAR_b.ENB = 1; + } else { + rtc_reg->RWKAR_b.ENB = 0; + } + ra_rtc_alarm_on(); +} + +void ra_rtc_set_alarm_func(void *cb, void *param) { + ra_rtc_period_off(); + ra_rtc_func_alarm = (ra_rtc_cb_t)cb; + ra_rtc_param_alarm = param; + ra_rtc_period_on(); +} + +#endif + +// adj: adjustment bit (number of sub clocks) +// 0 : no adjustment +// 0<: +// 0>: +// aadjp: specify adjustment period +// 0: 1 minute (RTC_PERIOD_MINUTE) +// 1: 10 seconds (RTC_PERIOD_SECOND) +void ra_rtc_set_adjustment(int adj, int aadjp) { + int tmp_int; + aadjp &= 1; + if (adj == 0) { + // no adjustment + rtc_reg->RADJ = 0x00; + while (rtc_reg->RADJ != 0x00) { + ; + } + } else if (adj > 0) { + // plus adjustment + rtc_reg->RADJ = 0x00; + while (rtc_reg->RADJ != 0x00) { + ; + } + // enable auto adjustment + rtc_reg->RCR2_b.AADJE = 1; + while (rtc_reg->RCR2_b.AADJE != 1) { + ; + } + rtc_reg->RCR2_b.AADJP = + aadjp == RTC_PERIOD_MINUTE ? RTC_PERIOD_MINUTE : RTC_PERIOD_SECOND; + while (rtc_reg->RCR2_b.AADJP != aadjp) { + ; + } + tmp_int = 0x40 | (0x3F & adj); + rtc_reg->RADJ = (uint8_t)tmp_int; + while (rtc_reg->RADJ != (uint8_t)tmp_int) { + ; + } + } else { + // minus adjustment + rtc_reg->RADJ = 0x00; + while (rtc_reg->RADJ != 0x00) { + ; + } + // enable adjustment + rtc_reg->RCR2_b.AADJE = 1; + while (rtc_reg->RCR2_b.AADJE != 1) { + ; + } + rtc_reg->RCR2_b.AADJP = + aadjp == RTC_PERIOD_MINUTE ? RTC_PERIOD_MINUTE : RTC_PERIOD_SECOND; + while (rtc_reg->RCR2_b.AADJP != aadjp) { + ; + } + tmp_int = 0x80 | (0x3F & abs(adj)); + rtc_reg->RADJ = (uint8_t)tmp_int; + while (rtc_reg->RADJ != (uint8_t)tmp_int) { + ; + } + } +} + +uint8_t ra_rtc_get_adjustment(void) { + return rtc_reg->RADJ; +} + +bool ra_rtc_set_time(ra_rtc_t *time) { + // Write 0 to RTC start bit + rtc_reg->RCR2_b.START = 0x0; + // Wait for start bit to clear + while (0 != rtc_reg->RCR2_b.START) { + ; + } + // Alarm enable bits are undefined after a reset, + // disable non-required alarm features + rtc_reg->RWKAR_b.ENB = 0; + rtc_reg->RDAYAR_b.ENB = 0; + rtc_reg->RMONAR_b.ENB = 0; + rtc_reg->RYRAREN_b.ENB = 0; + // Operate RTC in 24-hr mode + rtc_reg->RCR2_b.HR24 = 0x1; + rtc_reg->RYRCNT = (uint16_t)int_to_bcd(time->year % 100); + rtc_reg->RMONCNT = (uint8_t)int_to_bcd(time->month); + rtc_reg->RDAYCNT = (uint8_t)int_to_bcd(time->date); + rtc_reg->RHRCNT = (uint8_t)int_to_bcd(time->hour); + rtc_reg->RMINCNT = (uint8_t)int_to_bcd(time->minute); + rtc_reg->RSECCNT = (uint8_t)int_to_bcd(time->second); + rtc_reg->RWKCNT = (uint8_t)int_to_bcd(time->weekday); + // Start the clock + rtc_reg->RCR2_b.START = 0x1; + // Wait until the start bit is set to 1 + while (1 != rtc_reg->RCR2_b.START) { + ; + } + return true; +} + +bool ra_rtc_get_time(ra_rtc_t *time) { + time->year = (uint16_t)(bcd_to_int((uint8_t)rtc_reg->RYRCNT) + 2000); + time->month = (uint8_t)bcd_to_int(rtc_reg->RMONCNT); + time->date = (uint8_t)bcd_to_int(rtc_reg->RDAYCNT); + time->hour = (uint8_t)bcd_to_int((uint8_t)(0x3f & rtc_reg->RHRCNT)); + time->minute = (uint8_t)bcd_to_int((uint8_t)rtc_reg->RMINCNT); + time->second = (uint8_t)bcd_to_int((uint8_t)rtc_reg->RSECCNT); + time->weekday = (uint8_t)bcd_to_int((uint8_t)rtc_reg->RWKCNT); + return true; +} + +static void wait(volatile int count) { + while (count--) { + __asm__ __volatile__ ("nop"); + } +} + +// source +// 0: subclock +// 1: LOCO +static void ra_rtc_set_subclock(uint8_t source) { + // Set RTC clock input from sub-clock, and supply to RTC module + rtc_reg->RCR4_b.RCKSEL = source; + if (0 == source) { + R_BSP_SoftwareDelay(100, BSP_DELAY_UNITS_MILLISECONDS); + } else { + R_BSP_SoftwareDelay(200, BSP_DELAY_UNITS_MICROSECONDS); + } + // Stop the clock + rtc_reg->RCR2_b.START = 0x0; + // Wait for start bit to clear + while (0 != rtc_reg->RCR2_b.START) { + ; + } + if (source == 1) { + rtc_reg->RFRH = 0; + rtc_reg->RFRL = (uint16_t)0x00ff; // assume 32.768khz + } + rtc_reg->RCR2_b.CNTMD = 0; + while (0 != rtc_reg->RCR2_b.CNTMD) { + ; + } + // Reset the RTC unit + rtc_reg->RCR2_b.RESET = 0x1; + // Wait until reset is complete + while (0 != rtc_reg->RCR2_b.RESET) { + ; + } + // Start the clock + rtc_reg->RCR2_b.START = 0x1; + // Wait until the start bit is set to 1 + while (1 != rtc_reg->RCR2_b.START) { + ; + } +} + +bool ra_rtc_init(uint8_t source) { + system_reg->PRCR = 0xA503; + // Check if the MCU has come from a cold start (power on reset) + if (0 == system_reg->RSTSR2_b.CWSF) { + // cold start + system_reg->VBTCR1_b.BPWSWSTP = 1; + // Set the warm start flag + system_reg->RSTSR2_b.CWSF = 1; + // Disable the sub-clock oscillator + system_reg->SOSCCR_b.SOSTP = 1; + // Wait for register modification to complete + while (1 != system_reg->SOSCCR_b.SOSTP) { + ; + } + // Start sub-clock + system_reg->SOSCCR_b.SOSTP = 0; + // Perform 8 delay iterations + for (uint8_t i = 0; i < 8; i++) { + // Wait in while loop for ~0.5 seconds + wait(0xFFFFE); + } + } else { + // Start sub-clock + system_reg->SOSCCR_b.SOSTP = 0; + // Wait for the register modification to complete + while (0 != system_reg->SOSCCR_b.SOSTP) { + ; + } + } + system_reg->PRCR = 0xA500; + // call back + #if defined(VECTOR_NUMBER_RTC_ALARM) + ra_rtc_func_alarm = NULL; + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + ra_rtc_func_period = NULL; + #endif + if ((rtc_reg->RCR2_b.START == 0) || (rtc_reg->RCR4_b.RCKSEL != source)) { + rtc_reg->RCR1 = 0; + rtc_reg->RCR2 = 0; + ra_rtc_set_subclock(source); + } + return true; +} + +bool ra_rtc_deinit(void) { + #if defined(VECTOR_NUMBER_RTC_ALARM) + ra_rtc_alarm_off(); + ra_rtc_func_alarm = NULL; + ra_rtc_param_alarm = NULL; + #endif + #if defined(VECTOR_NUMBER_RTC_PERIOD) + ra_rtc_period_off(); + ra_rtc_func_period = NULL; + ra_rtc_param_period = NULL; + #endif + rtc_reg->RCR4_b.RCKSEL = 1; + rtc_reg->RCR1 = 0; + return true; +} + +void rtc_alarm_periodic_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + #if defined(VECTOR_NUMBER_RTC_PERIOD) + if (irq == RTC_PERIOD_IRQn) { + if (ra_rtc_func_period) { + ra_rtc_func_period(ra_rtc_param_period); + } + } + #endif + #if defined(VECTOR_NUMBER_RTC_ALARM) + if (irq == RTC_ALARM_IRQn) { + if (ra_rtc_func_alarm) { + ra_rtc_func_alarm(ra_rtc_param_alarm); + } + } + #endif + R_BSP_IrqStatusClear(irq); +} + +#if defined(VECTOR_NUMBER_RTC_CARRY) +void rtc_carry_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); +} +#endif diff --git a/ports/renesas-ra/ra/ra_rtc.h b/ports/renesas-ra/ra/ra_rtc.h new file mode 100644 index 000000000..0cad5ebd1 --- /dev/null +++ b/ports/renesas-ra/ra/ra_rtc.h @@ -0,0 +1,70 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RTC_H_ +#define RA_RTC_H_ + +#include <stdint.h> +#include <stdbool.h> + +#define RTC_PERIOD_MINUTE 0x00 +#define RTC_PERIOD_SECOND 0x01 + +typedef struct { + unsigned short year; + unsigned char month; + unsigned char date; + unsigned char weekday; + unsigned char hour; + unsigned char minute; + unsigned char second; +} ra_rtc_t; + +typedef void (*ra_rtc_cb_t)(void *); + +int ra_rtc_get_year(void); +int ra_rtc_get_month(void); +int ra_rtc_get_date(void); +int ra_rtc_get_hour(void); +int ra_rtc_get_minute(void); +int ra_rtc_get_second(void); +int ra_rtc_get_weekday(void); +void ra_rtc_period_on(); +void ra_rtc_period_off(); +void ra_rtc_set_period_time(uint32_t period); +void ra_rtc_set_period_func(void *cb, void *param); +void ra_rtc_alarm_on(void); +void ra_rtc_alarm_off(void); +void ra_rtc_set_alarm_time(int hour, int min, int week_flag); +void ra_rtc_set_alarm_func(void *cb, void *param); +void ra_rtc_set_adjustment(int adj, int aadjp); +uint8_t ra_rtc_get_adjustment(void); +bool ra_rtc_set_time(ra_rtc_t *time); +bool ra_rtc_get_time(ra_rtc_t *time); +bool ra_rtc_init(uint8_t source); +bool ra_rtc_deinit(void); +void rtc_alarm_periodic_isr(void); +void rtc_carry_isr(void); + +#endif /* RA_RTC_H_ */ diff --git a/ports/renesas-ra/ra/ra_sci.c b/ports/renesas-ra/ra/ra_sci.c new file mode 100644 index 000000000..8cf26680c --- /dev/null +++ b/ports/renesas-ra/ra/ra_sci.c @@ -0,0 +1,1233 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_data.h" +#include "ra_config.h" +#include "ra_gpio.h" +#include "ra_int.h" +#include "ra_utils.h" +#include "ra_sci.h" + +#if !defined(RA_PRI_UART) +#define RA_PRI_UART (1) +#endif + +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Wunused-parameter" +// #pragma GCC diagnostic ignored "-Wconversion" +// #pragma GCC diagnostic ignored "-Wshift-negative-value" +// #pragma GCC diagnostic ignored "-Wunused-but-set-variable" +// #pragma GCC diagnostic ignored "-Wsequence-point" +// #pragma GCC diagnostic ignored "-Wunused-function" +#endif + +enum +{ + #if defined(VECTOR_NUMBER_SCI0_RXI) + SCI0_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + SCI1_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + SCI2_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + SCI3_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + SCI4_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + SCI5_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + SCI6_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + SCI7_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + SCI8_IDX, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + SCI9_IDX, + #endif + SCI_IDX_MAX, +}; + +static const IRQn_Type idx_to_rxirq[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + VECTOR_NUMBER_SCI0_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + VECTOR_NUMBER_SCI1_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + VECTOR_NUMBER_SCI2_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + VECTOR_NUMBER_SCI3_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + VECTOR_NUMBER_SCI4_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + VECTOR_NUMBER_SCI5_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + VECTOR_NUMBER_SCI6_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + VECTOR_NUMBER_SCI7_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + VECTOR_NUMBER_SCI8_RXI, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + VECTOR_NUMBER_SCI9_RXI, + #endif +}; + +static const IRQn_Type idx_to_txirq[] = { + #if defined(VECTOR_NUMBER_SCI0_TXI) + VECTOR_NUMBER_SCI0_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI1_TXI) + VECTOR_NUMBER_SCI1_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI2_TXI) + VECTOR_NUMBER_SCI2_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI3_TXI) + VECTOR_NUMBER_SCI3_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI4_TXI) + VECTOR_NUMBER_SCI4_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI5_TXI) + VECTOR_NUMBER_SCI5_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI6_TXI) + VECTOR_NUMBER_SCI6_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI7_TXI) + VECTOR_NUMBER_SCI7_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI8_TXI) + VECTOR_NUMBER_SCI8_TXI, + #endif + #if defined(VECTOR_NUMBER_SCI9_TXI) + VECTOR_NUMBER_SCI9_TXI, + #endif +}; + +static const IRQn_Type idx_to_teirq[] = { + #if defined(VECTOR_NUMBER_SCI0_TEI) + VECTOR_NUMBER_SCI0_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI1_TEI) + VECTOR_NUMBER_SCI1_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI2_TEI) + VECTOR_NUMBER_SCI2_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI3_TEI) + VECTOR_NUMBER_SCI3_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI4_TEI) + VECTOR_NUMBER_SCI4_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI5_TEI) + VECTOR_NUMBER_SCI5_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI6_TEI) + VECTOR_NUMBER_SCI6_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI7_TEI) + VECTOR_NUMBER_SCI7_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI8_TEI) + VECTOR_NUMBER_SCI8_TEI, + #endif + #if defined(VECTOR_NUMBER_SCI9_TEI) + VECTOR_NUMBER_SCI9_TEI, + #endif +}; + +static const IRQn_Type idx_to_erirq[] = { + #if defined(VECTOR_NUMBER_SCI0_ERI) + VECTOR_NUMBER_SCI0_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI1_ERI) + VECTOR_NUMBER_SCI1_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI2_ERI) + VECTOR_NUMBER_SCI2_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI3_ERI) + VECTOR_NUMBER_SCI3_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI4_ERI) + VECTOR_NUMBER_SCI4_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI5_ERI) + VECTOR_NUMBER_SCI5_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI6_ERI) + VECTOR_NUMBER_SCI6_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI7_ERI) + VECTOR_NUMBER_SCI7_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI8_ERI) + VECTOR_NUMBER_SCI8_ERI, + #endif + #if defined(VECTOR_NUMBER_SCI9_ERI) + VECTOR_NUMBER_SCI9_ERI, + #endif +}; + +static uint32_t ch_to_idx[SCI_CH_MAX] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + SCI0_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + SCI1_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + SCI2_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + SCI3_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + SCI4_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + SCI5_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + SCI6_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + SCI7_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + SCI8_IDX, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + SCI9_IDX, + #else + 0, + #endif +}; + +static R_SCI0_Type *sci_regs[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + (R_SCI0_Type *)0x40070000, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + (R_SCI0_Type *)0x40070020, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + (R_SCI0_Type *)0x40070040, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + (R_SCI0_Type *)0x40070060, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + (R_SCI0_Type *)0x40070080, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + (R_SCI0_Type *)0x400700a0, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + (R_SCI0_Type *)0x400700c0, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + (R_SCI0_Type *)0x400700e0, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + (R_SCI0_Type *)0x40070100, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + (R_SCI0_Type *)0x40070120, + #endif +}; + +static uint32_t sci_module_mask[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + R_MSTP_MSTPCRB_MSTPB31_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + R_MSTP_MSTPCRB_MSTPB30_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + R_MSTP_MSTPCRB_MSTPB29_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + R_MSTP_MSTPCRB_MSTPB28_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + R_MSTP_MSTPCRB_MSTPB27_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + R_MSTP_MSTPCRB_MSTPB26_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + R_MSTP_MSTPCRB_MSTPB25_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + R_MSTP_MSTPCRB_MSTPB24_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + R_MSTP_MSTPCRB_MSTPB23_Msk, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + R_MSTP_MSTPCRB_MSTPB22_Msk, + #endif +}; + +static const ra_af_pin_t ra_sci_tx_pins[] = { + #if defined(RA4M1) + + { AF_SCI1, 0, P101 }, + { AF_SCI1, 0, P205 }, + { AF_SCI1, 0, P411 }, + + { AF_SCI2, 1, P213 }, + { AF_SCI2, 1, P401 }, + { AF_SCI2, 1, P501 }, + + { AF_SCI2, 2, P102 }, + { AF_SCI1, 2, P112 }, + { AF_SCI1, 2, P302 }, + + { AF_SCI2, 9, P109 }, + { AF_SCI2, 9, P203 }, + { AF_SCI2, 9, P409 }, + { AF_SCI2, 9, P602 }, + + #elif defined(RA4W1) + { AF_SCI1, 0, P101 }, + + { AF_SCI2, 1, P213 }, + + { AF_SCI1, 4, P205 }, + + { AF_SCI2, 9, P109 }, + + #elif defined(RA6M1) + + { AF_SCI1, 0, P101 }, + { AF_SCI1, 0, P411 }, + + { AF_SCI2, 1, P213 }, + + { AF_SCI1, 2, P112 }, + { AF_SCI1, 2, P302 }, + + { AF_SCI2, 3, P409 }, + + { AF_SCI1, 4, P205 }, + + { AF_SCI1, 8, P105 }, + + { AF_SCI2, 9, P109 }, + { AF_SCI2, 9, P602 }, + + #elif defined(RA6M2) + + { AF_SCI1, 0, P101 }, + { AF_SCI1, 0, P411 }, + + { AF_SCI1, 1, P213 }, + { AF_SCI2, 1, P709 }, + + { AF_SCI1, 2, P112 }, + { AF_SCI1, 2, P302 }, + + { AF_SCI2, 3, P310 }, + { AF_SCI2, 3, P409 }, + + { AF_SCI1, 4, P205 }, + { AF_SCI1, 4, P512 }, + + { AF_SCI2, 5, P501 }, + + { AF_SCI1, 6, P305 }, + { AF_SCI1, 6, P506 }, + + { AF_SCI2, 7, P401 }, + { AF_SCI2, 7, P613 }, + + { AF_SCI1, 8, P105 }, + + { AF_SCI2, 9, P109 }, + { AF_SCI2, 9, P203 }, + { AF_SCI2, 9, P602 }, + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define SCI_TX_PINS_SIZE sizeof(ra_sci_tx_pins) / sizeof(ra_af_pin_t) + +static const ra_af_pin_t ra_sci_rx_pins[] = { + #if defined(RA4M1) + + { AF_SCI1, 0, P100 }, + { AF_SCI1, 0, P104 }, + { AF_SCI1, 0, P206 }, + { AF_SCI1, 0, P410 }, + + { AF_SCI2, 1, P212 }, + { AF_SCI2, 1, P402 }, + { AF_SCI2, 1, P502 }, + { AF_SCI2, 1, P708 }, + + { AF_SCI1, 2, P301 }, + + { AF_SCI2, 9, P110 }, + { AF_SCI2, 9, P202 }, + { AF_SCI2, 9, P408 }, + { AF_SCI2, 9, P601 }, + + #elif defined(RA4W1) + { AF_SCI1, 0, P100 }, + { AF_SCI1, 0, P104 }, + + { AF_SCI2, 1, P212 }, + { AF_SCI2, 1, P402 }, + + { AF_SCI1, 4, P206 }, + + { AF_SCI2, 9, P110 }, + + #elif defined(RA6M1) + + { AF_SCI1, 0, P100 }, + { AF_SCI1, 0, P410 }, + + { AF_SCI2, 1, P212 }, + { AF_SCI2, 1, P708 }, + + { AF_SCI1, 2, P113 }, + { AF_SCI1, 2, P301 }, + + { AF_SCI2, 3, P408 }, + + { AF_SCI1, 4, P206 }, + + { AF_SCI1, 8, P104 }, + + { AF_SCI2, 9, P110 }, + { AF_SCI2, 9, P601 }, + + #elif defined(RA6M2) + + { AF_SCI1, 0, P100 }, + { AF_SCI1, 0, P410 }, + + { AF_SCI1, 1, P212 }, + { AF_SCI2, 1, P708 }, + + { AF_SCI1, 2, P113 }, + { AF_SCI1, 2, P301 }, + + { AF_SCI2, 3, P309 }, + { AF_SCI2, 3, P408 }, + + { AF_SCI1, 4, P206 }, + { AF_SCI1, 4, P511 }, + + { AF_SCI2, 5, P502 }, + + { AF_SCI1, 6, P304 }, + { AF_SCI1, 6, P505 }, + + { AF_SCI2, 7, P402 }, + { AF_SCI2, 7, P614 }, + + { AF_SCI1, 8, P104 }, + + { AF_SCI2, 9, P110 }, + { AF_SCI2, 9, P202 }, + { AF_SCI2, 9, P601 }, + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define SCI_RX_PINS_SIZE sizeof(ra_sci_rx_pins) / sizeof(ra_af_pin_t) + +static const ra_af_pin_t ra_sci_cts_pins[] = { + #if defined(RA4M1) + + { AF_SCI1, 0, P103 }, + { AF_SCI1, 0, P401 }, + { AF_SCI1, 0, P407 }, + { AF_SCI1, 0, P413 }, + + { AF_SCI2, 1, P101 }, + { AF_SCI2, 1, P403 }, + { AF_SCI1, 1, P408 }, + { AF_SCI2, 1, P504 }, + + { AF_SCI1, 2, P110 }, + { AF_SCI1, 2, P203 }, + + { AF_SCI2, 9, P108 }, + { AF_SCI2, 9, P205 }, + { AF_SCI2, 9, P301 }, + { AF_SCI2, 9, P603 }, + + #elif defined(RA4W1) + { AF_SCI1, 0, P103 }, + + { AF_SCI2, 1, P101 }, + + { AF_SCI1, 4, P407 }, + + { AF_SCI2, 9, P108 }, + { AF_SCI2, 9, P205 }, + + #elif defined(RA6M1) + + { AF_SCI1, 0, P103 }, + { AF_SCI1, 0, P413 }, + + { AF_SCI2, 1, P101 }, + + { AF_SCI1, 2, P110 }, + + { AF_SCI2, 3, P411 }, + + { AF_SCI1, 4, P401 }, + { AF_SCI1, 4, P407 }, + + { AF_SCI1, 8, P107 }, + + { AF_SCI2, 9, P108 }, + { AF_SCI2, 9, P301 }, + + #elif defined(RA6M2) + + { AF_SCI1, 0, P103 }, + { AF_SCI1, 0, P413 }, + + { AF_SCI2, 1, P101 }, + { AF_SCI2, 1, P711 }, + + { AF_SCI1, 2, P110 }, + { AF_SCI1, 2, P203 }, + + { AF_SCI2, 3, P312 }, + { AF_SCI2, 3, P411 }, + + { AF_SCI1, 4, P401 }, + { AF_SCI1, 4, P407 }, + + { AF_SCI2, 5, P504 }, + + { AF_SCI1, 6, P307 }, + { AF_SCI1, 6, P503 }, + + { AF_SCI2, 7, P403 }, + { AF_SCI2, 7, P611 }, + + { AF_SCI1, 8, P107 }, + + { AF_SCI2, 9, P108 }, + { AF_SCI2, 9, P205 }, + { AF_SCI2, 9, P301 }, + { AF_SCI2, 9, P603 }, + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define SCI_CTS_PINS_SIZE sizeof(ra_sci_cts_pins) / sizeof(ra_af_pin_t) + +typedef struct _sci_fifo { + volatile uint32_t tail, head, len, busy; + uint8_t *bufp; + uint32_t size; +} sci_fifo; + +static uint32_t ra_sci_init_flag[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + 0, + #endif +}; +static SCI_CB sci_cb[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + (SCI_CB)0, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + (SCI_CB)0, + #endif +}; +static uint8_t ch_9bit[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + 0, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + 0, + #endif +}; +static uint8_t tx_buf[SCI_IDX_MAX][SCI_TX_BUF_SIZE]; +static uint8_t rx_buf[SCI_IDX_MAX][SCI_RX_BUF_SIZE]; +static volatile sci_fifo tx_fifo[SCI_IDX_MAX]; +static volatile sci_fifo rx_fifo[SCI_IDX_MAX]; +static uint32_t m_cts_pin[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + PIN_END, + #endif +}; +static uint32_t m_rts_pin[] = { + #if defined(VECTOR_NUMBER_SCI0_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI1_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI2_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI3_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI4_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI5_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI6_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI7_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI8_RXI) + PIN_END, + #endif + #if defined(VECTOR_NUMBER_SCI9_RXI) + PIN_END, + #endif +}; + +static void delay_us(volatile unsigned int us) { + us *= 48; + while (us-- > 0) { + ; + } +} + +bool ra_af_find_ch_af(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint32_t *ch, uint32_t *af) { + bool find = false; + uint32_t i; + for (i = 0; i < size; i++) { + if (af_pin->pin == pin) { + find = true; + *ch = af_pin->ch; + *af = af_pin->af; + break; + } + af_pin++; + } + return find; +} + +static void ra_sci_tx_set_pin(uint32_t pin) { + bool find = false; + uint32_t ch; + uint32_t af; + find = ra_af_find_ch_af((ra_af_pin_t *)&ra_sci_tx_pins, SCI_TX_PINS_SIZE, pin, &ch, &af); + if (find) { + ra_gpio_config(pin, GPIO_MODE_AF_PP, 0, 0, af); + } +} + +static void ra_sci_rx_set_pin(uint32_t pin) { + bool find = false; + uint32_t ch; + uint32_t af; + find = ra_af_find_ch_af((ra_af_pin_t *)&ra_sci_rx_pins, SCI_RX_PINS_SIZE, pin, &ch, &af); + if (find) { + ra_gpio_config(pin, GPIO_MODE_INPUT, 1, 0, af); + } +} + +static void ra_sci_cts_set_pin(uint32_t pin) { + bool find = false; + uint32_t ch; + uint32_t af; + find = ra_af_find_ch_af((ra_af_pin_t *)&ra_sci_cts_pins, SCI_CTS_PINS_SIZE, pin, &ch, &af); + if (find) { + ra_gpio_config(pin, GPIO_MODE_INPUT, 1, 0, af); + } +} + +static void ra_sci_module_start(uint32_t ch) { + ra_mstpcrb_start(sci_module_mask[ch_to_idx[ch]]); +} + +static void ra_sci_module_stop(uint32_t ch) { + ra_mstpcrb_stop(sci_module_mask[ch_to_idx[ch]]); +} + +void ra_sci_rx_set_callback(int ch, SCI_CB cb) { + sci_cb[ch_to_idx[ch]] = cb; +} + +static void ra_sci_irq_disable(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + R_BSP_IrqDisable(idx_to_rxirq[idx]); + R_BSP_IrqDisable(idx_to_txirq[idx]); + R_BSP_IrqDisable(idx_to_teirq[idx]); + R_BSP_IrqDisable(idx_to_erirq[idx]); + R_BSP_IrqStatusClear(idx_to_rxirq[idx]); + R_BSP_IrqStatusClear(idx_to_txirq[idx]); + R_BSP_IrqStatusClear(idx_to_teirq[idx]); + R_BSP_IrqStatusClear(idx_to_erirq[idx]); +} + +static void ra_sci_irq_enable(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + R_BSP_IrqEnable(idx_to_rxirq[idx]); + R_BSP_IrqEnable(idx_to_txirq[idx]); + R_BSP_IrqEnable(idx_to_teirq[idx]); + R_BSP_IrqEnable(idx_to_erirq[idx]); +} + +void ra_sci_rxirq_disable(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + R_BSP_IrqDisable(idx_to_rxirq[idx]); +} + +void ra_sci_rxirq_enable(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + R_BSP_IrqEnable(idx_to_rxirq[idx]); +} + +bool ra_sci_is_rxirq_enable(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + uint32_t _irq = (uint32_t)idx_to_rxirq[idx]; + return NVIC->ISER[(_irq >> 5UL)] == (uint32_t)(1UL << (_irq & 0x1FUL)); +} + +static void ra_sci_irq_priority(uint32_t ch, uint32_t ipl) { + uint32_t idx = ch_to_idx[ch]; + R_BSP_IrqCfg(idx_to_rxirq[idx], ipl, (void *)NULL); + R_BSP_IrqCfg(idx_to_txirq[idx], ipl, (void *)NULL); + R_BSP_IrqCfg(idx_to_teirq[idx], ipl, (void *)NULL); + R_BSP_IrqCfg(idx_to_erirq[idx], ipl, (void *)NULL); +} + +static void ra_sci_isr_rx(uint32_t ch) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t idx = ch_to_idx[ch]; + uint16_t d; + if (ch_9bit[idx]) { + d = (uint16_t)sci_regs[idx]->RDRHL; + } else { + d = (uint16_t)sci_regs[idx]->RDR; + } + if (sci_cb[idx]) { + if ((*sci_cb[idx])(ch, (int)d)) { + // goto ra_sci_isr_rx_exit; + } + } + uint32_t size = rx_fifo[idx].size; + sci_fifo *rxfifo = (sci_fifo *)&rx_fifo[idx]; + if (rxfifo->len < size) { + uint32_t i = rxfifo->head; + if (ch_9bit[idx]) { + *(uint16_t *)(rxfifo->bufp + i) = (uint16_t)d; + i += 2; + rxfifo->len += 2; + } else { + *(rxfifo->bufp + i) = (uint8_t)d; + i++; + rxfifo->len++; + } + rxfifo->head = i % size; + if (m_rts_pin[idx] != PIN_END) { + if (rxfifo->len > (size - RA_SCI_FLOW_START_NUM)) { + ra_gpio_write(m_rts_pin[idx], 1); + } + } + } +// ra_sci_isr_rx_exit: + R_BSP_IrqStatusClear(irq); +} + +static void ra_sci_isr_er(uint32_t ch) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + R_BSP_IrqStatusClear(irq); + uint32_t idx = ch_to_idx[ch]; + R_SCI0_Type *sci_reg = sci_regs[idx]; + sci_reg->RDR; + while (0 != (sci_reg->SSR & 0x38)) { + sci_reg->RDR; + sci_reg->SSR = (uint8_t)((sci_reg->SSR & ~0x38) | 0xc0); + if (0 != (sci_reg->SSR & 0x38)) { + __asm__ __volatile__ ("nop"); + } + } +} + +static void ra_sci_isr_tx(uint32_t ch) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t idx = ch_to_idx[ch]; + uint32_t size = tx_fifo[idx].size; + sci_fifo *txfifo = (sci_fifo *)&tx_fifo[idx]; + if (txfifo->len != 0) { + uint32_t i = txfifo->tail; + if (ch_9bit[idx]) { + sci_regs[idx]->TDRHL = *(uint16_t *)(txfifo->bufp + i); + i += 2; + txfifo->len -= 2; + } else { + sci_regs[idx]->TDR = (uint8_t)*(txfifo->bufp + i); + i++; + txfifo->len--; + } + txfifo->tail = i % size; + } else { + /* tx_fifo[idx].len == 0 */ + /* after transfer completed */ + uint8_t scr = sci_regs[idx]->SCR; + scr &= (uint8_t) ~0x80; /* TIE disable */ + scr |= (uint8_t)0x04; /* TEIE enable */ + sci_regs[idx]->SCR = scr; + } + R_BSP_IrqStatusClear(irq); +} + +void ra_sci_isr_te(uint32_t ch) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t idx = ch_to_idx[ch]; + tx_fifo[idx].busy = 0; + sci_regs[idx]->SCR &= (uint8_t) ~0x84; /* TIE and TEIE disable */ + R_BSP_IrqStatusClear(irq); +} + +int ra_sci_rx_ch(uint32_t ch) { + uint16_t c; + uint32_t idx = ch_to_idx[ch]; + uint32_t size = rx_fifo[idx].size; + sci_fifo *rxfifo = (sci_fifo *)&rx_fifo[idx]; + if (rxfifo->len) { + uint32_t state = ra_disable_irq(); + uint32_t i = rxfifo->tail; + if (ch_9bit[idx]) { + c = *(uint16_t *)(rxfifo->bufp + i); + i += 2; + rxfifo->len -= 2; + } else { + c = (uint16_t)*(rxfifo->bufp + i); + i++; + rxfifo->len--; + } + rxfifo->tail = i % size; + if (m_rts_pin[idx] != PIN_END) { + if (rxfifo->len <= (size - RA_SCI_FLOW_START_NUM)) { + ra_gpio_write(m_rts_pin[idx], 0); + } + } + ra_enable_irq(state); + } else { + c = 0; + } + return (int)c; +} + +int ra_sci_rx_any(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + return (int)(rx_fifo[idx].len != 0); +} + +void ra_sci_tx_ch(uint32_t ch, int c) { + uint32_t idx = ch_to_idx[ch]; + uint32_t size = tx_fifo[idx].size; + sci_fifo *txfifo = (sci_fifo *)&tx_fifo[idx]; + while (tx_fifo[idx].len == size) { + } + uint32_t state = ra_disable_irq(); + uint32_t i = tx_fifo[idx].head; + if (ch_9bit[idx]) { + *(uint16_t *)(txfifo->bufp + i) = (uint16_t)c; + i += 2; + txfifo->len += 2; + } else { + *(txfifo->bufp + i) = (uint8_t)c; + i++; + txfifo->len++; + } + txfifo->head = i % size; + if (!txfifo->busy) { + txfifo->busy = 1; + uint8_t scr = sci_regs[idx]->SCR; + if ((scr & 0xa0) != 0) { + sci_regs[idx]->SCR &= ~0xa0; + } + sci_regs[idx]->SCR |= 0xa0; /* TIE and TE enable */ + } + ra_enable_irq(state); +} + +int ra_sci_tx_wait(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + return (int)(tx_fifo[idx].len != (tx_fifo[idx].size - 1)); +} + +void ra_sci_tx_break(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + R_SCI0_Type *sci_reg = sci_regs[idx]; + uint8_t scr = sci_reg->SCR; + uint8_t smr = sci_reg->SMR; + sci_reg->SCR = 0; + while (sci_reg->SCR != 0) { + ; + } + sci_reg->SMR_b.STOP = 1; + sci_reg->SCR = scr; + sci_reg->TDR = 0; + while (sci_reg->SSR_b.TDRE == 0) { + ; + } + sci_reg->SMR = smr; + return; +} + +void ra_sci_tx_str(uint32_t ch, uint8_t *p) { + int c; + uint32_t idx = ch_to_idx[ch]; + if (ch_9bit[idx]) { + uint16_t *q = (uint16_t *)p; + while ((c = *q++) != 0) { + ra_sci_tx_ch(ch, (int)c); + } + } else { + while ((c = (int)*p++) != 0) { + ra_sci_tx_ch(ch, (int)c); + } + } +} + +static void ra_sci_fifo_set(sci_fifo *fifo, uint8_t *bufp, uint32_t size) { + fifo->head = 0; + fifo->tail = 0; + fifo->len = 0; + fifo->busy = 0; + fifo->bufp = bufp; + fifo->size = size; +} + +void ra_sci_txfifo_set(uint32_t ch, uint8_t *bufp, uint32_t size) { + uint32_t idx = ch_to_idx[ch]; + sci_fifo *fifo = (sci_fifo *)&tx_fifo[idx]; + ra_sci_fifo_set(fifo, bufp, size); +} + +void ra_sci_rxfifo_set(uint32_t ch, uint8_t *bufp, uint32_t size) { + uint32_t idx = ch_to_idx[ch]; + sci_fifo *fifo = (sci_fifo *)&rx_fifo[idx]; + ra_sci_fifo_set(fifo, bufp, size); +} + +static void ra_sci_fifo_init(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + ra_sci_txfifo_set(ch, (uint8_t *)&tx_buf[idx][0], SCI_TX_BUF_SIZE); + ra_sci_rxfifo_set(ch, (uint8_t *)&rx_buf[idx][0], SCI_RX_BUF_SIZE); +} + +void ra_sci_set_baud(uint32_t ch, uint32_t baud) { + uint32_t idx = ch_to_idx[ch]; + R_SCI0_Type *sci_reg = sci_regs[idx]; + // Only works for 115200 bps + // ToDo: support other bps + if (baud == 0) { + /* ABCS=1 */ + sci_reg->SMR_b.CKS = 0; /* PCLKA */ + sci_reg->BRR = (uint8_t)((int)PCLK / SCI_DEF_BAUD / 16 - 1); + } else if (baud > 19200) { + /* ABCS=1 */ + sci_reg->SMR_b.CKS = 0; /* PCLKA */ + sci_reg->BRR = (uint8_t)((int)PCLK / baud / 16 - 1); + } else { + /* ABCS=1 */ + sci_reg->SMR_b.CKS = 2; /* PCLKA/16 */ + sci_reg->BRR = (uint8_t)((int)PCLK / baud / 256 - 1); + } +} + +/* + * bits: 7, 8, 9 + * parity: none:0, odd:1, even:2 + */ +void ra_sci_init_with_flow(uint32_t ch, uint32_t tx_pin, uint32_t rx_pin, uint32_t baud, uint32_t bits, uint32_t parity, uint32_t stop, uint32_t flow, uint32_t cts_pin, uint32_t rts_pin) { + uint8_t smr = 0; + uint8_t scmr = (uint8_t)0xf2; + uint32_t idx = ch_to_idx[ch]; + R_SCI0_Type *sci_reg = sci_regs[idx]; + if (ra_sci_init_flag[idx] == 0) { + ra_sci_fifo_init(ch); + sci_cb[idx] = 0; + ra_sci_init_flag[idx]++; + } else { + ra_sci_init_flag[idx]++; + return; + } + ra_sci_module_start(ch); + ra_sci_tx_set_pin(tx_pin); + ra_sci_rx_set_pin(rx_pin); + if (flow) { + if (cts_pin != (uint32_t)PIN_END) { + m_cts_pin[idx] = cts_pin; + ra_sci_cts_set_pin(cts_pin); + } + if (rts_pin != (uint32_t)PIN_END) { + m_rts_pin[idx] = rts_pin; + ra_gpio_config(rts_pin, GPIO_MODE_OUTPUT_PP, false, 0, 0); + ra_gpio_write(rts_pin, 0); + } + } + ra_sci_irq_disable(ch); + ra_sci_irq_priority(ch, RA_PRI_UART); + uint32_t state = ra_disable_irq(); + sci_reg->SCR = 0; + while (sci_reg->SCR != 0) { + ; + } + if (bits == 7) { + smr |= (uint8_t)0x40; + } else { + smr &= (uint8_t) ~0x40; + } + if (parity != 0) { + smr |= (uint8_t)0x20; + } else { + smr &= (uint8_t) ~0x20; + } + if (parity == 1) { + smr |= (uint8_t)0x10; + } else { + smr &= (uint8_t) ~0x10; + } + if (stop == 2) { + smr |= (uint8_t)0x80; + } else { + smr &= (uint8_t) ~0x80; + } + sci_reg->SMR = smr; + if (bits == 9) { + scmr &= (uint8_t) ~0x10; + ch_9bit[idx] = 1; + } else { + scmr |= (uint8_t)0x10; + ch_9bit[idx] = 0; + } + if (flow) { + sci_reg->SPMR |= 0x01; + } + sci_reg->SCMR = scmr; + sci_reg->SEMR = (uint8_t)0xc0; + ra_sci_set_baud(ch, baud); + delay_us(10); + sci_reg->SCR = (uint8_t)0x50; + ra_sci_irq_enable(ch); + ra_enable_irq(state); + if (!ra_sci_init_flag[idx]) { + ra_sci_init_flag[idx] = true; + } +} + +void ra_sci_init(uint32_t ch, uint32_t tx_pin, uint32_t rx_pin, uint32_t baud, uint32_t bits, uint32_t parity, uint32_t stop, uint32_t flow) { + ra_sci_init_with_flow(ch, tx_pin, rx_pin, baud, bits, parity, stop, flow, PIN_END, PIN_END); +} + +void ra_sci_deinit(uint32_t ch) { + uint32_t idx = ch_to_idx[ch]; + if (ra_sci_init_flag[idx] != 0) { + ra_sci_init_flag[idx]--; + if (ra_sci_init_flag[idx] == 0) { + ra_sci_irq_disable(ch); + ra_sci_module_stop(ch); + sci_cb[idx] = 0; + } + } +} + +/* rx interrupt */ +void sci_uart_rxi_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = irq_to_ch[(uint32_t)irq]; + ra_sci_isr_rx(ch); +} + +/* tx interrupt */ +void sci_uart_txi_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = irq_to_ch[(uint32_t)irq]; + ra_sci_isr_tx(ch); +} + +/* er interrupt */ +void sci_uart_eri_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = irq_to_ch[(uint32_t)irq]; + ra_sci_isr_er(ch); +} + +/* te interrupt */ +void sci_uart_tei_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = irq_to_ch[(uint32_t)irq]; + ra_sci_isr_te(ch); +} diff --git a/ports/renesas-ra/ra/ra_sci.h b/ports/renesas-ra/ra/ra_sci.h new file mode 100644 index 000000000..0a672f367 --- /dev/null +++ b/ports/renesas-ra/ra/ra_sci.h @@ -0,0 +1,72 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef PORTS_RA_RA_RA_SCI_H_ +#define PORTS_RA_RA_RA_SCI_H_ + +#include <stdint.h> + +#define RA_SCI_FLOW_START_NUM (16) + +typedef int (*SCI_CB)(uint32_t ch, uint32_t d); + +// static bool find_irq_to_ch(IRQn_Type *irq_tbl, IRQn_Type irq, uint32_t *ch); +// static void delay_us(volatile unsigned int us); +bool ra_af_find_ch_af(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint32_t *ch, uint32_t *af); +// static void ra_sci_tx_set_pin(uint32_t pin); +// static void ra_sci_rx_set_pin(uint32_t pin); +// static void ra_sci_cts_set_pin(uint32_t pin); +// static void ra_sci_module_start(uint32_t ch); +// static void ra_sci_module_stop(uint32_t ch); +void ra_sci_rx_set_callback(int ch, SCI_CB cb); +// static void ra_sci_irq_disable(uint32_t ch); +// static void ra_sci_irq_enable(uint32_t ch); +void ra_sci_rxirq_disable(uint32_t ch); +void ra_sci_rxirq_enable(uint32_t ch); +bool ra_sci_is_rxirq_enable(uint32_t ch); +// static void ra_sci_irq_priority(uint32_t ch, uint32_t ipl); +// static void ra_sci_isr_rx(uint32_t ch); +// static void ra_sci_isr_er(uint32_t ch); +// static void ra_sci_isr_tx(uint32_t ch); +void ra_sci_isr_te(uint32_t ch); +int ra_sci_rx_ch(uint32_t ch); +int ra_sci_rx_any(uint32_t ch); +void ra_sci_tx_ch(uint32_t ch, int c); +int ra_sci_tx_wait(uint32_t ch); +void ra_sci_tx_break(uint32_t ch); +void ra_sci_tx_str(uint32_t ch, uint8_t *p); +// static void ra_sci_fifo_set(sci_fifo *fifo, uint8_t *bufp, uint32_t size); +void ra_sci_txfifo_set(uint32_t ch, uint8_t *bufp, uint32_t size); +void ra_sci_rxfifo_set(uint32_t ch, uint8_t *bufp, uint32_t size); +// static void sci_fifo_init(uint32_t ch); +void ra_sci_set_baud(uint32_t ch, uint32_t baud); +void ra_sci_init_with_flow(uint32_t ch, uint32_t tx_pin, uint32_t rx_pin, uint32_t baud, uint32_t bits, uint32_t parity, uint32_t stop, uint32_t flow, uint32_t cts_pin, uint32_t rts_pin); +void ra_sci_init(uint32_t ch, uint32_t tx_pin, uint32_t rx_pin, uint32_t baud, uint32_t bits, uint32_t parity, uint32_t stop, uint32_t flow); +void ra_sci_deinit(uint32_t ch); +void sci_uart_rxi_isr(void); +void sci_uart_txi_isr(void); +void sci_uart_eri_isr(void); +void sci_uart_tei_isr(void); + +#endif /* PORTS_RA_RA_RA_SCI_H_ */ diff --git a/ports/renesas-ra/ra/ra_spi.c b/ports/renesas-ra/ra/ra_spi.c new file mode 100644 index 000000000..b7f78cd6d --- /dev/null +++ b/ports/renesas-ra/ra/ra_spi.c @@ -0,0 +1,457 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_data.h" +#include "ra_config.h" +#include "ra_gpio.h" +#include "ra_utils.h" +#include "ra_spi.h" + +#if defined(__GNUC__) +#pragma GCC diagnostic ignored "-Wunused-parameter" +#pragma GCC diagnostic ignored "-Wconversion" +// #pragma GCC diagnostic ignored "-Wshift-negative-value" +// #pragma GCC diagnostic ignored "-Wunused-but-set-variable" +// #pragma GCC diagnostic ignored "-Wsequence-point" +// #pragma GCC diagnostic ignored "-Wunused-function" +#endif + +static R_SPI0_Type *spi_regs[] = { + (R_SPI0_Type *)0x40072000, + (R_SPI0_Type *)0x40072100, +}; + +static const ra_af_pin_t mosi_pins[] = { + #if defined(RA4M1) + + { AF_SPI, 0, P101 }, /* MOSIA */ + { AF_SPI, 0, P411 }, /* MOSIA */ + { AF_SPI, 1, P109 }, /* MOSIB */ + { AF_SPI, 1, P203 }, /* MOSIB */ + + #elif defined(RA4W1) + + { AF_SPI, 0, P101 }, /* MOSIA */ + { AF_SPI, 1, P109 }, /* MOSIB */ + + #elif defined(RA6M1) + + { AF_SPI, 0, P101 }, /* MOSIA_A */ + { AF_SPI, 0, P411 }, /* MOSIA_B */ + { AF_SPI, 1, P109 }, /* MOSIB_B */ + + #elif defined(RA6M2) + + { AF_SPI, 0, P101 }, /* MOSIA_A */ + { AF_SPI, 0, P411 }, /* MOSIA_B */ + { AF_SPI, 1, P109 }, /* MOSIB_B */ + { AF_SPI, 1, P203 }, /* MOSIB_A */ + { AF_SPI, 1, P701 }, /* MOSIB_C */ + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define MOSI_PINS_SIZE sizeof(mosi_pins) / sizeof(ra_af_pin_t) + +static const ra_af_pin_t miso_pins[] = { + #if defined(RA4M1) + + { AF_SPI, 0, P100 }, /* MISOA */ + { AF_SPI, 0, P410 }, /* MISOA */ + { AF_SPI, 1, P110 }, /* MISOB */ + { AF_SPI, 1, P202 }, /* MISOB */ + + #elif defined(RA4W1) + + { AF_SPI, 0, P100 }, /* MISOA */ + { AF_SPI, 1, P110 }, /* MISOB */ + + #elif defined(RA6M1) + + { AF_SPI, 0, P100 }, /* MISOA_A */ + { AF_SPI, 0, P410 }, /* MISOA_B */ + { AF_SPI, 1, P110 }, /* MISOB_B */ + + #elif defined(RA6M2) + + { AF_SPI, 0, P100 }, /* MISOA_A */ + { AF_SPI, 0, P410 }, /* MISOA_B */ + { AF_SPI, 1, P110 }, /* MISOB_B */ + { AF_SPI, 1, P202 }, /* MISOB_A */ + { AF_SPI, 1, P700 }, /* MISOB_C */ + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define MISO_PINS_SIZE sizeof(miso_pins) / sizeof(ra_af_pin_t) + +static const ra_af_pin_t sck_pins[] = { + #if defined(RA4M1) + + { AF_SPI, 0, P102 }, /* RSPCKA */ + { AF_SPI, 0, P412 }, /* RSPCKA */ + { AF_SPI, 1, P111 }, /* RSPCKB */ + { AF_SPI, 1, P204 }, /* RSPCKB */ + + #elif defined(RA4W1) + + { AF_SPI, 0, P102 }, /* RSPCKA */ + { AF_SPI, 1, P111 }, /* RSPCKB */ + + #elif defined(RA6M1) + + { AF_SPI, 0, P102 }, /* RSPCKA_A */ + { AF_SPI, 0, P412 }, /* RSPCKA_B */ + { AF_SPI, 1, P111 }, /* RSPCKB_B */ + + #elif defined(RA6M2) + + { AF_SPI, 0, P102 }, /* RSPCKA_A */ + { AF_SPI, 0, P412 }, /* RSPCKA_B */ + { AF_SPI, 1, P111 }, /* RSPCKB_B */ + { AF_SPI, 1, P204 }, /* RSPCKB_A */ + { AF_SPI, 1, P702 }, /* RSPCKB_C */ + + #else + #error "CMSIS MCU Series is not specified." + #endif +}; +#define SCK_PINS_SIZE sizeof(sck_pins) / sizeof(ra_af_pin_t) + +bool ra_af_find_ch(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint8_t *ch) { + bool find = false; + uint32_t i; + for (i = 0; i < size; i++) { + if (af_pin->pin == pin) { + find = true; + *ch = af_pin->ch; + break; + } + af_pin++; + } + return find; +} + +bool ra_spi_find_af_ch(uint32_t mosi, uint32_t miso, uint32_t sck, uint8_t *ch) { + bool find = false; + uint8_t mosi_ch; + uint8_t miso_ch; + uint8_t sck_ch; + find = ra_af_find_ch((ra_af_pin_t *)&mosi_pins, MOSI_PINS_SIZE, mosi, &mosi_ch); + if (find) { + find = ra_af_find_ch((ra_af_pin_t *)&miso_pins, MISO_PINS_SIZE, miso, &miso_ch); + if (find) { + find = ra_af_find_ch((ra_af_pin_t *)&sck_pins, SCK_PINS_SIZE, sck, &sck_ch); + if (find) { + find = (mosi_ch == miso_ch) && (miso_ch == sck_ch); + if (find) { + *ch = mosi_ch; + } else { + *ch = 0; + } + } + } + } + return find; +} + +static void ra_spi_module_start(uint32_t ch) { + if (ch == 0) { + ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB19_Msk); + } else { + ra_mstpcrb_start(R_MSTP_MSTPCRB_MSTPB18_Msk); + } +} + +static void ra_spi_module_stop(uint32_t ch) { + if (ch == 0) { + ra_mstpcrb_stop(R_MSTP_MSTPCRB_MSTPB19_Msk); + } else { + ra_mstpcrb_stop(R_MSTP_MSTPCRB_MSTPB18_Msk); + } +} + +static void ra_spi_set_pin(uint32_t pin, bool miso) { + if (miso) { + ra_gpio_config(pin, GPIO_MODE_INPUT, 1, 0, AF_SPI); + } else { + ra_gpio_config(pin, GPIO_MODE_AF_PP, 0, 0, AF_SPI); + } +} + +void ra_spi_set_bits(uint32_t ch, uint32_t bits) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + if (bits == 8) { + spi_reg->SPDCR_b.SPBYT = 1; + spi_reg->SPDCR_b.SPLW = 0; + spi_reg->SPCMD_b[0].SPB = 0x7; + } else if (bits == 16) { + spi_reg->SPDCR_b.SPBYT = 0; + spi_reg->SPDCR_b.SPLW = 0; + spi_reg->SPCMD_b[0].SPB = 0xf; + } else if (bits == 32) { + spi_reg->SPDCR_b.SPBYT = 0; + spi_reg->SPDCR_b.SPLW = 1; + spi_reg->SPCMD_b[0].SPB = 0x3; + } +} + +void ra_spi_set_clk(uint32_t ch, uint32_t baud) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + if (baud == 0) { + return; + } + spi_reg->SPCR_b.SPE = 0; + spi_reg->SPBR = (PCLK / 2 / baud) - 1; + spi_reg->SPCR_b.SPE = 1; +} + +void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + if (lsb_first) { + spi_reg->SPCMD_b[0].LSBF = 1; // LSB first + } else { + spi_reg->SPCMD_b[0].LSBF = 0; // MSB first + } +} + +void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + if (polarity != 0) { + // CPOL(Clock Polarity) + spi_reg->SPCMD_b[0].CPOL = 1; + } else { + spi_reg->SPCMD_b[0].CPOL = 0; + } + if (phase != 0) { + // CPHA(Clock Phase) + spi_reg->SPCMD_b[0].CPHA = 1; + } else { + spi_reg->SPCMD_b[0].CPHA = 0; + } +} + +void ra_spi_set_ch(uint32_t ch) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + spi_reg->SPCR = 0x00; // disable SPI + spi_reg->SPSR = 0xa0; + spi_reg->SPPCR = 0x00; // fixed idle value, disable loop-back mode + spi_reg->SPSCR = 0x00; // Disable sequence control + spi_reg->SPDCR = 0x40; // SPBYT=1, SPLW=0 byte access + spi_reg->SPCMD[0] = 0xe700; // LSBF=0, SPB=7, BRDV=0, CPOL=0, CPHA=0 + spi_reg->SPCR2 = 0x10; + spi_reg->SPCR = 0x48; // Start SPI in master mode +} + +uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR_BY = (uint8_t)(b); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + return (uint8_t)(spi_reg->SPDR_BY); +} + +void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 8); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR_BY = (uint8_t)(*buf++); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + spi_reg->SPDR_BY; + } +} + +void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 8); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR_BY = (uint8_t)(0); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + *buf++ = (uint8_t)spi_reg->SPDR_BY; + } +} + +void ra_spi_write_bytes16(uint32_t ch, uint16_t *buf, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 16); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR_HA = (uint16_t)(*buf++); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + spi_reg->SPDR_HA; + } +} + +void ra_spi_write_bytes32(uint32_t ch, uint32_t *buf, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 32); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR = (uint32_t)(*buf++); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + spi_reg->SPDR; + } +} + +void ra_spi_write_bytes(uint32_t ch, uint32_t bits, uint8_t *buf, uint32_t count) { + if (bits == 8) { + ra_spi_write_bytes8(ch, buf, count); + } else if (bits == 16) { + ra_spi_write_bytes16(ch, (uint16_t *)buf, count >> 1); + } else if (bits == 32) { + ra_spi_write_bytes32(ch, (uint32_t *)buf, count >> 2); + } +} + +void ra_spi_transfer8(uint32_t ch, uint8_t *dst, uint8_t *src, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 8); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR_BY = (uint8_t)(*src++); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + *dst++ = (uint8_t)(spi_reg->SPDR_BY); + } +} + +void ra_spi_transfer16(uint32_t ch, uint16_t *dst, uint16_t *src, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 16); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR_HA = (uint16_t)(*src++); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + *dst++ = (uint16_t)(spi_reg->SPDR_HA); + } +} + +void ra_spi_transfer32(uint32_t ch, uint32_t *dst, uint32_t *src, uint32_t count) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + ra_spi_set_bits(ch, 32); + while (count-- > 0) { + while (spi_reg->SPSR_b.SPTEF == 0) { + ; + } + spi_reg->SPDR = (uint32_t)(*src++); + while (spi_reg->SPSR_b.SPRF == 0) { + ; + } + *dst++ = (uint32_t)(spi_reg->SPDR); + } +} + +void ra_spi_transfer(uint32_t ch, uint32_t bits, uint8_t *dst, uint8_t *src, uint32_t count, uint32_t timeout) { + if (bits == 8) { + ra_spi_transfer8(ch, dst, src, count); + } else if (bits == 16) { + ra_spi_transfer16(ch, (uint16_t *)dst, (uint16_t *)src, count >> 1); + } else if (bits == 32) { + ra_spi_transfer32(ch, (uint32_t *)dst, (uint32_t *)src, count >> 2); + } +} + +void ra_spi_start_xfer(uint32_t ch, uint16_t spcmd, uint8_t spbr) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + spi_reg->SPCR_b.SPE = 0; // disable + spi_reg->SPCMD[0] = spcmd; + spi_reg->SPBR = spbr; + spi_reg->SPCR_b.SPE = 1; // enable +} + +void ra_spi_end_xfer(uint32_t ch) { + (void)ch; +} + +void ra_spi_get_conf(uint32_t ch, uint16_t *spcmd, uint8_t *spbr) { + R_SPI0_Type *spi_reg = (R_SPI0_Type *)spi_regs[ch]; + *spcmd = spi_reg->SPCMD[0]; + *spbr = spi_reg->SPBR; +} + +void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase) { + ra_gpio_mode_output(cs); + ra_gpio_write(cs, 1); + ra_spi_module_start(ch); + ra_spi_set_pin(mosi, false); + ra_spi_set_pin(miso, true); + ra_spi_set_pin(sck, false); + ra_spi_set_mode(ch, polarity, phase); + ra_spi_set_ch(ch); + ra_spi_set_clk(ch, baud); + ra_spi_set_bits(ch, bits); + ra_spi_set_lsb_first(ch, 0); // MSB first + return; +} + +void ra_spi_deinit(uint32_t ch, uint32_t cs) { + ra_spi_module_stop(ch); +} + +__WEAK void spi_rxi_isr(void) { + // dummy +} + +__WEAK void spi_txi_isr(void) { + // dummy +} + +__WEAK void spi_tei_isr(void) { + // dummy +} + +__WEAK void spi_eri_isr(void) { + // dummy +} diff --git a/ports/renesas-ra/ra/ra_spi.h b/ports/renesas-ra/ra/ra_spi.h new file mode 100644 index 000000000..e75acf870 --- /dev/null +++ b/ports/renesas-ra/ra/ra_spi.h @@ -0,0 +1,63 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_SPI_H_ +#define RA_RA_SPI_H_ + +#include <stdint.h> +#include <stdbool.h> + +#include "ra_config.h" +#include "ra_gpio.h" + +bool ra_af_find_ch(ra_af_pin_t *af_pin, uint32_t size, uint32_t pin, uint8_t *ch); +bool ra_spi_find_af_ch(uint32_t mosi, uint32_t miso, uint32_t sck, uint8_t *ch); + +// static void ra_spi_module_start(uint32_t ch); +// static void ra_spi_module_stop(uint32_t ch); +// static void ra_spi_set_pin(uint8_t pin); + +void ra_spi_set_bits(uint32_t ch, uint32_t bits); +void ra_spi_set_clk(uint32_t ch, uint32_t baud); +void ra_spi_set_lsb_first(uint32_t ch, uint32_t lsb_first); +void ra_spi_set_mode(uint32_t ch, uint32_t polarity, uint32_t phase); +void ra_spi_set_ch(uint32_t ch); + +uint8_t ra_spi_write_byte(uint32_t ch, uint8_t b); +void ra_spi_read_bytes8(uint32_t ch, uint8_t *buf, uint32_t count); +void ra_spi_write_bytes8(uint32_t ch, uint8_t *buf, uint32_t count); +void ra_spi_write_bytes16(uint32_t ch, uint16_t *buf, uint32_t count); +void ra_spi_write_bytes32(uint32_t ch, uint32_t *buf, uint32_t count); +void ra_spi_write_bytes(uint32_t ch, uint32_t bits, uint8_t *buf, uint32_t count); +void ra_spi_transfer8(uint32_t ch, uint8_t *dst, uint8_t *src, uint32_t count); +void ra_spi_transfer16(uint32_t ch, uint16_t *dst, uint16_t *src, uint32_t count); +void ra_spi_transfer32(uint32_t ch, uint32_t *dst, uint32_t *src, uint32_t count); +void ra_spi_transfer(uint32_t ch, uint32_t bits, uint8_t *dst, uint8_t *src, uint32_t count, uint32_t timeout); +void ra_spi_start_xfer(uint32_t ch, uint16_t spcmd, uint8_t spbr); +void ra_spi_end_xfer(uint32_t ch); +void ra_spi_get_conf(uint32_t ch, uint16_t *spcmd, uint8_t *spbr); +void ra_spi_init(uint32_t ch, uint32_t mosi, uint32_t miso, uint32_t sck, uint32_t cs, uint32_t baud, uint32_t bits, uint32_t polarity, uint32_t phase); +void ra_spi_deinit(uint32_t ch, uint32_t cs); + +#endif /* RA_RA_SPI_H_ */ diff --git a/ports/renesas-ra/ra/ra_timer.c b/ports/renesas-ra/ra/ra_timer.c new file mode 100644 index 000000000..5f2adcdfa --- /dev/null +++ b/ports/renesas-ra/ra/ra_timer.c @@ -0,0 +1,155 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <stdint.h> +#include <stdbool.h> +#include "hal_data.h" +#include "ra_config.h" +#include "ra_int.h" +#include "ra_utils.h" +#include "ra_timer.h" + +#define AGT_CH_SIZE 2 + +enum AGT_SOURCE { + AGT_PCLKB = 0, + AGT_PCLKB8, + AGT_PCLKB2 = 3, + AGT_AGTKCLK, + AGT_AGT0UNDER, + AGT_AGTSCLK +}; + +static R_AGT0_Type *agt_regs[AGT_CH_SIZE] = { + (R_AGT0_Type *)0x40084000, + (R_AGT0_Type *)0x40084100 +}; + +static uint8_t ch_to_irq[AGT_CH_SIZE] = { + #if defined(VECTOR_NUMBER_AGT0_INT) + VECTOR_NUMBER_AGT0_INT, + #else + 0, + #endif + #if defined(VECTOR_NUMBER_AGT1_INT) + VECTOR_NUMBER_AGT1_INT, + #else + 0, + #endif +}; +static float ra_agt_freq[AGT_CH_SIZE]; +static volatile uint32_t ra_agt_counter[AGT_CH_SIZE]; +static AGT_TIMER_CB ra_agt_timer_cb[AGT_CH_SIZE]; +static void *ra_agt_timer_param[AGT_CH_SIZE]; + +void ra_agt_timer_set_callback(uint32_t ch, AGT_TIMER_CB cb, void *param) { + ra_agt_timer_cb[ch] = cb; + ra_agt_timer_param[ch] = param; +} + +static void ra_agt_timer_chk_callback(uint32_t ch) { + ra_agt_counter[ch] += 1; + if (ra_agt_timer_cb[ch]) { + (*ra_agt_timer_cb[ch])(ra_agt_timer_param[ch]); + } +} + +void ra_agt_timer_start(uint32_t ch) { + agt_regs[ch]->AGTCR_b.TSTART = 1; /* start counter */ +} + +void ra_agt_timer_stop(uint32_t ch) { + agt_regs[ch]->AGTCR_b.TSTART = 0; /* stop counter */ +} + +void ra_agt_timer_set_freq(uint32_t ch, float freq) { + R_AGT0_Type *agt_reg = agt_regs[ch]; + uint8_t source = 0; + uint16_t period = 0; + uint8_t cks = 0; + ra_agt_counter[ch] = 0; + if (freq > (float)(PCLK / 2)) { + return; + } else if (freq > 1000.0) { + source = AGT_PCLKB2; + period = (uint16_t)((float)(PCLK / 2) / freq); + } else if (freq > 1.0) { + source = AGT_AGTSCLK; + cks = 2; + period = (uint16_t)((float)(32768 / 4) / freq); + } else if (freq > 0.01) { + source = AGT_AGTSCLK; + period = (uint16_t)((float)(32768 / 128) / freq); + cks = 7; + } else { + return; + } + ra_agt_freq[ch] = freq; + agt_reg->AGTCR_b.TSTART = 0; // stop counter + agt_reg->AGTMR2 = cks; + agt_reg->AGTMR1 = (uint8_t)(source << 4); // mode is timer mode + agt_reg->AGT = (uint16_t)period; +} + +float ra_agt_timer_get_freq(uint32_t ch) { + return ra_agt_freq[ch]; +} + +void ra_agt_timer_init(uint32_t ch, float freq) { + R_AGT0_Type *agt_reg = agt_regs[ch]; + if (ch == 0) { + ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD3_Msk); + } else { + ra_mstpcrd_start(R_MSTP_MSTPCRD_MSTPD2_Msk); + } + ra_agt_timer_set_freq(ch, freq); + agt_reg->AGTCR_b.TUNDF = 1; // underflow interrupt + R_BSP_IrqCfgEnable((IRQn_Type const)ch_to_irq[ch], RA_PRI_TIM5, (void *)NULL); +} + +void ra_agt_timer_deinit(uint32_t ch) { + NVIC_DisableIRQ((IRQn_Type const)ch_to_irq[ch]); + ra_agt_timer_stop(ch); + ra_agt_timer_cb[ch] = (AGT_TIMER_CB)0; + ra_agt_timer_param[ch] = (void *)0; + if (ch == 0) { + ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD3_Msk); + } else { + ra_mstpcrd_stop(R_MSTP_MSTPCRD_MSTPD2_Msk); + } +} + +__WEAK void agt_int_isr(void) { + IRQn_Type irq = R_FSP_CurrentIrqGet(); + uint32_t ch = irq_to_ch[(uint32_t)irq]; + R_BSP_IrqStatusClear(irq); + ra_agt_timer_chk_callback(ch); +} + +extern uint32_t uwTick; + +uint32_t mtick() { + return uwTick; +} diff --git a/ports/renesas-ra/ra/ra_timer.h b/ports/renesas-ra/ra/ra_timer.h new file mode 100644 index 000000000..a04ecd709 --- /dev/null +++ b/ports/renesas-ra/ra/ra_timer.h @@ -0,0 +1,53 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_TIMER_H_ +#define RA_RA_TIMER_H_ + +#include <stdint.h> + +void SysTick_Handler(void); +uint32_t HAL_GetTick(void); + +#define DEF_CLKDEV 2 +#define TENUSEC_COUNT (PCLK / DEF_CLKDEV / 100000) +#define MSEC_COUNT (PCLK / DEF_CLKDEV / 100) + +__attribute__((naked)) void min_delay(__attribute__((unused)) uint32_t loop_cnt); + +typedef void (*AGT_TIMER_CB)(void *); + +void ra_agt_timer_set_callback(uint32_t ch, AGT_TIMER_CB cb, void *param); +void ra_agt_int_isr0(void); +void ra_agt_int_isr1(void); +void ra_agt_timer_start(uint32_t ch); +void ra_agt_timer_stop(uint32_t ch); +void ra_agt_timer_set_freq(uint32_t ch, float freq); +float ra_agt_timer_get_freq(uint32_t ch); +void ra_agt_timer_init(uint32_t ch, float freq); +void ra_agt_timer_deinit(uint32_t ch); +__WEAK void agt_int_isr(void); +uint32_t mtick(); + +#endif /* RA_RA_TIMER_H_ */ diff --git a/ports/renesas-ra/ra/ra_utils.c b/ports/renesas-ra/ra/ra_utils.c new file mode 100644 index 000000000..94e30ded1 --- /dev/null +++ b/ports/renesas-ra/ra/ra_utils.c @@ -0,0 +1,90 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "hal_data.h" +#include "ra_config.h" +#include "ra_utils.h" + +static R_SYSTEM_Type *system_reg = (R_SYSTEM_Type *)0x4001E000; +static R_MSTP_Type *mstp_reg = (R_MSTP_Type *)0x40047000; + +void ra_mstpcra_stop(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + system_reg->MSTPCRA |= mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcra_start(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + system_reg->MSTPCRA &= ~mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcrb_stop(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + mstp_reg->MSTPCRB |= mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcrb_start(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + mstp_reg->MSTPCRB &= ~mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcrc_stop(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + mstp_reg->MSTPCRC |= mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcrc_start(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + mstp_reg->MSTPCRC &= ~mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcrd_stop(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + mstp_reg->MSTPCRD |= mod_mask; + system_reg->PRCR = 0xa500; +} + +void ra_mstpcrd_start(uint32_t mod_mask) { + system_reg->PRCR = 0xa502; + mstp_reg->MSTPCRD &= ~mod_mask; + system_reg->PRCR = 0xa500; +} + +__WEAK void ctsu_write_isr(void) { + // dummy +} + +__WEAK void ctsu_read_isr(void) { + // dummy +} + +__WEAK void ctsu_end_isr(void) { + // dummy +} diff --git a/ports/renesas-ra/ra/ra_utils.h b/ports/renesas-ra/ra/ra_utils.h new file mode 100644 index 000000000..4da30d06c --- /dev/null +++ b/ports/renesas-ra/ra/ra_utils.h @@ -0,0 +1,56 @@ +/* + * The MIT License (MIT) + * + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RA_RA_UTILS_H_ +#define RA_RA_UTILS_H_ + +#include <stdint.h> +#include <stdbool.h> + +__attribute__((always_inline)) static inline void ra_enable_irq(__attribute__((unused)) uint32_t state) { + __asm__ volatile ("cpsie f" + : + : + : "memory"); +} + +__attribute__((always_inline)) static inline uint32_t ra_disable_irq(void) { + uint32_t state; + __asm__ volatile ("cpsid f" + : "=r" (state) + : + : "memory"); + return state; +} + +void ra_mstpcra_stop(uint32_t mod_mask); +void ra_mstpcra_start(uint32_t mod_mask); +void ra_mstpcrb_stop(uint32_t mod_mask); +void ra_mstpcrb_start(uint32_t mod_mask); +void ra_mstpcrc_stop(uint32_t mod_mask); +void ra_mstpcrc_start(uint32_t mod_mask); +void ra_mstpcrd_stop(uint32_t mod_mask); +void ra_mstpcrd_start(uint32_t mod_mask); + +#endif /* RA_RA_UTILS_H_ */ diff --git a/ports/renesas-ra/ra_it.c b/ports/renesas-ra/ra_it.c new file mode 100644 index 000000000..de5a4e8da --- /dev/null +++ b/ports/renesas-ra/ra_it.c @@ -0,0 +1,244 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021, 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> + +#include "py/obj.h" +#include "py/mphal.h" +#include "ra_it.h" +#include "pendsv.h" +#include "irq.h" +#include "powerctrl.h" +#include "pybthread.h" +#include "gccollect.h" +#include "extint.h" +#include "timer.h" +#include "uart.h" +#include "storage.h" + +extern void __fatal_error(const char *); + +/******************************************************************************/ +/* Cortex-M4 Processor Exceptions Handlers */ +/******************************************************************************/ + +// Set the following to 1 to get some more information on the Hard Fault +// More information about decoding the fault registers can be found here: +// http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dui0646a/Cihdjcfc.html + +STATIC char *fmt_hex(uint32_t val, char *buf) { + const char *hexDig = "0123456789abcdef"; + + buf[0] = hexDig[(val >> 28) & 0x0f]; + buf[1] = hexDig[(val >> 24) & 0x0f]; + buf[2] = hexDig[(val >> 20) & 0x0f]; + buf[3] = hexDig[(val >> 16) & 0x0f]; + buf[4] = hexDig[(val >> 12) & 0x0f]; + buf[5] = hexDig[(val >> 8) & 0x0f]; + buf[6] = hexDig[(val >> 4) & 0x0f]; + buf[7] = hexDig[(val >> 0) & 0x0f]; + buf[8] = '\0'; + + return buf; +} + +STATIC void print_reg(const char *label, uint32_t val) { + char hexStr[9]; + + mp_hal_stdout_tx_str(label); + mp_hal_stdout_tx_str(fmt_hex(val, hexStr)); + mp_hal_stdout_tx_str("\r\n"); +} + +STATIC void print_hex_hex(const char *label, uint32_t val1, uint32_t val2) { + char hex_str[9]; + mp_hal_stdout_tx_str(label); + mp_hal_stdout_tx_str(fmt_hex(val1, hex_str)); + mp_hal_stdout_tx_str(" "); + mp_hal_stdout_tx_str(fmt_hex(val2, hex_str)); + mp_hal_stdout_tx_str("\r\n"); +} + +// The ARMv7M Architecture manual (section B.1.5.6) says that upon entry +// to an exception, that the registers will be in the following order on the +// // stack: R0, R1, R2, R3, R12, LR, PC, XPSR + +typedef struct { + uint32_t r0, r1, r2, r3, r12, lr, pc, xpsr; +} ExceptionRegisters_t; + +int pyb_hard_fault_debug = 0; + +void HardFault_C_Handler(ExceptionRegisters_t *regs) { + if (!pyb_hard_fault_debug) { + powerctrl_mcu_reset(); + } + + #if MICROPY_HW_ENABLE_USB + // We need to disable the USB so it doesn't try to write data out on + // the VCP and then block indefinitely waiting for the buffer to drain. + pyb_usb_flags = 0; + #endif + + mp_hal_stdout_tx_str("HardFault\r\n"); + + print_reg("R0 ", regs->r0); + print_reg("R1 ", regs->r1); + print_reg("R2 ", regs->r2); + print_reg("R3 ", regs->r3); + print_reg("R12 ", regs->r12); + print_reg("SP ", (uint32_t)regs); + print_reg("LR ", regs->lr); + print_reg("PC ", regs->pc); + print_reg("XPSR ", regs->xpsr); + + #if __CORTEX_M >= 3 + uint32_t cfsr = SCB->CFSR; + + print_reg("HFSR ", SCB->HFSR); + print_reg("CFSR ", cfsr); + if (cfsr & 0x80) { + print_reg("MMFAR ", SCB->MMFAR); + } + if (cfsr & 0x8000) { + print_reg("BFAR ", SCB->BFAR); + } + #endif + + if ((void *)&_ram_start <= (void *)regs && (void *)regs < (void *)&_ram_end) { + mp_hal_stdout_tx_str("Stack:\r\n"); + uint32_t *stack_top = &_estack; + if ((void *)regs < (void *)&_sstack) { + // stack not in static stack area so limit the amount we print + stack_top = (uint32_t *)regs + 32; + } + for (uint32_t *sp = (uint32_t *)regs; sp < stack_top; ++sp) { + print_hex_hex(" ", (uint32_t)sp, *sp); + } + } + + /* Go to infinite loop when Hard Fault exception occurs */ + while (1) { + __fatal_error("HardFault"); + } +} + +// Naked functions have no compiler generated gunk, so are the best thing to +// use for asm functions. +__attribute__((naked)) +void HardFault_Handler(void) { + + // From the ARMv7M Architecture Reference Manual, section B.1.5.6 + // on entry to the Exception, the LR register contains, amongst other + // things, the value of CONTROL.SPSEL. This can be found in bit 3. + // + // If CONTROL.SPSEL is 0, then the exception was stacked up using the + // main stack pointer (aka MSP). If CONTROL.SPSEL is 1, then the exception + // was stacked up using the process stack pointer (aka PSP). + + #if __CORTEX_M == 0 + __asm volatile ( + " mov r0, lr \n" + " lsr r0, r0, #3 \n" // Shift Bit 3 into carry to see which stack pointer we should use. + " mrs r0, msp \n" // Make R0 point to main stack pointer + " bcc .use_msp \n" // Keep MSP in R0 if SPSEL (carry) is 0 + " mrs r0, psp \n" // Make R0 point to process stack pointer + " .use_msp: \n" + " b HardFault_C_Handler \n" // Off to C land + ); + #else + __asm volatile ( + " tst lr, #4 \n" // Test Bit 3 to see which stack pointer we should use. + " ite eq \n" // Tell the assembler that the nest 2 instructions are if-then-else + " mrseq r0, msp \n" // Make R0 point to main stack pointer + " mrsne r0, psp \n" // Make R0 point to process stack pointer + " b HardFault_C_Handler \n" // Off to C land + ); + #endif +} + +#if 0 +/** + * @brief This function handles NMI exception. + * @param None + * @retval None + */ +void NMI_Handler(void) { +} +#endif + +/** + * @brief This function handles Memory Manage exception. + * @param None + * @retval None + */ +void MemManage_Handler(void) { + /* Go to infinite loop when Memory Manage exception occurs */ + while (1) { + __fatal_error("MemManage"); + } +} + +/** + * @brief This function handles Bus Fault exception. + * @param None + * @retval None + */ +void BusFault_Handler(void) { + /* Go to infinite loop when Bus Fault exception occurs */ + while (1) { + __fatal_error("BusFault"); + } +} + +/** + * @brief This function handles Usage Fault exception. + * @param None + * @retval None + */ +void UsageFault_Handler(void) { + /* Go to infinite loop when Usage Fault exception occurs */ + while (1) { + __fatal_error("UsageFault"); + } +} + +/** + * @brief This function handles SVCall exception. + * @param None + * @retval None + */ +void SVC_Handler(void) { +} + +/** + * @brief This function handles Debug Monitor exception. + * @param None + * @retval None + */ +void DebugMon_Handler(void) { +} diff --git a/ports/renesas-ra/ra_it.h b/ports/renesas-ra/ra_it.h new file mode 100644 index 000000000..beec74f4f --- /dev/null +++ b/ports/renesas-ra/ra_it.h @@ -0,0 +1,42 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021,2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_IT_H +#define MICROPY_INCLUDED_RENESAS_RA_IT_H + +extern int pyb_hard_fault_debug; + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); + +#endif // MICROPY_INCLUDED_RENESAS_RA_IT_H diff --git a/ports/renesas-ra/rtc.h b/ports/renesas-ra/rtc.h new file mode 100644 index 000000000..1aec48aea --- /dev/null +++ b/ports/renesas-ra/rtc.h @@ -0,0 +1,69 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RA_RTC_H +#define MICROPY_INCLUDED_RA_RTC_H + +#include "py/obj.h" +extern const mp_obj_type_t pyb_rtc_type; + +typedef struct +{ + uint8_t Hours; + uint8_t Minutes; + uint8_t Seconds; + uint8_t TimeFormat; + uint32_t SubSeconds; + uint32_t SecondFraction; + uint32_t DayLightSaving; + uint32_t StoreOperation; +} RTC_TimeTypeDef; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t WeekDay; + uint8_t Month; + uint8_t Date; + uint8_t Year; +} RTC_DateTypeDef; + +#define RTC_FORMAT_BIN 0x000000000U +#define RTC_FORMAT_BCD 0x000000001U + +#define DUMMY_DATE {0, 11, 4, 18} +#define DUMMY_TIME {12, 0, 0, 0, 0, 0, 0, 0} + +void rtc_get_time(RTC_TimeTypeDef *time); +void rtc_get_date(RTC_DateTypeDef *date); +void rtc_init_start(bool force_init); +void rtc_init_finalise(void); + +mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args); + +#endif // MICROPY_INCLUDED_RA_RTC_H diff --git a/ports/renesas-ra/softtimer.c b/ports/renesas-ra/softtimer.c new file mode 100644 index 000000000..c9c59cab0 --- /dev/null +++ b/ports/renesas-ra/softtimer.c @@ -0,0 +1,148 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include "py/gc.h" +#include "py/mphal.h" +#include "py/runtime.h" +#include "irq.h" +#include "softtimer.h" + +#define TICKS_PERIOD 0x80000000 +#define TICKS_DIFF(t1, t0) ((int32_t)(((t1 - t0 + TICKS_PERIOD / 2) & (TICKS_PERIOD - 1)) - TICKS_PERIOD / 2)) + +extern __IO uint32_t uwTick; + +volatile uint32_t soft_timer_next; + +// Pointer to the pairheap of soft timer objects. +// This may contain bss/data pointers as well as GC-heap pointers, +// and is explicitly GC traced by soft_timer_gc_mark_all(). +STATIC soft_timer_entry_t *soft_timer_heap; + +STATIC int soft_timer_lt(mp_pairheap_t *n1, mp_pairheap_t *n2) { + soft_timer_entry_t *e1 = (soft_timer_entry_t *)n1; + soft_timer_entry_t *e2 = (soft_timer_entry_t *)n2; + return TICKS_DIFF(e1->expiry_ms, e2->expiry_ms) < 0; +} + +STATIC void soft_timer_schedule_systick(uint32_t ticks_ms) { + uint32_t irq_state = disable_irq(); + uint32_t uw_tick = uwTick; + if (TICKS_DIFF(ticks_ms, uw_tick) <= 0) { + soft_timer_next = uw_tick + 1; + } else { + soft_timer_next = ticks_ms; + } + enable_irq(irq_state); +} + +void soft_timer_deinit(void) { + // Pop off all the nodes which are allocated on the GC-heap. + uint32_t irq_state = raise_irq_pri(IRQ_PRI_PENDSV); + soft_timer_entry_t *heap_from = soft_timer_heap; + soft_timer_entry_t *heap_to = (soft_timer_entry_t *)mp_pairheap_new(soft_timer_lt); + while (heap_from != NULL) { + soft_timer_entry_t *entry = (soft_timer_entry_t *)mp_pairheap_peek(soft_timer_lt, &heap_from->pairheap); + heap_from = (soft_timer_entry_t *)mp_pairheap_pop(soft_timer_lt, &heap_from->pairheap); + if (!(entry->flags & SOFT_TIMER_FLAG_GC_ALLOCATED)) { + heap_to = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &heap_to->pairheap, &entry->pairheap); + } + } + soft_timer_heap = heap_to; + restore_irq_pri(irq_state); +} + +// Must be executed at IRQ_PRI_PENDSV +void soft_timer_handler(void) { + uint32_t ticks_ms = uwTick; + soft_timer_entry_t *heap = soft_timer_heap; + while (heap != NULL && TICKS_DIFF(heap->expiry_ms, ticks_ms) <= 0) { + soft_timer_entry_t *entry = heap; + heap = (soft_timer_entry_t *)mp_pairheap_pop(soft_timer_lt, &heap->pairheap); + if (entry->flags & SOFT_TIMER_FLAG_PY_CALLBACK) { + mp_sched_schedule(entry->py_callback, MP_OBJ_FROM_PTR(entry)); + } else { + entry->c_callback(entry); + } + if (entry->mode == SOFT_TIMER_MODE_PERIODIC) { + entry->expiry_ms += entry->delta_ms; + heap = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &heap->pairheap, &entry->pairheap); + } + } + soft_timer_heap = heap; + if (heap == NULL) { + // No more timers left, set largest delay possible + soft_timer_next = uwTick; + } else { + // Set soft_timer_next so SysTick calls us back at the correct time + soft_timer_schedule_systick(heap->expiry_ms); + } +} + +void soft_timer_gc_mark_all(void) { + // Mark all soft timer nodes that are allocated on the GC-heap. + // To avoid deep C recursion, pop and recreate the pairheap as nodes are marked. + uint32_t irq_state = raise_irq_pri(IRQ_PRI_PENDSV); + soft_timer_entry_t *heap_from = soft_timer_heap; + soft_timer_entry_t *heap_to = (soft_timer_entry_t *)mp_pairheap_new(soft_timer_lt); + while (heap_from != NULL) { + soft_timer_entry_t *entry = (soft_timer_entry_t *)mp_pairheap_peek(soft_timer_lt, &heap_from->pairheap); + heap_from = (soft_timer_entry_t *)mp_pairheap_pop(soft_timer_lt, &heap_from->pairheap); + if (entry->flags & SOFT_TIMER_FLAG_GC_ALLOCATED) { + gc_collect_root((void **)&entry, 1); + } + heap_to = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &heap_to->pairheap, &entry->pairheap); + } + soft_timer_heap = heap_to; + restore_irq_pri(irq_state); +} + +void soft_timer_static_init(soft_timer_entry_t *entry, uint16_t mode, uint32_t delta_ms, void (*cb)(soft_timer_entry_t *)) { + mp_pairheap_init_node(soft_timer_lt, &entry->pairheap); + entry->flags = 0; + entry->mode = mode; + entry->delta_ms = delta_ms; + entry->c_callback = cb; +} + +void soft_timer_insert(soft_timer_entry_t *entry, uint32_t initial_delta_ms) { + mp_pairheap_init_node(soft_timer_lt, &entry->pairheap); + entry->expiry_ms = mp_hal_ticks_ms() + initial_delta_ms; + uint32_t irq_state = raise_irq_pri(IRQ_PRI_PENDSV); + soft_timer_heap = (soft_timer_entry_t *)mp_pairheap_push(soft_timer_lt, &soft_timer_heap->pairheap, &entry->pairheap); + if (entry == soft_timer_heap) { + // This new timer became the earliest one so set soft_timer_next + soft_timer_schedule_systick(entry->expiry_ms); + } + restore_irq_pri(irq_state); +} + +void soft_timer_remove(soft_timer_entry_t *entry) { + uint32_t irq_state = raise_irq_pri(IRQ_PRI_PENDSV); + soft_timer_heap = (soft_timer_entry_t *)mp_pairheap_delete(soft_timer_lt, &soft_timer_heap->pairheap, &entry->pairheap); + restore_irq_pri(irq_state); +} diff --git a/ports/renesas-ra/softtimer.h b/ports/renesas-ra/softtimer.h new file mode 100644 index 000000000..aec885c54 --- /dev/null +++ b/ports/renesas-ra/softtimer.h @@ -0,0 +1,66 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2019 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_SOFTTIMER_H +#define MICROPY_INCLUDED_RENESAS_RA_SOFTTIMER_H + +#include "py/pairheap.h" + +#define SOFT_TIMER_FLAG_PY_CALLBACK (1) +#define SOFT_TIMER_FLAG_GC_ALLOCATED (2) + +#define SOFT_TIMER_MODE_ONE_SHOT (1) +#define SOFT_TIMER_MODE_PERIODIC (2) + +typedef struct _soft_timer_entry_t { + mp_pairheap_t pairheap; + uint16_t flags; + uint16_t mode; + uint32_t expiry_ms; + uint32_t delta_ms; // for periodic mode + union { + void (*c_callback)(struct _soft_timer_entry_t *); + mp_obj_t py_callback; + }; +} soft_timer_entry_t; + +extern volatile uint32_t soft_timer_next; + +void soft_timer_deinit(void); +void soft_timer_handler(void); +void soft_timer_gc_mark_all(void); + +void soft_timer_static_init(soft_timer_entry_t *entry, uint16_t mode, uint32_t delta_ms, void (*cb)(soft_timer_entry_t *)); +void soft_timer_insert(soft_timer_entry_t *entry, uint32_t initial_delta_ms); +void soft_timer_remove(soft_timer_entry_t *entry); + +// The timer will be reinserted into the heap so that it is called after initial_delta_ms milliseconds. +// After that, if it's periodic, it will continue to be called every entry->delta_ms milliseconds. +static inline void soft_timer_reinsert(soft_timer_entry_t *entry, uint32_t initial_delta_ms) { + soft_timer_remove(entry); + soft_timer_insert(entry, initial_delta_ms); +} + +#endif // MICROPY_INCLUDED_RENESAS_RA_SOFTTIMER_H diff --git a/ports/renesas-ra/spi.h b/ports/renesas-ra/spi.h new file mode 100644 index 000000000..47d9c1356 --- /dev/null +++ b/ports/renesas-ra/spi.h @@ -0,0 +1,44 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021, 2022 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_RA_SPI_H +#define MICROPY_INCLUDED_RA_SPI_H + +// A transfer of "len" bytes should take len*8*1000/baudrate milliseconds. +// To simplify the calculation we assume the baudrate is never less than 8kHz +// and use that value for the baudrate in the formula, plus a small constant. +#define SPI_TRANSFER_TIMEOUT(len) ((len) + 100) + +void spi_init0(void); +void spi_init(uint32_t ch); +void spi_deinit(uint32_t ch); +int spi_find_index(mp_obj_t id); +void spi_set_params(uint32_t ch, int32_t baudrate, + int32_t polarity, int32_t phase, int32_t bits, int32_t firstbit); +void spi_transfer(uint32_t ch, uint32_t bits, size_t len, const uint8_t *src, uint8_t *dest, uint32_t timeout); + +#endif // MICROPY_INCLUDED_RA_SPI_H diff --git a/ports/renesas-ra/storage.c b/ports/renesas-ra/storage.c new file mode 100644 index 000000000..dad999188 --- /dev/null +++ b/ports/renesas-ra/storage.c @@ -0,0 +1,429 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013-2018 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/mperrno.h" +#include "extmod/vfs_fat.h" + +#include "systick.h" +#include "led.h" +#include "storage.h" +#include "irq.h" + +#if MICROPY_HW_ENABLE_STORAGE + +#define STORAGE_SYSTICK_MASK (0x1ff) // 512ms +#define STORAGE_IDLE_TICK(tick) (((tick) & ~(SYSTICK_DISPATCH_NUM_SLOTS - 1) & STORAGE_SYSTICK_MASK) == 0) + +#if defined(MICROPY_HW_BDEV2_IOCTL) +#define FLASH_PART2_START_BLOCK (FLASH_PART1_START_BLOCK + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) +#endif + +static bool storage_is_initialised = false; + +// ToDo: check how to implement +// static void storage_systick_callback(uint32_t ticks_ms); + +void storage_init(void) { + if (!storage_is_initialised) { + storage_is_initialised = true; + + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_INIT, 0); + + #if defined(MICROPY_HW_BDEV2_IOCTL) + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_INIT, 0); + #endif + } +} + +uint32_t storage_get_block_size(void) { + return FLASH_BLOCK_SIZE; +} + +uint32_t storage_get_block_count(void) { + #if defined(MICROPY_HW_BDEV2_IOCTL) + return FLASH_PART2_START_BLOCK + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0); + #else + return FLASH_PART1_START_BLOCK + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0); + #endif +} + +void storage_irq_handler(void) { + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_IRQ_HANDLER, 0); + #if defined(MICROPY_HW_BDEV2_IOCTL) + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_IRQ_HANDLER, 0); + #endif +} + +void storage_flush(void) { + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_SYNC, 0); + #if defined(MICROPY_HW_BDEV2_IOCTL) + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_SYNC, 0); + #endif +} + +static void build_partition(uint8_t *buf, int boot, int type, uint32_t start_block, uint32_t num_blocks) { + buf[0] = boot; + + if (num_blocks == 0) { + buf[1] = 0; + buf[2] = 0; + buf[3] = 0; + } else { + buf[1] = 0xff; + buf[2] = 0xff; + buf[3] = 0xff; + } + + buf[4] = type; + + if (num_blocks == 0) { + buf[5] = 0; + buf[6] = 0; + buf[7] = 0; + } else { + buf[5] = 0xff; + buf[6] = 0xff; + buf[7] = 0xff; + } + + buf[8] = start_block; + buf[9] = start_block >> 8; + buf[10] = start_block >> 16; + buf[11] = start_block >> 24; + + buf[12] = num_blocks; + buf[13] = num_blocks >> 8; + buf[14] = num_blocks >> 16; + buf[15] = num_blocks >> 24; +} + +bool storage_read_block(uint8_t *dest, uint32_t block) { + // printf("RD %u\n", block); + if (block == 0) { + // fake the MBR so we can decide on our own partition table + + for (int i = 0; i < 446; i++) { + dest[i] = 0; + } + + build_partition(dest + 446, 0, 0x01 /* FAT12 */, FLASH_PART1_START_BLOCK, MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)); + #if defined(MICROPY_HW_BDEV2_IOCTL) + build_partition(dest + 462, 0, 0x01 /* FAT12 */, FLASH_PART2_START_BLOCK, MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)); + #else + build_partition(dest + 462, 0, 0, 0, 0); + #endif + build_partition(dest + 478, 0, 0, 0, 0); + build_partition(dest + 494, 0, 0, 0, 0); + + dest[510] = 0x55; + dest[511] = 0xaa; + + return true; + + #if defined(MICROPY_HW_BDEV_READBLOCK) + } else if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) { + return MICROPY_HW_BDEV_READBLOCK(dest, block - FLASH_PART1_START_BLOCK); + #endif + } else { + return false; + } +} + +bool storage_write_block(const uint8_t *src, uint32_t block) { + // printf("WR %u\n", block); + if (block == 0) { + // can't write MBR, but pretend we did + return true; + #if defined(MICROPY_HW_BDEV_WRITEBLOCK) + } else if (FLASH_PART1_START_BLOCK <= block && block < FLASH_PART1_START_BLOCK + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) { + return MICROPY_HW_BDEV_WRITEBLOCK(src, block - FLASH_PART1_START_BLOCK); + #endif + } else { + return false; + } +} + +int storage_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks) { + #if defined(MICROPY_HW_BDEV_READBLOCKS) + if (FLASH_PART1_START_BLOCK <= block_num && block_num + num_blocks <= FLASH_PART1_START_BLOCK + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) { + return MICROPY_HW_BDEV_READBLOCKS(dest, block_num - FLASH_PART1_START_BLOCK, num_blocks); + } + #endif + + #if defined(MICROPY_HW_BDEV2_READBLOCKS) + if (FLASH_PART2_START_BLOCK <= block_num && block_num + num_blocks <= FLASH_PART2_START_BLOCK + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) { + return MICROPY_HW_BDEV2_READBLOCKS(dest, block_num - FLASH_PART2_START_BLOCK, num_blocks); + } + #endif + + for (size_t i = 0; i < num_blocks; i++) { + if (!storage_read_block(dest + i * FLASH_BLOCK_SIZE, block_num + i)) { + return -MP_EIO; // error + } + } + return 0; // success +} + +int storage_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks) { + #if defined(MICROPY_HW_BDEV_WRITEBLOCKS) + if (FLASH_PART1_START_BLOCK <= block_num && block_num + num_blocks <= FLASH_PART1_START_BLOCK + MICROPY_HW_BDEV_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) { + return MICROPY_HW_BDEV_WRITEBLOCKS(src, block_num - FLASH_PART1_START_BLOCK, num_blocks); + } + #endif + + #if defined(MICROPY_HW_BDEV2_WRITEBLOCKS) + if (FLASH_PART2_START_BLOCK <= block_num && block_num + num_blocks <= FLASH_PART2_START_BLOCK + MICROPY_HW_BDEV2_IOCTL(BDEV_IOCTL_NUM_BLOCKS, 0)) { + return MICROPY_HW_BDEV2_WRITEBLOCKS(src, block_num - FLASH_PART2_START_BLOCK, num_blocks); + } + #endif + + for (size_t i = 0; i < num_blocks; i++) { + if (!storage_write_block(src + i * FLASH_BLOCK_SIZE, block_num + i)) { + return -MP_EIO; // error + } + } + return 0; // success +} + +/******************************************************************************/ +// MicroPython bindings +// +// Expose the flash as an object with the block protocol. + +#if (MICROPY_VFS_LFS1 || MICROPY_VFS_LFS2) && MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE +// Board uses littlefs and internal flash, so enable extended block protocol on internal flash +#define PYB_FLASH_NATIVE_BLOCK_SIZE (FLASH_BLOCK_SIZE) +#define MICROPY_HW_BDEV_READBLOCKS_EXT(dest, bl, off, len) (flash_bdev_readblocks_ext((dest), (bl), (off), (len))) +#define MICROPY_HW_BDEV_WRITEBLOCKS_EXT(dest, bl, off, len) (flash_bdev_writeblocks_ext((dest), (bl), (off), (len))) +#endif + +#ifndef PYB_FLASH_NATIVE_BLOCK_SIZE +#define PYB_FLASH_NATIVE_BLOCK_SIZE (FLASH_BLOCK_SIZE) +#endif + +#if defined(MICROPY_HW_BDEV_READBLOCKS_EXT) +// Size of blocks is PYB_FLASH_NATIVE_BLOCK_SIZE +int storage_readblocks_ext(uint8_t *dest, uint32_t block, uint32_t offset, uint32_t len) { + return MICROPY_HW_BDEV_READBLOCKS_EXT(dest, block, offset, len); +} +#endif + +typedef struct _pyb_flash_obj_t { + mp_obj_base_t base; + uint32_t start; // in bytes + uint32_t len; // in bytes +} pyb_flash_obj_t; + +// This Flash object represents the entire available flash, with emulated partition table at start +const pyb_flash_obj_t pyb_flash_obj = { + { &pyb_flash_type }, + -(FLASH_PART1_START_BLOCK * FLASH_BLOCK_SIZE), // to offset FLASH_PART1_START_BLOCK + 0, // actual size handled in ioctl, MP_BLOCKDEV_IOCTL_BLOCK_COUNT case +}; + +STATIC void pyb_flash_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pyb_flash_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (self == &pyb_flash_obj) { + mp_printf(print, "Flash()"); + } else { + mp_printf(print, "Flash(start=%u, len=%u)", self->start, self->len); + } +} + +STATIC mp_obj_t pyb_flash_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *all_args) { + // Parse arguments + enum { ARG_start, ARG_len }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_start, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + { MP_QSTR_len, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = -1} }, + }; + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all_kw_array(n_args, n_kw, all_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + if (args[ARG_start].u_int == -1 && args[ARG_len].u_int == -1) { + // Default singleton object that accesses entire flash, including virtual partition table + return MP_OBJ_FROM_PTR(&pyb_flash_obj); + } + + pyb_flash_obj_t *self = m_new_obj(pyb_flash_obj_t); + self->base.type = &pyb_flash_type; + + uint32_t bl_len = (storage_get_block_count() - FLASH_PART1_START_BLOCK) * FLASH_BLOCK_SIZE; + + mp_int_t start = args[ARG_start].u_int; + if (start == -1) { + start = 0; + } else if (!(0 <= start && start < bl_len && start % PYB_FLASH_NATIVE_BLOCK_SIZE == 0)) { + mp_raise_ValueError(NULL); + } + + mp_int_t len = args[ARG_len].u_int; + if (len == -1) { + len = bl_len - start; + } else if (!(0 < len && start + len <= bl_len && len % PYB_FLASH_NATIVE_BLOCK_SIZE == 0)) { + mp_raise_ValueError(NULL); + } + + self->start = start; + self->len = len; + + return MP_OBJ_FROM_PTR(self); +} + +STATIC mp_obj_t pyb_flash_readblocks(size_t n_args, const mp_obj_t *args) { + pyb_flash_obj_t *self = MP_OBJ_TO_PTR(args[0]); + uint32_t block_num = mp_obj_get_int(args[1]); + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[2], &bufinfo, MP_BUFFER_WRITE); + mp_uint_t ret = -MP_EIO; + if (n_args == 3) { + // Cast self->start to signed in case it's pyb_flash_obj with negative start + block_num += FLASH_PART1_START_BLOCK + (int32_t)self->start / FLASH_BLOCK_SIZE; + ret = storage_read_blocks(bufinfo.buf, block_num, bufinfo.len / FLASH_BLOCK_SIZE); + } + #if defined(MICROPY_HW_BDEV_READBLOCKS_EXT) + else if (self != &pyb_flash_obj) { + // Extended block read on a sub-section of the flash storage + uint32_t offset = mp_obj_get_int(args[3]); + block_num += self->start / PYB_FLASH_NATIVE_BLOCK_SIZE; + ret = MICROPY_HW_BDEV_READBLOCKS_EXT(bufinfo.buf, block_num, offset, bufinfo.len); + } + #endif + return MP_OBJ_NEW_SMALL_INT(ret); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_flash_readblocks_obj, 3, 4, pyb_flash_readblocks); + +STATIC mp_obj_t pyb_flash_writeblocks(size_t n_args, const mp_obj_t *args) { + pyb_flash_obj_t *self = MP_OBJ_TO_PTR(args[0]); + uint32_t block_num = mp_obj_get_int(args[1]); + mp_buffer_info_t bufinfo; + mp_get_buffer_raise(args[2], &bufinfo, MP_BUFFER_READ); + mp_uint_t ret = -MP_EIO; + if (n_args == 3) { + // Cast self->start to signed in case it's pyb_flash_obj with negative start + block_num += FLASH_PART1_START_BLOCK + (int32_t)self->start / FLASH_BLOCK_SIZE; + ret = storage_write_blocks(bufinfo.buf, block_num, bufinfo.len / FLASH_BLOCK_SIZE); + } + #if defined(MICROPY_HW_BDEV_WRITEBLOCKS_EXT) + else if (self != &pyb_flash_obj) { + // Extended block write on a sub-section of the flash storage + uint32_t offset = mp_obj_get_int(args[3]); + block_num += self->start / PYB_FLASH_NATIVE_BLOCK_SIZE; + ret = MICROPY_HW_BDEV_WRITEBLOCKS_EXT(bufinfo.buf, block_num, offset, bufinfo.len); + } + #endif + return MP_OBJ_NEW_SMALL_INT(ret); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_flash_writeblocks_obj, 3, 4, pyb_flash_writeblocks); + +STATIC mp_obj_t pyb_flash_ioctl(mp_obj_t self_in, mp_obj_t cmd_in, mp_obj_t arg_in) { + pyb_flash_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_int_t cmd = mp_obj_get_int(cmd_in); + switch (cmd) { + case MP_BLOCKDEV_IOCTL_INIT: { + mp_int_t ret = 0; + storage_init(); + if (mp_obj_get_int(arg_in) == 1) { + // Will be using extended block protocol + if (self == &pyb_flash_obj) { + ret = -1; + } + } + return MP_OBJ_NEW_SMALL_INT(ret); + } + case MP_BLOCKDEV_IOCTL_DEINIT: + storage_flush(); + return MP_OBJ_NEW_SMALL_INT(0); // TODO properly + case MP_BLOCKDEV_IOCTL_SYNC: + storage_flush(); + return MP_OBJ_NEW_SMALL_INT(0); + + case MP_BLOCKDEV_IOCTL_BLOCK_COUNT: { + mp_int_t n; + if (self == &pyb_flash_obj) { + // Get true size + n = storage_get_block_count(); + } else { + n = self->len / FLASH_BLOCK_SIZE; + } + return MP_OBJ_NEW_SMALL_INT(n); + } + + case MP_BLOCKDEV_IOCTL_BLOCK_SIZE: { + mp_int_t n = FLASH_BLOCK_SIZE; + return MP_OBJ_NEW_SMALL_INT(n); + } + + case MP_BLOCKDEV_IOCTL_BLOCK_ERASE: { + int ret = 0; + return MP_OBJ_NEW_SMALL_INT(ret); + } + + default: + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_3(pyb_flash_ioctl_obj, pyb_flash_ioctl); + +STATIC const mp_rom_map_elem_t pyb_flash_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_readblocks), MP_ROM_PTR(&pyb_flash_readblocks_obj) }, + { MP_ROM_QSTR(MP_QSTR_writeblocks), MP_ROM_PTR(&pyb_flash_writeblocks_obj) }, + { MP_ROM_QSTR(MP_QSTR_ioctl), MP_ROM_PTR(&pyb_flash_ioctl_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(pyb_flash_locals_dict, pyb_flash_locals_dict_table); + +const mp_obj_type_t pyb_flash_type = { + { &mp_type_type }, + .name = MP_QSTR_Flash, + .print = pyb_flash_print, + .make_new = pyb_flash_make_new, + .locals_dict = (mp_obj_dict_t *)&pyb_flash_locals_dict, +}; + +void pyb_flash_init_vfs(fs_user_mount_t *vfs) { + vfs->base.type = &mp_fat_vfs_type; + vfs->blockdev.flags |= MP_BLOCKDEV_FLAG_NATIVE | MP_BLOCKDEV_FLAG_HAVE_IOCTL; + vfs->fatfs.drv = vfs; + #if MICROPY_FATFS_MULTI_PARTITION + vfs->fatfs.part = 1; // flash filesystem lives on first partition + #endif + vfs->blockdev.readblocks[0] = MP_OBJ_FROM_PTR(&pyb_flash_readblocks_obj); + vfs->blockdev.readblocks[1] = MP_OBJ_FROM_PTR(&pyb_flash_obj); + vfs->blockdev.readblocks[2] = MP_OBJ_FROM_PTR(storage_read_blocks); // native version + vfs->blockdev.writeblocks[0] = MP_OBJ_FROM_PTR(&pyb_flash_writeblocks_obj); + vfs->blockdev.writeblocks[1] = MP_OBJ_FROM_PTR(&pyb_flash_obj); + vfs->blockdev.writeblocks[2] = MP_OBJ_FROM_PTR(storage_write_blocks); // native version + vfs->blockdev.u.ioctl[0] = MP_OBJ_FROM_PTR(&pyb_flash_ioctl_obj); + vfs->blockdev.u.ioctl[1] = MP_OBJ_FROM_PTR(&pyb_flash_obj); +} + +#endif diff --git a/ports/renesas-ra/storage.h b/ports/renesas-ra/storage.h new file mode 100644 index 000000000..683ab3de2 --- /dev/null +++ b/ports/renesas-ra/storage.h @@ -0,0 +1,67 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RA_STORAGE_H +#define MICROPY_INCLUDED_RA_STORAGE_H + +#include "drivers/memory/spiflash.h" + +#define FLASH_BLOCK_SIZE (512) +#define FLASH_PART1_START_BLOCK (0x100) + +// Try to match Python-level VFS block protocol where possible for these constants +enum { + BDEV_IOCTL_INIT = 1, + BDEV_IOCTL_SYNC = 3, + BDEV_IOCTL_NUM_BLOCKS = 4, + BDEV_IOCTL_BLOCK_ERASE = 6, + BDEV_IOCTL_IRQ_HANDLER = 7, +}; + +void storage_init(void); +uint32_t storage_get_block_size(void); +uint32_t storage_get_block_count(void); +void storage_flush(void); +bool storage_read_block(uint8_t *dest, uint32_t block); +bool storage_write_block(const uint8_t *src, uint32_t block); + +// these return 0 on success, negative errno on error +int storage_read_blocks(uint8_t *dest, uint32_t block_num, uint32_t num_blocks); +int storage_write_blocks(const uint8_t *src, uint32_t block_num, uint32_t num_blocks); +int storage_readblocks_ext(uint8_t *dest, uint32_t block, uint32_t offset, uint32_t len); + +int32_t flash_bdev_ioctl(uint32_t op, uint32_t arg); +bool flash_bdev_readblock(uint8_t *dest, uint32_t block); +bool flash_bdev_writeblock(const uint8_t *src, uint32_t block); +int flash_bdev_readblocks_ext(uint8_t *dest, uint32_t block, uint32_t offset, uint32_t len); +int flash_bdev_writeblocks_ext(const uint8_t *src, uint32_t block, uint32_t offset, uint32_t len); + +extern const struct _mp_obj_type_t pyb_flash_type; +extern const struct _pyb_flash_obj_t pyb_flash_obj; + +struct _fs_user_mount_t; +void pyb_flash_init_vfs(struct _fs_user_mount_t *vfs); + +#endif // MICROPY_INCLUDED_RA_STORAGE_H diff --git a/ports/renesas-ra/systick.c b/ports/renesas-ra/systick.c new file mode 100644 index 000000000..e88166b11 --- /dev/null +++ b/ports/renesas-ra/systick.c @@ -0,0 +1,187 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "py/runtime.h" +#include "py/mphal.h" +#include "irq.h" +#include "pendsv.h" +#include "systick.h" +#include "softtimer.h" +#include "pybthread.h" +#include "hal_data.h" + +volatile uint32_t uwTick; + +uint32_t HAL_GetTick(void) { + return uwTick; +} + +systick_dispatch_t systick_dispatch_table[SYSTICK_DISPATCH_NUM_SLOTS]; + +void SysTick_Handler(void) { + // Instead of calling HAL_IncTick we do the increment here of the counter. + // This is purely for efficiency, since SysTick is called 1000 times per + // second at the highest interrupt priority. + uint32_t uw_tick = uwTick + 1; + uwTick = uw_tick; + + // Read the systick control regster. This has the side effect of clearing + // the COUNTFLAG bit, which makes the logic in mp_hal_ticks_us + // work properly. + SysTick->CTRL; + + // Dispatch to any registered handlers in a cycle + systick_dispatch_t f = systick_dispatch_table[uw_tick & (SYSTICK_DISPATCH_NUM_SLOTS - 1)]; + if (f != NULL) { + f(uw_tick); + } + + if (soft_timer_next == uw_tick) { + pendsv_schedule_dispatch(PENDSV_DISPATCH_SOFT_TIMER, soft_timer_handler); + } + + #if MICROPY_PY_THREAD + if (pyb_thread_enabled) { + if (pyb_thread_cur->timeslice == 0) { + if (pyb_thread_cur->run_next != pyb_thread_cur) { + SCB->ICSR = SCB_ICSR_PENDSVSET_Msk; + } + } else { + --pyb_thread_cur->timeslice; + } + } + #endif +} + +// We provide our own version of HAL_Delay that calls __WFI while waiting, +// and works when interrupts are disabled. This function is intended to be +// used only by the ST HAL functions. +void HAL_Delay(uint32_t Delay) { + if (query_irq() == IRQ_STATE_ENABLED) { + // IRQs enabled, so can use systick counter to do the delay + uint32_t start = uwTick; + // Wraparound of tick is taken care of by 2's complement arithmetic. + while (uwTick - start < Delay) { + // Enter sleep mode, waiting for (at least) the SysTick interrupt. + __WFI(); + } + } else { + // IRQs disabled, use mp_hal_delay_ms routine. + mp_hal_delay_ms(Delay); + } +} + +// Core delay function that does an efficient sleep and may switch thread context. +// If IRQs are enabled then we must have the GIL. +void mp_hal_delay_ms(mp_uint_t Delay) { + if (query_irq() == IRQ_STATE_ENABLED) { + // IRQs enabled, so can use systick counter to do the delay + uint32_t start = uwTick; + // Wraparound of tick is taken care of by 2's complement arithmetic. + do { + // This macro will execute the necessary idle behaviour. It may + // raise an exception, switch threads or enter sleep mode (waiting for + // (at least) the SysTick interrupt). + MICROPY_EVENT_POLL_HOOK + } while (uwTick - start < Delay); + } else { + // IRQs disabled, so need to use a busy loop for the delay. + // To prevent possible overflow of the counter we use a double loop. + volatile uint32_t count_1ms; + while (Delay-- > 0) { + count_1ms = (MICROPY_HW_MCU_PCLK / 1000 / 10); + while (count_1ms-- > 0) { + __asm__ __volatile__ ("nop"); + } + } + } +} + +// delay for given number of microseconds +void mp_hal_delay_us(mp_uint_t usec) { + if (query_irq() == IRQ_STATE_ENABLED) { + // IRQs enabled, so can use systick counter to do the delay + uint32_t start = mp_hal_ticks_us(); + while (mp_hal_ticks_us() - start < usec) { + } + } else { + // IRQs disabled, so need to use a busy loop for the delay + volatile uint32_t ucount = (MICROPY_HW_MCU_PCLK / 1000000 / 10) * usec; + while (ucount-- > 0) { + __asm__ __volatile__ ("nop"); + } + } +} + +bool systick_has_passed(uint32_t start_tick, uint32_t delay_ms) { + return HAL_GetTick() - start_tick >= delay_ms; +} + +// waits until at least delay_ms milliseconds have passed from the sampling of +// startTick. Handles overflow properly. Assumes stc was taken from +// HAL_GetTick() some time before calling this function. +void systick_wait_at_least(uint32_t start_tick, uint32_t delay_ms) { + while (!systick_has_passed(start_tick, delay_ms)) { + __WFI(); // enter sleep mode, waiting for interrupt + } +} + +mp_uint_t mp_hal_ticks_ms(void) { + return uwTick; +} + +// The SysTick timer counts down at 168 MHz, so we can use that knowledge +// to grab a microsecond counter. +// +// We assume that HAL_GetTickis returns milliseconds. +mp_uint_t mp_hal_ticks_us(void) { + mp_uint_t irq_state = disable_irq(); + uint32_t counter = SysTick->VAL; + uint32_t milliseconds = HAL_GetTick(); + uint32_t status = SysTick->CTRL; + enable_irq(irq_state); + + // It's still possible for the countflag bit to get set if the counter was + // reloaded between reading VAL and reading CTRL. With interrupts disabled + // it definitely takes less than 50 HCLK cycles between reading VAL and + // reading CTRL, so the test (counter > 50) is to cover the case where VAL + // is +ve and very close to zero, and the COUNTFLAG bit is also set. + if ((status & SysTick_CTRL_COUNTFLAG_Msk) && counter > 50) { + // This means that the HW reloaded VAL between the time we read VAL and the + // time we read CTRL, which implies that there is an interrupt pending + // to increment the tick counter. + milliseconds++; + } + uint32_t load = SysTick->LOAD; + counter = load - counter; // Convert from decrementing to incrementing + + // ((load + 1) / 1000) is the number of counts per microsecond. + // + // counter / ((load + 1) / 1000) scales from the systick clock to microseconds + // and is the same thing as (counter * 1000) / (load + 1) + return milliseconds * 1000 + (counter * 1000) / (load + 1); +} diff --git a/ports/renesas-ra/systick.h b/ports/renesas-ra/systick.h new file mode 100644 index 000000000..a4ee50dd5 --- /dev/null +++ b/ports/renesas-ra/systick.h @@ -0,0 +1,60 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_SYSTICK_H +#define MICROPY_INCLUDED_RENESAS_RA_SYSTICK_H + +// Works for x between 0 and 16 inclusive +#define POW2_CEIL(x) ((((x) - 1) | ((x) - 1) >> 1 | ((x) - 1) >> 2 | ((x) - 1) >> 3) + 1) + +enum { + SYSTICK_DISPATCH_DMA = 0, + #if MICROPY_HW_ENABLE_STORAGE + SYSTICK_DISPATCH_STORAGE, + #endif + #if MICROPY_PY_NETWORK && MICROPY_PY_LWIP + SYSTICK_DISPATCH_LWIP, + #endif + SYSTICK_DISPATCH_MAX +}; + +#define SYSTICK_DISPATCH_NUM_SLOTS POW2_CEIL(SYSTICK_DISPATCH_MAX) + +typedef void (*systick_dispatch_t)(uint32_t); + +extern systick_dispatch_t systick_dispatch_table[SYSTICK_DISPATCH_NUM_SLOTS]; + +static inline void systick_enable_dispatch(size_t slot, systick_dispatch_t f) { + systick_dispatch_table[slot] = f; +} + +static inline void systick_disable_dispatch(size_t slot) { + systick_dispatch_table[slot] = NULL; +} + +void systick_wait_at_least(uint32_t stc, uint32_t delay_ms); +bool systick_has_passed(uint32_t stc, uint32_t delay_ms); + +#endif // MICROPY_INCLUDED_RENESAS_RA_SYSTICK_H diff --git a/ports/renesas-ra/timer.c b/ports/renesas-ra/timer.c new file mode 100644 index 000000000..93b378ac3 --- /dev/null +++ b/ports/renesas-ra/timer.c @@ -0,0 +1,569 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdint.h> +#include <string.h> + +#include "py/runtime.h" +#include "py/gc.h" +#include "timer.h" +#include "pin.h" +#include "irq.h" + +#define TIMER_SIZE 2 + +void timer_irq_handler(void *param); +STATIC mp_obj_t pyb_timer_freq(size_t n_args, const mp_obj_t *args); + +#if defined(TIMER_CHANNEL) +typedef struct _pyb_timer_channel_obj_t { + mp_obj_base_t base; + struct _pyb_timer_obj_t *timer; + uint8_t channel; + mp_obj_t callback; + struct _pyb_timer_channel_obj_t *next; +} pyb_timer_channel_obj_t; +#endif + +typedef struct _pyb_timer_obj_t { + mp_obj_base_t base; + uint8_t tim_id; + mp_obj_t callback; + #if defined(TIMER_CHANNEL) + pyb_timer_channel_obj_t *channel; + #endif +} pyb_timer_obj_t; +#define PYB_TIMER_OBJ_ALL_NUM MP_ARRAY_SIZE(MP_STATE_PORT(pyb_timer_obj_all)) + +STATIC mp_obj_t pyb_timer_deinit(mp_obj_t self_in); +STATIC mp_obj_t pyb_timer_callback(mp_obj_t self_in, mp_obj_t callback); +#if defined(TIMER_CHANNEL) +STATIC mp_obj_t pyb_timer_channel_callback(mp_obj_t self_in, mp_obj_t callback); +#endif +static const int ra_agt_timer_ch[TIMER_SIZE] = {1, 2}; + +void timer_init0(void) { + for (uint i = 0; i < PYB_TIMER_OBJ_ALL_NUM; i++) { + MP_STATE_PORT(pyb_timer_obj_all)[i] = NULL; + } +} + +// unregister all interrupt sources +void timer_deinit(void) { + for (uint i = 0; i < PYB_TIMER_OBJ_ALL_NUM; i++) { + pyb_timer_obj_t *tim = MP_STATE_PORT(pyb_timer_obj_all)[i]; + if (tim != NULL) { + pyb_timer_deinit(MP_OBJ_FROM_PTR(tim)); + } + } +} + +/* + * Timer Class + */ + +STATIC void pyb_timer_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + mp_printf(print, "Timer(%u)", self->tim_id); +} + +/// \method init(*, freq, prescaler, period) +/// Initialise the timer. Initialisation must be either by frequency (in Hz) +/// or by prescaler and period: +/// +/// tim.init(freq=100) # set the timer to trigger at 100Hz +/// +/// Keyword arguments: +/// +/// - `freq` - specifies the periodic frequency of the timer. You migh also +/// view this as the frequency with which the timer goes through +/// one complete cycle. +////// +/// - `callback` - as per Timer.callback() +////// +/// You must either specify freq. +STATIC mp_obj_t pyb_timer_init_helper(pyb_timer_obj_t *self, size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + // enum { ARG_freq, ARG_prescaler, ARG_period, ARG_tick_hz, ARG_mode, ARG_div, ARG_callback, ARG_deadtime }; + enum { ARG_freq, ARG_callback }; + static const mp_arg_t allowed_args[] = { + { MP_QSTR_freq, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + }; + // parse args + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args, pos_args, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + // init TIM + for (int i = 1; i <= TIMER_SIZE; i++) { + ra_agt_timer_set_callback(i - 1, (AGT_TIMER_CB)timer_irq_handler, (void *)&ra_agt_timer_ch[i - 1]); + } + ra_agt_timer_init(self->tim_id - 1, 1.0f); + if (args[ARG_freq].u_obj != mp_const_none) { + mp_obj_t freq_args[2]; + freq_args[0] = self; + freq_args[1] = args[ARG_freq].u_obj; + pyb_timer_freq(2, (const mp_obj_t *)&freq_args); + } else { + mp_raise_TypeError(MP_ERROR_TEXT("must specify either freq, period, or prescaler and period")); + } + // Enable ARPE so that the auto-reload register is buffered. + // This allows to smoothly change the frequency of the timer. + // Start the timer running + if (args[ARG_callback].u_obj == mp_const_none) { + // do nothing + } else { + pyb_timer_callback(MP_OBJ_FROM_PTR(self), args[ARG_callback].u_obj); + } + return mp_const_none; +} + +/// \classmethod \constructor(id, ...) +/// Construct a new timer object of the given id. If additional +/// arguments are given, then the timer is initialised by `init(...)`. +/// `id` can be 1 to 14, excluding 3. +STATIC mp_obj_t pyb_timer_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 1, MP_OBJ_FUN_ARGS_MAX, true); + + // get the timer id + mp_int_t tim_id = mp_obj_get_int(args[0]); + // create new Timer object + pyb_timer_obj_t *tim; + if (MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1] == NULL) { + // create new Timer object + tim = m_new_obj(pyb_timer_obj_t); + memset(tim, 0, sizeof(*tim)); + tim->base.type = &pyb_timer_type; + tim->tim_id = tim_id; + tim->callback = mp_const_none; + MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1] = tim; + } else { + // reference existing Timer object + tim = MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1]; + } + if (n_args > 1 || n_kw > 0) { + // start the peripheral + mp_map_t kw_args; + mp_map_init_fixed_table(&kw_args, n_kw, args + n_args); + pyb_timer_init_helper(tim, n_args - 1, args + 1, &kw_args); + } + return MP_OBJ_FROM_PTR(tim); +} + +STATIC mp_obj_t pyb_timer_init(size_t n_args, const mp_obj_t *args, mp_map_t *kw_args) { + return pyb_timer_init_helper(MP_OBJ_TO_PTR(args[0]), n_args - 1, args + 1, kw_args); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_init_obj, 1, pyb_timer_init); + +/// \method deinit() +/// Deinitialises the timer. +/// +/// Disables the callback (and the associated irq). +/// Disables any channel callbacks (and the associated irq). +/// Stops the timer, and disables the timer peripheral. +STATIC mp_obj_t pyb_timer_deinit(mp_obj_t self_in) { + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + + // Disable the base interrupt + pyb_timer_callback(self_in, mp_const_none); + + #if defined(TIMER_CHANNEL) + pyb_timer_channel_obj_t *chan = self->channel; + self->channel = NULL; + + // Disable the channel interrupts + while (chan != NULL) { + pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), mp_const_none); + pyb_timer_channel_obj_t *prev_chan = chan; + chan = chan->next; + prev_chan->next = NULL; + } + #endif + + ra_agt_timer_deinit(self->tim_id - 1); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_timer_deinit_obj, pyb_timer_deinit); + +#if defined(TIMER_CHANNEL) +/// \method channel(channel, mode, ...) +/// +/// If only a channel number is passed, then a previously initialized channel +/// object is returned (or `None` if there is no previous channel). +/// +/// Othwerwise, a TimerChannel object is initialized and returned. +/// +/// Each channel can be configured to perform pwm, output compare, or +/// input capture. All channels share the same underlying timer, which means +/// that they share the same timer clock. +/// +STATIC mp_obj_t pyb_timer_channel(size_t n_args, const mp_obj_t *pos_args, mp_map_t *kw_args) { + static const mp_arg_t allowed_args[] = { + { MP_QSTR_callback, MP_ARG_KW_ONLY | MP_ARG_OBJ, {.u_rom_obj = MP_ROM_NONE} }, + { MP_QSTR_compare, MP_ARG_KW_ONLY | MP_ARG_INT, {.u_int = 0} }, + }; + + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(pos_args[0]); + mp_int_t channel = mp_obj_get_int(pos_args[1]); + + if (channel < 1 || channel > 4) { + mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT("invalid channel (%d)"), channel); + } + + pyb_timer_channel_obj_t *chan = self->channel; + pyb_timer_channel_obj_t *prev_chan = NULL; + + while (chan != NULL) { + if (chan->channel == channel) { + break; + } + prev_chan = chan; + chan = chan->next; + } + + // If only the channel number is given return the previously allocated + // channel (or None if no previous channel). + if (n_args == 2 && kw_args->used == 0) { + if (chan) { + return MP_OBJ_FROM_PTR(chan); + } + return mp_const_none; + } + + // If there was already a channel, then remove it from the list. Note that + // the order we do things here is important so as to appear atomic to + // the IRQ handler. + if (chan) { + // Turn off any IRQ associated with the channel. + pyb_timer_channel_callback(MP_OBJ_FROM_PTR(chan), mp_const_none); + + // Unlink the channel from the list. + if (prev_chan) { + prev_chan->next = chan->next; + } + self->channel = chan->next; + chan->next = NULL; + } + + // Allocate and initialize a new channel + mp_arg_val_t args[MP_ARRAY_SIZE(allowed_args)]; + mp_arg_parse_all(n_args - 2, pos_args + 2, kw_args, MP_ARRAY_SIZE(allowed_args), allowed_args, args); + + chan = m_new_obj(pyb_timer_channel_obj_t); + memset(chan, 0, sizeof(*chan)); + chan->base.type = &pyb_timer_channel_type; + chan->timer = self; + chan->channel = channel; + chan->callback = args[1].u_obj; + + mp_obj_t pin_obj = args[2].u_obj; + if (pin_obj != mp_const_none) { + // ToDo + } + // Link the channel to the timer before we turn the channel on. + // Note that this needs to appear atomic to the IRQ handler (the write + // to self->channel is atomic, so we're good, but I thought I'd mention + // in case this was ever changed in the future). + chan->next = self->channel; + self->channel = chan; + + // ToDo + return MP_OBJ_FROM_PTR(chan); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_KW(pyb_timer_channel_obj, 2, pyb_timer_channel); +#endif + +#if TIMER_COUNTER +// Not implemented +/// \method counter([value]) +/// Get or set the timer counter. +STATIC mp_obj_t pyb_timer_counter(size_t n_args, const mp_obj_t *args) { + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + // get + return mp_obj_new_int((int)ra_agt_timer_get_counter(self->tim_id)); + } else { + // set + ra_agt_timer_set_counter((unsigned int)self->tim_id, (unsigned long)mp_obj_get_int(args[1])); + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_counter_obj, 1, 2, pyb_timer_counter); +#endif + +/// \method freq([value]) +/// Get or set the frequency for the timer (changes prescaler and period if set). +STATIC mp_obj_t pyb_timer_freq(size_t n_args, const mp_obj_t *args) { + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]); + int ch = self->tim_id - 1; + if (n_args == 1) { + // get + #if MICROPY_PY_BUILTINS_FLOAT + float freq = ra_agt_timer_get_freq(ch); + return mp_obj_new_float(freq); + #else + uint32_t freq = (uint32_t)ra_agt_timer_get_freq(ch); + return mp_obj_new_int(freq); + #endif + } else { + // set + uint32_t freq; + if (0) { + #if MICROPY_PY_BUILTINS_FLOAT + } else if (mp_obj_is_type(args[1], &mp_type_float)) { + freq = (int)mp_obj_get_float(args[1]); + #endif + } else { + freq = mp_obj_get_int(args[1]); + } + if (freq == 0) { + mp_raise_ValueError(MP_ERROR_TEXT("freq must not be 0")); + } + ra_agt_timer_stop(ch); + ra_agt_timer_set_freq(ch, (float)freq); + ra_agt_timer_start(ch); + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_freq_obj, 1, 2, pyb_timer_freq); + +#if TIMER_PERIOD +// Not implemented +/// \method period([value]) +/// Get or set the period of the timer. +STATIC mp_obj_t pyb_timer_period(size_t n_args, const mp_obj_t *args) { + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + // get + return mp_obj_new_int((int)ra_agt_timer_get_period(self->tim_id)); + return mp_const_none; + } else { + // set + ra_agt_timer_set_period((uint32_t)self->tim_id, (uint16_t)mp_obj_get_int(args[1])); + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_period_obj, 1, 2, pyb_timer_period); +#endif + +/// \method callback(fun) +/// Set the function to be called when the timer triggers. +/// `fun` is passed 1 argument, the timer object. +/// If `fun` is `None` then the callback will be disabled. +STATIC mp_obj_t pyb_timer_callback(mp_obj_t self_in, mp_obj_t callback) { + pyb_timer_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (callback == mp_const_none) { + // stop interrupt (but not timer) + // __HAL_TIM_DISABLE_IT(&self->tim, TIM_IT_UPDATE); + self->callback = mp_const_none; + } else if (mp_obj_is_callable(callback)) { + // __HAL_TIM_DISABLE_IT(&self->tim, TIM_IT_UPDATE); + self->callback = callback; + // start timer, so that it interrupts on overflow, but clear any + // pending interrupts which may have been set by initializing it. + // __HAL_TIM_CLEAR_FLAG(&self->tim, TIM_IT_UPDATE); + // HAL_TIM_Base_Start_IT(&self->tim); // This will re-enable the IRQ + // HAL_NVIC_EnableIRQ(self->irqn); + } else { + mp_raise_ValueError(MP_ERROR_TEXT("callback must be None or a callable object")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_timer_callback_obj, pyb_timer_callback); + +STATIC const mp_rom_map_elem_t pyb_timer_locals_dict_table[] = { + // instance methods + { MP_ROM_QSTR(MP_QSTR_init), MP_ROM_PTR(&pyb_timer_init_obj) }, + { MP_ROM_QSTR(MP_QSTR_deinit), MP_ROM_PTR(&pyb_timer_deinit_obj) }, + #if TIMER_COUNTER + { MP_ROM_QSTR(MP_QSTR_counter), MP_ROM_PTR(&pyb_timer_counter_obj) }, + #endif + { MP_ROM_QSTR(MP_QSTR_freq), MP_ROM_PTR(&pyb_timer_freq_obj) }, + #if TIMER_PERIOD + { MP_ROM_QSTR(MP_QSTR_period), MP_ROM_PTR(&pyb_timer_period_obj) }, + #endif + { MP_ROM_QSTR(MP_QSTR_callback), MP_ROM_PTR(&pyb_timer_callback_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(pyb_timer_locals_dict, pyb_timer_locals_dict_table); + +const mp_obj_type_t pyb_timer_type = { + { &mp_type_type }, + .name = MP_QSTR_Timer, + .print = pyb_timer_print, + .make_new = pyb_timer_make_new, + .locals_dict = (mp_obj_dict_t *)&pyb_timer_locals_dict, +}; + +#if defined(TIMER_CHANNEL) +/* + * Timer Channel + */ + +/// \moduleref pyb +/// \class TimerChannel - setup a channel for a timer. +/// +/// Timer channels are used to generate/capture a signal using a timer. +/// +/// TimerChannel objects are created using the Timer.channel() method. +STATIC void pyb_timer_channel_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(self_in); + + mp_printf(print, "TimerChannel(timer=%u, channel=%u", + self->timer->tim_id, + self->channel); +} + +/// \method capture([value]) +/// Get or set the capture value associated with a channel. +/// capture, compare, and pulse_width are all aliases for the same function. +/// capture is the logical name to use when the channel is in input capture mode. + +/// \method compare([value]) +/// Get or set the compare value associated with a channel. +/// capture, compare, and pulse_width are all aliases for the same function. +/// compare is the logical name to use when the channel is in output compare mode. + +/// \method pulse_width([value]) +/// Get or set the pulse width value associated with a channel. +/// capture, compare, and pulse_width are all aliases for the same function. +/// pulse_width is the logical name to use when the channel is in PWM mode. +/// +/// In edge aligned mode, a pulse_width of `period + 1` corresponds to a duty cycle of 100% +/// In center aligned mode, a pulse width of `period` corresponds to a duty cycle of 100% +STATIC mp_obj_t pyb_timer_channel_capture_compare(size_t n_args, const mp_obj_t *args) { + pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(args[0]); + if (n_args == 1) { + // get + return mp_const_none; + } else { + // set + // __HAL_TIM_SET_COMPARE(&self->timer->tim, TIMER_CHANNEL(self), mp_obj_get_int(args[1]) & TIMER_CNT_MASK(self->timer)); + return mp_const_none; + } +} +STATIC MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_timer_channel_capture_compare_obj, 1, 2, pyb_timer_channel_capture_compare); + +/// \method callback(fun) +/// Set the function to be called when the timer channel triggers. +/// `fun` is passed 1 argument, the timer object. +/// If `fun` is `None` then the callback will be disabled. +STATIC mp_obj_t pyb_timer_channel_callback(mp_obj_t self_in, mp_obj_t callback) { + pyb_timer_channel_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (callback == mp_const_none) { + // stop interrupt (but not timer) + // _HAL_TIM_DISABLE_IT(&self->timer->tim, TIMER_IRQ_MASK(self->channel)); + self->callback = mp_const_none; + } else if (mp_obj_is_callable(callback)) { + self->callback = callback; + uint8_t tim_id = self->timer->tim_id; + // __HAL_TIM_CLEAR_IT(&self->timer->tim, TIMER_IRQ_MASK(self->channel)); + if (tim_id == 1) { + // HAL_NVIC_EnableIRQ(TIM1_CC_IRQn); + } else { + // HAL_NVIC_EnableIRQ(self->timer->irqn); + } + // start timer, so that it interrupts on overflow + } else { + mp_raise_ValueError(MP_ERROR_TEXT("callback must be None or a callable object")); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_timer_channel_callback_obj, pyb_timer_channel_callback); + +STATIC const mp_rom_map_elem_t pyb_timer_channel_locals_dict_table[] = { + // instance methods + { MP_ROM_QSTR(MP_QSTR_callback), MP_ROM_PTR(&pyb_timer_channel_callback_obj) }, + { MP_ROM_QSTR(MP_QSTR_capture), MP_ROM_PTR(&pyb_timer_channel_capture_compare_obj) }, + { MP_ROM_QSTR(MP_QSTR_compare), MP_ROM_PTR(&pyb_timer_channel_capture_compare_obj) }, +}; +STATIC MP_DEFINE_CONST_DICT(pyb_timer_channel_locals_dict, pyb_timer_channel_locals_dict_table); + +STATIC const mp_obj_type_t pyb_timer_channel_type = { + { &mp_type_type }, + .name = MP_QSTR_TimerChannel, + .print = pyb_timer_channel_print, + .locals_dict = (mp_obj_dict_t *)&pyb_timer_channel_locals_dict, +}; +#endif + +STATIC void timer_handle_irq_channel(pyb_timer_obj_t *tim, uint8_t channel, mp_obj_t callback) { + + // execute callback if it's set + if (callback != mp_const_none) { + mp_sched_lock(); + // When executing code within a handler we must lock the GC to prevent + // any memory allocations. We must also catch any exceptions. + gc_lock(); + nlr_buf_t nlr; + if (nlr_push(&nlr) == 0) { + mp_call_function_1(callback, MP_OBJ_FROM_PTR(tim)); + nlr_pop(); + } else { + // Uncaught exception; disable the callback so it doesn't run again. + tim->callback = mp_const_none; + // __HAL_TIM_DISABLE_IT(&tim->tim, irq_mask); + if (channel == 0) { + mp_printf(MICROPY_ERROR_PRINTER, "uncaught exception in Timer(%u) interrupt handler\n", tim->tim_id); + } else { + mp_printf(MICROPY_ERROR_PRINTER, "uncaught exception in Timer(%u) channel %u interrupt handler\n", tim->tim_id, channel); + } + mp_obj_print_exception(&mp_plat_print, MP_OBJ_FROM_PTR(nlr.ret_val)); + } + gc_unlock(); + mp_sched_unlock(); + } +} + +void timer_irq_handler(void *param) { + uint tim_id = *(uint *)param; + if ((tim_id != 0) && (tim_id - 1 < PYB_TIMER_OBJ_ALL_NUM)) { + // get the timer object + pyb_timer_obj_t *tim = MP_STATE_PORT(pyb_timer_obj_all)[tim_id - 1]; + + if (tim == NULL) { + // do nohting + return; + } + timer_handle_irq_channel(tim, 0, tim->callback); + // Check to see if a timer channel interrupt was pending + #if defined(TIMER_CHANNEL) + pyb_timer_channel_obj_t *chan = tim->channel; + while (chan != NULL) { + timer_handle_irq_channel(tim, chan->channel, chan->callback); + // handled |= TIMER_IRQ_MASK(chan->channel); + chan = chan->next; + } + #endif + // ToDo + // Finally, clear any remaining interrupt sources. Otherwise we'll + // just get called continuously. + // uint32_t unhandled = 0; + // if (unhandled != 0) { + // printf("Unhandled interrupt SR=0x%02x (now disabled)\n", (unsigned int)unhandled); + // } + } +} diff --git a/ports/renesas-ra/timer.h b/ports/renesas-ra/timer.h new file mode 100644 index 000000000..a4bfb63c5 --- /dev/null +++ b/ports/renesas-ra/timer.h @@ -0,0 +1,36 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_RA_TIMER_H +#define MICROPY_INCLUDED_RA_TIMER_H + +extern const mp_obj_type_t pyb_timer_type; + +void timer_init0(void); +void timer_deinit(void); + +#endif // MICROPY_INCLUDED_RA_TIMER_H diff --git a/ports/renesas-ra/uart.c b/ports/renesas-ra/uart.c new file mode 100644 index 000000000..ddb77bfd5 --- /dev/null +++ b/ports/renesas-ra/uart.c @@ -0,0 +1,514 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> +#include <string.h> +#include <stdarg.h> + +#include "py/runtime.h" +#include "py/stream.h" +#include "py/mperrno.h" +#include "py/mphal.h" +#include "shared/runtime/interrupt_char.h" +#include "shared/runtime/mpirq.h" +#include "uart.h" +#include "irq.h" +#include "pendsv.h" + +typedef int (*KEYEX_CB)(uint32_t d); + +extern void NORETURN __fatal_error(const char *msg); +#if MICROPY_KBD_EXCEPTION +extern int mp_interrupt_char; +static KEYEX_CB keyex_cb[MICROPY_HW_MAX_UART] = {(KEYEX_CB)NULL}; + +static int chk_kbd_interrupt(int d) { + if (d == mp_interrupt_char) { + pendsv_kbd_intr(); + return 1; + } else { + return 0; + } +} + +static void set_kbd_interrupt(uint32_t ch, void *keyex) { + ra_sci_rxirq_disable(ch); + keyex_cb[ch] = (KEYEX_CB)keyex; + ra_sci_rxirq_enable(ch); +} + +#endif + +static void uart_rx_cb(uint32_t ch, int d) { + pyb_uart_obj_t *self = MP_STATE_PORT(pyb_uart_obj_all)[ch]; + if (self == NULL) { + // UART object has not been set, so we can't do anything, not + // even disable the IRQ. This should never happen. + return; + } + #if MICROPY_KBD_EXCEPTION + if (keyex_cb[ch]) { + (*keyex_cb[ch])(d); + } + #endif + // Check the flags to see if the user handler should be called + if (self->mp_irq_trigger) { + mp_irq_handler(self->mp_irq_obj); + } +} + +void uart_init0(void) { +} + +// unregister all interrupt sources +void uart_deinit_all(void) { + for (int i = 0; i < MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all)); i++) { + pyb_uart_obj_t *uart_obj = MP_STATE_PORT(pyb_uart_obj_all)[i]; + if (uart_obj != NULL && !uart_obj->is_static) { + uart_deinit(uart_obj); + MP_STATE_PORT(pyb_uart_obj_all)[i] = NULL; + } + } +} + +bool uart_exists(int uart_id) { + if (uart_id > MP_ARRAY_SIZE(MP_STATE_PORT(pyb_uart_obj_all))) { + // safeguard against pyb_uart_obj_all array being configured too small + return false; + } + switch (uart_id) { + #if defined(MICROPY_HW_UART0_TX) && defined(MICROPY_HW_UART0_RX) + case HW_UART_0: + return true; + #endif + + #if defined(MICROPY_HW_UART1_TX) && defined(MICROPY_HW_UART1_RX) + case HW_UART_1: + return true; + #endif + + #if defined(MICROPY_HW_UART2_TX) && defined(MICROPY_HW_UART2_RX) + case HW_UART_2: + return true; + #endif + + #if defined(MICROPY_HW_UART3_TX) && defined(MICROPY_HW_UART3_RX) + case HW_UART_3: + return true; + #endif + + #if defined(MICROPY_HW_UART4_TX) && defined(MICROPY_HW_UART4_RX) + case HW_UART_4: + return true; + #endif + + #if defined(MICROPY_HW_UART5_TX) && defined(MICROPY_HW_UART5_RX) + case HW_UART_5: + return true; + #endif + + #if defined(MICROPY_HW_UART6_TX) && defined(MICROPY_HW_UART6_RX) + case HW_UART_6: + return true; + #endif + + #if defined(MICROPY_HW_UART7_TX) && defined(MICROPY_HW_UART7_RX) + case HW_UART_7: + return true; + #endif + + #if defined(MICROPY_HW_UART8_TX) && defined(MICROPY_HW_UART8_RX) + case HW_UART_8: + return true; + #endif + + #if defined(MICROPY_HW_UART9_TX) && defined(MICROPY_HW_UART9_RX) + case HW_UART_9: + return true; + #endif + + default: + return false; + } +} + +// assumes Init parameters have been set up correctly +bool uart_init(pyb_uart_obj_t *uart_obj, + uint32_t baudrate, uint32_t bits, uint32_t parity, uint32_t stop, uint32_t flow) { + uart_obj->baudrate = (uint32_t)baudrate; + uart_obj->bits = (uint8_t)bits; + uart_obj->parity = (uint8_t)parity; + uart_obj->stop = (uint8_t)stop; + uart_obj->flow = (uint8_t)flow; + + const machine_pin_obj_t *pins[4] = {0}; + + switch (uart_obj->uart_id) { + #if defined(MICROPY_HW_UART0_TX) && defined(MICROPY_HW_UART0_RX) + case HW_UART_0: + pins[0] = MICROPY_HW_UART0_TX; + pins[1] = MICROPY_HW_UART0_RX; + #if defined(MICROPY_HW_UART0_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART0_RTS; + } + #endif + #if defined(MICROPY_HW_UART0_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART0_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART1_TX) && defined(MICROPY_HW_UART1_RX) + case HW_UART_1: + pins[0] = MICROPY_HW_UART1_TX; + pins[1] = MICROPY_HW_UART1_RX; + #if defined(MICROPY_HW_UART1_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART1_RTS; + } + #endif + #if defined(MICROPY_HW_UART1_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART1_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART2_TX) && defined(MICROPY_HW_UART2_RX) + case HW_UART_2: + pins[0] = MICROPY_HW_UART2_TX; + pins[1] = MICROPY_HW_UART2_RX; + #if defined(MICROPY_HW_UART2_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART2_RTS; + } + #endif + #if defined(MICROPY_HW_UART2_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART2_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART3_TX) && defined(MICROPY_HW_UART3_RX) + case HW_UART_3: + pins[0] = MICROPY_HW_UART3_TX; + pins[1] = MICROPY_HW_UART3_RX; + #if defined(MICROPY_HW_UART3_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART3_RTS; + } + #endif + #if defined(MICROPY_HW_UART3_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART3_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART4_TX) && defined(MICROPY_HW_UART4_RX) + case HW_UART_4: + pins[0] = MICROPY_HW_UART4_TX; + pins[1] = MICROPY_HW_UART4_RX; + #if defined(MICROPY_HW_UART4_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART4_RTS; + } + #endif + #if defined(MICROPY_HW_UART4_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART4_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART5_TX) && defined(MICROPY_HW_UART5_RX) + case HW_UART_5: + pins[0] = MICROPY_HW_UART5_TX; + pins[1] = MICROPY_HW_UART5_RX; + #if defined(MICROPY_HW_UART5_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART5_RTS; + } + #endif + #if defined(MICROPY_HW_UART5_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART5_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART6_TX) && defined(MICROPY_HW_UART6_RX) + case HW_UART_6: + pins[0] = MICROPY_HW_UART6_TX; + pins[1] = MICROPY_HW_UART6_RX; + #if defined(MICROPY_HW_UART6_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART6_RTS; + } + #endif + #if defined(MICROPY_HW_UART6_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART6_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART7_TX) && defined(MICROPY_HW_UART7_RX) + case HW_UART_7: + pins[0] = MICROPY_HW_UART7_TX; + pins[1] = MICROPY_HW_UART7_RX; + #if defined(MICROPY_HW_UART7_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART7_RTS; + } + #endif + #if defined(MICROPY_HW_UART7_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART7_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART8_TX) && defined(MICROPY_HW_UART8_RX) + case HW_UART_8: + pins[0] = MICROPY_HW_UART8_TX; + pins[1] = MICROPY_HW_UART8_RX; + #if defined(MICROPY_HW_UART8_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART8_RTS; + } + #endif + #if defined(MICROPY_HW_UART8_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART8_CTS; + } + #endif + break; + #endif + + #if defined(MICROPY_HW_UART9_TX) && defined(MICROPY_HW_UART9_RX) + case HW_UART_9: + pins[0] = MICROPY_HW_UART9_TX; + pins[1] = MICROPY_HW_UART9_RX; + #if defined(MICROPY_HW_UART9_RTS) + if (flow) { + pins[2] = MICROPY_HW_UART9_RTS; + } + #endif + #if defined(MICROPY_HW_UART9_CTS) + if (flow) { + pins[3] = MICROPY_HW_UART9_CTS; + } + #endif + break; + #endif + + default: + // UART does not exist or is not configured for this board + return false; + } + uart_obj->tx = pins[0]; + uart_obj->rx = pins[1]; + uart_obj->rts = pins[2]; + uart_obj->cts = pins[3]; + + if (flow && (uart_obj->rts != 0) && (uart_obj->cts != 0)) { + ra_sci_init_with_flow(uart_obj->uart_id, (uint32_t)uart_obj->tx->pin, (uint32_t)uart_obj->rx->pin, baudrate, bits, parity, stop, flow, (uint32_t)uart_obj->rts->pin, (uint32_t)uart_obj->cts->pin); + } else { + ra_sci_init(uart_obj->uart_id, (uint32_t)uart_obj->tx->pin, (uint32_t)uart_obj->rx->pin, baudrate, bits, parity, stop, flow); + } + ra_sci_rx_set_callback((int)uart_obj->uart_id, (SCI_CB)uart_rx_cb); + uart_obj->is_enabled = true; + uart_obj->attached_to_repl = false; + + if (bits == 9 && parity == UART_PARITY_NONE) { + uart_obj->char_mask = 0x1ff; + uart_obj->char_width = CHAR_WIDTH_9BIT; + } else { + if (bits == 9 || parity == UART_PARITY_NONE) { + uart_obj->char_mask = 0xff; + } else { + uart_obj->char_mask = 0x7f; + } + uart_obj->char_width = CHAR_WIDTH_8BIT; + } + + uart_obj->mp_irq_trigger = 0; + uart_obj->mp_irq_obj = NULL; + + return true; +} + +void uart_irq_config(pyb_uart_obj_t *self, bool enable) { + if (self->mp_irq_trigger) { + if (enable) { + ra_sci_rxirq_enable(self->uart_id); + } else { + ra_sci_rxirq_disable(self->uart_id); + } + } +} + +void uart_set_rxbuf(pyb_uart_obj_t *self, size_t len, void *buf) { + // len = 0 (no interrupt) is not supported. static buf is used. + self->read_buf_len = len; + self->read_buf = buf; + if (len) { + int ch = (int)self->uart_id; + ra_sci_rxfifo_set(ch, (uint8_t *)buf, (uint32_t)len); + } +} + +void uart_deinit(pyb_uart_obj_t *self) { + self->is_enabled = false; + ra_sci_deinit(self->uart_id); +} + +void uart_attach_to_repl(pyb_uart_obj_t *self, bool attached) { + self->attached_to_repl = attached; + #if MICROPY_KBD_EXCEPTION + if (attached) { + set_kbd_interrupt((int)self->uart_id, (SCI_CB)chk_kbd_interrupt); + } else { + set_kbd_interrupt((int)self->uart_id, (SCI_CB)NULL); + } + #endif +} + +mp_uint_t uart_rx_any(pyb_uart_obj_t *self) { + int ch = (int)self->uart_id; + return ra_sci_rx_any(ch); +} + +mp_uint_t uart_tx_avail(pyb_uart_obj_t *self) { + int ch = (int)self->uart_id; + return ra_sci_tx_wait(ch); +} + +// Waits at most timeout milliseconds for at least 1 char to become ready for +// reading (from buf or for direct reading). +// Returns true if something available, false if not. +bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout) { + int ch = (int)self->uart_id; + uint32_t start = HAL_GetTick(); + for (;;) { + if (ra_sci_rx_any(ch)) { + return true; + } + if (HAL_GetTick() - start >= timeout) { + return false; // timeout + } + MICROPY_EVENT_POLL_HOOK + } +} + +// assumes there is a character available +int uart_rx_char(pyb_uart_obj_t *self) { + int ch = (int)self->uart_id; + return ra_sci_rx_ch(ch); +} + +// Waits at most timeout milliseconds for TX register to become empty. +// Returns true if can write, false if can't. +bool uart_tx_wait(pyb_uart_obj_t *self, uint32_t timeout) { + uint32_t start = HAL_GetTick(); + for (;;) { + if (uart_tx_avail(self)) { + return true; + } + if (HAL_GetTick() - start >= timeout) { + return false; // timeout + } + MICROPY_EVENT_POLL_HOOK + } +} + +// src - a pointer to the data to send (16-bit aligned for 9-bit chars) +// num_chars - number of characters to send (9-bit chars count for 2 bytes from src) +// *errcode - returns 0 for success, MP_Exxx on error +// returns the number of characters sent (valid even if there was an error) +size_t uart_tx_data(pyb_uart_obj_t *self, const void *src_in, size_t num_chars, int *errcode) { + int ch = (int)self->uart_id; + uint8_t *d8 = (uint8_t *)src_in; + uint16_t *d16 = (uint16_t *)src_in; + if (num_chars == 0) { + *errcode = 0; + return 0; + } + int i; + if (self->char_width == CHAR_WIDTH_9BIT) { + for (i = 0; i < (int)num_chars; i++) { + ra_sci_tx_ch(ch, (int)*d16++); + } + } else { + for (i = 0; i < (int)num_chars; i++) { + ra_sci_tx_ch(ch, (int)*d8++); + } + } + + *errcode = 0; + return (size_t)num_chars; +} + +void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len) { + int errcode; + uart_tx_data(uart_obj, str, len, &errcode); +} + +STATIC mp_uint_t uart_irq_trigger(mp_obj_t self_in, mp_uint_t new_trigger) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + uart_irq_config(self, false); + self->mp_irq_trigger = new_trigger; + uart_irq_config(self, true); + return 0; +} + +STATIC mp_uint_t uart_irq_info(mp_obj_t self_in, mp_uint_t info_type) { + pyb_uart_obj_t *self = MP_OBJ_TO_PTR(self_in); + if (info_type == MP_IRQ_INFO_FLAGS) { + return self->mp_irq_flags; + } else if (info_type == MP_IRQ_INFO_TRIGGERS) { + return self->mp_irq_trigger; + } + return 0; +} + +const mp_irq_methods_t uart_irq_methods = { + .trigger = uart_irq_trigger, + .info = uart_irq_info, +}; diff --git a/ports/renesas-ra/uart.h b/ports/renesas-ra/uart.h new file mode 100644 index 000000000..01f1bc82d --- /dev/null +++ b/ports/renesas-ra/uart.h @@ -0,0 +1,115 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef MICROPY_INCLUDED_RA_UART_H +#define MICROPY_INCLUDED_RA_UART_H + +#include "shared/runtime/mpirq.h" +#include "pin.h" + +typedef enum { + HW_UART_0 = 0, + HW_UART_1 = 1, + HW_UART_2 = 2, + HW_UART_3 = 3, + HW_UART_4 = 4, + HW_UART_5 = 5, + HW_UART_6 = 6, + HW_UART_7 = 7, + HW_UART_8 = 8, + HW_UART_9 = 9, +} pyb_uart_t; + +#define CHAR_WIDTH_8BIT (0) +#define CHAR_WIDTH_9BIT (1) + +#define UART_WORDLENGTH_8B (8) +#define UART_STOPBITS_1 (1) +#define UART_STOPBITS_2 (2) +#define UART_PARITY_NONE (0) +#define UART_PARITY_ODD (1) +#define UART_PARITY_EVEN (2) + +#define UART_HWCONTROL_CTS (1) +#define UART_HWCONTROL_RTS (2) + +// OR-ed IRQ flags which are allowed to be used by the user +#define MP_UART_ALLOWED_FLAGS ((uint32_t)0x00000010) + +// OR-ed IRQ flags which should not be touched by the user +#define MP_UART_RESERVED_FLAGS ((uint16_t)0x0020) + +typedef struct _pyb_uart_obj_t { + mp_obj_base_t base; + pyb_uart_t uart_id : 8; + uint32_t baudrate; + const machine_pin_obj_t *rx; + const machine_pin_obj_t *tx; + const machine_pin_obj_t *cts; + const machine_pin_obj_t *rts; + uint8_t bits; + uint8_t parity; + uint8_t stop; + uint8_t flow; + bool is_static : 1; + bool is_enabled : 1; + bool attached_to_repl; // whether the UART is attached to REPL + byte char_width; // 0 for 7,8 bit chars, 1 for 9 bit chars + uint16_t char_mask; // 0x7f for 7 bit, 0xff for 8 bit, 0x1ff for 9 bit + uint16_t timeout; // timeout waiting for first char + uint16_t timeout_char; // timeout waiting between chars + uint16_t read_buf_len; // len in chars; buf can hold len-1 chars + byte *read_buf; // byte or uint16_t, depending on char size + uint16_t mp_irq_trigger; // user IRQ trigger mask + uint16_t mp_irq_flags; // user IRQ active IRQ flags + mp_irq_obj_t *mp_irq_obj; // user IRQ object +} pyb_uart_obj_t; + +extern const mp_obj_type_t pyb_uart_type; +extern const mp_irq_methods_t uart_irq_methods; + +void uart_init0(void); +void uart_deinit_all(void); +bool uart_exists(int uart_id); +bool uart_init(pyb_uart_obj_t *uart_obj, + uint32_t baudrate, uint32_t bits, uint32_t parity, uint32_t stop, uint32_t flow); +void uart_irq_config(pyb_uart_obj_t *self, bool enable); +void uart_set_rxbuf(pyb_uart_obj_t *self, size_t len, void *buf); +void uart_deinit(pyb_uart_obj_t *uart_obj); +// void uart_irq_handler(mp_uint_t uart_id); + +void uart_attach_to_repl(pyb_uart_obj_t *self, bool attached); +uint32_t uart_get_baudrate(pyb_uart_obj_t *self); +mp_uint_t uart_rx_any(pyb_uart_obj_t *uart_obj); +mp_uint_t uart_tx_avail(pyb_uart_obj_t *uart_obj); +bool uart_rx_wait(pyb_uart_obj_t *self, uint32_t timeout); +int uart_rx_char(pyb_uart_obj_t *uart_obj); +bool uart_tx_wait(pyb_uart_obj_t *self, uint32_t timeout); +size_t uart_tx_data(pyb_uart_obj_t *self, const void *src_in, size_t num_chars, int *errcode); +void uart_tx_strn(pyb_uart_obj_t *uart_obj, const char *str, uint len); + +#endif // MICROPY_INCLUDED_RA_UART_H diff --git a/ports/renesas-ra/usrsw.c b/ports/renesas-ra/usrsw.c new file mode 100644 index 000000000..b0e2396cd --- /dev/null +++ b/ports/renesas-ra/usrsw.c @@ -0,0 +1,147 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * Copyright (c) 2021 Renesas Electronics Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include <stdio.h> + +#include "py/runtime.h" +#include "py/mphal.h" +#include "extint.h" +#include "pin.h" +#include "usrsw.h" + +#if MICROPY_HW_HAS_SWITCH + +/// \moduleref pyb +/// \class Switch - switch object +/// +/// A Switch object is used to control a push-button switch. +/// +/// Usage: +/// +/// sw = pyb.Switch() # create a switch object +/// sw() # get state (True if pressed, False otherwise) +/// sw.callback(f) # register a callback to be called when the +/// # switch is pressed down +/// sw.callback(None) # remove the callback +/// +/// Example: +/// +/// pyb.Switch().callback(lambda: pyb.LED(1).toggle()) + +// this function inits the switch GPIO so that it can be used +void switch_init0(void) { + mp_hal_pin_config(MICROPY_HW_USRSW_PIN, MP_HAL_PIN_MODE_INPUT, MICROPY_HW_USRSW_PULL, GPIO_LOW_POWER, 0); +} + +int switch_get(void) { + int val = (mp_hal_pin_read(MICROPY_HW_USRSW_PIN) != 0); + return val == MICROPY_HW_USRSW_PRESSED; +} + +/******************************************************************************/ +// MicroPython bindings + +typedef struct _pyb_switch_obj_t { + mp_obj_base_t base; +} pyb_switch_obj_t; + +STATIC const pyb_switch_obj_t pyb_switch_obj = {{&pyb_switch_type}}; + +void pyb_switch_print(const mp_print_t *print, mp_obj_t self_in, mp_print_kind_t kind) { + mp_print_str(print, "Switch()"); +} + +/// \classmethod \constructor() +/// Create and return a switch object. +STATIC mp_obj_t pyb_switch_make_new(const mp_obj_type_t *type, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // check arguments + mp_arg_check_num(n_args, n_kw, 0, 0, false); + + // No need to clear the callback member: if it's already been set and registered + // with extint then we don't want to reset that behaviour. If it hasn't been set, + // then no extint will be called until it is set via the callback method. + + // return static switch object + return MP_OBJ_FROM_PTR(&pyb_switch_obj); +} + +/// \method \call() +/// Return the switch state: `True` if pressed down, `False` otherwise. +mp_obj_t pyb_switch_call(mp_obj_t self_in, size_t n_args, size_t n_kw, const mp_obj_t *args) { + // get switch state + mp_arg_check_num(n_args, n_kw, 0, 0, false); + return switch_get() ? mp_const_true : mp_const_false; +} + +mp_obj_t pyb_switch_value(mp_obj_t self_in) { + (void)self_in; + return mp_obj_new_bool(switch_get()); +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(pyb_switch_value_obj, pyb_switch_value); + +STATIC mp_obj_t switch_callback(mp_obj_t line) { + if (MP_STATE_PORT(pyb_switch_callback) != mp_const_none) { + mp_call_function_0(MP_STATE_PORT(pyb_switch_callback)); + } + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_1(switch_callback_obj, switch_callback); + +/// \method callback(fun) +/// Register the given function to be called when the switch is pressed down. +/// If `fun` is `None`, then it disables the callback. +mp_obj_t pyb_switch_callback(mp_obj_t self_in, mp_obj_t callback) { + MP_STATE_PORT(pyb_switch_callback) = callback; + // Init the EXTI each time this function is called, since the EXTI + // may have been disabled by an exception in the interrupt, or the + // user disabling the line explicitly. + extint_register(MP_OBJ_FROM_PTR(MICROPY_HW_USRSW_PIN), + MICROPY_HW_USRSW_EXTI_MODE, + MICROPY_HW_USRSW_PULL, + callback == mp_const_none ? mp_const_none : MP_OBJ_FROM_PTR(&switch_callback_obj), + true); + return mp_const_none; +} +STATIC MP_DEFINE_CONST_FUN_OBJ_2(pyb_switch_callback_obj, pyb_switch_callback); + +STATIC const mp_rom_map_elem_t pyb_switch_locals_dict_table[] = { + { MP_ROM_QSTR(MP_QSTR_value), MP_ROM_PTR(&pyb_switch_value_obj) }, + { MP_ROM_QSTR(MP_QSTR_callback), MP_ROM_PTR(&pyb_switch_callback_obj) }, +}; + +STATIC MP_DEFINE_CONST_DICT(pyb_switch_locals_dict, pyb_switch_locals_dict_table); + +const mp_obj_type_t pyb_switch_type = { + { &mp_type_type }, + .name = MP_QSTR_Switch, + .print = pyb_switch_print, + .make_new = pyb_switch_make_new, + .call = pyb_switch_call, + .locals_dict = (mp_obj_dict_t *)&pyb_switch_locals_dict, +}; + +#endif // MICROPY_HW_HAS_SWITCH diff --git a/ports/renesas-ra/usrsw.h b/ports/renesas-ra/usrsw.h new file mode 100644 index 000000000..ac82719c3 --- /dev/null +++ b/ports/renesas-ra/usrsw.h @@ -0,0 +1,34 @@ +/* + * This file is part of the MicroPython project, http://micropython.org/ + * + * The MIT License (MIT) + * + * Copyright (c) 2013, 2014 Damien P. George + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ +#ifndef MICROPY_INCLUDED_RENESAS_RA_USRSW_H +#define MICROPY_INCLUDED_RENESAS_RA_USRSW_H + +void switch_init0(void); +int switch_get(void); + +extern const mp_obj_type_t pyb_switch_type; + +#endif // MICROPY_INCLUDED_RENESAS_RA_USRSW_H |