diff options
| -rw-r--r-- | ports/stm32/boards/PYBD_SF2/f722_qspi.ld | 4 | ||||
| -rw-r--r-- | ports/stm32/boards/PYBD_SF2/mpconfigboard.h | 2 | ||||
| -rw-r--r-- | ports/stm32/boards/PYBD_SF6/f767.ld | 4 | ||||
| -rw-r--r-- | ports/stm32/boards/PYBD_SF6/mpconfigboard.h | 2 | ||||
| -rw-r--r-- | ports/stm32/mpconfigboard_common.h | 10 | ||||
| -rw-r--r-- | ports/stm32/vfs_rom_ioctl.c | 20 |
6 files changed, 21 insertions, 21 deletions
diff --git a/ports/stm32/boards/PYBD_SF2/f722_qspi.ld b/ports/stm32/boards/PYBD_SF2/f722_qspi.ld index 05126233e..f5e676983 100644 --- a/ports/stm32/boards/PYBD_SF2/f722_qspi.ld +++ b/ports/stm32/boards/PYBD_SF2/f722_qspi.ld @@ -41,8 +41,8 @@ _heap_start = _ebss; /* heap starts just after statically allocated memory */ _heap_end = _sstack; /* ROMFS location */ -_micropy_hw_romfs_part1_start = ORIGIN(FLASH_ROMFS); -_micropy_hw_romfs_part1_size = LENGTH(FLASH_ROMFS); +_micropy_hw_romfs_part0_start = ORIGIN(FLASH_ROMFS); +_micropy_hw_romfs_part0_size = LENGTH(FLASH_ROMFS); /* Define output sections */ SECTIONS diff --git a/ports/stm32/boards/PYBD_SF2/mpconfigboard.h b/ports/stm32/boards/PYBD_SF2/mpconfigboard.h index e8923bf9b..3ae11125d 100644 --- a/ports/stm32/boards/PYBD_SF2/mpconfigboard.h +++ b/ports/stm32/boards/PYBD_SF2/mpconfigboard.h @@ -67,7 +67,7 @@ void board_sleep(int value); // ROMFS config #define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (1) #define MICROPY_HW_ROMFS_QSPI_SPIFLASH_OBJ (&spi_bdev2.spiflash) -#define MICROPY_HW_ROMFS_ENABLE_PART1 (1) +#define MICROPY_HW_ROMFS_ENABLE_PART0 (1) // SPI flash #1, for R/W storage #define MICROPY_HW_SOFTQSPI_SCK_LOW(self) (GPIOE->BSRR = (0x10000 << 11)) diff --git a/ports/stm32/boards/PYBD_SF6/f767.ld b/ports/stm32/boards/PYBD_SF6/f767.ld index 68da1f19d..0ee6cf763 100644 --- a/ports/stm32/boards/PYBD_SF6/f767.ld +++ b/ports/stm32/boards/PYBD_SF6/f767.ld @@ -38,7 +38,7 @@ _heap_start = _ebss; /* heap starts just after statically allocated memory */ _heap_end = _sstack; /* ROMFS location */ -_micropy_hw_romfs_part1_start = ORIGIN(FLASH_ROMFS); -_micropy_hw_romfs_part1_size = LENGTH(FLASH_ROMFS); +_micropy_hw_romfs_part0_start = ORIGIN(FLASH_ROMFS); +_micropy_hw_romfs_part0_size = LENGTH(FLASH_ROMFS); INCLUDE common_bl.ld diff --git a/ports/stm32/boards/PYBD_SF6/mpconfigboard.h b/ports/stm32/boards/PYBD_SF6/mpconfigboard.h index 526a11117..45261523b 100644 --- a/ports/stm32/boards/PYBD_SF6/mpconfigboard.h +++ b/ports/stm32/boards/PYBD_SF6/mpconfigboard.h @@ -48,7 +48,7 @@ // ROMFS config #define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (1) #define MICROPY_HW_ROMFS_QSPI_SPIFLASH_OBJ (&spi_bdev2.spiflash) -#define MICROPY_HW_ROMFS_ENABLE_PART1 (1) +#define MICROPY_HW_ROMFS_ENABLE_PART0 (1) // Extra UART config #define MICROPY_HW_UART7_TX (pyb_pin_W16) diff --git a/ports/stm32/mpconfigboard_common.h b/ports/stm32/mpconfigboard_common.h index 2a650077f..e01a4d4b8 100644 --- a/ports/stm32/mpconfigboard_common.h +++ b/ports/stm32/mpconfigboard_common.h @@ -77,16 +77,16 @@ #define MICROPY_HW_ROMFS_ENABLE_EXTERNAL_QSPI (0) #endif +// Whether to enable ROMFS partition 0. +#ifndef MICROPY_HW_ROMFS_ENABLE_PART0 +#define MICROPY_HW_ROMFS_ENABLE_PART0 (0) +#endif + // Whether to enable ROMFS partition 1. #ifndef MICROPY_HW_ROMFS_ENABLE_PART1 #define MICROPY_HW_ROMFS_ENABLE_PART1 (0) #endif -// Whether to enable ROMFS partition 2. -#ifndef MICROPY_HW_ROMFS_ENABLE_PART2 -#define MICROPY_HW_ROMFS_ENABLE_PART2 (0) -#endif - // Whether to enable storage on the internal flash of the MCU #ifndef MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE #define MICROPY_HW_ENABLE_INTERNAL_FLASH_STORAGE (1) diff --git a/ports/stm32/vfs_rom_ioctl.c b/ports/stm32/vfs_rom_ioctl.c index 5024d44e5..1fa4408c5 100644 --- a/ports/stm32/vfs_rom_ioctl.c +++ b/ports/stm32/vfs_rom_ioctl.c @@ -36,6 +36,13 @@ #if MICROPY_VFS_ROM_IOCTL +#if MICROPY_HW_ROMFS_ENABLE_PART0 && !defined(MICROPY_HW_ROMFS_PART0_START) +#define MICROPY_HW_ROMFS_PART0_START (uintptr_t)(&_micropy_hw_romfs_part0_start) +#define MICROPY_HW_ROMFS_PART0_SIZE (uintptr_t)(&_micropy_hw_romfs_part0_size) +extern uint8_t _micropy_hw_romfs_part0_start; +extern uint8_t _micropy_hw_romfs_part0_size; +#endif + #if MICROPY_HW_ROMFS_ENABLE_PART1 && !defined(MICROPY_HW_ROMFS_PART1_START) #define MICROPY_HW_ROMFS_PART1_START (uintptr_t)(&_micropy_hw_romfs_part1_start) #define MICROPY_HW_ROMFS_PART1_SIZE (uintptr_t)(&_micropy_hw_romfs_part1_size) @@ -43,22 +50,15 @@ extern uint8_t _micropy_hw_romfs_part1_start; extern uint8_t _micropy_hw_romfs_part1_size; #endif -#if MICROPY_HW_ROMFS_ENABLE_PART2 && !defined(MICROPY_HW_ROMFS_PART2_START) -#define MICROPY_HW_ROMFS_PART2_START (uintptr_t)(&_micropy_hw_romfs_part2_start) -#define MICROPY_HW_ROMFS_PART2_SIZE (uintptr_t)(&_micropy_hw_romfs_part2_size) -extern uint8_t _micropy_hw_romfs_part2_start; -extern uint8_t _micropy_hw_romfs_part2_size; -#endif - #define ROMFS_MEMORYVIEW(base, size) {{&mp_type_memoryview}, 'B', 0, (size), (void *)(base)} static const mp_obj_array_t romfs_obj_table[] = { + #if MICROPY_HW_ROMFS_ENABLE_PART0 + ROMFS_MEMORYVIEW(MICROPY_HW_ROMFS_PART0_START, MICROPY_HW_ROMFS_PART0_SIZE), + #endif #if MICROPY_HW_ROMFS_ENABLE_PART1 ROMFS_MEMORYVIEW(MICROPY_HW_ROMFS_PART1_START, MICROPY_HW_ROMFS_PART1_SIZE), #endif - #if MICROPY_HW_ROMFS_ENABLE_PART2 - ROMFS_MEMORYVIEW(MICROPY_HW_ROMFS_PART2_START, MICROPY_HW_ROMFS_PART2_SIZE), - #endif }; mp_obj_t mp_vfs_rom_ioctl(size_t n_args, const mp_obj_t *args) { |