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Diffstat (limited to 'ports/stm32/machine_adc.c')
-rw-r--r--ports/stm32/machine_adc.c32
1 files changed, 20 insertions, 12 deletions
diff --git a/ports/stm32/machine_adc.c b/ports/stm32/machine_adc.c
index 14384429c..a6e960911 100644
--- a/ports/stm32/machine_adc.c
+++ b/ports/stm32/machine_adc.c
@@ -30,7 +30,7 @@
#include "py/mphal.h"
#include "adc.h"
-#if defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L0) || defined(STM32L4) || defined(STM32N6) || defined(STM32WB) || defined(STM32WL)
+#if defined(STM32F0) || defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L0) || defined(STM32L4) || defined(STM32N6) || defined(STM32U5) || defined(STM32WB) || defined(STM32WL)
#define ADC_V2 (1)
#else
#define ADC_V2 (0)
@@ -88,6 +88,9 @@
#elif defined(STM32N6)
#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_46CYCLES_5
#define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_246CYCLES_5
+#elif defined(STM32U5)
+#define ADC_SAMPLETIME_DEFAULT ADC_SAMPLETIME_5CYCLES
+#define ADC_SAMPLETIME_DEFAULT_INT ADC_SAMPLETIME_391CYCLES_5
#endif
// Timeout for waiting for end-of-conversion
@@ -175,6 +178,8 @@ static void adc_wait_eoc(ADC_TypeDef *adc, int32_t timeout_ms) {
#if defined(STM32H7)
static const uint8_t adc_cr_to_bits_table[] = {16, 14, 12, 10, 8, 8, 8, 8};
+#elif defined(STM32U5)
+static const uint8_t adc_cr_to_bits_table[] = {14, 12, 10, 8};
#else
static const uint8_t adc_cr_to_bits_table[] = {12, 10, 8, 6};
#endif
@@ -188,7 +193,7 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
if (adc == ADC1) {
#if defined(STM32H5)
__HAL_RCC_ADC_CLK_ENABLE();
- #elif defined(STM32G4) || defined(STM32H7) || defined(STM32N6)
+ #elif defined(STM32G4) || defined(STM32H7) || defined(STM32N6) || defined(STM32U5)
__HAL_RCC_ADC12_CLK_ENABLE();
#else
__HAL_RCC_ADC1_CLK_ENABLE();
@@ -198,7 +203,7 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
if (adc == ADC2) {
#if defined(STM32H5)
__HAL_RCC_ADC_CLK_ENABLE();
- #elif defined(STM32G4) || defined(STM32H7) || defined(STM32N6)
+ #elif defined(STM32G4) || defined(STM32H7) || defined(STM32N6) || defined(STM32U5)
__HAL_RCC_ADC12_CLK_ENABLE();
#else
__HAL_RCC_ADC2_CLK_ENABLE();
@@ -221,7 +226,7 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
adc->CFGR2 = 2 << ADC_CFGR2_CKMODE_Pos; // PCLK/4 (synchronous clock mode)
#elif defined(STM32F4) || defined(STM32F7) || defined(STM32L4)
ADCx_COMMON->CCR = 0; // ADCPR=PCLK/2
- #elif defined(STM32G4) || defined(STM32H5)
+ #elif defined(STM32G4) || defined(STM32H5) || defined(STM32U5)
ADC12_COMMON->CCR = 7 << ADC_CCR_PRESC_Pos; // PCLK/16 (asynchronous clock mode)
#elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
ADC12_COMMON->CCR = 3 << ADC_CCR_CKMODE_Pos;
@@ -240,13 +245,13 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
ADC_COMMON->CCR = 0 << ADC_CCR_PRESC_Pos; // PRESC=1
#endif
- #if defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32N6) || defined(STM32WB)
+ #if defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32N6) || defined(STM32U5) || defined(STM32WB)
if (adc->CR & ADC_CR_DEEPPWD) {
adc->CR = 0; // disable deep powerdown
}
#endif
- #if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L0) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
+ #if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L0) || defined(STM32L4) || defined(STM32U5) || defined(STM32WB) || defined(STM32WL)
if (!(adc->CR & ADC_CR_ADVREGEN)) {
adc->CR = ADC_CR_ADVREGEN; // enable VREG
#if defined(STM32H7)
@@ -262,7 +267,7 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
// ADC isn't enabled so calibrate it now
#if defined(STM32F0) || defined(STM32G0) || defined(STM32L0) || defined(STM32WL)
LL_ADC_StartCalibration(adc);
- #elif defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32WB)
+ #elif defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32U5) || defined(STM32WB)
LL_ADC_StartCalibration(adc, LL_ADC_SINGLE_ENDED);
#elif defined(STM32N6)
ADC_HandleTypeDef hadc;
@@ -324,7 +329,7 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
uint32_t cfgr = res << ADC_CFGR_RES_Pos;
adc->CFGR = (adc->CFGR & ~cfgr_clr) | cfgr;
- #elif defined(STM32N6)
+ #elif defined(STM32N6) || defined(STM32U5)
uint32_t cfgr1_clr = ADC_CFGR1_CONT | ADC_CFGR1_EXTEN | ADC_CFGR1_RES;
uint32_t cfgr1 = res << ADC_CFGR1_RES_Pos;
@@ -334,7 +339,7 @@ void adc_config(ADC_TypeDef *adc, uint32_t bits) {
}
static int adc_get_bits(ADC_TypeDef *adc) {
- #if defined(STM32F0) || defined(STM32G0) || defined(STM32L0) || defined(STM32N6) || defined(STM32WL)
+ #if defined(STM32F0) || defined(STM32G0) || defined(STM32L0) || defined(STM32N6) || defined(STM32U5) || defined(STM32WL)
uint32_t res = (adc->CFGR1 & ADC_CFGR1_RES) >> ADC_CFGR1_RES_Pos;
#elif defined(STM32F4) || defined(STM32F7) || defined(STM32L1)
uint32_t res = (adc->CR1 & ADC_CR1_RES) >> ADC_CR1_RES_Pos;
@@ -436,9 +441,9 @@ static void adc_config_channel(ADC_TypeDef *adc, uint32_t channel, uint32_t samp
}
*smpr = (*smpr & ~(7 << (channel * 3))) | sample_time << (channel * 3); // select sample time
- #elif defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32N6) || defined(STM32WB)
+ #elif defined(STM32G4) || defined(STM32H5) || defined(STM32H7) || defined(STM32L4) || defined(STM32N6) || defined(STM32U5) || defined(STM32WB)
- #if defined(STM32G4) || defined(STM32H5) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32N6)
+ #if defined(STM32G4) || defined(STM32H5) || defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ) || defined(STM32N6) || defined(STM32U5)
ADC_Common_TypeDef *adc_common = ADC12_COMMON;
#elif defined(STM32H7)
ADC_Common_TypeDef *adc_common = adc == ADC3 ? ADC3_COMMON : ADC12_COMMON;
@@ -453,6 +458,9 @@ static void adc_config_channel(ADC_TypeDef *adc, uint32_t channel, uint32_t samp
#if defined(STM32G4)
} else if (channel == ADC_CHANNEL_TEMPSENSOR_ADC1) {
adc_common->CCR |= ADC_CCR_VSENSESEL;
+ #elif defined(STM32U5)
+ } else if (channel == ADC_CHANNEL_TEMPSENSOR) {
+ adc_common->CCR |= ADC_CCR_VSENSEEN;
#else
} else if (channel == ADC_CHANNEL_TEMPSENSOR) {
adc_common->CCR |= ADC_CCR_TSEN;
@@ -471,7 +479,7 @@ static void adc_config_channel(ADC_TypeDef *adc, uint32_t channel, uint32_t samp
#endif
}
- #if defined(STM32G4) || defined(STM32H5) || defined(STM32N6) || defined(STM32WB)
+ #if defined(STM32G4) || defined(STM32H5) || defined(STM32N6) || defined(STM32U5) || defined(STM32WB)
// MCU uses encoded literals for internal channels -> extract ADC channel for following code
if (__LL_ADC_IS_CHANNEL_INTERNAL(channel)) {
channel = __LL_ADC_CHANNEL_TO_DECIMAL_NB(channel);
generated by cgit v1.2.3 (git 2.46.0) at 2025-10-31 20:12:08 +0000