1 files changed, 17 insertions, 10 deletions

diff --git a/ports/stm32/rtc.c b/ports/stm32/rtc.c
index fb106e179..72abcd75f 100644
--- a/ports/stm32/rtc.c
+++ b/ports/stm32/rtc.c
@@ -108,7 +108,7 @@ void rtc_init_start(bool force_init) {
     // Enable the RTC APB bus clock, to communicate with the RTC.
     #if defined(STM32H5)
     __HAL_RCC_RTC_CLK_ENABLE();
-    #elif defined(STM32G0) || defined(STM32WL)
+    #elif defined(STM32G0) || defined(STM32U5) || defined(STM32WL)
     __HAL_RCC_RTCAPB_CLK_ENABLE();
     #endif
 
@@ -179,7 +179,7 @@ void rtc_init_start(bool force_init) {
             // Clear source Reset Flag
             __HAL_RCC_CLEAR_RESET_FLAGS();
             // Turn the LSI on (it may need this even if the RTC is running)
-            #if defined(STM32H5)
+            #if defined(STM32H5) || defined(STM32U5)
             RCC->BDCR |= RCC_BDCR_LSION;
             #else
             RCC->CSR |= RCC_CSR_LSION;
@@ -192,7 +192,7 @@ void rtc_init_start(bool force_init) {
         if (rtc_running) {
             // Provide information about the registers that indicated the RTC is running.
             // Bits are (MSB first): LSIRDY LSION LSEBYP LSERDY LSEON
-            #if defined(STM32H5)
+            #if defined(STM32H5) || defined(STM32U5)
             rtc_info |= (RCC->BDCR >> RCC_BDCR_LSEON_Pos & 7) | (RCC->BDCR >> RCC_BDCR_LSION_Pos & 3) << 8;
             #else
             rtc_info |= (RCC->BDCR & 7) | (RCC->CSR & 3) << 8;
@@ -276,7 +276,7 @@ void rtc_init_finalise() {
     RTC_CalendarConfig();
     #if defined(STM32G0)
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_PWRRST) != RESET) {
-    #elif defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32WB) || defined(STM32WL)
+    #elif defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32U5) || defined(STM32WB) || defined(STM32WL)
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_BORRST) != RESET) {
     #else
     if (__HAL_RCC_GET_FLAG(RCC_FLAG_PORRST) != RESET) {
@@ -327,7 +327,7 @@ static HAL_StatusTypeDef PYB_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct
                 return HAL_TIMEOUT;
             }
         }
-        #elif defined(STM32H5) || defined(STM32N6)
+        #elif defined(STM32H5) || defined(STM32N6) || defined(STM32U5)
         // Wait for Backup domain Write protection disable
         while (!LL_PWR_IsEnabledBkUpAccess()) {
             if (HAL_GetTick() - tickstart > RCC_DBP_TIMEOUT_VALUE) {
@@ -412,7 +412,7 @@ static HAL_StatusTypeDef PYB_RTC_Init(RTC_HandleTypeDef *hrtc) {
         #elif defined(STM32F7)
         hrtc->Instance->OR &= (uint32_t) ~RTC_OR_ALARMTYPE;
         hrtc->Instance->OR |= (uint32_t)(hrtc->Init.OutPutType);
-        #elif defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32N6) || defined(STM32WL)
+        #elif defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32N6) || defined(STM32U5) || defined(STM32WL)
         hrtc->Instance->CR &= (uint32_t) ~RTC_CR_TAMPALRM_TYPE_Msk;
         hrtc->Instance->CR |= (uint32_t)(hrtc->Init.OutPutType);
         #else
@@ -521,6 +521,11 @@ static HAL_StatusTypeDef PYB_RTC_MspInit_Finalise(RTC_HandleTypeDef *hrtc) {
 
     // enable RTC peripheral clock
     __HAL_RCC_RTC_ENABLE();
+
+    #if defined(STM32U5)
+    __HAL_RCC_RTCAPB_CLK_ENABLE();
+    __HAL_RCC_RTCAPB_CLKAM_ENABLE();
+    #endif
     return HAL_OK;
 }
 
@@ -685,7 +690,7 @@ mp_obj_t pyb_rtc_datetime(size_t n_args, const mp_obj_t *args) {
 }
 MP_DEFINE_CONST_FUN_OBJ_VAR_BETWEEN(pyb_rtc_datetime_obj, 1, 2, pyb_rtc_datetime);
 
-#if defined(STM32F0) || defined(STM32H5) || defined(STM32L0)
+#if defined(STM32F0) || defined(STM32H5) || defined(STM32L0) || defined(STM32U5)
 #define RTC_WKUP_IRQn RTC_IRQn
 #elif defined(STM32G0)
 #define RTC_WKUP_IRQn RTC_TAMP_IRQn
@@ -806,6 +811,8 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
         #elif defined(STM32H7)
         EXTI_D1->IMR1 |= 1 << EXTI_RTC_WAKEUP;
         EXTI->RTSR1 |= 1 << EXTI_RTC_WAKEUP;
+        #elif defined(STM32U5)
+        // do nothing
         #else
         EXTI->IMR |= 1 << EXTI_RTC_WAKEUP;
         EXTI->RTSR |= 1 << EXTI_RTC_WAKEUP;
@@ -814,7 +821,7 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
         // clear interrupt flags
         #if defined(STM32G0) || defined(STM32G4) || defined(STM32WL)
         RTC->ICSR &= ~RTC_ICSR_WUTWF;
-        #elif defined(STM32H5) || defined(STM32N6)
+        #elif defined(STM32H5) || defined(STM32N6) || defined(STM32U5)
         LL_RTC_ClearFlag_WUT(RTC);
         #elif defined(STM32H7A3xx) || defined(STM32H7A3xxQ) || defined(STM32H7B3xx) || defined(STM32H7B3xxQ)
         RTC->SR &= ~RTC_SR_WUTF;
@@ -825,7 +832,7 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
         EXTI->PR1 = 1 << EXTI_RTC_WAKEUP;
         #elif defined(STM32H7)
         EXTI_D1->PR1 = 1 << EXTI_RTC_WAKEUP;
-        #elif defined(STM32G0) || defined(STM32H5) || defined(STM32N6)
+        #elif defined(STM32G0) || defined(STM32H5) || defined(STM32N6) || defined(STM32U5)
         // Do nothing
         #else
         EXTI->PR = 1 << EXTI_RTC_WAKEUP;
@@ -841,7 +848,7 @@ mp_obj_t pyb_rtc_wakeup(size_t n_args, const mp_obj_t *args) {
         RTC->WPR = 0xff;
 
         // disable external interrupts on line EXTI_RTC_WAKEUP
-        #if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32N6) || defined(STM32WB) || defined(STM32WL)
+        #if defined(STM32G0) || defined(STM32G4) || defined(STM32H5) || defined(STM32L4) || defined(STM32N6) || defined(STM32U5) || defined(STM32WB) || defined(STM32WL)
         EXTI->IMR1 &= ~(1 << EXTI_RTC_WAKEUP);
         #elif defined(STM32H7)
         EXTI_D1->IMR1 |= 1 << EXTI_RTC_WAKEUP;