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Diffstat (limited to 'ports/stm32/system_stm32.c')
-rw-r--r--ports/stm32/system_stm32.c81
1 files changed, 39 insertions, 42 deletions
diff --git a/ports/stm32/system_stm32.c b/ports/stm32/system_stm32.c
index 46dd58ba2..30c8bfd89 100644
--- a/ports/stm32/system_stm32.c
+++ b/ports/stm32/system_stm32.c
@@ -163,8 +163,7 @@ void __fatal_error(const char *msg);
*
* Timers run from APBx if APBx_PRESC=1, else 2x APBx
*/
-void SystemClock_Config(void)
-{
+void SystemClock_Config(void) {
#if defined(STM32F7)
// The DFU bootloader changes the clocksource register from its default power
// on reset value, so we set it back here, so the clocksources are the same
@@ -225,7 +224,7 @@ void SystemClock_Config(void)
RCC_OscInitStruct.PLL.PLLR = MICROPY_HW_CLK_PLLR;
RCC_OscInitStruct.MSIState = RCC_MSI_OFF;
#else
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE|RCC_OSCILLATORTYPE_MSI;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_MSI;
RCC_OscInitStruct.MSIState = RCC_MSI_ON;
RCC_OscInitStruct.MSICalibrationValue = RCC_MSICALIBRATION_DEFAULT;
RCC_OscInitStruct.MSIClockRange = RCC_MSIRANGE_6;
@@ -247,7 +246,7 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.ClockType |= (RCC_CLOCKTYPE_D3PCLK1 | RCC_CLOCKTYPE_D1PCLK1);
#endif
-#if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
+ #if defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
#if defined(STM32F7)
#define FREQ_BKP BKP31R
#elif defined(STM32L4)
@@ -265,7 +264,7 @@ void SystemClock_Config(void)
uint32_t b1 = (m >> 26) & 0x7;
uint32_t b2 = (m >> 29) & 0x7;
q = (m >> 18) & 0xf;
- p = (((m >> 16) & 0x03)+1)*2;
+ p = (((m >> 16) & 0x03) + 1) * 2;
n = (m >> 6) & 0x3ff;
m &= 0x3f;
if ((q < 2) || (q > 15) || (p > 8) || (p < 2) || (n < 192) || (n >= 433) || (m < 2)) {
@@ -289,7 +288,7 @@ void SystemClock_Config(void)
RCC_ClkInitStruct.AHBCLKDivider = h; //RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = b1; //RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = b2; //RCC_HCLK_DIV2;
-#else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
+ #else // defined(MICROPY_HW_CLK_LAST_FREQ) && MICROPY_HW_CLK_LAST_FREQ
RCC_OscInitStruct.PLL.PLLM = MICROPY_HW_CLK_PLLM;
RCC_OscInitStruct.PLL.PLLN = MICROPY_HW_CLK_PLLN;
RCC_OscInitStruct.PLL.PLLP = MICROPY_HW_CLK_PLLP;
@@ -305,28 +304,28 @@ void SystemClock_Config(void)
#endif
#if defined(STM32F4) || defined(STM32F7)
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
#elif defined(STM32L4)
- RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
#elif defined(STM32H7)
- RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
- RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
+ RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
#endif
-#endif
+ #endif
- if(HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
- __fatal_error("HAL_RCC_OscConfig");
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ __fatal_error("HAL_RCC_OscConfig");
}
-#if defined(STM32H7)
+ #if defined(STM32H7)
/* PLL3 for USB Clock */
PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_USB;
PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_PLL3;
@@ -341,15 +340,14 @@ void SystemClock_Config(void)
if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
}
-#endif
+ #endif
-#if defined(STM32F7)
- /* Activate the OverDrive to reach the 200 MHz Frequency */
- if (HAL_PWREx_EnableOverDrive() != HAL_OK)
- {
- __fatal_error("HAL_PWREx_EnableOverDrive");
- }
-#endif
+ #if defined(STM32F7)
+ /* Activate the OverDrive to reach the 200 MHz Frequency */
+ if (HAL_PWREx_EnableOverDrive() != HAL_OK) {
+ __fatal_error("HAL_PWREx_EnableOverDrive");
+ }
+ #endif
uint32_t vco_out = RCC_OscInitStruct.PLL.PLLN * (MICROPY_HW_CLK_VALUE / 1000000) / RCC_OscInitStruct.PLL.PLLM;
uint32_t sysclk_mhz = vco_out / RCC_OscInitStruct.PLL.PLLP;
@@ -358,28 +356,28 @@ void SystemClock_Config(void)
__fatal_error("HAL_RCC_ClockConfig");
}
-#if defined(STM32H7)
- /* Activate CSI clock mandatory for I/O Compensation Cell*/
- __HAL_RCC_CSI_ENABLE() ;
+ #if defined(STM32H7)
+ /* Activate CSI clock mandatory for I/O Compensation Cell*/
+ __HAL_RCC_CSI_ENABLE();
- /* Enable SYSCFG clock mandatory for I/O Compensation Cell */
- __HAL_RCC_SYSCFG_CLK_ENABLE() ;
+ /* Enable SYSCFG clock mandatory for I/O Compensation Cell */
+ __HAL_RCC_SYSCFG_CLK_ENABLE();
- /* Enable the I/O Compensation Cell */
- HAL_EnableCompensationCell();
+ /* Enable the I/O Compensation Cell */
+ HAL_EnableCompensationCell();
- /* Enable the USB voltage level detector */
- HAL_PWREx_EnableUSBVoltageDetector();
-#endif
+ /* Enable the USB voltage level detector */
+ HAL_PWREx_EnableUSBVoltageDetector();
+ #endif
-#if defined(STM32L4)
+ #if defined(STM32L4)
// Enable MSI-Hardware auto calibration mode with LSE
HAL_RCCEx_EnableMSIPLLMode();
RCC_PeriphCLKInitTypeDef PeriphClkInitStruct;
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1|RCC_PERIPHCLK_I2C1
- |RCC_PERIPHCLK_USB |RCC_PERIPHCLK_ADC
- |RCC_PERIPHCLK_RNG |RCC_PERIPHCLK_RTC;
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_I2C1
+ | RCC_PERIPHCLK_USB | RCC_PERIPHCLK_ADC
+ | RCC_PERIPHCLK_RNG | RCC_PERIPHCLK_RTC;
PeriphClkInitStruct.I2c1ClockSelection = RCC_I2C1CLKSOURCE_PCLK1;
PeriphClkInitStruct.Sai1ClockSelection = RCC_SAI1CLKSOURCE_PLLSAI1;
@@ -412,11 +410,10 @@ void SystemClock_Config(void)
PeriphClkInitStruct.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
#endif
PeriphClkInitStruct.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_SAI1CLK
- |RCC_PLLSAI1_48M2CLK
- |RCC_PLLSAI1_ADC1CLK;
+ | RCC_PLLSAI1_48M2CLK
+ | RCC_PLLSAI1_ADC1CLK;
- if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK)
- {
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
__fatal_error("HAL_RCCEx_PeriphCLKConfig");
}
@@ -424,10 +421,10 @@ void SystemClock_Config(void)
HAL_PWREx_ControlVoltageScaling(PWR_REGULATOR_VOLTAGE_SCALE1);
- HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
+ HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq() / 1000);
HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
NVIC_SetPriority(SysTick_IRQn, NVIC_EncodePriority(NVIC_PRIORITYGROUP_4, TICK_INT_PRIORITY, 0));
-#endif
+ #endif
}
#endif
generated by cgit v1.2.3 (git 2.46.0) at 2025-09-23 07:19:47 +0000