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-rw-r--r--ports/bare-arm/mpconfigport.h3
-rw-r--r--ports/esp32/network_ppp.c4
-rw-r--r--ports/mimxrt/Makefile112
-rw-r--r--ports/mimxrt/board_init.c3
-rw-r--r--ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h42
-rw-r--r--ports/mimxrt/boards/MIMXRT1052_clock_config.c130
-rw-r--r--ports/mimxrt/boards/MIMXRT1052_clock_config.h102
-rw-r--r--ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h56
-rw-r--r--ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk1
-rw-r--r--ports/mimxrt/eth.c8
-rw-r--r--ports/mimxrt/machine_i2s.c10
-rw-r--r--ports/mimxrt/machine_pwm.c2
-rw-r--r--ports/mimxrt/machine_rtc.c2
-rw-r--r--ports/minimal/mpconfigport.h6
-rw-r--r--ports/nrf/mpconfigport.h1
-rw-r--r--ports/powerpc/mpconfigport.h1
-rw-r--r--ports/unix/variants/minimal/mpconfigvariant.h3
-rw-r--r--ports/zephyr/mpconfigport_minimal.h1
18 files changed, 287 insertions, 200 deletions
diff --git a/ports/bare-arm/mpconfigport.h b/ports/bare-arm/mpconfigport.h
index 65bb67f7b..f4b87f23e 100644
--- a/ports/bare-arm/mpconfigport.h
+++ b/ports/bare-arm/mpconfigport.h
@@ -37,6 +37,9 @@
// Python internal features
#define MICROPY_ERROR_REPORTING (MICROPY_ERROR_REPORTING_NONE)
+// Fine control over Python builtins, classes, modules, etc.
+#define MICROPY_PY_SYS (0)
+
// Type definitions for the specific machine
typedef int32_t mp_int_t; // must be pointer size
diff --git a/ports/esp32/network_ppp.c b/ports/esp32/network_ppp.c
index 18e0c8816..725d21048 100644
--- a/ports/esp32/network_ppp.c
+++ b/ports/esp32/network_ppp.c
@@ -153,8 +153,8 @@ static mp_obj_t network_ppp_poll(size_t n_args, const mp_obj_t *args) {
}
mp_int_t total_len = 0;
- mp_obj_t stream = self->stream;
- while (stream != mp_const_none) {
+ mp_obj_t stream;
+ while (self->state >= STATE_ACTIVE && (stream = self->stream) != mp_const_none) {
uint8_t buf[256];
int err;
mp_uint_t len = mp_stream_rw(stream, buf, sizeof(buf), &err, 0);
diff --git a/ports/mimxrt/Makefile b/ports/mimxrt/Makefile
index 7788b54ca..fea7e56da 100644
--- a/ports/mimxrt/Makefile
+++ b/ports/mimxrt/Makefile
@@ -52,7 +52,8 @@ include $(TOP)/py/py.mk
include $(TOP)/extmod/extmod.mk
# Set SDK directory based on MCU_SERIES
-MCU_DIR = lib/nxp_driver/sdk/devices/$(MCU_SERIES)
+MCUX_SDK_DIR = lib/nxp_driver/sdk
+MCU_DIR = $(MCUX_SDK_DIR)/devices/$(MCU_SERIES)
# Select linker scripts based on MCU_SERIES
LD_FILES = boards/$(MCU_SERIES).ld boards/common.ld
@@ -72,8 +73,6 @@ GEN_PINS_SRC = $(BUILD)/pins_gen.c
INC += -I$(BOARD_DIR)
INC += -I$(BUILD)
INC += -I$(TOP)
-INC += -I$(TOP)/$(MCU_DIR)
-INC += -I$(TOP)/$(MCU_DIR)/drivers
INC += -I$(TOP)/lib/cmsis/inc
INC += -I$(TOP)/lib/oofatfs
INC += -I$(TOP)/lib/tinyusb/hw
@@ -111,35 +110,38 @@ SRC_TINYUSB_C += \
# All settings for Ethernet support are controller by the value of MICROPY_PY_LWIP
ifeq ($(MICROPY_PY_LWIP),1)
SRC_ETH_C += \
- $(MCU_DIR)/drivers/fsl_enet.c \
+ $(MCUX_SDK_DIR)/drivers/enet/fsl_enet.c \
hal/phy/device/phydp83825/fsl_phydp83825.c \
hal/phy/device/phydp83848/fsl_phydp83848.c \
hal/phy/device/phyksz8081/fsl_phyksz8081.c \
hal/phy/device/phylan8720/fsl_phylan8720.c \
hal/phy/device/phyrtl8211f/fsl_phyrtl8211f.c \
hal/phy/mdio/enet/fsl_enet_mdio.c
+
+INC_HAL_IMX += \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/enet
endif
# NXP SDK sources
SRC_HAL_IMX_C += \
$(MCU_DIR)/drivers/fsl_clock.c \
- $(MCU_DIR)/drivers/fsl_common.c \
- $(MCU_DIR)/drivers/fsl_dmamux.c \
- $(MCU_DIR)/drivers/fsl_edma.c \
- $(MCU_DIR)/drivers/fsl_flexram.c \
- $(MCU_DIR)/drivers/fsl_flexspi.c \
- $(MCU_DIR)/drivers/fsl_gpc.c \
- $(MCU_DIR)/drivers/fsl_gpio.c \
- $(MCU_DIR)/drivers/fsl_gpt.c \
- $(MCU_DIR)/drivers/fsl_lpi2c.c \
- $(MCU_DIR)/drivers/fsl_lpspi.c \
- $(MCU_DIR)/drivers/fsl_lpspi_edma.c \
- $(MCU_DIR)/drivers/fsl_pit.c \
- $(MCU_DIR)/drivers/fsl_pwm.c \
- $(MCU_DIR)/drivers/fsl_sai.c \
- $(MCU_DIR)/drivers/fsl_snvs_hp.c \
- $(MCU_DIR)/drivers/fsl_snvs_lp.c \
- $(MCU_DIR)/drivers/fsl_wdog.c \
+ $(MCUX_SDK_DIR)/drivers/common/fsl_common.c \
+ $(MCUX_SDK_DIR)/drivers/common/fsl_common_arm.c \
+ $(MCUX_SDK_DIR)/drivers/dmamux/fsl_dmamux.c \
+ $(MCUX_SDK_DIR)/drivers/edma/fsl_edma.c \
+ $(MCUX_SDK_DIR)/drivers/flexram/fsl_flexram.c \
+ $(MCUX_SDK_DIR)/drivers/flexspi/fsl_flexspi.c \
+ $(MCUX_SDK_DIR)/drivers/igpio/fsl_gpio.c \
+ $(MCUX_SDK_DIR)/drivers/gpt/fsl_gpt.c \
+ $(MCUX_SDK_DIR)/drivers/lpi2c/fsl_lpi2c.c \
+ $(MCUX_SDK_DIR)/drivers/lpspi/fsl_lpspi.c \
+ $(MCUX_SDK_DIR)/drivers/lpspi/fsl_lpspi_edma.c \
+ $(MCUX_SDK_DIR)/drivers/pit/fsl_pit.c \
+ $(MCUX_SDK_DIR)/drivers/pwm/fsl_pwm.c \
+ $(MCUX_SDK_DIR)/drivers/sai/fsl_sai.c \
+ $(MCUX_SDK_DIR)/drivers/snvs_hp/fsl_snvs_hp.c \
+ $(MCUX_SDK_DIR)/drivers/snvs_lp/fsl_snvs_lp.c \
+ $(MCUX_SDK_DIR)/drivers/wdog01/fsl_wdog.c \
$(MCU_DIR)/system_$(MCU_SERIES)$(MCU_CORE).c \
# Use a specific boot header for 1062 so the Teensy loader doesn't erase the filesystem.
@@ -149,18 +151,42 @@ else
SRC_HAL_IMX_C += $(MCU_DIR)/xip/fsl_flexspi_nor_boot.c
endif
+INC_HAL_IMX += \
+ -I$(TOP)/$(MCU_DIR) \
+ -I$(TOP)/$(MCU_DIR)/drivers \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/common \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/dmamux \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/edma \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/flexram \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/flexspi \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/igpio \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/gpt \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpi2c \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpspi \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpuart \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/pit \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/pwm \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/sai \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/snvs_hp \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/snvs_lp \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/wdog01 \
+
ifeq ($(MICROPY_HW_SDRAM_AVAIL),1)
-SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_semc.c
+SRC_HAL_IMX_C += $(MCUX_SDK_DIR)/drivers/semc/fsl_semc.c
+INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/semc
endif
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
-SRC_HAL_IMX_C += $(MCU_DIR)/drivers/fsl_usdhc.c
+SRC_HAL_IMX_C += $(MCUX_SDK_DIR)/drivers/usdhc/fsl_usdhc.c
+INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/usdhc
endif
ifeq ($(MCU_SERIES),$(filter $(MCU_SERIES), MIMXRT1015 MIMXRT1021 MIMXRT1052 MIMXRT1062 MIMXRT1064 MIMXRT1176))
SRC_HAL_IMX_C += \
- $(MCU_DIR)/drivers/fsl_qtmr.c \
+ $(MCUX_SDK_DIR)/drivers/qtmr_1/fsl_qtmr.c \
$(MCU_DIR)/drivers/fsl_romapi.c
+
+INC_HAL_IMX += -I$(TOP)/$(MCUX_SDK_DIR)/drivers/qtmr_1
endif
# If not empty, then it is 10xx.
@@ -171,24 +197,42 @@ APPLICATION_ADDR := 0x3000C000
endif
ifeq ($(MCU_SERIES), MIMXRT1176)
-INC += -I$(TOP)/$(MCU_DIR)/drivers/cm7
-
SRC_HAL_IMX_C += \
$(MCU_DIR)/drivers/cm7/fsl_cache.c \
$(MCU_DIR)/drivers/fsl_dcdc.c \
$(MCU_DIR)/drivers/fsl_pmu.c \
- $(MCU_DIR)/drivers/fsl_common_arm.c \
$(MCU_DIR)/drivers/fsl_anatop_ai.c \
- $(MCU_DIR)/drivers/fsl_caam.c \
- $(MCU_DIR)/drivers/fsl_lpadc.c \
- $(MCU_DIR)/drivers/fsl_mu.c
+ $(MCU_DIR)/drivers/fsl_soc_src.c \
+ $(MCU_DIR)/drivers/fsl_gpc.c \
+ $(MCUX_SDK_DIR)/drivers/caam/fsl_caam.c \
+ $(MCUX_SDK_DIR)/drivers/lpadc/fsl_lpadc.c \
+ $(MCUX_SDK_DIR)/drivers/mu/fsl_mu.c
+
+INC_HAL_IMX += \
+ -I$(TOP)/$(MCU_DIR)/drivers/cm7 \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/caam \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/lpadc \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/mu
+
+CFLAGS += -DCACHE_MODE_WRITE_THROUGH=1
else
SRC_HAL_IMX_C += \
- $(MCU_DIR)/drivers/fsl_adc.c \
- $(MCU_DIR)/drivers/fsl_cache.c \
- $(MCU_DIR)/drivers/fsl_trng.c
+ $(MCUX_SDK_DIR)/drivers/adc_12b1msps_sar/fsl_adc.c \
+ $(MCUX_SDK_DIR)/drivers/cache/armv7-m7/fsl_cache.c \
+ $(MCUX_SDK_DIR)/drivers/gpc_1/fsl_gpc.c \
+ $(MCUX_SDK_DIR)/drivers/src/fsl_src.c \
+ $(MCUX_SDK_DIR)/drivers/trng/fsl_trng.c
+
+INC_HAL_IMX += \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/adc_12b1msps_sar \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/cache/armv7-m7 \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/gpc_1 \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/src \
+ -I$(TOP)/$(MCUX_SDK_DIR)/drivers/trng
endif
+INC += $(INC_HAL_IMX)
+
# C source files
SRC_C += \
board_init.c \
@@ -371,8 +415,6 @@ CFLAGS += \
-DMICROPY_HW_FLASH_SIZE=$(MICROPY_HW_FLASH_SIZE) \
-DMICROPY_HW_SDRAM_AVAIL=$(MICROPY_HW_SDRAM_AVAIL) \
-DMICROPY_HW_SDRAM_SIZE=$(MICROPY_HW_SDRAM_SIZE) \
- -DSPI_RETRY_TIMES=1000000 \
- -DUART_RETRY_TIMES=1000000 \
-DXIP_BOOT_HEADER_ENABLE=1 \
-DXIP_EXTERNAL_FLASH=1 \
-fdata-sections \
diff --git a/ports/mimxrt/board_init.c b/ports/mimxrt/board_init.c
index 88de27ea7..0643da064 100644
--- a/ports/mimxrt/board_init.c
+++ b/ports/mimxrt/board_init.c
@@ -52,6 +52,9 @@ void board_init(void) {
SCB_EnableICache();
// Init clock
BOARD_BootClockRUN();
+ #if !defined(MIMXRT117x_SERIES)
+ CLOCK_SetMode(kCLOCK_ModeRun);
+ #endif
SystemCoreClockUpdate();
// Enable IOCON clock
diff --git a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
index 59a5c4fa6..bf9157e9c 100644
--- a/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
+++ b/ports/mimxrt/boards/MIMXRT1050_EVK/mpconfigboard.h
@@ -21,14 +21,14 @@
#define MICROPY_HW_UART_INDEX { 1, 3, 2, 6, 8 }
#define IOMUX_TABLE_UART \
- { IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
- { IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
- { IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
+ { IOMUXC_GPIO_AD_B0_12_LPUART1_TXD }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RXD }, \
+ { IOMUXC_GPIO_AD_B1_02_LPUART2_TXD }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RXD }, \
+ { IOMUXC_GPIO_AD_B1_06_LPUART3_TXD }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RXD }, \
{ 0 }, { 0 }, \
{ 0 }, { 0 }, \
- { IOMUXC_GPIO_AD_B0_02_LPUART6_TX }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RX }, \
+ { IOMUXC_GPIO_AD_B0_02_LPUART6_TXD }, { IOMUXC_GPIO_AD_B0_03_LPUART6_RXD }, \
{ 0 }, { 0 }, \
- { IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
+ { IOMUXC_GPIO_AD_B1_10_LPUART8_TXD }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RXD },
#define IOMUX_TABLE_UART_CTS_RTS \
{ IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B }, { IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B }, \
@@ -111,22 +111,22 @@
}
// --- SEMC --- //
-#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
-#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
-#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
-#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
-#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
-#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
-#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
-#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
-#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
-#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
-#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
-#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
-#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
-#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
-#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
-#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
+#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DA00
+#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DA01
+#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DA02
+#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DA03
+#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DA04
+#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DA05
+#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DA06
+#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DA07
+#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DA08
+#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DA09
+#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DA10
+#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DA11
+#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DA12
+#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DA13
+#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DA14
+#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DA15
#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
diff --git a/ports/mimxrt/boards/MIMXRT1052_clock_config.c b/ports/mimxrt/boards/MIMXRT1052_clock_config.c
index bff43ae5e..de65a3e58 100644
--- a/ports/mimxrt/boards/MIMXRT1052_clock_config.c
+++ b/ports/mimxrt/boards/MIMXRT1052_clock_config.c
@@ -1,5 +1,5 @@
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -22,11 +22,11 @@
/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
!!GlobalInfo
-product: Clocks v5.0
+product: Clocks v10.0
processor: MIMXRT1052xxxxB
package_id: MIMXRT1052DVL6B
mcu_data: ksdk2_0
-processor_version: 0.0.0
+processor_version: 0.12.10
board: IMXRT1050-EVKB
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
@@ -40,8 +40,6 @@ board: IMXRT1050-EVKB
/*******************************************************************************
* Variables
******************************************************************************/
-/* System clock frequency. */
-extern uint32_t SystemCoreClock;
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
@@ -64,7 +62,6 @@ outputs:
- {id: CLK_1M.outFreq, value: 1 MHz}
- {id: CLK_24M.outFreq, value: 24 MHz}
- {id: CSI_CLK_ROOT.outFreq, value: 12 MHz}
-- {id: ENET1_TX_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_125M_CLK.outFreq, value: 2.4 MHz}
- {id: ENET_25M_REF_CLK.outFreq, value: 1.2 MHz}
- {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
@@ -92,7 +89,7 @@ outputs:
- {id: SAI3_MCLK3.outFreq, value: 30 MHz}
- {id: SEMC_CLK_ROOT.outFreq, value: 75 MHz}
- {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
-- {id: TRACE_CLK_ROOT.outFreq, value: 352/3 MHz}
+- {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
- {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
- {id: USDHC1_CLK_ROOT.outFreq, value: 198 MHz}
- {id: USDHC2_CLK_ROOT.outFreq, value: 198 MHz}
@@ -104,7 +101,7 @@ settings:
- {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
- {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
- {id: CCM.SEMC_PODF.scale, value: '8'}
-- {id: CCM.TRACE_PODF.scale, value: '3', locked: true}
+- {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
- {id: CCM_ANALOG.PLL1_BYPASS.sel, value: CCM_ANALOG.PLL1}
- {id: CCM_ANALOG.PLL1_PREDIV.scale, value: '1', locked: true}
- {id: CCM_ANALOG.PLL1_VDIV.scale, value: '50', locked: true}
@@ -125,31 +122,45 @@ settings:
- {id: CCM_ANALOG.PLL4.denom, value: '50'}
- {id: CCM_ANALOG.PLL4.div, value: '47'}
- {id: CCM_ANALOG.PLL5.denom, value: '1'}
-- {id: CCM_ANALOG.PLL5.div, value: '40'}
+- {id: CCM_ANALOG.PLL5.div, value: '31', locked: true}
- {id: CCM_ANALOG.PLL5.num, value: '0'}
+- {id: CCM_ANALOG.PLL5_BYPASS.sel, value: CCM_ANALOG.PLL5_POST_DIV}
+- {id: CCM_ANALOG.PLL5_POST_DIV.scale, value: '2'}
+- {id: CCM_ANALOG.VIDEO_DIV.scale, value: '4'}
- {id: CCM_ANALOG_PLL_ENET_POWERDOWN_CFG, value: 'Yes'}
- {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
+- {id: CCM_ANALOG_PLL_VIDEO_POWERDOWN_CFG, value: 'No'}
sources:
-- {id: XTALOSC24M.OSC.outFreq, value: 24 MHz, enabled: true}
- {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
/*******************************************************************************
* Variables for BOARD_BootClockRUN configuration
******************************************************************************/
-const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN = {
- .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
- .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+const clock_arm_pll_config_t armPllConfig_BOARD_BootClockRUN =
+{
+ .loopDivider = 100, /* PLL loop divider, Fout = Fin * 50 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
-const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN = {
- .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
- .numerator = 0, /* 30 bit numerator of fractional loop divider */
- .denominator = 1, /* 30 bit denominator of fractional loop divider */
- .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
+{
+ .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
-const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN = {
- .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
- .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
+{
+ .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
+};
+const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN =
+{
+ .loopDivider = 31, /* PLL loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .postDivider = 8, /* Divider after PLL */
+ .numerator = 0, /* 30 bit numerator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .denominator = 1, /* 30 bit denominator of fractional loop divider, Fout = Fin * ( loopDivider + numerator / denominator ) */
+ .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
};
/*******************************************************************************
* Code for BOARD_BootClockRUN configuration
@@ -213,10 +224,9 @@ void BOARD_BootClockRUN(void) {
CLOCK_SetDiv(kCLOCK_Usdhc2Div, 1);
/* Set Usdhc2 clock source. */
CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
-/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
- * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
- * unchanged.
- * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
+ /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
/* Disable Semc clock gate. */
CLOCK_DisableClock(kCLOCK_Semc);
@@ -227,10 +237,9 @@ void BOARD_BootClockRUN(void) {
/* Set Semc clock source. */
CLOCK_SetMux(kCLOCK_SemcMux, 0);
#endif
-/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
- * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
- * unchanged.
- * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
+ /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Disable Flexspi clock gate. */
CLOCK_DisableClock(kCLOCK_FlexSpi);
@@ -257,9 +266,9 @@ void BOARD_BootClockRUN(void) {
/* Disable TRACE clock gate. */
CLOCK_DisableClock(kCLOCK_Trace);
/* Set TRACE_PODF. */
- CLOCK_SetDiv(kCLOCK_TraceDiv, 2);
+ CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
/* Set Trace clock source. */
- CLOCK_SetMux(kCLOCK_TraceMux, 2);
+ CLOCK_SetMux(kCLOCK_TraceMux, 0);
/* Disable SAI1 clock gate. */
CLOCK_DisableClock(kCLOCK_Sai1);
/* Set SAI1_CLK_PRED. */
@@ -351,10 +360,12 @@ void BOARD_BootClockRUN(void) {
/* Init ARM PLL. */
CLOCK_InitArmPll(&armPllConfig_BOARD_BootClockRUN);
/* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
- * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left
- * unchanged. Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as
- * well.*/
+ * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
#ifndef SKIP_SYSCLK_INIT
+ #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
+ #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
+ #endif
/* Init System PLL. */
CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
/* Init System pfd0. */
@@ -365,13 +376,10 @@ void BOARD_BootClockRUN(void) {
CLOCK_InitSysPfd(kCLOCK_Pfd2, 24);
/* Init System pfd3. */
CLOCK_InitSysPfd(kCLOCK_Pfd3, 16);
- /* Disable pfd offset. */
- CCM_ANALOG->PLL_SYS &= ~CCM_ANALOG_PLL_SYS_PFD_OFFSET_EN_MASK;
#endif
/* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
- * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left
- * unchanged. Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as
- * well.*/
+ * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
+ * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
#if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
/* Init Usb1 PLL. */
CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
@@ -395,21 +403,30 @@ void BOARD_BootClockRUN(void) {
CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
/* Enable Audio PLL output. */
CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
- /* DeInit Video PLL. */
- CLOCK_DeinitVideoPll();
- /* Bypass Video PLL. */
- CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_BYPASS_MASK;
- /* Set divider for Video PLL. */
- CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(0);
- /* Enable Video PLL output. */
- CCM_ANALOG->PLL_VIDEO |= CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Init Video PLL. */
+ uint32_t pllVideo;
+ /* Disable Video PLL output before initial Video PLL. */
+ CCM_ANALOG->PLL_VIDEO &= ~CCM_ANALOG_PLL_VIDEO_ENABLE_MASK;
+ /* Bypass PLL first */
+ CCM_ANALOG->PLL_VIDEO = (CCM_ANALOG->PLL_VIDEO & (~CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC_MASK)) |
+ CCM_ANALOG_PLL_VIDEO_BYPASS_MASK | CCM_ANALOG_PLL_VIDEO_BYPASS_CLK_SRC(0);
+ CCM_ANALOG->PLL_VIDEO_NUM = CCM_ANALOG_PLL_VIDEO_NUM_A(0);
+ CCM_ANALOG->PLL_VIDEO_DENOM = CCM_ANALOG_PLL_VIDEO_DENOM_B(1);
+ pllVideo = (CCM_ANALOG->PLL_VIDEO & (~(CCM_ANALOG_PLL_VIDEO_DIV_SELECT_MASK | CCM_ANALOG_PLL_VIDEO_POWERDOWN_MASK))) |
+ CCM_ANALOG_PLL_VIDEO_ENABLE_MASK | CCM_ANALOG_PLL_VIDEO_DIV_SELECT(31);
+ pllVideo |= CCM_ANALOG_PLL_VIDEO_POST_DIV_SELECT(1);
+ CCM_ANALOG->MISC2 = (CCM_ANALOG->MISC2 & (~CCM_ANALOG_MISC2_VIDEO_DIV_MASK)) | CCM_ANALOG_MISC2_VIDEO_DIV(3);
+ CCM_ANALOG->PLL_VIDEO = pllVideo;
+ while ((CCM_ANALOG->PLL_VIDEO & CCM_ANALOG_PLL_VIDEO_LOCK_MASK) == 0) {
+ }
+ /* Disable bypass for Video PLL. */
+ CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllVideo, 0);
/* DeInit Enet PLL. */
CLOCK_DeinitEnetPll();
/* Bypass Enet PLL. */
CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllEnet, 1);
/* Set Enet output divider. */
- CCM_ANALOG->PLL_ENET =
- (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
+ CCM_ANALOG->PLL_ENET = (CCM_ANALOG->PLL_ENET & (~CCM_ANALOG_PLL_ENET_DIV_SELECT_MASK)) | CCM_ANALOG_PLL_ENET_DIV_SELECT(1);
/* Enable Enet output. */
CCM_ANALOG->PLL_ENET |= CCM_ANALOG_PLL_ENET_ENABLE_MASK;
/* Enable Enet25M output. */
@@ -429,8 +446,7 @@ void BOARD_BootClockRUN(void) {
/* Set per clock source. */
CLOCK_SetMux(kCLOCK_PerclkMux, 0);
/* Set lvds1 clock source. */
- CCM_ANALOG->MISC1 =
- (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
+ CCM_ANALOG->MISC1 = (CCM_ANALOG->MISC1 & (~CCM_ANALOG_MISC1_LVDS1_CLK_SEL_MASK)) | CCM_ANALOG_MISC1_LVDS1_CLK_SEL(0);
/* Set clock out1 divider. */
CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
/* Set clock out1 source. */
@@ -457,13 +473,19 @@ void BOARD_BootClockRUN(void) {
IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
/* Set MQS configuration. */
IOMUXC_MQSConfig(IOMUXC_GPR, kIOMUXC_MqsPwmOverSampleRate32, 0);
- /* Set ENET Tx clock source. */
- IOMUXC_EnableMode(IOMUXC_GPR, kIOMUXC_GPR_ENET1RefClkMode, false);
+ /* Set ENET Ref clock source. */
+ #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
+ #elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
+ /* Backward compatibility for original bitfield name */
+ IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
+ #else
+ #error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
+ #endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
/* Set GPT1 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
/* Set GPT2 High frequency reference clock source. */
IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
/* Set SystemCoreClock variable. */
SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
- CLOCK_SetMode(kCLOCK_ModeRun);
}
diff --git a/ports/mimxrt/boards/MIMXRT1052_clock_config.h b/ports/mimxrt/boards/MIMXRT1052_clock_config.h
index 358a6f03b..0e7febef3 100644
--- a/ports/mimxrt/boards/MIMXRT1052_clock_config.h
+++ b/ports/mimxrt/boards/MIMXRT1052_clock_config.h
@@ -1,5 +1,5 @@
/*
- * Copyright 2017-2019 NXP
+ * Copyright 2022 NXP
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@@ -13,9 +13,9 @@
/*******************************************************************************
* Definitions
******************************************************************************/
-#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
+#define BOARD_XTAL0_CLK_HZ 24000000U /*!< Board xtal0 frequency in Hz */
-#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
+#define BOARD_XTAL32K_CLK_HZ 32768U /*!< Board xtal32k frequency in Hz */
/*******************************************************************************
************************ BOARD_InitBootClocks function ************************
******************************************************************************/
@@ -40,54 +40,55 @@ void BOARD_InitBootClocks(void);
/*******************************************************************************
* Definitions for BOARD_BootClockRUN configuration
******************************************************************************/
-#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
+#define BOARD_BOOTCLOCKRUN_CORE_CLOCK 600000000U /*!< Core clock frequency: 600000000Hz */
/* Clock outputs (values are in Hz): */
-#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
-#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
-#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
-#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
-#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
-#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
-#define BOARD_BOOTCLOCKRUN_ENET1_TX_CLK 2400000UL
-#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
-#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
-#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
-#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
-#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
-#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 9642857UL
-#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
-#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
-#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
-#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
-#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
-#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
-#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
-#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
-#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
-#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
-#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
-#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 117333333UL
-#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 40000000UL
-#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
-#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
-#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_AHB_CLK_ROOT 600000000UL
+#define BOARD_BOOTCLOCKRUN_CAN_CLK_ROOT 40000000UL
+#define BOARD_BOOTCLOCKRUN_CKIL_SYNC_CLK_ROOT 32768UL
+#define BOARD_BOOTCLOCKRUN_CLKO1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLKO2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_CLK_1M 1000000UL
+#define BOARD_BOOTCLOCKRUN_CLK_24M 24000000UL
+#define BOARD_BOOTCLOCKRUN_CSI_CLK_ROOT 12000000UL
+#define BOARD_BOOTCLOCKRUN_ENET_125M_CLK 2400000UL
+#define BOARD_BOOTCLOCKRUN_ENET_25M_REF_CLK 1200000UL
+#define BOARD_BOOTCLOCKRUN_ENET_REF_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_ENET_TX_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO1_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXIO2_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_FLEXSPI_CLK_ROOT 160000000UL
+#define BOARD_BOOTCLOCKRUN_GPT1_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_GPT2_IPG_CLK_HIGHFREQ 75000000UL
+#define BOARD_BOOTCLOCKRUN_IPG_CLK_ROOT 150000000UL
+#define BOARD_BOOTCLOCKRUN_LCDIF_CLK_ROOT 67500000UL
+#define BOARD_BOOTCLOCKRUN_LPI2C_CLK_ROOT 60000000UL
+#define BOARD_BOOTCLOCKRUN_LPSPI_CLK_ROOT 105600000UL
+#define BOARD_BOOTCLOCKRUN_LVDS1_CLK 1200000000UL
+#define BOARD_BOOTCLOCKRUN_MQS_MCLK 63529411UL
+#define BOARD_BOOTCLOCKRUN_PERCLK_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_PLL7_MAIN_CLK 24000000UL
+#define BOARD_BOOTCLOCKRUN_SAI1_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK2 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI1_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI2_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI2_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SAI3_CLK_ROOT 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK1 63529411UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK2 0UL
+#define BOARD_BOOTCLOCKRUN_SAI3_MCLK3 30000000UL
+#define BOARD_BOOTCLOCKRUN_SEMC_CLK_ROOT 75000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_CLK_ROOT 30000000UL
+#define BOARD_BOOTCLOCKRUN_SPDIF0_EXTCLK_OUT 0UL
+#define BOARD_BOOTCLOCKRUN_TRACE_CLK_ROOT 132000000UL
+#define BOARD_BOOTCLOCKRUN_UART_CLK_ROOT 80000000UL
+#define BOARD_BOOTCLOCKRUN_USBPHY1_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USBPHY2_CLK 0UL
+#define BOARD_BOOTCLOCKRUN_USDHC1_CLK_ROOT 198000000UL
+#define BOARD_BOOTCLOCKRUN_USDHC2_CLK_ROOT 198000000UL
/*! @brief Arm PLL set for BOARD_BootClockRUN configuration.
*/
@@ -98,6 +99,9 @@ extern const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN;
/*! @brief Sys PLL for BOARD_BootClockRUN configuration.
*/
extern const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN;
+/*! @brief Video PLL set for BOARD_BootClockRUN configuration.
+ */
+extern const clock_video_pll_config_t videoPllConfig_BOARD_BootClockRUN;
/*******************************************************************************
* API for BOARD_BootClockRUN configuration
diff --git a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h
index 627b1aa3b..0ed32653f 100644
--- a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h
+++ b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.h
@@ -23,14 +23,14 @@
#define MICROPY_HW_UART_INDEX { 0, 1, 2, 3, 8, 4 }
#define IOMUX_TABLE_UART \
- { IOMUXC_GPIO_AD_B0_12_LPUART1_TX }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RX }, \
- { IOMUXC_GPIO_AD_B1_02_LPUART2_TX }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RX }, \
- { IOMUXC_GPIO_AD_B1_06_LPUART3_TX }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RX }, \
- { IOMUXC_GPIO_B1_00_LPUART4_TX }, { IOMUXC_GPIO_B1_01_LPUART4_RX }, \
+ { IOMUXC_GPIO_AD_B0_12_LPUART1_TXD }, { IOMUXC_GPIO_AD_B0_13_LPUART1_RXD }, \
+ { IOMUXC_GPIO_AD_B1_02_LPUART2_TXD }, { IOMUXC_GPIO_AD_B1_03_LPUART2_RXD }, \
+ { IOMUXC_GPIO_AD_B1_06_LPUART3_TXD }, { IOMUXC_GPIO_AD_B1_07_LPUART3_RXD }, \
+ { IOMUXC_GPIO_B1_00_LPUART4_TXD }, { IOMUXC_GPIO_B1_01_LPUART4_RXD }, \
{ 0 }, { 0 }, \
{ 0 }, { 0 }, \
{ 0 }, { 0 }, \
- { IOMUXC_GPIO_AD_B1_10_LPUART8_TX }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RX },
+ { IOMUXC_GPIO_AD_B1_10_LPUART8_TXD }, { IOMUXC_GPIO_AD_B1_11_LPUART8_RXD },
#define IOMUX_TABLE_UART_CTS_RTS \
{ IOMUXC_GPIO_AD_B0_14_LPUART1_CTS_B }, { IOMUXC_GPIO_AD_B0_15_LPUART1_RTS_B }, \
@@ -98,13 +98,13 @@
#define I2S_GPIO_MAP \
{ \
- I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin J4 09 */ \
- I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin J4 11 */ \
- I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin J4 10 */ \
- I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin J4 12 */ \
- I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin J4 14 */ \
- I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin J4 15 */ \
- I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00) /* pin J4 13 */ \
+ I2S_GPIO(1, MCK, TX, GPIO_AD_B1_09, IOMUXC_GPIO_AD_B1_09_SAI1_MCLK), /* pin J4 09 */ \
+ I2S_GPIO(1, SCK, RX, GPIO_AD_B1_11, IOMUXC_GPIO_AD_B1_11_SAI1_RX_BCLK), /* pin J4 11 */ \
+ I2S_GPIO(1, WS, RX, GPIO_AD_B1_10, IOMUXC_GPIO_AD_B1_10_SAI1_RX_SYNC), /* pin J4 10 */ \
+ I2S_GPIO(1, SD, RX, GPIO_AD_B1_12, IOMUXC_GPIO_AD_B1_12_SAI1_RX_DATA00), /* pin J4 12 */ \
+ I2S_GPIO(1, SCK, TX, GPIO_AD_B1_14, IOMUXC_GPIO_AD_B1_14_SAI1_TX_BCLK), /* pin J4 14 */ \
+ I2S_GPIO(1, WS, TX, GPIO_AD_B1_15, IOMUXC_GPIO_AD_B1_15_SAI1_TX_SYNC), /* pin J4 15 */ \
+ I2S_GPIO(1, SD, TX, GPIO_AD_B1_13, IOMUXC_GPIO_AD_B1_13_SAI1_TX_DATA00) /* pin J4 13 */ \
}
#define USDHC_DUMMY_PIN NULL, 0
@@ -140,22 +140,22 @@
{ IOMUXC_GPIO_EMC_40_ENET_MDC, 0, 0xB0E9u },
// --- SEMC --- //
-#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DATA00
-#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DATA01
-#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DATA02
-#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DATA03
-#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DATA04
-#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DATA05
-#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DATA06
-#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DATA07
-#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DATA08
-#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DATA09
-#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DATA10
-#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DATA11
-#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DATA12
-#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DATA13
-#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DATA14
-#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DATA15
+#define MIMXRT_IOMUXC_SEMC_DATA00 IOMUXC_GPIO_EMC_00_SEMC_DA00
+#define MIMXRT_IOMUXC_SEMC_DATA01 IOMUXC_GPIO_EMC_01_SEMC_DA01
+#define MIMXRT_IOMUXC_SEMC_DATA02 IOMUXC_GPIO_EMC_02_SEMC_DA02
+#define MIMXRT_IOMUXC_SEMC_DATA03 IOMUXC_GPIO_EMC_03_SEMC_DA03
+#define MIMXRT_IOMUXC_SEMC_DATA04 IOMUXC_GPIO_EMC_04_SEMC_DA04
+#define MIMXRT_IOMUXC_SEMC_DATA05 IOMUXC_GPIO_EMC_05_SEMC_DA05
+#define MIMXRT_IOMUXC_SEMC_DATA06 IOMUXC_GPIO_EMC_06_SEMC_DA06
+#define MIMXRT_IOMUXC_SEMC_DATA07 IOMUXC_GPIO_EMC_07_SEMC_DA07
+#define MIMXRT_IOMUXC_SEMC_DATA08 IOMUXC_GPIO_EMC_30_SEMC_DA08
+#define MIMXRT_IOMUXC_SEMC_DATA09 IOMUXC_GPIO_EMC_31_SEMC_DA09
+#define MIMXRT_IOMUXC_SEMC_DATA10 IOMUXC_GPIO_EMC_32_SEMC_DA10
+#define MIMXRT_IOMUXC_SEMC_DATA11 IOMUXC_GPIO_EMC_33_SEMC_DA11
+#define MIMXRT_IOMUXC_SEMC_DATA12 IOMUXC_GPIO_EMC_34_SEMC_DA12
+#define MIMXRT_IOMUXC_SEMC_DATA13 IOMUXC_GPIO_EMC_35_SEMC_DA13
+#define MIMXRT_IOMUXC_SEMC_DATA14 IOMUXC_GPIO_EMC_36_SEMC_DA14
+#define MIMXRT_IOMUXC_SEMC_DATA15 IOMUXC_GPIO_EMC_37_SEMC_DA15
#define MIMXRT_IOMUXC_SEMC_ADDR00 IOMUXC_GPIO_EMC_09_SEMC_ADDR00
#define MIMXRT_IOMUXC_SEMC_ADDR01 IOMUXC_GPIO_EMC_10_SEMC_ADDR01
diff --git a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk
index 7ea107b00..1bc38ccba 100644
--- a/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk
+++ b/ports/mimxrt/boards/SEEED_ARCH_MIX/mpconfigboard.mk
@@ -19,4 +19,3 @@ USE_UF2_BOOTLOADER = 1
FROZEN_MANIFEST ?= $(BOARD_DIR)/manifest.py
-CFLAGS += -DSPI_RETRY_TIMES=1000000
diff --git a/ports/mimxrt/eth.c b/ports/mimxrt/eth.c
index 1ac19b83d..1fbd9d389 100644
--- a/ports/mimxrt/eth.c
+++ b/ports/mimxrt/eth.c
@@ -397,9 +397,11 @@ void eth_init_0(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
enet_config.txAccelerConfig = kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled;
// Set interrupt
enet_config.interrupt |= ENET_TX_INTERRUPT | ENET_RX_INTERRUPT;
+ // Set callback
+ enet_config.callback = eth_irq_handler;
+ enet_config.userData = (void *)self;
ENET_Init(ENET, &g_handle, &enet_config, &buffConfig[0], hw_addr, source_clock);
- ENET_SetCallback(&g_handle, eth_irq_handler, (void *)self);
NVIC_SetPriority(ENET_IRQn, IRQ_PRI_PENDSV);
ENET_EnableInterrupts(ENET, ENET_RX_INTERRUPT);
ENET_ClearInterruptStatus(ENET, ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT);
@@ -461,9 +463,11 @@ void eth_init_1(eth_t *self, int eth_id, const phy_operations_t *phy_ops, int ph
enet_config.txAccelerConfig = kENET_TxAccelIpCheckEnabled | kENET_TxAccelProtoCheckEnabled;
// Set interrupt
enet_config.interrupt = ENET_TX_INTERRUPT | ENET_RX_INTERRUPT;
+ // Set callback
+ enet_config.callback = eth_irq_handler;
+ enet_config.userData = (void *)self;
ENET_Init(ENET_1, &g_handle_1, &enet_config, &buffConfig_1[0], hw_addr_1, source_clock);
- ENET_SetCallback(&g_handle_1, eth_irq_handler, (void *)self);
ENET_ClearInterruptStatus(ENET_1, ENET_TX_INTERRUPT | ENET_RX_INTERRUPT | ENET_ERR_INTERRUPT);
ENET_EnableInterrupts(ENET_1, ENET_RX_INTERRUPT);
ENET_ActiveRead(ENET_1);
diff --git a/ports/mimxrt/machine_i2s.c b/ports/mimxrt/machine_i2s.c
index 8553cb285..b57da4ad1 100644
--- a/ports/mimxrt/machine_i2s.c
+++ b/ports/mimxrt/machine_i2s.c
@@ -35,8 +35,14 @@
#include "fsl_iomuxc.h"
#include "fsl_dmamux.h"
#include "fsl_edma.h"
+#include "fsl_common.h"
#include "fsl_sai.h"
+#ifndef FSL_FEATURE_SAI_FIFO_COUNTn
+// Back-compat with mcux-sdk 2.11
+#define FSL_FEATURE_SAI_FIFO_COUNTn(x) FSL_FEATURE_SAI_FIFO_COUNT
+#endif
+
// Notes on this port's specific implementation of I2S:
// - the DMA callback is used to implement the asynchronous background operations, for non-blocking mode
// - all 3 Modes of operation are implemented using the peripheral drivers in the NXP MCUXpresso SDK
@@ -538,14 +544,14 @@ static bool i2s_init(machine_i2s_obj_t *self) {
EDMA_PrepareTransfer(&transferConfig,
self->dma_buffer_dcache_aligned, bytes_per_sample,
(void *)destAddr, bytes_per_sample,
- (FSL_FEATURE_SAI_FIFO_COUNT - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
+ (FSL_FEATURE_SAI_FIFO_COUNTn(self->i2s_inst) - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
SIZEOF_DMA_BUFFER_IN_BYTES, kEDMA_MemoryToPeripheral);
} else { // RX
uint32_t srcAddr = SAI_RxGetDataRegisterAddress(self->i2s_inst, SAI_CHANNEL_0);
EDMA_PrepareTransfer(&transferConfig,
(void *)srcAddr, bytes_per_sample,
self->dma_buffer_dcache_aligned, bytes_per_sample,
- (FSL_FEATURE_SAI_FIFO_COUNT - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
+ (FSL_FEATURE_SAI_FIFO_COUNTn(self->i2s_inst) - saiConfig.fifo.fifoWatermark) * bytes_per_sample,
SIZEOF_DMA_BUFFER_IN_BYTES, kEDMA_PeripheralToMemory);
}
diff --git a/ports/mimxrt/machine_pwm.c b/ports/mimxrt/machine_pwm.c
index b68521281..df76ed2b8 100644
--- a/ports/mimxrt/machine_pwm.c
+++ b/ports/mimxrt/machine_pwm.c
@@ -241,7 +241,9 @@ static void configure_flexpwm(machine_pwm_obj_t *self) {
pwmConfig.pairOperation = kPWM_Independent;
}
pwmConfig.clockSource = kPWM_BusClock;
+ #if !defined(FSL_FEATURE_PWM_HAS_NO_WAITEN) || (!FSL_FEATURE_PWM_HAS_NO_WAITEN)
pwmConfig.enableWait = false;
+ #endif
pwmConfig.initializationControl = self->sync ? kPWM_Initialize_MasterSync : kPWM_Initialize_LocalSync;
if (PWM_Init(self->instance, self->submodule, &pwmConfig) == kStatus_Fail) {
diff --git a/ports/mimxrt/machine_rtc.c b/ports/mimxrt/machine_rtc.c
index e6c519991..b025e3926 100644
--- a/ports/mimxrt/machine_rtc.c
+++ b/ports/mimxrt/machine_rtc.c
@@ -156,7 +156,7 @@ void machine_rtc_start(void) {
SNVS->HPCOMR |= SNVS_HPCOMR_NPSWA_EN_MASK;
// Do a basic init.
SNVS_LP_Init(SNVS);
- #if FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER
+ #if defined(FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER) && (FSL_FEATURE_SNVS_HAS_MULTIPLE_TAMPER > 0)
// Disable all external Tamper
SNVS_LP_DisableAllExternalTamper(SNVS);
#endif
diff --git a/ports/minimal/mpconfigport.h b/ports/minimal/mpconfigport.h
index 87287cbc6..b542c124d 100644
--- a/ports/minimal/mpconfigport.h
+++ b/ports/minimal/mpconfigport.h
@@ -21,6 +21,12 @@
// Use the minimum headroom in the chunk allocator for parse nodes.
#define MICROPY_ALLOC_PARSE_CHUNK_INIT (16)
+// Disable all optional sys module features.
+#define MICROPY_PY_SYS_MODULES (0)
+#define MICROPY_PY_SYS_EXIT (0)
+#define MICROPY_PY_SYS_PATH (0)
+#define MICROPY_PY_SYS_ARGV (0)
+
// type definitions for the specific machine
typedef intptr_t mp_int_t; // must be pointer size
diff --git a/ports/nrf/mpconfigport.h b/ports/nrf/mpconfigport.h
index d944fc8a1..d361d01cc 100644
--- a/ports/nrf/mpconfigport.h
+++ b/ports/nrf/mpconfigport.h
@@ -289,7 +289,6 @@
#define MICROPY_PY_GENERATOR_PEND_THROW (1)
#define MICROPY_PY_MATH (1)
#define MICROPY_PY_STRUCT (1)
-#define MICROPY_PY_SYS (1)
#define MICROPY_PY_SYS_PATH_ARGV_DEFAULTS (1)
#endif
diff --git a/ports/powerpc/mpconfigport.h b/ports/powerpc/mpconfigport.h
index 091e94bda..fcb66bab1 100644
--- a/ports/powerpc/mpconfigport.h
+++ b/ports/powerpc/mpconfigport.h
@@ -81,7 +81,6 @@
#define MICROPY_PY_CMATH (0)
#define MICROPY_PY_IO (0)
#define MICROPY_PY_STRUCT (1)
-#define MICROPY_PY_SYS (1)
#define MICROPY_MODULE_FROZEN_MPY (1)
#define MICROPY_CPYTHON_COMPAT (0)
#define MICROPY_LONGINT_IMPL (MICROPY_LONGINT_IMPL_MPZ)
diff --git a/ports/unix/variants/minimal/mpconfigvariant.h b/ports/unix/variants/minimal/mpconfigvariant.h
index 97ed786b8..2edac41c7 100644
--- a/ports/unix/variants/minimal/mpconfigvariant.h
+++ b/ports/unix/variants/minimal/mpconfigvariant.h
@@ -61,6 +61,5 @@
#define MICROPY_PY_BUILTINS_RANGE_ATTRS (1)
#define MICROPY_PY_GENERATOR_PEND_THROW (1)
-// Enable just the sys and os built-in modules.
-#define MICROPY_PY_SYS (1)
+// Add just the os built-in module.
#define MICROPY_PY_OS (1)
diff --git a/ports/zephyr/mpconfigport_minimal.h b/ports/zephyr/mpconfigport_minimal.h
index 24e0c9f1a..c802ba525 100644
--- a/ports/zephyr/mpconfigport_minimal.h
+++ b/ports/zephyr/mpconfigport_minimal.h
@@ -59,7 +59,6 @@
#define MICROPY_PY_BUILTINS_STR_OP_MODULO (1)
#define MICROPY_PY_BUILTINS_BYTEARRAY (1)
#define MICROPY_PY_BUILTINS_DICT_FROMKEYS (1)
-#define MICROPY_PY_SYS (1)
#ifdef CONFIG_BOARD
#define MICROPY_HW_BOARD_NAME "zephyr-" CONFIG_BOARD
generated by cgit v1.2.3 (git 2.46.0) at 2025-08-26 03:30:16 +0000