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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Allows `MICROPY_HW_QSPIFLASH_SIZE_BITS_LOG2` and
`MICROPY_HW_QSPI_MPU_REGION_SIZE` to be arbitrary expressions, eg function
calls.
The `storage.h` header needs to be included in case access to `spi_bdev_t`
is needed by the macros.
Signed-off-by: Damien George <damien@micropython.org>
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Options for a board to configure ROMFS are:
- Leave ROMFS disabled, do nothing.
- Enable by defining `MICROPY_HW_ROMFS_ENABLE_PARTx` to 1 and then in the
linker script define `_micropy_hw_romfs_partX_start` and
`_micropy_hw_romfs_partX_size`.
- Enable by defining `MICROPY_HW_ROMFS_ENABLE_PARTx` to 1 and also define
`MICROPY_HW_ROMFS_PARTx_START` and `MICROPY_HW_ROMFS_PARTx_SIZE` which
can be arbitrary expressions (not necessarily static)
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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This commit allows the user of this driver to intercept the SPI flash
initialisation routine and possibly take some action based on the JEDEC id,
for example change the `mp_spiflash_t::chip_params` element.
To do this, enable `MICROPY_HW_SPIFLASH_DETECT_DEVICE` and define a
function called `mp_spiflash_detect()`.
Signed-off-by: Damien George <damien@micropython.org>
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This commit allows the user of this driver to dynamically configure the SPI
flash chip parameters. For this, enable `MICROPY_HW_SPIFLASH_CHIP_PARAMS`
and then set the `mp_spiflash_t::chip_params` element to point to a valid
`mp_spiflash_chip_params_t` struct.
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Jos Verlinde <Jos_Verlinde@hotmail.com>
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Signed-off-by: Jos Verlinde <Jos_Verlinde@hotmail.com>
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mpremote now supports `mpremote rm -r`.
Addresses #9802 and #16845.
Signed-off-by: Jos Verlinde <Jos_Verlinde@hotmail.com>
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Signed-off-by: Damien George <damien@micropython.org>
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This test is not intended to be run automatically and does not have a
corresponding .exp file.
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Supports Murata 1YN for WiFi and BLE.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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To match the instruction length, so the DFS is restored to the XIP value
after an erase or write (due to the final wait WIP).
Signed-off-by: Damien George <damien@micropython.org>
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It's not needed, the MPU configures the XIP as non-cacheable.
Signed-off-by: Damien George <damien@micropython.org>
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Now raises an exception if the pin doesn't support the alternate function
unit number and line type, eg UART0_TX (previously it only checked the
peripheral).
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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They will be generated as part of the build.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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This allows HE to execute code from the ROMFS in MRAM.
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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To allow writing to MRAM region.
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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This allows the correct start up functions to be called by the stdlib.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Unlike HWSEM, the MHU IRQ can wake up cores from low-power modes, making it
better suited for notifying remote cores. Note that no special function is
required to wake up a remote core—the act of sending a message alone will
notify it.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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This channel can be used to communicate (pass messages) between the M55
cores in the RTSS. Currently it's only used to notify the cores.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Lightsleep current is around 23mA. Deepsleep current is sub 50uA.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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The right service call to get UID is SERVICES_system_get_eui_extension
which returns an 8 bytes UID.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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The byte order (endianness) seems to be swapped when read in 8D-8D-8D in
XIP mode, for most flashes, with the exception of MX which seems to swap
half-words.
This commit adds a flash setting to allow parts to enable half-word swap
when data is written, to fix this issue. By default, only endianness is
fixed.
Tested with both MX and ISSI parts on AE3, flash test and simple file
write/read.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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The OSPI controller supports concurrent direct/XIP accesses, there's no
need to disable XIP on direct access. In addition to improving the
performance, this change lays the groundwork for supporting access by
the HP and HE cores simultaneously.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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This change increases XIP read speed to ~30Mbytes/s at 50MHz DDR:
- Enable continuous mode.
- Remove hard-coded settings.
- Set XIP continuous mode timeout.
The prefetch remains disabled. Although enabling the prefetch gives the
best performance for the CPU in XIP mode, it must be disabled when the NPU
accesses the OSPI flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Leaving this pin low in combination with the default EM settings enables
flash protection for the EM flash.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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