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So that pre-commit and CI will check formatting and linting.
Signed-off-by: Damien George <damien@micropython.org>
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Signed-off-by: Damien George <damien@micropython.org>
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Running `ruff format tools/cc1` picks up `tools/cc1` which is a Python file
that does not have a .py file extension.
Signed-off-by: Christian Clauss <cclauss@me.com>
Signed-off-by: Damien George <damien@micropython.org>
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Add abort setup code `nlr_set_abort` to the standard runtime executor.
This makes the standard runtime respond to abort signal without any further
modifications.
- When aborted, the program exits with 137 exit code (configurable, same as
posix sig abort), to differentiate from a normal shutdown.
- When exited by exception/crash, the program will exit with exit code 1
(configurable).
- When exited by exception KeyboardInterrupt, the program will exit with
exit code 130 (configurable, same as posix sig int).
- When exited with a exit code (from Python environment), this code is
propagated. When a different object is passed, exit code is set to 1 and
the value printed, to be consistent with Python docs:
https://python.readthedocs.io/en/latest/library/exceptions.html#SystemExit
Signed-off-by: John Smith <jsmith@jsmith.cz>
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This adds type casting to avoid build errors on certain systems.
Signed-off-by: Yanfeng Liu <yfliu2008@qq.com>
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This commit lets the native emitter generate shorter code when clearing
exception objects on RV32.
Since there are no direct generic ASM functions to set a specific
immediate to a local variable, the native emitter usually generates an
immediate assignment to a temporary register and then a store of that
register into the chosen local variable. This pattern is also followed
when clearing certain local variables related to exception handling,
using MP_OBJ_NULL as the immediate value to set.
Given that at the moment MP_OBJ_NULL is defined to be 0 (with some other
spots in the native emitter that leverage that fact when checking the
state of the variables mentioned earlier), and that the RV32 CPU has a
dedicated register that is hardwired to read 0, a new method to set
local variables to MP_OBJ_NULL is introduced.
When generating RV32 code, the new macro will skip the intermediate
register assignment and directly uses the X0/ZERO register to set the
chosen local variable to MP_OBJ_NULL. Other platforms will still
generate the same code sequence as before this change.
This is a followup to 40585eaa8f1b603f0094b73764e8ce5623812ecf.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This field exists to cache the lnotab field removed from v2 in #17639 by
ddf2c3afb17c0ea3dd678d02d9c2f01bed5a3020, and is now unused.
Signed-off-by: Anson Mansfield <amansfield@mantaro.com>
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This commit changes the sequences generated for not-equal and
less-than-or-equal comparisons, in favour of better replacements.
The new not-equal comparison generates a sequence of equal size but
without the burden of a jump to set the output value, this also had
the effect of reducing the size of the code generator as only two
opcodes need to be generated instead of three.
The less-than-or-equal sequence, on the other hand, is actually two
bytes shorter and does not contain any jumps. If Zcb opcodes can be
used for performing the final XOR operation then two more bytes could be
saved on each comparison. The same remarks about having a shorter
generator due to two opcodes being generated instead of three still
applies here.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit shortens register-indexed load/store emitter functions, by
reusing integer-indexed equivalent operations as part of the sequence
generation process.
Before these changes, register-indexed load/store emitters would follow
two steps to generate the sequence: generate opcodes to fix up the
register offset to make it point to the exact position in memory where
the operation should take place, and then perform the load/store
operation itself using 0 as an offset from the recalculated address
register.
Since there is already a generic optimised emitter for integer-indexed
load/stores, that bit of code can be reused rather than having an ad-hoc
implementation that is tailored to operate on an offset of 0. Removing
the custom emitter code in favour of calling the general integer-indexed
emitter saves around 150 bytes without any changes in the emitter
behaviour (generating the same opcode sequence and making use of future
improvement in that emitter too).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit minimises the amount of code required to perform validation
of load/store opcodes, streamlining their validation and serialisation.
Load/store opcodes used to be handled as a special case due to how its
peculiar syntax yields parse node arguments that cannot be handled by
the regular validation and serialisation functions.
The changes in this commit attempt to reduce the amount of special code
needed for those opcodes to its bare minimum, by removing the special
opcode handling step, merging the validation and serialisation pass for
the combined offset + base register operand, and integrate said changes
in the existing argument handling structure.
That allowed to rework the special operand parsing function to make it
smaller, and remove the code that performed the special case validation
and emitted the opcode.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit simplifies the way arguments are validated when processing
RV32 inline assembler opcodes.
Opcode arguments were handled in two separate passes, one that performed
a pure validation (with an early rejection in case of errors), and
another that converted the parse node into a serialised value but
without any error checking.
Considering that the validation pass effectively performed the parse
node conversion and then discarded its result once validated, it is
preferable to hold onto the serialised result to reuse it later at
opcode generation time.
With these changes, those two passes are merged into one single
operation when applicable (basically any opcode that doesn't use an
integer offset), removing a fair amount of duplicate code. The size
savings should be around half a kilobyte, with no other changes in the
assembler's behaviour.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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TinyUSB's `dwc2_phy_init()` only sets the PWRDWN bit in the GCCFG register
but doesn't configure VBUS sensing, which is required for the DWC2 USB
controller to detect host connection on STM32F4 and STM32F7 series.
Without VBUS sensing configured, USB devices fail to enumerate on these
platforms when using the TinyUSB stack, while the legacy STM32 USB stack
works because it includes this configuration.
This commit adds VBUS sensing configuration in `pyb_usbd_init()` for
TinyUSB mode on STM32F4/F7:
- When VBUS detect pin is configured (typically PA9): Enable "B device"
VBUS sensing (USB_OTG_GCCFG_VBUSBSEN)
- When no VBUS pin: Force VBUS valid (USB_OTG_GCCFG_NOVBUSSENS)
Tested on:
- NUCLEO-F429ZI: USB now enumerates successfully (CDC + MSC)
- NUCLEO-H563ZI: No regression (STM32H5 uses different register layout)
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
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Implements USB MSC functionality for STM32 port when using TinyUSB stack,
supporting both internal Flash and SD card storage mediums.
Signed-off-by: Andrew Leech <andrew@alelec.net>
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This commit adapts the stm32 port to allow switching from STM USB stack to
TinyUSB stack.
Using TinyUSB improves consistancy with other MicroPython ports and brings
in the ability to use the runtime USB definition support recently added to
other TinyUSB based ports.
By default the existing STM USB stack is used. TinyUSB can be enabled in a
board configuration with:
#define MICROPY_HW_TINYUSB_STACK (1)
Or, it can be enabled from the command line with:
make -C ports/stm32 CFLAGS_EXTRA='-DMICROPY_HW_TINYUSB_STACK=1'
Signed-off-by: Andrew Leech <andrew@alelec.net>
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It's very STM32 USB stack specific and doesn't generalise well to other
ports. So remove it.
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
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Implemented the keyword-only parameter `invert` for the `UART.init` method
in accordance with the docs:
- added constants `UART.INV_TX` and `UART.INV_RX`
- added the new `invert` keyword parameter to the `uart_init` function
- adapted the `uart_init` call
- added invert setting to `uart_print` output
The feature applies only to STM32H7.
Signed-off-by: ennyKey <ennyKey@fn.de>
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This change adds NUCLEO-U5A5ZJ-Q support to the STM32 port.
NUCLEO-U5A5ZJ-Q: https://www.st.com/ja/evaluation-tools/nucleo-u5a5zj-q.html
This board use STM32U5A5ZJ: https://www.st.com/ja/microcontrollers-microprocessors/stm32u5a5zj.html
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
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This change adds STM32U5 support to the STM32 port.
STM32U5A5ZJ: https://www.st.com/ja/microcontrollers-microprocessors/stm32u5a5zj.html
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
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Added STM32N6 with HAL1.2.0
Added STM32U5 with HAL1.8.0
Updated STM32WB from HAL1.10.0 to HAL1.23.0
Signed-off-by: Andrew Leech <andrew.leech@planetinnovation.com.au>
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There are multiple RP2350 boards missing RISC-V builds. Some were missing
entries in their `board.json` or a CMake file altogether. This commit
fixes them.
Signed-off-by: Craftzman7 <zezetta@icloud.com>
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Changes in this commit:
- Change ticks overhead value for SAMD51. The value was too large and thus
timing was quite bad. At 120Mhz it's now within +/- 30ns.
- Set the pin to output mode. That way, all Pin identifiers are accepted
as argument, not only Pin objects.
Tested with ItsyBitsy M4 and M0 boards.
Signed-off-by: robert-hh <robert@hammelrath.com>
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While clarifying the meaning of the arguments to `mp_quicksort`, I noticed
that by pre-adjusting the `head` argument similar to what was already done
for `tail`, code size could be saved by eliminating repeated calculation of
`h + 1`.
Signed-off-by: Jeff Epler <jepler@unpythonic.net>
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This commit introduces a test file (along with its necessary data) to
test MPY files pass/reject cases, due to either mismatching architecture
flag requirements or unneeded "no-flags" values set.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit lets "run-tests.py" use the encoded architecture flags
provided by the interpreter when invoking "mpy-cross".
If architecture flags are detected, they're mapped into the necessary
strings needed by "mpy-cross"'s "-march-flags" argument, so that tests
will always use all available extensions reported by the target.
Currently this is limited to the RV32 platform, as it is the only one
that is making use of this facility as of now. This also lets the QEMU
port remove forced arguments to "mpy-cross" when running the test suite.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit extends the "micropython/import_mpy_native_gc" test with a
pre-built serialised MPY file built for RV32.
Before this commit, the test was skipped on said platform due to the
lack of a known-good MPY file to test the import procedure against.
Now the test is executed as part of the general CI test checks.
The MPY file's Makefile script was also updated to cater for modern
Linux environments where the required Python interpreter's command name
isn't "python", but "python3" instead (this occurs when using the past
two LTS Ubuntu releases for example). This is the same kind of change
made in 31a008c6e26eccc3798a9ab4169019a02eadb830.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit adds the currently supported architecture flags value as the
upper part of "sys.implementation._mpy".
This had the side effect of perturbing quite a bit of testing
infrastructure and invalidating documentation related to MPY files. To
make the test suite run successfully and keep the documentation in sync
the following changes have been made:
* The target info feature check file now isolates eventual architecture
flags and adds them as a separate field
* The test runner now picks up the new architecture flags field, reports
it to STDOUT if needed and stores it for future uses
* Relevant test files for MPY files import code had to be updated to
mask out the architecture flags bits in order to perform correctly
* MPY file format documentation was updated to show how to mask off and
properly display the architecture flags information.
This works out of the box if the flag bits can fit in a smallint value
once merged with the MPY file header value.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit extends "mpy-cross"'s parsing of the architecture flags
value command line, allowing raw integer values as well as flag strings.
Integers can be represented as either decimal, binary, or hexadecimal
values, using the usual C language prefixes to mark non-base 10 values.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit extends "mpy-tool.py"'s disassembly output of a given MPY
file (triggered via the "-d" command line option) to include newly added
fields.
Now the target architecture for the chosen MPY file is printed out to
screen in human-readable format and, if present, architecture-specific
flags.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit introduces the MPY architecture flags checking code specific
for the RV32 target, currently checking for the only additional
extension that is supported by the runtime: Zba.
The warnings inside "mpy-cross" have also been removed since now there
is a way to reject incompatible MPY files at runtime.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This commit extends the MPY file format in a backwards-compatible way to
store an encoded form of architecture-specific flags that have been
specified in the "mpy-cross" command line, or that have been explicitly
set as part of a native emitter configuration.
The file format changes are as follows:
* The features byte, previously containing the target native
architecture and the minor file format version, now claims bit 6 as a
flag indicating the presence of an encoded architecture flags integer
* If architecture flags need to be stored, they are placed right after
the MPY file header.
This means that properly-written MPY parsers, if encountering a MPY file
containing encoded architecture flags, should raise an error since no
architecture identifiers have been defined that make use of bits 6 and
7 in the referenced header byte. This should give enough guarantees of
backwards compatibility when this feature is used (improper parsers were
subjected to breakage anyway).
The encoded architecture flags could have been placed at the end, but:
* Having them right after the header makes the architecture
compatibility checks occur before having read the whole file in memory
(which still happens on certain platforms as the reader may be backed
by a memory buffer), and prevents eventual memory allocations that do
not take place if the module is rejected early
* Properly-written MPY file parsers should have checked the upper two
bits of the flags byte to be actually zero according to the format
specification available right before this change, so no assumptions
should have been made on the exact order of the chunks for an
unexpected format.
The meaning of the architecture flags value is backend-specific, with
the only common characteristic of being a variable-encoded unsigned
integer for the time being.
The changes made to the file format effectively limit the number of
possible target architectures to 16, of which 13 are already claimed.
There aren't that many new architectures planned to be supported for the
lifetime of the current MPY file format, so this change still leaves
space for architecture updates if needed.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
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This change adds NUCLEO_H7A3ZI_Q Core Board support to the STM32 port.
NUCLEO_H7A3ZI_Q:
https://www.st.com/en/evaluation-tools/nucleo-h7a3zi-q.html
This board uses STM32H7A3ZI:
https://www.st.com/en/microcontrollers-microprocessors/stm32h7a3zi.html
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
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STM32H7A3 uses PA11, PA12 to enable USB function via built-in USB OTG port
on NUCLEO board.
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
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For STM32H7, the following macro's value are different by ADC's version:
* ADC_CAL_ADDRESS
* ADC_CAL1
* TEMPSENSOR_CAL2_ADDR
Using macros defined by HAL become less dependent on ADC's version.
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
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STM32H7A3 has 2MB internal flash and each sector size is 8KB.
Signed-off-by: Yuuki NAGAO <wf.yn386@gmail.com>
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Signed-off-by: Kwabena W. Agyeman <kwagyeman@live.com>
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32-bit floats are needed for object representation C.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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This is consistent with the other ports (see py/mkrules.mk) and makes
more sense overall because it makes everything which is compiled use
the same flags; until now all compilation steps which ran before or in
absence of FreezeModules (e.g. qstr generation, compiling a single file
on the command line or in the IDE) would use different PP defs. This
didn't happen to cause any issues apparently but it's just more
consistent/safer to not do that.
Signed-off-by: stijn <stijn@ignitron.net>
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Setting RTS/DTR raises "Inappropriate ioctl for device" for pts devices.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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This is a Cortex-M55 board.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Using the newly added `uart_rx_any()` and system ticks functions.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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So it can be used for polling.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
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This makes the version string consistent with the one used in code, see
commit 9e89c752cb.
Signed-off-by: Daniël van de Giessen <daniel@dvdgiessen.nl>
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Now the default reference commit is the first parent of the selected
commit, instead of the first parent of HEAD.
Signed-off-by: Jeff Epler <jepler@unpythonic.net>
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This will show a line for both the reference and comparison, e.g.,
Reference: zephyr/boards: Add PocketBeagle 2 rev A1… [00a926e99e]
Comparison: metrics: Tersely show the commi… [merge of c7ac411e22]
When the comparison is a merge commit (as it is during CI) the second
parent of that commit is shown instead.
This will be helpful when checking which revision of the code size report
comment on a PR corresponds to which revision of the code.
Signed-off-by: Jeff Epler <jepler@unpythonic.net>
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This is the case in arm-none-eabi-gcc 14.2.1 (debian trixie).
This fixes a diagnostic like:
../../lib/libm_dbl/libm.h:92:9: error:
"DBL_EPSILON" redefined [-Werror]
/usr/lib/gcc/arm-none-eabi/14.2.1/include/float.h:114:9: note:
this is the location of the previous definition
when building MPS2_AN500 (qemu port).
Signed-off-by: Jeff Epler <jepler@unpythonic.net>
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