| Age | Commit message (Collapse) | Author |
|---|
|
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
The default dummy cycles may not match the actual flash frequency supported
by a certain board. For example, the MX chip uses 20 dummy cycles by
default which supports up to 200MHz DDR, but the maximum frequency
supported by the AE3 board is 50MHz DDR. So the dummy cycles for this
board can be as low as 6. It's important to set the correct dummy cycles,
as it results in doubling the XIP read speed, in the case of the AE3 board.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
This commit enables detecting the flash device in runtime, and uses the
settings of the detected device instead of board-defined flash settings.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Disable XIP instruction DDR for 8-bit instructions.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Define an MPU region for Open-AMP and remove hard-coded attribute.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
UTIMER is used by the HP.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
The same MicroPython firmware is built for the HE but with slightly
different options, for example no USB.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
With this new Makefile you can build the following:
make BOARD=MY_BOARD MCU_CORE=M55_HP # build HP firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_HE # build HE firmware/ToC.
make BOARD=MY_BOARD MCU_CORE=M55_DUAL # build HE+HP firmware + ToC.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Note that 128K at the beginning of MRAM is reserved for future bootloaders.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
ADC12 information has been added to pin struct.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Using SE services to get the SoC unique id.
Signed-off-by: Damien George <damien@micropython.org>
|
|
They both use SE services.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Calls the SE services to print information about the SoC.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Uses the SE services to provide a random seed.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Uses the SE services to provide random numbers.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Includes services to get random numbers, reset SoC, get unique-id, dump SoC
info, and CPU control services.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Includes an implementation of `system_tick_wfe_with_timeout_us()`.
Signed-off-by: Damien George <damien@micropython.org>
|
|
This commit adds the beginning of a new alif port with support for Alif
Ensemble MCUs. See https://alifsemi.com/
Supported features of this port added by this commit:
- UART REPL.
- TinyUSB support, for REPL and MSC.
- Octal SPI flash support, for filesystem.
- machine.Pin support.
General notes about the port:
- It uses make, similar to other bare-metal ports here.
- The toolchain is the standard arm-none-eabi- toolchain.
- Flashing a board can be done using either the built-in serial bootloader,
or JLink (both supported here).
- There are two required submodules (one for drivers/SDK, one for security
tools), both of which are open source and on GitHub.
- No special hardware or software is needed for development, just a board
connected over USB.
OpenMV have generously sponsored the development of this port.
Signed-off-by: Damien George <damien@micropython.org>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
From https://github.com/alifsemi/alif_vscode-tinyusb.git,
commit c79f39361d334ee44f44fed30c56e70dbb368649
Signed-off-by: Damien George <damien.p.george@gmail.com>
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
Signed-off-by: Damien George <damien@micropython.org>
|
|
This word appears in the upcoming alif port.
Signed-off-by: Damien George <damien@micropython.org>
|
|
The cyw43-driver now provides the Bluetooth initialisation code, making
`drivers/cyw43/cywbt.c` obsolete. To use the new code a port must enable
the `CYW43_ENABLE_BLUETOOTH_OVER_UART` option.
Some ports have yet to migrate to the new code, so in the meantime they can
explicitly add the old source to their source list and continue to use it
without change.
Signed-off-by: Damien George <damien@micropython.org>
|
|
This file is part of the updated cyw43-driver. It will only be used if
`CYW43_USE_SPI` is enabled.
Signed-off-by: Damien George <damien@micropython.org>
|
|
Configure flash timings dynamically to match the system clock. Reconfigure
timings after flash writes.
Changes are:
- ports/rp2/main.c: Set default flash timings.
- ports/rp2/modmachine.c: Configure optimal flash timings on freq change.
- ports/rp2/rp2_flash.c: Reconfigure flash when leaving critical section.
Signed-off-by: Phil Howard <github@gadgetoid.com>
|
|
Add a 256 byte (FLASH_PAGE_SIZE) SRAM copy buffer to allow copies from
PSRAM to flash. This would otherwise hardfault since PSRAM is disabled
when doing a write to flash.
Changes are:
- ports/rp2/rp2_flash.c: Add 256 byte (flash page size) SRAM copy buffer
for PSRAM to flash copies.
- ports/rp2/rp2_flash.c: Invalidate the XIP cache to purge any PSRAM
data before critical flash operations.
Co-authored-by: Phil Howard <github@gadgetoid.com>
Co-authored-by: Angus Gratton <angus@redyak.com.au>
Signed-off-by: Phil Howard <github@gadgetoid.com>
|
|
PSRAM will be used exclusively if MICROPY_GC_SPLIT_HEAP == 0, it will be
added to RAM if MICROPY_GC_SPLIT_HEAP == 1, and the system will fall back
to RAM only if it's not detected.
Due to the size of PSRAM, GC stack was overflowing and causing the GC to
scan through the entire memory pool. This caused noticable slowdowns
during GC. Increase the stack from 256 to 4096 bytes to avoid overflow and
increase the stack entry type size to accomodate 8MB+ PSRAM.
Changes are:
- ports/rp2/mpconfigport.h: Make split-heap optional and enable by default.
- ports/rp2/mpconfigport.h: Increase GC stack entry type to uint32_t.
- ports/rp2/mpconfigport.h: Raise GC stack size.
Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com>
Signed-off-by: Phil Howard <github@gadgetoid.com>
|
|
Performs a best-effort attempt to detect attached PSRAM, configure it and
*add* it to the MicroPython heap. If PSRAM is not present, should fall
back to use internal RAM.
Introduce two new port/board defines:
- MICROPY_HW_ENABLE_PSRAM to enable PSRAM.
- MICROPY_HW_PSRAM_CS_PIN to define the chip-select pin (required).
Changes are:
- ports/rp2/rp2_psram.[ch]: Add new PSRAM module.
- ports/rp2/main.c: Add optional PSRAM support.
- ports/rp2/CMakeLists.txt: Include rp2_psram.c.
- ports/rp2/mpconfigport.h: Add MICROPY_HW_ENABLE_PSRAM.
- ports/rp2/modmachine.c: Reconfigure PSRAM on freq change.
Co-authored-by: Kirk Benell <kirk.benell@sparkfun.com>
Co-authored-by: Mike Bell <mike@mercuna.com>
Signed-off-by: Phil Howard <phil@gadgetoid.com>
|
|
Currently the tool allows writing an invalid ROMFS image, with a bad header
or images smaller than minimum size, and only checks the image extension.
This commit allows deploying a ROMFS with either a ".img" or ".romfs"
extension (in the future support may be added for other extensions that
have different semantics, eg a manifest), and validates the image header
before writing.
Signed-off-by: iabdalkader <i.abdalkader@gmail.com>
|
|
Previously this information was recorded in a "status" field of the result,
but nothing ever parsed this result which led to non-differences not being
removed.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
|
|
MicroPython support for this behaviour was added in eb45d97898a.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
|
|
Since 7c1584aef1 MicroPython matches CPython in most cases, aside from
nested comprehensions.
This work was funded through GitHub Sponsors.
Signed-off-by: Angus Gratton <angus@redyak.com.au>
|
|
If picotool is not installed, it's fetched and built when compiling each
rp2 board. And the "develop" branch of picotool is used instead of a
release. Installing it manually using the "master" branch means the latest
released version is used (instead of a possibly unstable development
version), and also makes building each rp2 board a little faster.
Signed-off-by: Damien George <damien@micropython.org>
|
|
This is a known limitation, so better to give a clear warning than a
catch-all AssertionError. Happens for example when trying to use
soft-float on ARCH=armv6m
Also give more details on the assertion for unknown relocations, such that
one can see which symbol it affects etc, to aid in debugging.
References issue #14430.
Signed-off-by: Jon Nordby <jononor@gmail.com>
|
|
This commit removes a definition used back when ESP-IDF v4 was supported
by MicroPython. Those times are now long gone, and so is the need for
that particular definition to be set in the first place.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
|
|
This commit cleans up a couple of RISC-V specific directives in the
build script. Namely, removes the forced inclusion of the "riscv"
component and introduces proper mpy-cross flags.
The "riscv" component is already included by the ESP-IDF build
framework, as certain low-level components would not build otherwise, so
there is no need to add it to the required components list.
The architecture flag for mpy-cross is now set for RISC-V targets, as it
was previously set only for Xtensa targets (and it relied on a string
comparison rather than using the appropriate configuration variable).
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
|
|
This commit changes the gchelper implementation in use for RV32-based
targets (ESP32C3, ESP32C6) from the generic one written in C to the one
written in assembler that is specific to the CPU in question.
The native implementation is already exercised on most CI builds as it
is used by the QEMU port to compile and test the RV32 target.
Signed-off-by: Alessandro Gatti <a.gatti@frob.it>
|
