diff options
| -rw-r--r-- | src/include/storage/s_lock.h | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/src/include/storage/s_lock.h b/src/include/storage/s_lock.h index eff84708dc6..e77eb924f00 100644 --- a/src/include/storage/s_lock.h +++ b/src/include/storage/s_lock.h @@ -440,6 +440,11 @@ typedef unsigned int slock_t; #define TAS_SPIN(lock) (*(lock) ? 1 : TAS(lock)) /* + * The second operand of addi can hold a constant zero or a register number, + * hence constraint "=&b" to avoid allocating r0. "b" stands for "address + * base register"; most operands having this register-or-zero property are + * address bases, e.g. the second operand of lwax. + * * NOTE: per the Enhanced PowerPC Architecture manual, v1.0 dated 7-May-2002, * an isync is a sufficient synchronization barrier after a lwarx/stwcx loop. * On newer machines, we can use lwsync instead for better performance. @@ -476,7 +481,7 @@ tas(volatile slock_t *lock) #endif " li %1,0 \n" -: "=&r"(_t), "=r"(_res), "+m"(*lock) +: "=&b"(_t), "=r"(_res), "+m"(*lock) : "r"(lock) : "memory", "cc"); return _res; |