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<title>Memory simulation in µCsim</title>
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<h1>Memory simulation in <i>µCsim</i></h1>
Typical microprocessor system can look like this:
<p><img src="cpu-mem.svg" alt="[CPU-memory connection]" border="0"></p>
<h3><a name="address_space">Address space</a></h3>
In our terminology "<b>address space</b>" means a set of:
<ul>
<li>address bus lines </li>
<li>data bus lines </li>
<li>control (read/write) lines</li>
</ul>
Bus lines can be shared by address spaces, in this case number of control
line sets specifies the address spaces.
<p>Microcontrollers usually have more address spaces. Some is used inside
only, some can be used for external memories. </p>
<p>Address space does not store any value. It just specifies range of
addresses by <i>start address</i> (which is not necessarily zero) and <i>size</i>
which the CPU can provide when it tries to access a memory location.</p>
<h3><a name="chip">Memory chip</a></h3>
"<b>Memory chip</b>" is a circuit which can hold values in cells. Cells are
indexed from 0 up to size-1. Each cell stores some (usually 8) bits.
<p><img src="chip.svg" alt="[Memory chip]" border="0"></p>
<h3><a name="address_decoder">Address decoder</a></h3>
Addresses coming from an address space via address bus must be routed to
memory and translated to cell indexes. This is done by the "<b>address
decoder</b>". It listens addresses on the bus and control lines and
enables exactly one memory chip. This way cells of the memory chip appear in
the address space.
<p><img src="decoded.svg" boder="0" alt="[Decoded addresses]"> </p>
<p>It is possible that some addresses are not decoded. Writing to
such an address results data to be lost. Reading of a
non-decoded address results random value. Pullup or pulldown
resistors can be applied to data bus lines to provide a specific
value for read operations. </p>
<p>As it shown above, it is also possible that some cells of a chip is not
mapped to any address. </p>
<h3><a name="shared_chips">Mixed address spaces (shared chips)</a></h3>
Decoder connects an address of an address space to a cell of a
memory chip. Only one cell can be connected to each addresses but
same cell can be connected to more than one address spaces. This
is done by routing different control lines to the same chip
through logic <b>L</b>:
<p><img src="share-chip.svg" alt="[Sharing memchip]" border="0"> </p>
<p>Because each cell of a memory chip uses same read/write
control, in real world it is not possible to share individual
cells of a chip between address spaces. In µCsim simulator we
can define as many address decoders as we want so it is possible
to map any cell to any address. </p>
<h3><a name="banking">Memory banking</a></h3>
<p>Memory banking (or bank-switching) is a method to extend amount
of memory accessible by the CPU. Full amount of the memory which
is available for the CPU at a time is limited by the size of the
address space and can not be enlarged. But the address decoder can
dynamically change the map between some part of addresses and
memory chips. Dynamically mapped part of the address space becomes
<i>banked</i> this way. Banked addresses can be mapped to
different memory chips (or different part of a bigger chip)
according to an extra information called bank
selection. Selection is stored in a register and writable by the
software. Selector register should be at an address which is
non-banked. Selection is defined by a binary coded data, and
size of this data determines how many banks available behind the
banked addresses. Banks can store either code or data but using
them need support by the compiler.
</p>
<p>Banks in separate chips:</p>
<p><img src="bank_multichip.svg" alt="[Banks in multi chips]" border="0"></p>
<p>Banks in a single chip:</p>
<p><img src="bank_bigchip.svg" alt="[Banks in big chip]" border="0"></p>
<h3><a name="banding">Bit banding</a></h3>
<p>Banding...</p>
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