diff options
| author | Andrew Morton <akpm@osdl.org> | 2004-05-19 02:35:27 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@ppc970.osdl.org> | 2004-05-19 02:35:27 -0700 |
| commit | 897d49be87feb06747a3538e7fbf16cdcd349b75 (patch) | |
| tree | 7c67e19e472883d73cada84c1cd5d82362cb3f64 | |
| parent | 6fa1d901d520c1414a1cb3386bbaf0c51a445e20 (diff) | |
[PATCH] slab: enable runtime cache line size on i386
From: Manfred Spraul <manfred@colorfullife.com>
the attached patch switches the SLAB_HWCACHE_ALIGN alignment from the
compile time L1 cache line size to the runtime detected value for i386.
x86-64 already uses the runtime detection.
| -rw-r--r-- | include/asm-i386/processor.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/include/asm-i386/processor.h b/include/asm-i386/processor.h index bab235068f91..9d49ea237f30 100644 --- a/include/asm-i386/processor.h +++ b/include/asm-i386/processor.h @@ -649,6 +649,8 @@ extern inline void prefetchw(const void *x) extern void select_idle_routine(const struct cpuinfo_x86 *c); +#define cache_line_size() (boot_cpu_data.x86_cache_alignment) + #ifdef CONFIG_SCHED_SMT #define ARCH_HAS_SCHED_DOMAIN #define ARCH_HAS_SCHED_WAKE_IDLE |