diff options
Diffstat (limited to 'Documentation')
648 files changed, 18709 insertions, 5647 deletions
diff --git a/Documentation/ABI/stable/sysfs-block b/Documentation/ABI/stable/sysfs-block index 0ddffc9133d0..0ed10aeff86b 100644 --- a/Documentation/ABI/stable/sysfs-block +++ b/Documentation/ABI/stable/sysfs-block @@ -603,16 +603,10 @@ Date: July 2003 Contact: linux-block@vger.kernel.org Description: [RW] This controls how many requests may be allocated in the - block layer for read or write requests. Note that the total - allocated number may be twice this amount, since it applies only - to reads or writes (not the accumulated sum). - - To avoid priority inversion through request starvation, a - request queue maintains a separate request pool per each cgroup - when CONFIG_BLK_CGROUP is enabled, and this parameter applies to - each such per-block-cgroup request pool. IOW, if there are N - block cgroups, each request queue may have up to N request - pools, each independently regulated by nr_requests. + block layer. Noted this value only represents the quantity for a + single blk_mq_tags instance. The actual number for the entire + device depends on the hardware queue count, whether elevator is + enabled, and whether tags are shared. What: /sys/block/<disk>/queue/nr_zones diff --git a/Documentation/ABI/testing/debugfs-cec-error-inj b/Documentation/ABI/testing/debugfs-cec-error-inj index 8debcb08a3b5..c512f71bba8e 100644 --- a/Documentation/ABI/testing/debugfs-cec-error-inj +++ b/Documentation/ABI/testing/debugfs-cec-error-inj @@ -1,6 +1,6 @@ What: /sys/kernel/debug/cec/*/error-inj Date: March 2018 -Contact: Hans Verkuil <hverkuil-cisco@xs4all.nl> +Contact: Hans Verkuil <hverkuil@kernel.org> Description: The CEC Framework allows for CEC error injection commands through diff --git a/Documentation/ABI/testing/sysfs-bus-event_source-devices-vpa-dtl b/Documentation/ABI/testing/sysfs-bus-event_source-devices-vpa-dtl new file mode 100644 index 000000000000..7b7c789a5cf5 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-bus-event_source-devices-vpa-dtl @@ -0,0 +1,25 @@ +What: /sys/bus/event_source/devices/vpa_dtl/format +Date: February 2025 +Contact: Linux on PowerPC Developer List <linuxppc-dev at lists.ozlabs.org> +Description: Read-only. Attribute group to describe the magic bits + that go into perf_event_attr.config for a particular pmu. + (See ABI/testing/sysfs-bus-event_source-devices-format). + + Each attribute under this group defines a bit range of the + perf_event_attr.config. Supported attribute are listed + below:: + + event = "config:0-7" - event ID + + For example:: + + dtl_cede = "event=0x1" + +What: /sys/bus/event_source/devices/vpa_dtl/events +Date: February 2025 +Contact: Linux on PowerPC Developer List <linuxppc-dev at lists.ozlabs.org> +Description: (RO) Attribute group to describe performance monitoring events + for the Virtual Processor Dispatch Trace Log. Each attribute in + this group describes a single performance monitoring event + supported by vpa_dtl pmu. The name of the file is the name of + the event (See ABI/testing/sysfs-bus-event_source-devices-events). diff --git a/Documentation/ABI/testing/sysfs-class-drm b/Documentation/ABI/testing/sysfs-class-drm new file mode 100644 index 000000000000..d23fed5e29a7 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-class-drm @@ -0,0 +1,8 @@ +What: /sys/class/drm/.../boot_display +Date: January 2026 +Contact: Linux DRI developers <dri-devel@vger.kernel.org> +Description: + This file indicates that displays connected to the device were + used to display the boot sequence. If a display connected to + the device was used to display the boot sequence the file will + be present and contain "1". diff --git a/Documentation/ABI/testing/sysfs-class-power b/Documentation/ABI/testing/sysfs-class-power index 87a058e14e7e..4b21d5d23251 100644 --- a/Documentation/ABI/testing/sysfs-class-power +++ b/Documentation/ABI/testing/sysfs-class-power @@ -553,6 +553,43 @@ Description: Integer > 0: representing full cycles Integer = 0: cycle_count info is not available +What: /sys/class/power_supply/<supply_name>/internal_resistance +Date: August 2025 +Contact: linux-arm-msm@vger.kernel.org +Description: + Represent the battery's internal resistance, often referred + to as Equivalent Series Resistance (ESR). It is a dynamic + parameter that reflects the opposition to current flow within + the cell. It is not a fixed value but varies significantly + based on several operational conditions, including battery + state of charge (SoC), temperature, and whether the battery + is in a charging or discharging state. + + Access: Read + + Valid values: Represented in microohms + +What: /sys/class/power_supply/<supply_name>/state_of_health +Date: August 2025 +Contact: linux-arm-msm@vger.kernel.org +Description: + The state_of_health parameter quantifies the overall condition + of a battery as a percentage, reflecting its ability to deliver + rated performance relative to its original specifications. It is + dynamically computed using a combination of learned capacity + and impedance-based degradation indicators, both of which evolve + over the battery's lifecycle. + Note that the exact algorithms are kept secret by most battery + vendors and the value from different battery vendors cannot be + compared with each other as there is no vendor-agnostic definition + of "performance". Also this usually cannot be used for any + calculations (i.e. this is not the factor between charge_full and + charge_full_design). + + Access: Read + + Valid values: 0 - 100 (percent) + **USB Properties** What: /sys/class/power_supply/<supply_name>/input_current_limit diff --git a/Documentation/ABI/testing/sysfs-devices-power b/Documentation/ABI/testing/sysfs-devices-power index e4ec5de9a5dd..9bf7c8a267c5 100644 --- a/Documentation/ABI/testing/sysfs-devices-power +++ b/Documentation/ABI/testing/sysfs-devices-power @@ -274,15 +274,15 @@ What: /sys/devices/.../power/runtime_active_time Date: Jul 2010 Contact: Arjan van de Ven <arjan@linux.intel.com> Description: - Reports the total time that the device has been active. - Used for runtime PM statistics. + Reports the total time that the device has been active, in + milliseconds. Used for runtime PM statistics. What: /sys/devices/.../power/runtime_suspended_time Date: Jul 2010 Contact: Arjan van de Ven <arjan@linux.intel.com> Description: - Reports total time that the device has been suspended. - Used for runtime PM statistics. + Reports total time that the device has been suspended, in + milliseconds. Used for runtime PM statistics. What: /sys/devices/.../power/runtime_usage Date: Apr 2010 diff --git a/Documentation/ABI/testing/sysfs-devices-system-cpu b/Documentation/ABI/testing/sysfs-devices-system-cpu index ab8cd337f43a..8aed6d94c4cd 100644 --- a/Documentation/ABI/testing/sysfs-devices-system-cpu +++ b/Documentation/ABI/testing/sysfs-devices-system-cpu @@ -586,6 +586,7 @@ What: /sys/devices/system/cpu/vulnerabilities /sys/devices/system/cpu/vulnerabilities/srbds /sys/devices/system/cpu/vulnerabilities/tsa /sys/devices/system/cpu/vulnerabilities/tsx_async_abort + /sys/devices/system/cpu/vulnerabilities/vmscape Date: January 2018 Contact: Linux kernel mailing list <linux-kernel@vger.kernel.org> Description: Information about CPU vulnerabilities diff --git a/Documentation/ABI/testing/sysfs-driver-framer-pef2256 b/Documentation/ABI/testing/sysfs-driver-framer-pef2256 new file mode 100644 index 000000000000..29f97783bf07 --- /dev/null +++ b/Documentation/ABI/testing/sysfs-driver-framer-pef2256 @@ -0,0 +1,8 @@ +What: /sys/bus/platform/devices/xxx/version +Date: Sep 2025 +Contact: netdev@vger.kernel.org +Description: Reports the version of the PEF2256 framer + + Access: Read + + Valid values: Represented as string diff --git a/Documentation/ABI/testing/sysfs-kernel-mm-damon b/Documentation/ABI/testing/sysfs-kernel-mm-damon index 6791d879759e..b6b71db36ca7 100644 --- a/Documentation/ABI/testing/sysfs-kernel-mm-damon +++ b/Documentation/ABI/testing/sysfs-kernel-mm-damon @@ -77,6 +77,13 @@ Description: Writing a keyword for a monitoring operations set ('vaddr' for Note that only the operations sets that listed in 'avail_operations' file are valid inputs. +What: /sys/kernel/mm/damon/admin/kdamonds/<K>/contexts/<C>/addr_unit +Date: Aug 2025 +Contact: SeongJae Park <sj@kernel.org> +Description: Writing an integer to this file sets the 'address unit' + parameter of the given operations set of the context. Reading + the file returns the last-written 'address unit' value. + What: /sys/kernel/mm/damon/admin/kdamonds/<K>/contexts/<C>/monitoring_attrs/intervals/sample_us Date: Mar 2022 Contact: SeongJae Park <sj@kernel.org> diff --git a/Documentation/Makefile b/Documentation/Makefile index b98477df5ddf..820f07e0afe6 100644 --- a/Documentation/Makefile +++ b/Documentation/Makefile @@ -104,22 +104,6 @@ quiet_cmd_sphinx = SPHINX $@ --> file://$(abspath $(BUILDDIR)/$3/$4) cp $(if $(patsubst /%,,$(DOCS_CSS)),$(abspath $(srctree)/$(DOCS_CSS)),$(DOCS_CSS)) $(BUILDDIR)/$3/_static/; \ fi -YNL_INDEX:=$(srctree)/Documentation/networking/netlink_spec/index.rst -YNL_RST_DIR:=$(srctree)/Documentation/networking/netlink_spec -YNL_YAML_DIR:=$(srctree)/Documentation/netlink/specs -YNL_TOOL:=$(srctree)/tools/net/ynl/pyynl/ynl_gen_rst.py - -YNL_RST_FILES_TMP := $(patsubst %.yaml,%.rst,$(wildcard $(YNL_YAML_DIR)/*.yaml)) -YNL_RST_FILES := $(patsubst $(YNL_YAML_DIR)%,$(YNL_RST_DIR)%, $(YNL_RST_FILES_TMP)) - -$(YNL_INDEX): $(YNL_RST_FILES) - $(Q)$(YNL_TOOL) -o $@ -x - -$(YNL_RST_DIR)/%.rst: $(YNL_YAML_DIR)/%.yaml $(YNL_TOOL) - $(Q)$(YNL_TOOL) -i $< -o $@ - -htmldocs texinfodocs latexdocs epubdocs xmldocs: $(YNL_INDEX) - htmldocs: @$(srctree)/scripts/sphinx-pre-install --version-check @+$(foreach var,$(SPHINXDIRS),$(call loop_cmd,sphinx,html,$(var),,$(var))) @@ -186,7 +170,6 @@ refcheckdocs: $(Q)cd $(srctree);scripts/documentation-file-ref-check cleandocs: - $(Q)rm -f $(YNL_INDEX) $(YNL_RST_FILES) $(Q)rm -rf $(BUILDDIR) $(Q)$(MAKE) BUILDDIR=$(abspath $(BUILDDIR)) $(build)=Documentation/userspace-api/media clean diff --git a/Documentation/accel/amdxdna/amdnpu.rst b/Documentation/accel/amdxdna/amdnpu.rst index fbe0a7585345..42e54904f9a8 100644 --- a/Documentation/accel/amdxdna/amdnpu.rst +++ b/Documentation/accel/amdxdna/amdnpu.rst @@ -223,13 +223,13 @@ Userspace components Compiler -------- -Peano is an LLVM based open-source compiler for AMD XDNA Array compute tile -available at: +Peano is an LLVM based open-source single core compiler for AMD XDNA Array +compute tile. Peano is available at: https://github.com/Xilinx/llvm-aie -The open-source IREE compiler supports graph compilation of ML models for AMD -NPU and uses Peano underneath. It is available at: -https://github.com/nod-ai/iree-amd-aie +IRON is an open-source array compiler for AMD XDNA Array based NPU which uses +Peano underneath. IRON is available at: +https://github.com/Xilinx/mlir-aie Usermode Driver (UMD) --------------------- diff --git a/Documentation/accel/index.rst b/Documentation/accel/index.rst index bc85f26533d8..d8fa332d60a8 100644 --- a/Documentation/accel/index.rst +++ b/Documentation/accel/index.rst @@ -10,6 +10,7 @@ Compute Accelerators introduction amdxdna/index qaic/index + rocket/index .. only:: subproject and html diff --git a/Documentation/accel/rocket/index.rst b/Documentation/accel/rocket/index.rst new file mode 100644 index 000000000000..70f97bccf100 --- /dev/null +++ b/Documentation/accel/rocket/index.rst @@ -0,0 +1,19 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +===================================== + accel/rocket Rockchip NPU driver +===================================== + +The accel/rocket driver supports the Neural Processing Units (NPUs) inside some +Rockchip SoCs such as the RK3588. Rockchip calls it RKNN and sometimes RKNPU. + +The hardware is described in chapter 36 in the RK3588 TRM. + +This driver just powers the hardware on and off, allocates and maps buffers to +the device and submits jobs to the frontend unit. Everything else is done in +userspace, as a Gallium driver (also called rocket) that is part of the Mesa3D +project. + +Hardware currently supported: + +* RK3588 diff --git a/Documentation/accounting/delay-accounting.rst b/Documentation/accounting/delay-accounting.rst index 8ccc5af5ea1e..86d7902a657f 100644 --- a/Documentation/accounting/delay-accounting.rst +++ b/Documentation/accounting/delay-accounting.rst @@ -134,47 +134,72 @@ The above command can be used with -v to get more debug information. After the system starts, use `delaytop` to get the system-wide delay information, which includes system-wide PSI information and Top-N high-latency tasks. +Note: PSI support requires `CONFIG_PSI=y` and `psi=1` for full functionality. -`delaytop` supports sorting by CPU latency in descending order by default, -displays the top 20 high-latency tasks by default, and refreshes the latency -data every 2 seconds by default. +`delaytop` is an interactive tool for monitoring system pressure and task delays. +It supports multiple sorting options, display modes, and real-time keyboard controls. -Get PSI information and Top-N tasks delay, since system boot:: +Basic usage with default settings (sorts by CPU delay, shows top 20 tasks, refreshes every 2 seconds):: bash# ./delaytop - System Pressure Information: (avg10/avg60/avg300/total) - CPU some: 0.0%/ 0.0%/ 0.0%/ 345(ms) + System Pressure Information: (avg10/avg60vg300/total) + CPU some: 0.0%/ 0.0%/ 0.0%/ 106137(ms) CPU full: 0.0%/ 0.0%/ 0.0%/ 0(ms) Memory full: 0.0%/ 0.0%/ 0.0%/ 0(ms) Memory some: 0.0%/ 0.0%/ 0.0%/ 0(ms) - IO full: 0.0%/ 0.0%/ 0.0%/ 65(ms) - IO some: 0.0%/ 0.0%/ 0.0%/ 79(ms) + IO full: 0.0%/ 0.0%/ 0.0%/ 2240(ms) + IO some: 0.0%/ 0.0%/ 0.0%/ 2783(ms) IRQ full: 0.0%/ 0.0%/ 0.0%/ 0(ms) - Top 20 processes (sorted by CPU delay): - PID TGID COMMAND CPU(ms) IO(ms) SWAP(ms) RCL(ms) THR(ms) CMP(ms) WP(ms) IRQ(ms) - ---------------------------------------------------------------------------------------------- - 161 161 zombie_memcg_re 1.40 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 130 130 blkcg_punt_bio 1.37 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 444 444 scsi_tmf_0 0.73 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 1280 1280 rsyslogd 0.53 0.04 0.00 0.00 0.00 0.00 0.00 0.00 - 12 12 ksoftirqd/0 0.47 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 1277 1277 nbd-server 0.44 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 308 308 kworker/2:2-sys 0.41 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 55 55 netns 0.36 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 1187 1187 acpid 0.31 0.03 0.00 0.00 0.00 0.00 0.00 0.00 - 6184 6184 kworker/1:2-sys 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 186 186 kaluad 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 18 18 ksoftirqd/1 0.24 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 185 185 kmpath_rdacd 0.23 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 190 190 kstrp 0.23 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 2759 2759 agetty 0.20 0.03 0.00 0.00 0.00 0.00 0.00 0.00 - 1190 1190 kworker/0:3-sys 0.19 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 1272 1272 sshd 0.15 0.04 0.00 0.00 0.00 0.00 0.00 0.00 - 1156 1156 license 0.15 0.11 0.00 0.00 0.00 0.00 0.00 0.00 - 134 134 md 0.13 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - 6142 6142 kworker/3:2-xfs 0.13 0.00 0.00 0.00 0.00 0.00 0.00 0.00 - -Dynamic interactive interface of delaytop:: + [o]sort [M]memverbose [q]quit + Top 20 processes (sorted by cpu delay): + PID TGID COMMAND CPU(ms) IO(ms) IRQ(ms) MEM(ms) + ------------------------------------------------------------------------ + 110 110 kworker/15:0H-s 27.91 0.00 0.00 0.00 + 57 57 cpuhp/7 3.18 0.00 0.00 0.00 + 99 99 cpuhp/14 2.97 0.00 0.00 0.00 + 51 51 cpuhp/6 0.90 0.00 0.00 0.00 + 44 44 kworker/4:0H-sy 0.80 0.00 0.00 0.00 + 60 60 ksoftirqd/7 0.74 0.00 0.00 0.00 + 76 76 idle_inject/10 0.31 0.00 0.00 0.00 + 100 100 idle_inject/14 0.30 0.00 0.00 0.00 + 1309 1309 systemsettings 0.29 0.00 0.00 0.00 + 45 45 cpuhp/5 0.22 0.00 0.00 0.00 + 63 63 cpuhp/8 0.20 0.00 0.00 0.00 + 87 87 cpuhp/12 0.18 0.00 0.00 0.00 + 93 93 cpuhp/13 0.17 0.00 0.00 0.00 + 1265 1265 acpid 0.17 0.00 0.00 0.00 + 1552 1552 sshd 0.17 0.00 0.00 0.00 + 2584 2584 sddm-helper 0.16 0.00 0.00 0.00 + 1284 1284 rtkit-daemon 0.15 0.00 0.00 0.00 + 1326 1326 nde-netfilter 0.14 0.00 0.00 0.00 + 27 27 cpuhp/2 0.13 0.00 0.00 0.00 + 631 631 kworker/11:2-rc 0.11 0.00 0.00 0.00 + +Interactive keyboard controls during runtime:: + + o - Select sort field (CPU, IO, IRQ, Memory, etc.) + M - Toggle display mode (Default/Memory Verbose) + q - Quit + +Available sort fields(use -s/--sort or interactive command):: + + cpu(c) - CPU delay + blkio(i) - I/O delay + irq(q) - IRQ delay + mem(m) - Total memory delay + swapin(s) - Swapin delay (memory verbose mode only) + freepages(r) - Freepages reclaim delay (memory verbose mode only) + thrashing(t) - Thrashing delay (memory verbose mode only) + compact(p) - Compaction delay (memory verbose mode only) + wpcopy(w) - Write page copy delay (memory verbose mode only) + +Advanced usage examples:: + + # ./delaytop -s blkio + Sorted by IO delay + + # ./delaytop -s mem -M + Sorted by memory delay in memory verbose mode # ./delaytop -p pid Print delayacct stats diff --git a/Documentation/admin-guide/bug-hunting.rst b/Documentation/admin-guide/bug-hunting.rst index 30858757c9f2..7da0504388ec 100644 --- a/Documentation/admin-guide/bug-hunting.rst +++ b/Documentation/admin-guide/bug-hunting.rst @@ -252,7 +252,7 @@ For example, if you find a bug at the gspca's sonixj.c file, you can get its maintainers with:: $ ./scripts/get_maintainer.pl --bug -f drivers/media/usb/gspca/sonixj.c - Hans Verkuil <hverkuil@xs4all.nl> (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) + Hans Verkuil <hverkuil@kernel.org> (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) Mauro Carvalho Chehab <mchehab@kernel.org> (maintainer:MEDIA INPUT INFRASTRUCTURE (V4L/DVB),commit_signer:1/1=100%) Tejun Heo <tj@kernel.org> (commit_signer:1/1=100%) Bhaktipriya Shridhar <bhaktipriya96@gmail.com> (commit_signer:1/1=100%,authored:1/1=100%,added_lines:4/4=100%,removed_lines:9/9=100%) diff --git a/Documentation/admin-guide/cgroup-v2.rst b/Documentation/admin-guide/cgroup-v2.rst index 51c0bc4c2dc5..0e6c67ac585a 100644 --- a/Documentation/admin-guide/cgroup-v2.rst +++ b/Documentation/admin-guide/cgroup-v2.rst @@ -15,6 +15,9 @@ v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgrou .. CONTENTS + [Whenever any new section is added to this document, please also add + an entry here.] + 1. Introduction 1-1. Terminology 1-2. What is cgroup? @@ -25,9 +28,10 @@ v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgrou 2-2-2. Threads 2-3. [Un]populated Notification 2-4. Controlling Controllers - 2-4-1. Enabling and Disabling - 2-4-2. Top-down Constraint - 2-4-3. No Internal Process Constraint + 2-4-1. Availability + 2-4-2. Enabling and Disabling + 2-4-3. Top-down Constraint + 2-4-4. No Internal Process Constraint 2-5. Delegation 2-5-1. Model of Delegation 2-5-2. Delegation Containment @@ -61,14 +65,15 @@ v1 is available under :ref:`Documentation/admin-guide/cgroup-v1/index.rst <cgrou 5-4-1. PID Interface Files 5-5. Cpuset 5.5-1. Cpuset Interface Files - 5-6. Device + 5-6. Device controller 5-7. RDMA 5-7-1. RDMA Interface Files 5-8. DMEM + 5-8-1. DMEM Interface Files 5-9. HugeTLB 5.9-1. HugeTLB Interface Files 5-10. Misc - 5.10-1 Miscellaneous cgroup Interface Files + 5.10-1 Misc Interface Files 5.10-2 Migration and Ownership 5-11. Others 5-11-1. perf_event @@ -1001,6 +1006,24 @@ All cgroup core files are prefixed with "cgroup." Total number of dying cgroup subsystems (e.g. memory cgroup) at and beneath the current cgroup. + cgroup.stat.local + A read-only flat-keyed file which exists in non-root cgroups. + The following entry is defined: + + frozen_usec + Cumulative time that this cgroup has spent between freezing and + thawing, regardless of whether by self or ancestor groups. + NB: (not) reaching "frozen" state is not accounted here. + + Using the following ASCII representation of a cgroup's freezer + state, :: + + 1 _____ + frozen 0 __/ \__ + ab cd + + the duration being measured is the span between a and c. + cgroup.freeze A read-write single value file which exists on non-root cgroups. Allowed values are "0" and "1". The default is "0". diff --git a/Documentation/admin-guide/hw-vuln/attack_vector_controls.rst b/Documentation/admin-guide/hw-vuln/attack_vector_controls.rst index 6dd0800146f6..d0bdbd81dcf9 100644 --- a/Documentation/admin-guide/hw-vuln/attack_vector_controls.rst +++ b/Documentation/admin-guide/hw-vuln/attack_vector_controls.rst @@ -215,9 +215,10 @@ Spectre_v2 X X Spectre_v2_user X X * (Note 1) SRBDS X X X X SRSO X X X X -SSB (Note 4) +SSB X TAA X X X X * (Note 2) TSA X X X X +VMSCAPE X =============== ============== ============ ============= ============== ============ ======== Notes: @@ -229,9 +230,6 @@ Notes: 3 -- Disables SMT if cross-thread mitigations are fully enabled, the CPU is vulnerable, and STIBP is not supported - 4 -- Speculative store bypass is always enabled by default (no kernel - mitigation applied) unless overridden with spec_store_bypass_disable option - When an attack-vector is disabled, all mitigations for the vulnerabilities listed in the above table are disabled, unless mitigation is required for a different enabled attack-vector or a mitigation is explicitly selected via a diff --git a/Documentation/admin-guide/hw-vuln/index.rst b/Documentation/admin-guide/hw-vuln/index.rst index 89ca636081b7..55d747511f83 100644 --- a/Documentation/admin-guide/hw-vuln/index.rst +++ b/Documentation/admin-guide/hw-vuln/index.rst @@ -26,3 +26,4 @@ are configurable at compile, boot or run time. rsb old_microcode indirect-target-selection + vmscape diff --git a/Documentation/admin-guide/hw-vuln/vmscape.rst b/Documentation/admin-guide/hw-vuln/vmscape.rst new file mode 100644 index 000000000000..d9b9a2b6c114 --- /dev/null +++ b/Documentation/admin-guide/hw-vuln/vmscape.rst @@ -0,0 +1,110 @@ +.. SPDX-License-Identifier: GPL-2.0 + +VMSCAPE +======= + +VMSCAPE is a vulnerability that may allow a guest to influence the branch +prediction in host userspace. It particularly affects hypervisors like QEMU. + +Even if a hypervisor may not have any sensitive data like disk encryption keys, +guest-userspace may be able to attack the guest-kernel using the hypervisor as +a confused deputy. + +Affected processors +------------------- + +The following CPU families are affected by VMSCAPE: + +**Intel processors:** + - Skylake generation (Parts without Enhanced-IBRS) + - Cascade Lake generation - (Parts affected by ITS guest/host separation) + - Alder Lake and newer (Parts affected by BHI) + +Note that, BHI affected parts that use BHB clearing software mitigation e.g. +Icelake are not vulnerable to VMSCAPE. + +**AMD processors:** + - Zen series (families 0x17, 0x19, 0x1a) + +** Hygon processors:** + - Family 0x18 + +Mitigation +---------- + +Conditional IBPB +---------------- + +Kernel tracks when a CPU has run a potentially malicious guest and issues an +IBPB before the first exit to userspace after VM-exit. If userspace did not run +between VM-exit and the next VM-entry, no IBPB is issued. + +Note that the existing userspace mitigation against Spectre-v2 is effective in +protecting the userspace. They are insufficient to protect the userspace VMMs +from a malicious guest. This is because Spectre-v2 mitigations are applied at +context switch time, while the userspace VMM can run after a VM-exit without a +context switch. + +Vulnerability enumeration and mitigation is not applied inside a guest. This is +because nested hypervisors should already be deploying IBPB to isolate +themselves from nested guests. + +SMT considerations +------------------ + +When Simultaneous Multi-Threading (SMT) is enabled, hypervisors can be +vulnerable to cross-thread attacks. For complete protection against VMSCAPE +attacks in SMT environments, STIBP should be enabled. + +The kernel will issue a warning if SMT is enabled without adequate STIBP +protection. Warning is not issued when: + +- SMT is disabled +- STIBP is enabled system-wide +- Intel eIBRS is enabled (which implies STIBP protection) + +System information and options +------------------------------ + +The sysfs file showing VMSCAPE mitigation status is: + + /sys/devices/system/cpu/vulnerabilities/vmscape + +The possible values in this file are: + + * 'Not affected': + + The processor is not vulnerable to VMSCAPE attacks. + + * 'Vulnerable': + + The processor is vulnerable and no mitigation has been applied. + + * 'Mitigation: IBPB before exit to userspace': + + Conditional IBPB mitigation is enabled. The kernel tracks when a CPU has + run a potentially malicious guest and issues an IBPB before the first + exit to userspace after VM-exit. + + * 'Mitigation: IBPB on VMEXIT': + + IBPB is issued on every VM-exit. This occurs when other mitigations like + RETBLEED or SRSO are already issuing IBPB on VM-exit. + +Mitigation control on the kernel command line +---------------------------------------------- + +The mitigation can be controlled via the ``vmscape=`` command line parameter: + + * ``vmscape=off``: + + Disable the VMSCAPE mitigation. + + * ``vmscape=ibpb``: + + Enable conditional IBPB mitigation (default when CONFIG_MITIGATION_VMSCAPE=y). + + * ``vmscape=force``: + + Force vulnerability detection and mitigation even on processors that are + not known to be affected. diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt index 747a55abf494..74ca438d2d6d 100644 --- a/Documentation/admin-guide/kernel-parameters.txt +++ b/Documentation/admin-guide/kernel-parameters.txt @@ -2606,6 +2606,11 @@ for it. Intended to get systems with badly broken firmware running. + irqhandler.duration_warn_us= [KNL] + Warn if an IRQ handler exceeds the specified duration + threshold in microseconds. Useful for identifying + long-running IRQs in the system. + irqpoll [HW] When an interrupt is not handled search all handlers for it. Also check all handlers each timer @@ -3767,8 +3772,16 @@ mga= [HW,DRM] - microcode.force_minrev= [X86] - Format: <bool> + microcode= [X86] Control the behavior of the microcode loader. + Available options, comma separated: + + base_rev=X - with <X> with format: <u32> + Set the base microcode revision of each thread when in + debug mode. + + dis_ucode_ldr: disable the microcode loader + + force_minrev: Enable or disable the microcode minimal revision enforcement for the runtime microcode loader. @@ -3829,6 +3842,7 @@ srbds=off [X86,INTEL] ssbd=force-off [ARM64] tsx_async_abort=off [X86] + vmscape=off [X86] Exceptions: This does not have any effect on @@ -4589,7 +4603,7 @@ bit 2: print timer info bit 3: print locks info if CONFIG_LOCKDEP is on bit 4: print ftrace buffer - bit 5: replay all messages on consoles at the end of panic + bit 5: replay all kernel messages on consoles at the end of panic bit 6: print all CPUs backtrace (if available in the arch) bit 7: print only tasks in uninterruptible (blocked) state *Be aware* that this option may print a _lot_ of lines, @@ -6154,7 +6168,7 @@ rdt= [HW,X86,RDT] Turn on/off individual RDT features. List is: cmt, mbmtotal, mbmlocal, l3cat, l3cdp, l2cat, l2cdp, - mba, smba, bmec. + mba, smba, bmec, abmc. E.g. to turn on cmt and turn off mba use: rdt=cmt,!mba @@ -6405,8 +6419,9 @@ rodata= [KNL,EARLY] on Mark read-only kernel memory as read-only (default). off Leave read-only kernel memory writable for debugging. - full Mark read-only kernel memory and aliases as read-only - [arm64] + noalias Mark read-only kernel memory as read-only but retain + writable aliases in the direct map for regions outside + of the kernel image. [arm64] rockchip.usb_uart [EARLY] @@ -6428,6 +6443,9 @@ rootflags= [KNL] Set root filesystem mount option string + initramfs_options= [KNL] + Specify mount options for for the initramfs mount. + rootfstype= [KNL] Set root filesystem type rootwait [KNL] Wait (indefinitely) for root device to show up. @@ -8041,6 +8059,16 @@ vmpoff= [KNL,S390] Perform z/VM CP command after power off. Format: <command> + vmscape= [X86] Controls mitigation for VMscape attacks. + VMscape attacks can leak information from a userspace + hypervisor to a guest via speculative side-channels. + + off - disable the mitigation + ibpb - use Indirect Branch Prediction Barrier + (IBPB) mitigation (default) + force - force vulnerability detection even on + unaffected processors + vsyscall= [X86-64,EARLY] Controls the behavior of vsyscalls (i.e. calls to fixed addresses of 0xffffffffff600x00 from legacy diff --git a/Documentation/admin-guide/laptops/lg-laptop.rst b/Documentation/admin-guide/laptops/lg-laptop.rst index 67fd6932cef4..c4dd534f91ed 100644 --- a/Documentation/admin-guide/laptops/lg-laptop.rst +++ b/Documentation/admin-guide/laptops/lg-laptop.rst @@ -48,8 +48,8 @@ This value is reset to 100 when the kernel boots. Fan mode -------- -Writing 1/0 to /sys/devices/platform/lg-laptop/fan_mode disables/enables -the fan silent mode. +Writing 0/1/2 to /sys/devices/platform/lg-laptop/fan_mode sets fan mode to +Optimal/Silent/Performance respectively. USB charge diff --git a/Documentation/admin-guide/md.rst b/Documentation/admin-guide/md.rst index 4ff2cc291d18..1c2eacc94758 100644 --- a/Documentation/admin-guide/md.rst +++ b/Documentation/admin-guide/md.rst @@ -347,6 +347,54 @@ All md devices contain: active-idle like active, but no writes have been seen for a while (safe_mode_delay). + consistency_policy + This indicates how the array maintains consistency in case of unexpected + shutdown. It can be: + + none + Array has no redundancy information, e.g. raid0, linear. + + resync + Full resync is performed and all redundancy is regenerated when the + array is started after unclean shutdown. + + bitmap + Resync assisted by a write-intent bitmap. + + journal + For raid4/5/6, journal device is used to log transactions and replay + after unclean shutdown. + + ppl + For raid5 only, Partial Parity Log is used to close the write hole and + eliminate resync. + + The accepted values when writing to this file are ``ppl`` and ``resync``, + used to enable and disable PPL. + + uuid + This indicates the UUID of the array in the following format: + xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx + + bitmap_type + [RW] When read, this file will display the current and available + bitmap for this array. The currently active bitmap will be enclosed + in [] brackets. Writing an bitmap name or ID to this file will switch + control of this array to that new bitmap. Note that writing a new + bitmap for created array is forbidden. + + none + No bitmap + bitmap + The default internal bitmap + llbitmap + The lockless internal bitmap + +If bitmap_type is not none, then additional bitmap attributes bitmap/xxx or +llbitmap/xxx will be created after md device KOBJ_CHANGE event. + +If bitmap_type is bitmap, then the md device will also contain: + bitmap/location This indicates where the write-intent bitmap for the array is stored. @@ -401,35 +449,23 @@ All md devices contain: once the array becomes non-degraded, and this fact has been recorded in the metadata. - consistency_policy - This indicates how the array maintains consistency in case of unexpected - shutdown. It can be: - - none - Array has no redundancy information, e.g. raid0, linear. - - resync - Full resync is performed and all redundancy is regenerated when the - array is started after unclean shutdown. - - bitmap - Resync assisted by a write-intent bitmap. +If bitmap_type is llbitmap, then the md device will also contain: - journal - For raid4/5/6, journal device is used to log transactions and replay - after unclean shutdown. + llbitmap/bits + This is read-only, show status of bitmap bits, the number of each + value. - ppl - For raid5 only, Partial Parity Log is used to close the write hole and - eliminate resync. - - The accepted values when writing to this file are ``ppl`` and ``resync``, - used to enable and disable PPL. + llbitmap/metadata + This is read-only, show bitmap metadata, include chunksize, chunkshift, + chunks, offset and daemon_sleep. - uuid - This indicates the UUID of the array in the following format: - xxxxxxxx-xxxx-xxxx-xxxx-xxxxxxxxxxxx + llbitmap/daemon_sleep + This is read-write, time in seconds that daemon function will be + triggered to clear dirty bits. + llbitmap/barrier_idle + This is read-write, time in seconds that page barrier will be idled, + means dirty bits in the page will be cleared. As component devices are added to an md array, they appear in the ``md`` directory as new directories named:: diff --git a/Documentation/admin-guide/media/i2c-cardlist.rst b/Documentation/admin-guide/media/i2c-cardlist.rst index 1825a0bb47bd..fff962558cd5 100644 --- a/Documentation/admin-guide/media/i2c-cardlist.rst +++ b/Documentation/admin-guide/media/i2c-cardlist.rst @@ -91,7 +91,6 @@ ov5647 OmniVision OV5647 sensor ov5670 OmniVision OV5670 sensor ov5675 OmniVision OV5675 sensor ov5695 OmniVision OV5695 sensor -ov6650 OmniVision OV6650 sensor ov7251 OmniVision OV7251 sensor ov7640 OmniVision OV7640 sensor ov7670 OmniVision OV7670 sensor diff --git a/Documentation/admin-guide/media/ivtv.rst b/Documentation/admin-guide/media/ivtv.rst index 101f16d0263e..8b65ac3f5321 100644 --- a/Documentation/admin-guide/media/ivtv.rst +++ b/Documentation/admin-guide/media/ivtv.rst @@ -3,7 +3,7 @@ The ivtv driver =============== -Author: Hans Verkuil <hverkuil@xs4all.nl> +Author: Hans Verkuil <hverkuil@kernel.org> This is a v4l2 device driver for the Conexant cx23415/6 MPEG encoder/decoder. The cx23415 can do both encoding and decoding, the cx23416 can only do MPEG diff --git a/Documentation/admin-guide/mm/damon/start.rst b/Documentation/admin-guide/mm/damon/start.rst index ede14b679d02..ec8c34b2d32f 100644 --- a/Documentation/admin-guide/mm/damon/start.rst +++ b/Documentation/admin-guide/mm/damon/start.rst @@ -175,4 +175,4 @@ Below command makes every memory region of size >=4K that has not accessed for $ sudo damo start --damos_access_rate 0 0 --damos_sz_region 4K max \ --damos_age 60s max --damos_action pageout \ - <pid of your workload> + --target_pid <pid of your workload> diff --git a/Documentation/admin-guide/mm/damon/usage.rst b/Documentation/admin-guide/mm/damon/usage.rst index ff3a2dda1f02..2cae60b6f3ca 100644 --- a/Documentation/admin-guide/mm/damon/usage.rst +++ b/Documentation/admin-guide/mm/damon/usage.rst @@ -61,7 +61,7 @@ comma (","). │ :ref:`kdamonds <sysfs_kdamonds>`/nr_kdamonds │ │ :ref:`0 <sysfs_kdamond>`/state,pid,refresh_ms │ │ │ :ref:`contexts <sysfs_contexts>`/nr_contexts - │ │ │ │ :ref:`0 <sysfs_context>`/avail_operations,operations + │ │ │ │ :ref:`0 <sysfs_context>`/avail_operations,operations,addr_unit │ │ │ │ │ :ref:`monitoring_attrs <sysfs_monitoring_attrs>`/ │ │ │ │ │ │ intervals/sample_us,aggr_us,update_us │ │ │ │ │ │ │ intervals_goal/access_bp,aggrs,min_sample_us,max_sample_us @@ -188,9 +188,9 @@ details). At the moment, only one context per kdamond is supported, so only contexts/<N>/ ------------- -In each context directory, two files (``avail_operations`` and ``operations``) -and three directories (``monitoring_attrs``, ``targets``, and ``schemes``) -exist. +In each context directory, three files (``avail_operations``, ``operations`` +and ``addr_unit``) and three directories (``monitoring_attrs``, ``targets``, +and ``schemes``) exist. DAMON supports multiple types of :ref:`monitoring operations <damon_design_configurable_operations_set>`, including those for virtual address @@ -205,6 +205,9 @@ You can set and get what type of monitoring operations DAMON will use for the context by writing one of the keywords listed in ``avail_operations`` file and reading from the ``operations`` file. +``addr_unit`` file is for setting and getting the :ref:`address unit +<damon_design_addr_unit>` parameter of the operations set. + .. _sysfs_monitoring_attrs: contexts/<N>/monitoring_attrs/ diff --git a/Documentation/admin-guide/mm/transhuge.rst b/Documentation/admin-guide/mm/transhuge.rst index 370fba113460..1654211cc6cf 100644 --- a/Documentation/admin-guide/mm/transhuge.rst +++ b/Documentation/admin-guide/mm/transhuge.rst @@ -225,6 +225,42 @@ to "always" or "madvise"), and it'll be automatically shutdown when PMD-sized THP is disabled (when both the per-size anon control and the top-level control are "never") +process THP controls +-------------------- + +A process can control its own THP behaviour using the ``PR_SET_THP_DISABLE`` +and ``PR_GET_THP_DISABLE`` pair of prctl(2) calls. The THP behaviour set using +``PR_SET_THP_DISABLE`` is inherited across fork(2) and execve(2). These calls +support the following arguments:: + + prctl(PR_SET_THP_DISABLE, 1, 0, 0, 0): + This will disable THPs completely for the process, irrespective + of global THP controls or madvise(..., MADV_COLLAPSE) being used. + + prctl(PR_SET_THP_DISABLE, 1, PR_THP_DISABLE_EXCEPT_ADVISED, 0, 0): + This will disable THPs for the process except when the usage of THPs is + advised. Consequently, THPs will only be used when: + - Global THP controls are set to "always" or "madvise" and + madvise(..., MADV_HUGEPAGE) or madvise(..., MADV_COLLAPSE) is used. + - Global THP controls are set to "never" and madvise(..., MADV_COLLAPSE) + is used. This is the same behavior as if THPs would not be disabled on + a process level. + Note that MADV_COLLAPSE is currently always rejected if + madvise(..., MADV_NOHUGEPAGE) is set on an area. + + prctl(PR_SET_THP_DISABLE, 0, 0, 0, 0): + This will re-enable THPs for the process, as if they were never disabled. + Whether THPs will actually be used depends on global THP controls and + madvise() calls. + + prctl(PR_GET_THP_DISABLE, 0, 0, 0, 0): + This returns a value whose bits indicate how THP-disable is configured: + Bits + 1 0 Value Description + |0|0| 0 No THP-disable behaviour specified. + |0|1| 1 THP is entirely disabled for this process. + |1|1| 3 THP-except-advised mode is set for this process. + Khugepaged controls ------------------- @@ -383,6 +419,8 @@ option: ``huge=``. It can have following values: always Attempt to allocate huge pages every time we need a new page; + Always try PMD-sized huge pages first, and fall back to smaller-sized + huge pages if the PMD-sized huge page allocation fails; never Do not allocate huge pages. Note that ``madvise(..., MADV_COLLAPSE)`` @@ -390,7 +428,9 @@ never is specified everywhere; within_size - Only allocate huge page if it will be fully within i_size. + Only allocate huge page if it will be fully within i_size; + Always try PMD-sized huge pages first, and fall back to smaller-sized + huge pages if the PMD-sized huge page allocation fails; Also respect madvise() hints; advise diff --git a/Documentation/admin-guide/mm/zswap.rst b/Documentation/admin-guide/mm/zswap.rst index fd3370aa43fe..283d77217c6f 100644 --- a/Documentation/admin-guide/mm/zswap.rst +++ b/Documentation/admin-guide/mm/zswap.rst @@ -53,26 +53,17 @@ Zswap receives pages for compression from the swap subsystem and is able to evict pages from its own compressed pool on an LRU basis and write them back to the backing swap device in the case that the compressed pool is full. -Zswap makes use of zpool for the managing the compressed memory pool. Each -allocation in zpool is not directly accessible by address. Rather, a handle is +Zswap makes use of zsmalloc for the managing the compressed memory pool. Each +allocation in zsmalloc is not directly accessible by address. Rather, a handle is returned by the allocation routine and that handle must be mapped before being accessed. The compressed memory pool grows on demand and shrinks as compressed -pages are freed. The pool is not preallocated. By default, a zpool -of type selected in ``CONFIG_ZSWAP_ZPOOL_DEFAULT`` Kconfig option is created, -but it can be overridden at boot time by setting the ``zpool`` attribute, -e.g. ``zswap.zpool=zsmalloc``. It can also be changed at runtime using the sysfs -``zpool`` attribute, e.g.:: - - echo zsmalloc > /sys/module/zswap/parameters/zpool - -The zsmalloc type zpool has a complex compressed page storage method, and it -can achieve great storage densities. +pages are freed. The pool is not preallocated. When a swap page is passed from swapout to zswap, zswap maintains a mapping -of the swap entry, a combination of the swap type and swap offset, to the zpool -handle that references that compressed swap page. This mapping is achieved -with a red-black tree per swap type. The swap offset is the search key for the -tree nodes. +of the swap entry, a combination of the swap type and swap offset, to the +zsmalloc handle that references that compressed swap page. This mapping is +achieved with a red-black tree per swap type. The swap offset is the search +key for the tree nodes. During a page fault on a PTE that is a swap entry, the swapin code calls the zswap load function to decompress the page into the page allocated by the page @@ -96,11 +87,11 @@ attribute, e.g.:: echo lzo > /sys/module/zswap/parameters/compressor -When the zpool and/or compressor parameter is changed at runtime, any existing -compressed pages are not modified; they are left in their own zpool. When a -request is made for a page in an old zpool, it is uncompressed using its -original compressor. Once all pages are removed from an old zpool, the zpool -and its compressor are freed. +When the compressor parameter is changed at runtime, any existing compressed +pages are not modified; they are left in their own pool. When a request is +made for a page in an old pool, it is uncompressed using its original +compressor. Once all pages are removed from an old pool, the pool and its +compressor are freed. Some of the pages in zswap are same-value filled pages (i.e. contents of the page have same value or repetitive pattern). These pages include zero-filled diff --git a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst index cb376f335f40..167f9281fbf5 100644 --- a/Documentation/admin-guide/perf/dwc_pcie_pmu.rst +++ b/Documentation/admin-guide/perf/dwc_pcie_pmu.rst @@ -16,8 +16,8 @@ provides the following two features: - one 64-bit counter for Time Based Analysis (RX/TX data throughput and time spent in each low-power LTSSM state) and -- one 32-bit counter for Event Counting (error and non-error events for - a specified lane) +- one 32-bit counter per event for Event Counting (error and non-error + events for a specified lane) Note: There is no interrupt for counter overflow. diff --git a/Documentation/admin-guide/perf/fujitsu_uncore_pmu.rst b/Documentation/admin-guide/perf/fujitsu_uncore_pmu.rst new file mode 100644 index 000000000000..46595b788d3a --- /dev/null +++ b/Documentation/admin-guide/perf/fujitsu_uncore_pmu.rst @@ -0,0 +1,110 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +================================================ +Fujitsu Uncore Performance Monitoring Unit (PMU) +================================================ + +This driver supports the Uncore MAC PMUs and the Uncore PCI PMUs found +in Fujitsu chips. +Each MAC PMU on these chips is exposed as a uncore perf PMU with device name +mac_iod<iod>_mac<mac>_ch<ch>. +And each PCI PMU on these chips is exposed as a uncore perf PMU with device name +pci_iod<iod>_pci<pci>. + +The driver provides a description of its available events and configuration +options in sysfs, see /sys/bus/event_sources/devices/mac_iod<iod>_mac<mac>_ch<ch>/ +and /sys/bus/event_sources/devices/pci_iod<iod>_pci<pci>/. +This driver exports: +- formats, used by perf user space and other tools to configure events +- events, used by perf user space and other tools to create events + symbolically, e.g.: + perf stat -a -e mac_iod0_mac0_ch0/event=0x21/ ls + perf stat -a -e pci_iod0_pci0/event=0x24/ ls +- cpumask, used by perf user space and other tools to know on which CPUs + to open the events + +This driver supports the following events for MAC: +- cycles + This event counts MAC cycles at MAC frequency. +- read-count + This event counts the number of read requests to MAC. +- read-count-request + This event counts the number of read requests including retry to MAC. +- read-count-return + This event counts the number of responses to read requests to MAC. +- read-count-request-pftgt + This event counts the number of read requests including retry with PFTGT + flag. +- read-count-request-normal + This event counts the number of read requests including retry without PFTGT + flag. +- read-count-return-pftgt-hit + This event counts the number of responses to read requests which hit the + PFTGT buffer. +- read-count-return-pftgt-miss + This event counts the number of responses to read requests which miss the + PFTGT buffer. +- read-wait + This event counts outstanding read requests issued by DDR memory controller + per cycle. +- write-count + This event counts the number of write requests to MAC (including zero write, + full write, partial write, write cancel). +- write-count-write + This event counts the number of full write requests to MAC (not including + zero write). +- write-count-pwrite + This event counts the number of partial write requests to MAC. +- memory-read-count + This event counts the number of read requests from MAC to memory. +- memory-write-count + This event counts the number of full write requests from MAC to memory. +- memory-pwrite-count + This event counts the number of partial write requests from MAC to memory. +- ea-mac + This event counts energy consumption of MAC. +- ea-memory + This event counts energy consumption of memory. +- ea-memory-mac-write + This event counts the number of write requests from MAC to memory. +- ea-ha + This event counts energy consumption of HA. + + 'ea' is the abbreviation for 'Energy Analyzer'. + +Examples for use with perf:: + + perf stat -e mac_iod0_mac0_ch0/ea-mac/ ls + +And, this driver supports the following events for PCI: +- pci-port0-cycles + This event counts PCI cycles at PCI frequency in port0. +- pci-port0-read-count + This event counts read transactions for data transfer in port0. +- pci-port0-read-count-bus + This event counts read transactions for bus usage in port0. +- pci-port0-write-count + This event counts write transactions for data transfer in port0. +- pci-port0-write-count-bus + This event counts write transactions for bus usage in port0. +- pci-port1-cycles + This event counts PCI cycles at PCI frequency in port1. +- pci-port1-read-count + This event counts read transactions for data transfer in port1. +- pci-port1-read-count-bus + This event counts read transactions for bus usage in port1. +- pci-port1-write-count + This event counts write transactions for data transfer in port1. +- pci-port1-write-count-bus + This event counts write transactions for bus usage in port1. +- ea-pci + This event counts energy consumption of PCI. + + 'ea' is the abbreviation for 'Energy Analyzer'. + +Examples for use with perf:: + + perf stat -e pci_iod0_pci0/ea-pci/ ls + +Given that these are uncore PMUs the driver does not support sampling, therefore +"perf record" will not work. Per-task perf sessions are not supported. diff --git a/Documentation/admin-guide/perf/hisi-pmu.rst b/Documentation/admin-guide/perf/hisi-pmu.rst index 48992a0b8e94..c4c2cbbf88cb 100644 --- a/Documentation/admin-guide/perf/hisi-pmu.rst +++ b/Documentation/admin-guide/perf/hisi-pmu.rst @@ -18,9 +18,10 @@ HiSilicon SoC uncore PMU driver Each device PMU has separate registers for event counting, control and interrupt, and the PMU driver shall register perf PMU drivers like L3C, HHA and DDRC etc. The available events and configuration options shall -be described in the sysfs, see: +be described in the sysfs, see:: + +/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}> -/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}/hha{Y}/ddrc{Y}>. The "perf list" command shall list the available events from sysfs. Each L3C, HHA and DDRC is registered as a separate PMU with perf. The PMU @@ -112,6 +113,50 @@ uring channel. It is 2 bits. Some important codes are as follows: - 2'b00: default value, count the events which sent to the both uring and uring_ext channel; +6. ch: NoC PMU supports filtering the event counts of certain transaction +channel with this option. The current supported channels are as follows: + +- 3'b010: Request channel +- 3'b100: Snoop channel +- 3'b110: Response channel +- 3'b111: Data channel + +7. tt_en: NoC PMU supports counting only transactions that have tracetag set +if this option is set. See the 2nd list for more information about tracetag. + +For HiSilicon uncore PMU v3 whose identifier is 0x40, some uncore PMUs are +further divided into parts for finer granularity of tracing, each part has its +own dedicated PMU, and all such PMUs together cover the monitoring job of events +on particular uncore device. Such PMUs are described in sysfs with name format +slightly changed:: + +/sys/bus/event_source/devices/hisi_sccl{X}_<l3c{Y}_{Z}/ddrc{Y}_{Z}/noc{Y}_{Z}> + +Z is the sub-id, indicating different PMUs for part of hardware device. + +Usage of most PMUs with different sub-ids are identical. Specially, L3C PMU +provides ``ext`` option to allow exploration of even finer granual statistics +of L3C PMU. L3C PMU driver uses that as hint of termination when delivering +perf command to hardware: + +- ext=0: Default, could be used with event names. +- ext=1 and ext=2: Must be used with event codes, event names are not supported. + +An example of perf command could be:: + + $# perf stat -a -e hisi_sccl0_l3c1_0/rd_spipe/ sleep 5 + +or:: + + $# perf stat -a -e hisi_sccl0_l3c1_0/event=0x1,ext=1/ sleep 5 + +As above, ``hisi_sccl0_l3c1_0`` locates PMU of Super CPU CLuster 0, L3 cache 1 +pipe0. + +First command locates the first part of L3C since ``ext=0`` is implied by +default. Second command issues the counting on another part of L3C with the +event ``0x1``. + Users could configure IDs to count data come from specific CCL/ICL, by setting srcid_cmd & srcid_msk, and data desitined for specific CCL/ICL by setting tgtid_cmd & tgtid_msk. A set bit in srcid_msk/tgtid_msk means the PMU will not diff --git a/Documentation/admin-guide/perf/index.rst b/Documentation/admin-guide/perf/index.rst index 072b510385c4..47d9a3df6329 100644 --- a/Documentation/admin-guide/perf/index.rst +++ b/Documentation/admin-guide/perf/index.rst @@ -29,3 +29,4 @@ Performance monitor support cxl ampere_cspmu mrvl-pem-pmu + fujitsu_uncore_pmu diff --git a/Documentation/admin-guide/sysctl/kernel.rst b/Documentation/admin-guide/sysctl/kernel.rst index 8b49eab937d0..f3ee807b5d8b 100644 --- a/Documentation/admin-guide/sysctl/kernel.rst +++ b/Documentation/admin-guide/sysctl/kernel.rst @@ -890,7 +890,7 @@ bit 1 print system memory info bit 2 print timer info bit 3 print locks info if ``CONFIG_LOCKDEP`` is on bit 4 print ftrace buffer -bit 5 replay all messages on consoles at the end of panic +bit 5 replay all kernel messages on consoles at the end of panic bit 6 print all CPUs backtrace (if available in the arch) bit 7 print only tasks in uninterruptible (blocked) state ===== ============================================ diff --git a/Documentation/admin-guide/sysctl/net.rst b/Documentation/admin-guide/sysctl/net.rst index 7b0c4291c686..2ef50828aff1 100644 --- a/Documentation/admin-guide/sysctl/net.rst +++ b/Documentation/admin-guide/sysctl/net.rst @@ -222,6 +222,8 @@ rmem_max The maximum receive socket buffer size in bytes. +Default: 4194304 + rps_default_mask ---------------- @@ -247,6 +249,8 @@ wmem_max The maximum send socket buffer size in bytes. +Default: 4194304 + message_burst and message_cost ------------------------------ diff --git a/Documentation/admin-guide/xfs.rst b/Documentation/admin-guide/xfs.rst index a18328a5fb93..c85cd327af28 100644 --- a/Documentation/admin-guide/xfs.rst +++ b/Documentation/admin-guide/xfs.rst @@ -34,22 +34,6 @@ When mounting an XFS filesystem, the following options are accepted. to the file. Specifying a fixed ``allocsize`` value turns off the dynamic behaviour. - attr2 or noattr2 - The options enable/disable an "opportunistic" improvement to - be made in the way inline extended attributes are stored - on-disk. When the new form is used for the first time when - ``attr2`` is selected (either when setting or removing extended - attributes) the on-disk superblock feature bit field will be - updated to reflect this format being in use. - - The default behaviour is determined by the on-disk feature - bit indicating that ``attr2`` behaviour is active. If either - mount option is set, then that becomes the new default used - by the filesystem. - - CRC enabled filesystems always use the ``attr2`` format, and so - will reject the ``noattr2`` mount option if it is set. - discard or nodiscard (default) Enable/disable the issuing of commands to let the block device reclaim space freed by the filesystem. This is @@ -75,12 +59,6 @@ When mounting an XFS filesystem, the following options are accepted. across the entire filesystem rather than just on directories configured to use it. - ikeep or noikeep (default) - When ``ikeep`` is specified, XFS does not delete empty inode - clusters and keeps them around on disk. When ``noikeep`` is - specified, empty inode clusters are returned to the free - space pool. - inode32 or inode64 (default) When ``inode32`` is specified, it indicates that XFS limits inode creation to locations which will not result in inode @@ -253,9 +231,8 @@ latest version and try again. The deprecation will take place in two parts. Support for mounting V4 filesystems can now be disabled at kernel build time via Kconfig option. -The option will default to yes until September 2025, at which time it -will be changed to default to no. In September 2030, support will be -removed from the codebase entirely. +These options were changed to default to no in September 2025. In +September 2030, support will be removed from the codebase entirely. Note: Distributors may choose to withdraw V4 format support earlier than the dates listed above. @@ -268,8 +245,6 @@ Deprecated Mount Options ============================ ================ Mounting with V4 filesystem September 2030 Mounting ascii-ci filesystem September 2030 -ikeep/noikeep September 2025 -attr2/noattr2 September 2025 ============================ ================ @@ -285,6 +260,8 @@ Removed Mount Options osyncisdsync/osyncisosync v4.0 barrier v4.19 nobarrier v4.19 + ikeep/noikeep v6.18 + attr2/noattr2 v6.18 =========================== ======= sysctls @@ -312,9 +289,6 @@ The following sysctls are available for the XFS filesystem: removes unused preallocation from clean inodes and releases the unused space back to the free pool. - fs.xfs.speculative_cow_prealloc_lifetime - This is an alias for speculative_prealloc_lifetime. - fs.xfs.error_level (Min: 0 Default: 3 Max: 11) A volume knob for error reporting when internal errors occur. This will generate detailed messages & backtraces for filesystem @@ -341,17 +315,6 @@ The following sysctls are available for the XFS filesystem: This option is intended for debugging only. - fs.xfs.irix_symlink_mode (Min: 0 Default: 0 Max: 1) - Controls whether symlinks are created with mode 0777 (default) - or whether their mode is affected by the umask (irix mode). - - fs.xfs.irix_sgid_inherit (Min: 0 Default: 0 Max: 1) - Controls files created in SGID directories. - If the group ID of the new file does not match the effective group - ID or one of the supplementary group IDs of the parent dir, the - ISGID bit is cleared if the irix_sgid_inherit compatibility sysctl - is set. - fs.xfs.inherit_sync (Min: 0 Default: 1 Max: 1) Setting this to "1" will cause the "sync" flag set by the **xfs_io(8)** chattr command on a directory to be @@ -387,24 +350,20 @@ The following sysctls are available for the XFS filesystem: Deprecated Sysctls ================== -=========================================== ================ - Name Removal Schedule -=========================================== ================ -fs.xfs.irix_sgid_inherit September 2025 -fs.xfs.irix_symlink_mode September 2025 -fs.xfs.speculative_cow_prealloc_lifetime September 2025 -=========================================== ================ - +None currently. Removed Sysctls =============== -============================= ======= - Name Removed -============================= ======= - fs.xfs.xfsbufd_centisec v4.0 - fs.xfs.age_buffer_centisecs v4.0 -============================= ======= +========================================== ======= + Name Removed +========================================== ======= + fs.xfs.xfsbufd_centisec v4.0 + fs.xfs.age_buffer_centisecs v4.0 + fs.xfs.irix_symlink_mode v6.18 + fs.xfs.irix_sgid_inherit v6.18 + fs.xfs.speculative_cow_prealloc_lifetime v6.18 +========================================== ======= Error handling ============== diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm64/booting.rst index 2f666a7c303c..e4f953839f71 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -466,6 +466,17 @@ Before jumping into the kernel, the following conditions must be met: - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. + For CPUs with SPE data source filtering (FEAT_SPE_FDS): + + - If EL3 is present: + + - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): - If the kernel is entered at EL1 and EL2 is present: diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index f58ada4d6cb2..a15df4956849 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -441,6 +441,10 @@ HWCAP3_MTE_FAR HWCAP3_MTE_STORE_ONLY Functionality implied by ID_AA64PFR2_EL1.MTESTOREONLY == 0b0001. +HWCAP3_LSFE + Functionality implied by ID_AA64ISAR3_EL1.LSFE == 0b0001 + + 4. Unused AT_HWCAP bits ----------------------- diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst index b18ef4064bc0..a7ec57060f64 100644 --- a/Documentation/arch/arm64/silicon-errata.rst +++ b/Documentation/arch/arm64/silicon-errata.rst @@ -200,6 +200,8 @@ stable kernels. +----------------+-----------------+-----------------+-----------------------------+ | ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 | +----------------+-----------------+-----------------+-----------------------------+ +| ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 | ++----------------+-----------------+-----------------+-----------------------------+ | ARM | MMU-500 | #841119,826419 | ARM_SMMU_MMU_500_CPRE_ERRATA| | | | #562869,1047329 | | +----------------+-----------------+-----------------+-----------------------------+ diff --git a/Documentation/arch/arm64/sme.rst b/Documentation/arch/arm64/sme.rst index 4cb38330e704..583f2ee9cb97 100644 --- a/Documentation/arch/arm64/sme.rst +++ b/Documentation/arch/arm64/sme.rst @@ -81,17 +81,7 @@ The ZA matrix is square with each side having as many bytes as a streaming mode SVE vector. -3. Sharing of streaming and non-streaming mode SVE state ---------------------------------------------------------- - -It is implementation defined which if any parts of the SVE state are shared -between streaming and non-streaming modes. When switching between modes -via software interfaces such as ptrace if no register content is provided as -part of switching no state will be assumed to be shared and everything will -be zeroed. - - -4. System call behaviour +3. System call behaviour ------------------------- * On syscall PSTATE.ZA is preserved, if PSTATE.ZA==1 then the contents of the @@ -112,7 +102,7 @@ be zeroed. exceptions for execve() described in section 6. -5. Signal handling +4. Signal handling ------------------- * Signal handlers are invoked with PSTATE.SM=0, PSTATE.ZA=0, and TPIDR2_EL0=0. diff --git a/Documentation/arch/powerpc/index.rst b/Documentation/arch/powerpc/index.rst index 53fc9f89f3e4..1be2ee3f0361 100644 --- a/Documentation/arch/powerpc/index.rst +++ b/Documentation/arch/powerpc/index.rst @@ -37,6 +37,7 @@ powerpc vas-api vcpudispatch_stats vmemmap_dedup + vpa-dtl features diff --git a/Documentation/arch/powerpc/vpa-dtl.rst b/Documentation/arch/powerpc/vpa-dtl.rst new file mode 100644 index 000000000000..58d0022f993a --- /dev/null +++ b/Documentation/arch/powerpc/vpa-dtl.rst @@ -0,0 +1,156 @@ +.. SPDX-License-Identifier: GPL-2.0 +.. _vpa-dtl: + +=================================== +DTL (Dispatch Trace Log) +=================================== + +Athira Rajeev, 19 April 2025 + +.. contents:: + :depth: 3 + + +Basic overview +============== + +The pseries Shared Processor Logical Partition(SPLPAR) machines can +retrieve a log of dispatch and preempt events from the hypervisor +using data from Disptach Trace Log(DTL) buffer. With this information, +user can retrieve when and why each dispatch & preempt has occurred. +The vpa-dtl PMU exposes the Virtual Processor Area(VPA) DTL counters +via perf. + +Infrastructure used +=================== + +The VPA DTL PMU counters do not interrupt on overflow or generate any +PMI interrupts. Therefore, hrtimer is used to poll the DTL data. The timer +nterval can be provided by user via sample_period field in nano seconds. +vpa dtl pmu has one hrtimer added per vpa-dtl pmu thread. DTL (Dispatch +Trace Log) contains information about dispatch/preempt, enqueue time etc. +We directly copy the DTL buffer data as part of auxiliary buffer and it +will be processed later. This will avoid time taken to create samples +in the kernel space. The PMU driver collecting Dispatch Trace Log (DTL) +entries makes use of AUX support in perf infrastructure. On the tools side, +this data is made available as PERF_RECORD_AUXTRACE records. + +To correlate each DTL entry with other events across CPU's, an auxtrace_queue +is created for each CPU. Each auxtrace queue has a array/list of auxtrace buffers. +All auxtrace queues is maintained in auxtrace heap. The queues are sorted +based on timestamp. When the different PERF_RECORD_XX records are processed, +compare the timestamp of perf record with timestamp of top element in the +auxtrace heap so that DTL events can be co-related with other events +Process the auxtrace queue if the timestamp of element from heap is +lower than timestamp from entry in perf record. Sometimes it could happen that +one buffer is only partially processed. if the timestamp of occurrence of +another event is more than currently processed element in the queue, it will +move on to next perf record. So keep track of position of buffer to continue +processing next time. Update the timestamp of the auxtrace heap with the timestamp +of last processed entry from the auxtrace buffer. + +This infrastructure ensures dispatch trace log entries can be correlated +and presented along with other events like sched. + +vpa-dtl PMU example usage +========================= + +.. code-block:: sh + + # ls /sys/devices/vpa_dtl/ + events format perf_event_mux_interval_ms power subsystem type uevent + + +To capture the DTL data using perf record: +.. code-block:: sh + + # ./perf record -a -e sched:\*,vpa_dtl/dtl_all/ -c 1000000000 sleep 1 + +The result can be interpreted using perf record. Snippet of perf report -D + +.. code-block:: sh + + # ./perf report -D + +There are different PERF_RECORD_XX records. In that records corresponding to +auxtrace buffers includes: + +1. PERF_RECORD_AUX + Conveys that new data is available in AUX area + +2. PERF_RECORD_AUXTRACE_INFO + Describes offset and size of auxtrace data in the buffers + +3. PERF_RECORD_AUXTRACE + This is the record that defines the auxtrace data which here in case of + vpa-dtl pmu is dispatch trace log data. + +Snippet from perf report -D showing the PERF_RECORD_AUXTRACE dump + +.. code-block:: sh + +0 0 0x39b10 [0x30]: PERF_RECORD_AUXTRACE size: 0x690 offset: 0 ref: 0 idx: 0 tid: -1 cpu: 0 +. +. ... VPA DTL PMU data: size 1680 bytes, entries is 35 +. 00000000: boot_tb: 21349649546353231, tb_freq: 512000000 +. 00000030: dispatch_reason:decrementer interrupt, preempt_reason:H_CEDE, enqueue_to_dispatch_time:7064, ready_to_enqueue_time:187, waiting_to_ready_time:6611773 +. 00000060: dispatch_reason:priv doorbell, preempt_reason:H_CEDE, enqueue_to_dispatch_time:146, ready_to_enqueue_time:0, waiting_to_ready_time:15359437 +. 00000090: dispatch_reason:decrementer interrupt, preempt_reason:H_CEDE, enqueue_to_dispatch_time:4868, ready_to_enqueue_time:232, waiting_to_ready_time:5100709 +. 000000c0: dispatch_reason:priv doorbell, preempt_reason:H_CEDE, enqueue_to_dispatch_time:179, ready_to_enqueue_time:0, waiting_to_ready_time:30714243 +. 000000f0: dispatch_reason:priv doorbell, preempt_reason:H_CEDE, enqueue_to_dispatch_time:197, ready_to_enqueue_time:0, waiting_to_ready_time:15350648 +. 00000120: dispatch_reason:priv doorbell, preempt_reason:H_CEDE, enqueue_to_dispatch_time:213, ready_to_enqueue_time:0, waiting_to_ready_time:15353446 +. 00000150: dispatch_reason:priv doorbell, preempt_reason:H_CEDE, enqueue_to_dispatch_time:212, ready_to_enqueue_time:0, waiting_to_ready_time:15355126 +. 00000180: dispatch_reason:decrementer interrupt, preempt_reason:H_CEDE, enqueue_to_dispatch_time:6368, ready_to_enqueue_time:164, waiting_to_ready_time:5104665 + +Above is representation of dtl entry of below format: + +struct dtl_entry { + u8 dispatch_reason; + u8 preempt_reason; + u16 processor_id; + u32 enqueue_to_dispatch_time; + u32 ready_to_enqueue_time; + u32 waiting_to_ready_time; + u64 timebase; + u64 fault_addr; + u64 srr0; + u64 srr1; + +}; + +First two fields represent the dispatch reason and preempt reason. The post +processing of PERF_RECORD_AUXTRACE records will translate to meaningful data +for user to consume. + +Visualize the dispatch trace log entries with perf report +========================================================= + +.. code-block:: sh + + # ./perf record -a -e sched:*,vpa_dtl/dtl_all/ -c 1000000000 sleep 1 + [ perf record: Woken up 1 times to write data ] + [ perf record: Captured and wrote 0.300 MB perf.data ] + + # ./perf report + # Samples: 321 of event 'vpa-dtl' + # Event count (approx.): 321 + # + # Children Self Command Shared Object Symbol + # ........ ........ ....... ................. .............................. + # + 100.00% 100.00% swapper [kernel.kallsyms] [k] plpar_hcall_norets_notrace + +Visualize the dispatch trace log entries with perf script +========================================================= + +.. code-block:: sh + + # ./perf script + migration/9 67 [009] 105373.359903: sched:sched_waking: comm=perf pid=13418 prio=120 target_cpu=009 + migration/9 67 [009] 105373.359904: sched:sched_migrate_task: comm=perf pid=13418 prio=120 orig_cpu=9 dest_cpu=10 + migration/9 67 [009] 105373.359907: sched:sched_stat_runtime: comm=migration/9 pid=67 runtime=4050 [ns] + migration/9 67 [009] 105373.359908: sched:sched_switch: prev_comm=migration/9 prev_pid=67 prev_prio=0 prev_state=S ==> next_comm=swapper/9 next_pid=0 next_prio=120 + :256 256 [016] 105373.359913: vpa-dtl: timebase: 21403600706628832 dispatch_reason:decrementer interrupt, preempt_reason:H_CEDE, enqueue_to_dispatch_time:4854, ready_to_enqueue_time:139, waiting_to_ready_time:511842115 c0000000000fcd28 plpar_hcall_norets_notrace+0x18 ([kernel.kallsyms]) + :256 256 [017] 105373.360012: vpa-dtl: timebase: 21403600706679454 dispatch_reason:priv doorbell, preempt_reason:H_CEDE, enqueue_to_dispatch_time:236, ready_to_enqueue_time:0, waiting_to_ready_time:133864583 c0000000000fcd28 plpar_hcall_norets_notrace+0x18 ([kernel.kallsyms]) + perf 13418 [010] 105373.360048: sched:sched_stat_runtime: comm=perf pid=13418 runtime=139748 [ns] + perf 13418 [010] 105373.360052: sched:sched_waking: comm=migration/10 pid=72 prio=0 target_cpu=010 diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst index 2aa9be272d5d..2f449c9b15bd 100644 --- a/Documentation/arch/riscv/hwprobe.rst +++ b/Documentation/arch/riscv/hwprobe.rst @@ -327,6 +327,15 @@ The following keys are defined: * :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNSUPPORTED`: Misaligned vector accesses are not supported at all and will generate a misaligned address fault. +* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_MIPS_0`: A bitmask containing the + mips vendor extensions that are compatible with the + :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. + + * MIPS + + * :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor + extension is supported in the MIPS ISA extensions spec. + * :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the thead vendor extensions that are compatible with the :c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior. diff --git a/Documentation/arch/x86/topology.rst b/Documentation/arch/x86/topology.rst index c12837e61bda..86bec8ac2c4d 100644 --- a/Documentation/arch/x86/topology.rst +++ b/Documentation/arch/x86/topology.rst @@ -141,6 +141,197 @@ Thread-related topology information in the kernel: +System topology enumeration +=========================== + +The topology on x86 systems can be discovered using a combination of vendor +specific CPUID leaves which enumerate the processor topology and the cache +hierarchy. + +The CPUID leaves in their preferred order of parsing for each x86 vendor is as +follows: + +1) AMD + + 1) CPUID leaf 0x80000026 [Extended CPU Topology] (Core::X86::Cpuid::ExCpuTopology) + + The extended CPUID leaf 0x80000026 is the extension of the CPUID leaf 0xB + and provides the topology information of Core, Complex, CCD (Die), and + Socket in each level. + + Support for the leaf is discovered by checking if the maximum extended + CPUID level is >= 0x80000026 and then checking if `LogProcAtThisLevel` + in `EBX[15:0]` at a particular level (starting from 0) is non-zero. + + The `LevelType` in `ECX[15:8]` at the level provides the topology domain + the level describes - Core, Complex, CCD(Die), or the Socket. + + The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the + number of bits that need to be right-shifted from `ExtendedLocalApicId` + in `EDX[31:0]` in order to get a unique Topology ID for the topology + level. CPUs with the same Topology ID share the resources at that level. + + CPUID leaf 0x80000026 also provides more information regarding the power + and efficiency rankings, and about the core type on AMD processors with + heterogeneous characteristics. + + If CPUID leaf 0x80000026 is supported, further parsing is not required. + + 2) CPUID leaf 0x0000000B [Extended Topology Enumeration] (Core::X86::Cpuid::ExtTopEnum) + + The extended CPUID leaf 0x0000000B is the predecessor on the extended + CPUID leaf 0x80000026 and only describes the core, and the socket domains + of the processor topology. + + The support for the leaf is discovered by checking if the maximum supported + CPUID level is >= 0xB and then if `EBX[31:0]` at a particular level + (starting from 0) is non-zero. + + The `LevelType` in `ECX[15:8]` at the level provides the topology domain + that the level describes - Thread, or Processor (Socket). + + The kernel uses the `CoreMaskWidth` from `EAX[4:0]` to discover the + number of bits that need to be right-shifted from the `ExtendedLocalApicId` + in `EDX[31:0]` to get a unique Topology ID for that topology level. CPUs + sharing the Topology ID share the resources at that level. + + If CPUID leaf 0xB is supported, further parsing is not required. + + + 3) CPUID leaf 0x80000008 ECX [Size Identifiers] (Core::X86::Cpuid::SizeId) + + If neither the CPUID leaf 0x80000026 nor 0xB is supported, the number of + CPUs on the package is detected using the Size Identifier leaf + 0x80000008 ECX. + + The support for the leaf is discovered by checking if the supported + extended CPUID level is >= 0x80000008. + + The shifts from the APIC ID for the Socket ID is calculated from the + `ApicIdSize` field in `ECX[15:12]` if it is non-zero. + + If `ApicIdSize` is reported to be zero, the shift is calculated as the + order of the `number of threads` calculated from `NC` field in + `ECX[7:0]` which describes the `number of threads - 1` on the package. + + Unless Extended APIC ID is supported, the APIC ID used to find the + Socket ID is from the `LocalApicId` field of CPUID leaf 0x00000001 + `EBX[31:24]`. + + The topology parsing continues to detect if Extended APIC ID is + supported or not. + + + 4) CPUID leaf 0x8000001E [Extended APIC ID, Core Identifiers, Node Identifiers] + (Core::X86::Cpuid::{ExtApicId,CoreId,NodeId}) + + The support for Extended APIC ID can be detected by checking for the + presence of `TopologyExtensions` in `ECX[22]` of CPUID leaf 0x80000001 + [Feature Identifiers] (Core::X86::Cpuid::FeatureExtIdEcx). + + If Topology Extensions is supported, the APIC ID from `ExtendedApicId` + from CPUID leaf 0x8000001E `EAX[31:0]` should be preferred over that from + `LocalApicId` field of CPUID leaf 0x00000001 `EBX[31:24]` for topology + enumeration. + + On processors of Family 0x17 and above that do not support CPUID leaf + 0x80000026 or CPUID leaf 0xB, the shifts from the APIC ID for the Core + ID is calculated using the order of `number of threads per core` + calculated using the `ThreadsPerCore` field in `EBX[15:8]` which + describes `number of threads per core - 1`. + + On Processors of Family 0x15, the Core ID from `EBX[7:0]` is used as the + `cu_id` (Compute Unit ID) to detect CPUs that share the compute units. + + + All AMD processors that support the `TopologyExtensions` feature store the + `NodeId` from the `ECX[7:0]` of CPUID leaf 0x8000001E + (Core::X86::Cpuid::NodeId) as the per-CPU `node_id`. On older processors, + the `node_id` was discovered using MSR_FAM10H_NODE_ID MSR (MSR + 0x0xc001_100c). The presence of the NODE_ID MSR was detected by checking + `ECX[19]` of CPUID leaf 0x80000001 [Feature Identifiers] + (Core::X86::Cpuid::FeatureExtIdEcx). + + +2) Intel + + On Intel platforms, the CPUID leaves that enumerate the processor + topology are as follows: + + 1) CPUID leaf 0x1F (V2 Extended Topology Enumeration Leaf) + + The CPUID leaf 0x1F is the extension of the CPUID leaf 0xB and provides + the topology information of Core, Module, Tile, Die, DieGrp, and Socket + in each level. + + The support for the leaf is discovered by checking if the supported + CPUID level is >= 0x1F and then `EBX[31:0]` at a particular level + (starting from 0) is non-zero. + + The `Domain Type` in `ECX[15:8]` of the sub-leaf provides the topology + domain that the level describes - Core, Module, Tile, Die, DieGrp, and + Socket. + + The kernel uses the value from `EAX[4:0]` to discover the number of + bits that need to be right shifted from the `x2APIC ID` in `EDX[31:0]` + to get a unique Topology ID for the topology level. CPUs with the same + Topology ID share the resources at that level. + + If CPUID leaf 0x1F is supported, further parsing is not required. + + + 2) CPUID leaf 0x0000000B (Extended Topology Enumeration Leaf) + + The extended CPUID leaf 0x0000000B is the predecessor of the V2 Extended + Topology Enumeration Leaf 0x1F and only describes the core, and the + socket domains of the processor topology. + + The support for the leaf is iscovered by checking if the supported CPUID + level is >= 0xB and then checking if `EBX[31:0]` at a particular level + (starting from 0) is non-zero. + + CPUID leaf 0x0000000B shares the same layout as CPUID leaf 0x1F and + should be enumerated in a similar manner. + + If CPUID leaf 0xB is supported, further parsing is not required. + + + 3) CPUID leaf 0x00000004 (Deterministic Cache Parameters Leaf) + + On Intel processors that support neither CPUID leaf 0x1F, nor CPUID leaf + 0xB, the shifts for the SMT domains is calculated using the number of + CPUs sharing the L1 cache. + + Processors that feature Hyper-Threading is detected using `EDX[28]` of + CPUID leaf 0x1 (Basic CPUID Information). + + The order of `Maximum number of addressable IDs for logical processors + sharing this cache` from `EAX[25:14]` of level-0 of CPUID 0x4 provides + the shifts from the APIC ID required to compute the Core ID. + + The APIC ID and Package information is computed using the data from + CPUID leaf 0x1. + + + 4) CPUID leaf 0x00000001 (Basic CPUID Information) + + The mask and shifts to derive the Physical Package (socket) ID is + computed using the `Maximum number of addressable IDs for logical + processors in this physical package` from `EBX[23:16]` of CPUID leaf + 0x1. + + The APIC ID on the legacy platforms is derived from the `Initial APIC + ID` field from `EBX[31:24]` of CPUID leaf 0x1. + + +3) Centaur and Zhaoxin + + Similar to Intel, Centaur and Zhaoxin use a combination of CPUID leaf + 0x00000004 (Deterministic Cache Parameters Leaf) and CPUID leaf 0x00000001 + (Basic CPUID Information) to derive the topology information. + + + System topology examples ======================== diff --git a/Documentation/bpf/kfuncs.rst b/Documentation/bpf/kfuncs.rst index ae468b781d31..e38941370b90 100644 --- a/Documentation/bpf/kfuncs.rst +++ b/Documentation/bpf/kfuncs.rst @@ -335,9 +335,26 @@ consider doing refcnt != 0 check, especially when returning a KF_ACQUIRE pointer. Note as well that a KF_ACQUIRE kfunc that is KF_RCU should very likely also be KF_RET_NULL. +2.4.8 KF_RCU_PROTECTED flag +--------------------------- + +The KF_RCU_PROTECTED flag is used to indicate that the kfunc must be invoked in +an RCU critical section. This is assumed by default in non-sleepable programs, +and must be explicitly ensured by calling ``bpf_rcu_read_lock`` for sleepable +ones. + +If the kfunc returns a pointer value, this flag also enforces that the returned +pointer is RCU protected, and can only be used while the RCU critical section is +active. + +The flag is distinct from the ``KF_RCU`` flag, which only ensures that its +arguments are at least RCU protected pointers. This may transitively imply that +RCU protection is ensured, but it does not work in cases of kfuncs which require +RCU protection but do not take RCU protected arguments. + .. _KF_deprecated_flag: -2.4.8 KF_DEPRECATED flag +2.4.9 KF_DEPRECATED flag ------------------------ The KF_DEPRECATED flag is used for kfuncs which are scheduled to be diff --git a/Documentation/bpf/verifier.rst b/Documentation/bpf/verifier.rst index 95e6f80a407e..510d15bc697b 100644 --- a/Documentation/bpf/verifier.rst +++ b/Documentation/bpf/verifier.rst @@ -347,270 +347,6 @@ However, only the value of register ``r1`` is important to successfully finish verification. The goal of the liveness tracking algorithm is to spot this fact and figure out that both states are actually equivalent. -Data structures -~~~~~~~~~~~~~~~ - -Liveness is tracked using the following data structures:: - - enum bpf_reg_liveness { - REG_LIVE_NONE = 0, - REG_LIVE_READ32 = 0x1, - REG_LIVE_READ64 = 0x2, - REG_LIVE_READ = REG_LIVE_READ32 | REG_LIVE_READ64, - REG_LIVE_WRITTEN = 0x4, - REG_LIVE_DONE = 0x8, - }; - - struct bpf_reg_state { - ... - struct bpf_reg_state *parent; - ... - enum bpf_reg_liveness live; - ... - }; - - struct bpf_stack_state { - struct bpf_reg_state spilled_ptr; - ... - }; - - struct bpf_func_state { - struct bpf_reg_state regs[MAX_BPF_REG]; - ... - struct bpf_stack_state *stack; - } - - struct bpf_verifier_state { - struct bpf_func_state *frame[MAX_CALL_FRAMES]; - struct bpf_verifier_state *parent; - ... - } - -* ``REG_LIVE_NONE`` is an initial value assigned to ``->live`` fields upon new - verifier state creation; - -* ``REG_LIVE_WRITTEN`` means that the value of the register (or stack slot) is - defined by some instruction verified between this verifier state's parent and - verifier state itself; - -* ``REG_LIVE_READ{32,64}`` means that the value of the register (or stack slot) - is read by a some child state of this verifier state; - -* ``REG_LIVE_DONE`` is a marker used by ``clean_verifier_state()`` to avoid - processing same verifier state multiple times and for some sanity checks; - -* ``->live`` field values are formed by combining ``enum bpf_reg_liveness`` - values using bitwise or. - -Register parentage chains -~~~~~~~~~~~~~~~~~~~~~~~~~ - -In order to propagate information between parent and child states, a *register -parentage chain* is established. Each register or stack slot is linked to a -corresponding register or stack slot in its parent state via a ``->parent`` -pointer. This link is established upon state creation in ``is_state_visited()`` -and might be modified by ``set_callee_state()`` called from -``__check_func_call()``. - -The rules for correspondence between registers / stack slots are as follows: - -* For the current stack frame, registers and stack slots of the new state are - linked to the registers and stack slots of the parent state with the same - indices. - -* For the outer stack frames, only callee saved registers (r6-r9) and stack - slots are linked to the registers and stack slots of the parent state with the - same indices. - -* When function call is processed a new ``struct bpf_func_state`` instance is - allocated, it encapsulates a new set of registers and stack slots. For this - new frame, parent links for r6-r9 and stack slots are set to nil, parent links - for r1-r5 are set to match caller r1-r5 parent links. - -This could be illustrated by the following diagram (arrows stand for -``->parent`` pointers):: - - ... ; Frame #0, some instructions - --- checkpoint #0 --- - 1 : r6 = 42 ; Frame #0 - --- checkpoint #1 --- - 2 : call foo() ; Frame #0 - ... ; Frame #1, instructions from foo() - --- checkpoint #2 --- - ... ; Frame #1, instructions from foo() - --- checkpoint #3 --- - exit ; Frame #1, return from foo() - 3 : r1 = r6 ; Frame #0 <- current state - - +-------------------------------+-------------------------------+ - | Frame #0 | Frame #1 | - Checkpoint +-------------------------------+-------------------------------+ - #0 | r0 | r1-r5 | r6-r9 | fp-8 ... | - +-------------------------------+ - ^ ^ ^ ^ - | | | | - Checkpoint +-------------------------------+ - #1 | r0 | r1-r5 | r6-r9 | fp-8 ... | - +-------------------------------+ - ^ ^ ^ - |_______|_______|_______________ - | | | - nil nil | | | nil nil - | | | | | | | - Checkpoint +-------------------------------+-------------------------------+ - #2 | r0 | r1-r5 | r6-r9 | fp-8 ... | r0 | r1-r5 | r6-r9 | fp-8 ... | - +-------------------------------+-------------------------------+ - ^ ^ ^ ^ ^ - nil nil | | | | | - | | | | | | | - Checkpoint +-------------------------------+-------------------------------+ - #3 | r0 | r1-r5 | r6-r9 | fp-8 ... | r0 | r1-r5 | r6-r9 | fp-8 ... | - +-------------------------------+-------------------------------+ - ^ ^ - nil nil | | - | | | | - Current +-------------------------------+ - state | r0 | r1-r5 | r6-r9 | fp-8 ... | - +-------------------------------+ - \ - r6 read mark is propagated via these links - all the way up to checkpoint #1. - The checkpoint #1 contains a write mark for r6 - because of instruction (1), thus read propagation - does not reach checkpoint #0 (see section below). - -Liveness marks tracking -~~~~~~~~~~~~~~~~~~~~~~~ - -For each processed instruction, the verifier tracks read and written registers -and stack slots. The main idea of the algorithm is that read marks propagate -back along the state parentage chain until they hit a write mark, which 'screens -off' earlier states from the read. The information about reads is propagated by -function ``mark_reg_read()`` which could be summarized as follows:: - - mark_reg_read(struct bpf_reg_state *state, ...): - parent = state->parent - while parent: - if state->live & REG_LIVE_WRITTEN: - break - if parent->live & REG_LIVE_READ64: - break - parent->live |= REG_LIVE_READ64 - state = parent - parent = state->parent - -Notes: - -* The read marks are applied to the **parent** state while write marks are - applied to the **current** state. The write mark on a register or stack slot - means that it is updated by some instruction in the straight-line code leading - from the parent state to the current state. - -* Details about REG_LIVE_READ32 are omitted. - -* Function ``propagate_liveness()`` (see section :ref:`read_marks_for_cache_hits`) - might override the first parent link. Please refer to the comments in the - ``propagate_liveness()`` and ``mark_reg_read()`` source code for further - details. - -Because stack writes could have different sizes ``REG_LIVE_WRITTEN`` marks are -applied conservatively: stack slots are marked as written only if write size -corresponds to the size of the register, e.g. see function ``save_register_state()``. - -Consider the following example:: - - 0: (*u64)(r10 - 8) = 0 ; define 8 bytes of fp-8 - --- checkpoint #0 --- - 1: (*u32)(r10 - 8) = 1 ; redefine lower 4 bytes - 2: r1 = (*u32)(r10 - 8) ; read lower 4 bytes defined at (1) - 3: r2 = (*u32)(r10 - 4) ; read upper 4 bytes defined at (0) - -As stated above, the write at (1) does not count as ``REG_LIVE_WRITTEN``. Should -it be otherwise, the algorithm above wouldn't be able to propagate the read mark -from (3) to checkpoint #0. - -Once the ``BPF_EXIT`` instruction is reached ``update_branch_counts()`` is -called to update the ``->branches`` counter for each verifier state in a chain -of parent verifier states. When the ``->branches`` counter reaches zero the -verifier state becomes a valid entry in a set of cached verifier states. - -Each entry of the verifier states cache is post-processed by a function -``clean_live_states()``. This function marks all registers and stack slots -without ``REG_LIVE_READ{32,64}`` marks as ``NOT_INIT`` or ``STACK_INVALID``. -Registers/stack slots marked in this way are ignored in function ``stacksafe()`` -called from ``states_equal()`` when a state cache entry is considered for -equivalence with a current state. - -Now it is possible to explain how the example from the beginning of the section -works:: - - 0: call bpf_get_prandom_u32() - 1: r1 = 0 - 2: if r0 == 0 goto +1 - 3: r0 = 1 - --- checkpoint[0] --- - 4: r0 = r1 - 5: exit - -* At instruction #2 branching point is reached and state ``{ r0 == 0, r1 == 0, pc == 4 }`` - is pushed to states processing queue (pc stands for program counter). - -* At instruction #4: - - * ``checkpoint[0]`` states cache entry is created: ``{ r0 == 1, r1 == 0, pc == 4 }``; - * ``checkpoint[0].r0`` is marked as written; - * ``checkpoint[0].r1`` is marked as read; - -* At instruction #5 exit is reached and ``checkpoint[0]`` can now be processed - by ``clean_live_states()``. After this processing ``checkpoint[0].r1`` has a - read mark and all other registers and stack slots are marked as ``NOT_INIT`` - or ``STACK_INVALID`` - -* The state ``{ r0 == 0, r1 == 0, pc == 4 }`` is popped from the states queue - and is compared against a cached state ``{ r1 == 0, pc == 4 }``, the states - are considered equivalent. - -.. _read_marks_for_cache_hits: - -Read marks propagation for cache hits -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ - -Another point is the handling of read marks when a previously verified state is -found in the states cache. Upon cache hit verifier must behave in the same way -as if the current state was verified to the program exit. This means that all -read marks, present on registers and stack slots of the cached state, must be -propagated over the parentage chain of the current state. Example below shows -why this is important. Function ``propagate_liveness()`` handles this case. - -Consider the following state parentage chain (S is a starting state, A-E are -derived states, -> arrows show which state is derived from which):: - - r1 read - <------------- A[r1] == 0 - C[r1] == 0 - S ---> A ---> B ---> exit E[r1] == 1 - | - ` ---> C ---> D - | - ` ---> E ^ - |___ suppose all these - ^ states are at insn #Y - | - suppose all these - states are at insn #X - -* Chain of states ``S -> A -> B -> exit`` is verified first. - -* While ``B -> exit`` is verified, register ``r1`` is read and this read mark is - propagated up to state ``A``. - -* When chain of states ``C -> D`` is verified the state ``D`` turns out to be - equivalent to state ``B``. - -* The read mark for ``r1`` has to be propagated to state ``C``, otherwise state - ``C`` might get mistakenly marked as equivalent to state ``E`` even though - values for register ``r1`` differ between ``C`` and ``E``. - Understanding eBPF verifier messages ==================================== diff --git a/Documentation/conf.py b/Documentation/conf.py index 700516238d3f..f9828f3862f9 100644 --- a/Documentation/conf.py +++ b/Documentation/conf.py @@ -42,6 +42,15 @@ exclude_patterns = [] dyn_include_patterns = [] dyn_exclude_patterns = ["output"] +# Currently, only netlink/specs has a parser for yaml. +# Prefer using include patterns if available, as it is faster +if has_include_patterns: + dyn_include_patterns.append("netlink/specs/*.yaml") +else: + dyn_exclude_patterns.append("netlink/*.yaml") + dyn_exclude_patterns.append("devicetree/bindings/**.yaml") + dyn_exclude_patterns.append("core-api/kho/bindings/**.yaml") + # Properly handle include/exclude patterns # ---------------------------------------- @@ -102,12 +111,12 @@ extensions = [ "kernel_include", "kfigure", "maintainers_include", + "parser_yaml", "rstFlatTable", "sphinx.ext.autosectionlabel", "sphinx.ext.ifconfig", "translations", ] - # Since Sphinx version 3, the C function parser is more pedantic with regards # to type checking. Due to that, having macros at c:function cause problems. # Those needed to be escaped by using c_id_attributes[] array @@ -204,10 +213,11 @@ else: # Add any paths that contain templates here, relative to this directory. templates_path = ["sphinx/templates"] -# The suffix(es) of source filenames. -# You can specify multiple suffix as a list of string: -# source_suffix = ['.rst', '.md'] -source_suffix = '.rst' +# The suffixes of source filenames that will be automatically parsed +source_suffix = { + ".rst": "restructuredtext", + ".yaml": "yaml", +} # The encoding of source files. # source_encoding = 'utf-8-sig' diff --git a/Documentation/core-api/mm-api.rst b/Documentation/core-api/mm-api.rst index 5063179cfc70..68193a4cfcf5 100644 --- a/Documentation/core-api/mm-api.rst +++ b/Documentation/core-api/mm-api.rst @@ -118,7 +118,6 @@ More Memory Management Functions .. kernel-doc:: mm/memremap.c .. kernel-doc:: mm/hugetlb.c .. kernel-doc:: mm/swap.c -.. kernel-doc:: mm/zpool.c .. kernel-doc:: mm/memcontrol.c .. #kernel-doc:: mm/memory-tiers.c (build warnings) .. kernel-doc:: mm/shmem.c diff --git a/Documentation/dev-tools/kasan.rst b/Documentation/dev-tools/kasan.rst index 0a1418ab72fd..a034700da7c4 100644 --- a/Documentation/dev-tools/kasan.rst +++ b/Documentation/dev-tools/kasan.rst @@ -143,6 +143,9 @@ disabling KASAN altogether or controlling its features: Asymmetric mode: a bad access is detected synchronously on reads and asynchronously on writes. +- ``kasan.write_only=off`` or ``kasan.write_only=on`` controls whether KASAN + checks the write (store) accesses only or all accesses (default: ``off``). + - ``kasan.vmalloc=off`` or ``=on`` disables or enables tagging of vmalloc allocations (default: ``on``). diff --git a/Documentation/dev-tools/kcov.rst b/Documentation/dev-tools/kcov.rst index 6611434e2dd2..8127849d40f5 100644 --- a/Documentation/dev-tools/kcov.rst +++ b/Documentation/dev-tools/kcov.rst @@ -361,7 +361,12 @@ local tasks spawned by the process and the global task that handles USB bus #1: */ sleep(2); - n = __atomic_load_n(&cover[0], __ATOMIC_RELAXED); + /* + * The load to the coverage count should be an acquire to pair with + * pair with the corresponding write memory barrier (smp_wmb()) on + * the kernel-side in kcov_move_area(). + */ + n = __atomic_load_n(&cover[0], __ATOMIC_ACQUIRE); for (i = 0; i < n; i++) printf("0x%lx\n", cover[i + 1]); if (ioctl(fd, KCOV_DISABLE, 0)) diff --git a/Documentation/dev-tools/kunit/usage.rst b/Documentation/dev-tools/kunit/usage.rst index 066ecda1dd98..ebd06f5ea455 100644 --- a/Documentation/dev-tools/kunit/usage.rst +++ b/Documentation/dev-tools/kunit/usage.rst @@ -542,11 +542,31 @@ There is more boilerplate code involved, but it can: Parameterized Testing ~~~~~~~~~~~~~~~~~~~~~ -The table-driven testing pattern is common enough that KUnit has special -support for it. +To run a test case against multiple inputs, KUnit provides a parameterized +testing framework. This feature formalizes and extends the concept of +table-driven tests discussed previously. -By reusing the same ``cases`` array from above, we can write the test as a -"parameterized test" with the following. +A KUnit test is determined to be parameterized if a parameter generator function +is provided when registering the test case. A test user can either write their +own generator function or use one that is provided by KUnit. The generator +function is stored in ``kunit_case->generate_params`` and can be set using the +macros described in the section below. + +To establish the terminology, a "parameterized test" is a test which is run +multiple times (once per "parameter" or "parameter run"). Each parameter run has +both its own independent ``struct kunit`` (the "parameter run context") and +access to a shared parent ``struct kunit`` (the "parameterized test context"). + +Passing Parameters to a Test +^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +There are three ways to provide the parameters to a test: + +Array Parameter Macros: + + KUnit provides special support for the common table-driven testing pattern. + By applying either ``KUNIT_ARRAY_PARAM`` or ``KUNIT_ARRAY_PARAM_DESC`` to the + ``cases`` array from the previous section, we can create a parameterized test + as shown below: .. code-block:: c @@ -555,7 +575,7 @@ By reusing the same ``cases`` array from above, we can write the test as a const char *str; const char *sha1; }; - const struct sha1_test_case cases[] = { + static const struct sha1_test_case cases[] = { { .str = "hello world", .sha1 = "2aae6c35c94fcfb415dbe95f408b9ce91ee846ed", @@ -590,6 +610,318 @@ By reusing the same ``cases`` array from above, we can write the test as a {} }; +Custom Parameter Generator Function: + + The generator function is responsible for generating parameters one-by-one + and has the following signature: + ``const void* (*)(struct kunit *test, const void *prev, char *desc)``. + You can pass the generator function to the ``KUNIT_CASE_PARAM`` + or ``KUNIT_CASE_PARAM_WITH_INIT`` macros. + + The function receives the previously generated parameter as the ``prev`` argument + (which is ``NULL`` on the first call) and can also access the parameterized + test context passed as the ``test`` argument. KUnit calls this function + repeatedly until it returns ``NULL``, which signifies that a parameterized + test ended. + + Below is an example of how it works: + +.. code-block:: c + + #define MAX_TEST_BUFFER_SIZE 8 + + // Example generator function. It produces a sequence of buffer sizes that + // are powers of two, starting at 1 (e.g., 1, 2, 4, 8). + static const void *buffer_size_gen_params(struct kunit *test, const void *prev, char *desc) + { + long prev_buffer_size = (long)prev; + long next_buffer_size = 1; // Start with an initial size of 1. + + // Stop generating parameters if the limit is reached or exceeded. + if (prev_buffer_size >= MAX_TEST_BUFFER_SIZE) + return NULL; + + // For subsequent calls, calculate the next size by doubling the previous one. + if (prev) + next_buffer_size = prev_buffer_size << 1; + + return (void *)next_buffer_size; + } + + // Simple test to validate that kunit_kzalloc provides zeroed memory. + static void buffer_zero_test(struct kunit *test) + { + long buffer_size = (long)test->param_value; + // Use kunit_kzalloc to allocate a zero-initialized buffer. This makes the + // memory "parameter run managed," meaning it's automatically cleaned up at + // the end of each parameter run. + int *buf = kunit_kzalloc(test, buffer_size * sizeof(int), GFP_KERNEL); + + // Ensure the allocation was successful. + KUNIT_ASSERT_NOT_NULL(test, buf); + + // Loop through the buffer and confirm every element is zero. + for (int i = 0; i < buffer_size; i++) + KUNIT_EXPECT_EQ(test, buf[i], 0); + } + + static struct kunit_case buffer_test_cases[] = { + KUNIT_CASE_PARAM(buffer_zero_test, buffer_size_gen_params), + {} + }; + +Runtime Parameter Array Registration in the Init Function: + + For scenarios where you might need to initialize a parameterized test, you + can directly register a parameter array to the parameterized test context. + + To do this, you must pass the parameterized test context, the array itself, + the array size, and a ``get_description()`` function to the + ``kunit_register_params_array()`` macro. This macro populates + ``struct kunit_params`` within the parameterized test context, effectively + storing a parameter array object. The ``get_description()`` function will + be used for populating parameter descriptions and has the following signature: + ``void (*)(struct kunit *test, const void *param, char *desc)``. Note that it + also has access to the parameterized test context. + + .. important:: + When using this way to register a parameter array, you will need to + manually pass ``kunit_array_gen_params()`` as the generator function to + ``KUNIT_CASE_PARAM_WITH_INIT``. ``kunit_array_gen_params()`` is a KUnit + helper that will use the registered array to generate the parameters. + + If needed, instead of passing the KUnit helper, you can also pass your + own custom generator function that utilizes the parameter array. To + access the parameter array from within the parameter generator + function use ``test->params_array.params``. + + The ``kunit_register_params_array()`` macro should be called within a + ``param_init()`` function that initializes the parameterized test and has + the following signature ``int (*)(struct kunit *test)``. For a detailed + explanation of this mechanism please refer to the "Adding Shared Resources" + section that is after this one. This method supports registering both + dynamically built and static parameter arrays. + + The code snippet below shows the ``example_param_init_dynamic_arr`` test that + utilizes ``make_fibonacci_params()`` to create a dynamic array, which is then + registered using ``kunit_register_params_array()``. To see the full code + please refer to lib/kunit/kunit-example-test.c. + +.. code-block:: c + + /* + * Example of a parameterized test param_init() function that registers a dynamic + * array of parameters. + */ + static int example_param_init_dynamic_arr(struct kunit *test) + { + size_t seq_size; + int *fibonacci_params; + + kunit_info(test, "initializing parameterized test\n"); + + seq_size = 6; + fibonacci_params = make_fibonacci_params(test, seq_size); + if (!fibonacci_params) + return -ENOMEM; + /* + * Passes the dynamic parameter array information to the parameterized test + * context struct kunit. The array and its metadata will be stored in + * test->parent->params_array. The array itself will be located in + * params_data.params. + */ + kunit_register_params_array(test, fibonacci_params, seq_size, + example_param_dynamic_arr_get_desc); + return 0; + } + + static struct kunit_case example_test_cases[] = { + /* + * Note how we pass kunit_array_gen_params() to use the array we + * registered in example_param_init_dynamic_arr() to generate + * parameters. + */ + KUNIT_CASE_PARAM_WITH_INIT(example_params_test_with_init_dynamic_arr, + kunit_array_gen_params, + example_param_init_dynamic_arr, + example_param_exit_dynamic_arr), + {} + }; + +Adding Shared Resources +^^^^^^^^^^^^^^^^^^^^^^^ +All parameter runs in this framework hold a reference to the parameterized test +context, which can be accessed using the parent ``struct kunit`` pointer. The +parameterized test context is not used to execute any test logic itself; instead, +it serves as a container for shared resources. + +It's possible to add resources to share between parameter runs within a +parameterized test by using ``KUNIT_CASE_PARAM_WITH_INIT``, to which you pass +custom ``param_init()`` and ``param_exit()`` functions. These functions run once +before and once after the parameterized test, respectively. + +The ``param_init()`` function, with the signature ``int (*)(struct kunit *test)``, +can be used for adding resources to the ``resources`` or ``priv`` fields of +the parameterized test context, registering the parameter array, and any other +initialization logic. + +The ``param_exit()`` function, with the signature ``void (*)(struct kunit *test)``, +can be used to release any resources that were not parameterized test managed (i.e. +not automatically cleaned up after the parameterized test ends) and for any other +exit logic. + +Both ``param_init()`` and ``param_exit()`` are passed the parameterized test +context behind the scenes. However, the test case function receives the parameter +run context. Therefore, to manage and access shared resources from within a test +case function, you must use ``test->parent``. + +For instance, finding a shared resource allocated by the Resource API requires +passing ``test->parent`` to ``kunit_find_resource()``. This principle extends to +all other APIs that might be used in the test case function, including +``kunit_kzalloc()``, ``kunit_kmalloc_array()``, and others (see +Documentation/dev-tools/kunit/api/test.rst and the +Documentation/dev-tools/kunit/api/resource.rst). + +.. note:: + The ``suite->init()`` function, which executes before each parameter run, + receives the parameter run context. Therefore, any resources set up in + ``suite->init()`` are cleaned up after each parameter run. + +The code below shows how you can add the shared resources. Note that this code +utilizes the Resource API, which you can read more about here: +Documentation/dev-tools/kunit/api/resource.rst. To see the full version of this +code please refer to lib/kunit/kunit-example-test.c. + +.. code-block:: c + + static int example_resource_init(struct kunit_resource *res, void *context) + { + ... /* Code that allocates memory and stores context in res->data. */ + } + + /* This function deallocates memory for the kunit_resource->data field. */ + static void example_resource_free(struct kunit_resource *res) + { + kfree(res->data); + } + + /* This match function locates a test resource based on defined criteria. */ + static bool example_resource_alloc_match(struct kunit *test, struct kunit_resource *res, + void *match_data) + { + return res->data && res->free == example_resource_free; + } + + /* Function to initialize the parameterized test. */ + static int example_param_init(struct kunit *test) + { + int ctx = 3; /* Data to be stored. */ + void *data = kunit_alloc_resource(test, example_resource_init, + example_resource_free, + GFP_KERNEL, &ctx); + if (!data) + return -ENOMEM; + kunit_register_params_array(test, example_params_array, + ARRAY_SIZE(example_params_array)); + return 0; + } + + /* Example test that uses shared resources in test->resources. */ + static void example_params_test_with_init(struct kunit *test) + { + int threshold; + const struct example_param *param = test->param_value; + /* Here we pass test->parent to access the parameterized test context. */ + struct kunit_resource *res = kunit_find_resource(test->parent, + example_resource_alloc_match, + NULL); + + threshold = *((int *)res->data); + KUNIT_ASSERT_LE(test, param->value, threshold); + kunit_put_resource(res); + } + + static struct kunit_case example_test_cases[] = { + KUNIT_CASE_PARAM_WITH_INIT(example_params_test_with_init, kunit_array_gen_params, + example_param_init, NULL), + {} + }; + +As an alternative to using the KUnit Resource API for sharing resources, you can +place them in ``test->parent->priv``. This serves as a more lightweight method +for resource storage, best for scenarios where complex resource management is +not required. + +As stated previously ``param_init()`` and ``param_exit()`` get the parameterized +test context. So, you can directly use ``test->priv`` within ``param_init/exit`` +to manage shared resources. However, from within the test case function, you must +navigate up to the parent ``struct kunit`` i.e. the parameterized test context. +Therefore, you need to use ``test->parent->priv`` to access those same +resources. + +The resources placed in ``test->parent->priv`` will need to be allocated in +memory to persist across the parameter runs. If memory is allocated using the +KUnit memory allocation APIs (described more in the "Allocating Memory" section +below), you won't need to worry about deallocation. The APIs will make the memory +parameterized test 'managed', ensuring that it will automatically get cleaned up +after the parameterized test concludes. + +The code below demonstrates example usage of the ``priv`` field for shared +resources: + +.. code-block:: c + + static const struct example_param { + int value; + } example_params_array[] = { + { .value = 3, }, + { .value = 2, }, + { .value = 1, }, + { .value = 0, }, + }; + + /* Initialize the parameterized test context. */ + static int example_param_init_priv(struct kunit *test) + { + int ctx = 3; /* Data to be stored. */ + int arr_size = ARRAY_SIZE(example_params_array); + + /* + * Allocate memory using kunit_kzalloc(). Since the `param_init` + * function receives the parameterized test context, this memory + * allocation will be scoped to the lifetime of the parameterized test. + */ + test->priv = kunit_kzalloc(test, sizeof(int), GFP_KERNEL); + + /* Assign the context value to test->priv.*/ + *((int *)test->priv) = ctx; + + /* Register the parameter array. */ + kunit_register_params_array(test, example_params_array, arr_size, NULL); + return 0; + } + + static void example_params_test_with_init_priv(struct kunit *test) + { + int threshold; + const struct example_param *param = test->param_value; + + /* By design, test->parent will not be NULL. */ + KUNIT_ASSERT_NOT_NULL(test, test->parent); + + /* Here we use test->parent->priv to access the shared resource. */ + threshold = *(int *)test->parent->priv; + + KUNIT_ASSERT_LE(test, param->value, threshold); + } + + static struct kunit_case example_tests[] = { + KUNIT_CASE_PARAM_WITH_INIT(example_params_test_with_init_priv, + kunit_array_gen_params, + example_param_init_priv, NULL), + {} + }; + Allocating Memory ----------------- diff --git a/Documentation/devicetree/bindings/.yamllint b/Documentation/devicetree/bindings/.yamllint index fea5231e1320..532799501800 100644 --- a/Documentation/devicetree/bindings/.yamllint +++ b/Documentation/devicetree/bindings/.yamllint @@ -4,7 +4,7 @@ rules: quoted-strings: required: only-when-needed extra-allowed: - - '[$^,[]' + - '[$^[]' - '^/$' line-length: # 80 chars should be enough, but don't fail if a line is longer diff --git a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt b/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt deleted file mode 100644 index f5ad0ff69fae..000000000000 --- a/Documentation/devicetree/bindings/arm/altera/socfpga-sdram-edac.txt +++ /dev/null @@ -1,15 +0,0 @@ -Altera SOCFPGA SDRAM Error Detection & Correction [EDAC] -The EDAC accesses a range of registers in the SDRAM controller. - -Required properties: -- compatible : should contain "altr,sdram-edac" or "altr,sdram-edac-a10" -- altr,sdr-syscon : phandle of the sdr module -- interrupts : Should contain the SDRAM ECC IRQ in the - appropriate format for the IRQ controller. - -Example: - sdramedac { - compatible = "altr,sdram-edac"; - altr,sdr-syscon = <&sdr>; - interrupts = <0 39 4>; - }; diff --git a/Documentation/devicetree/bindings/arm/apple.yaml b/Documentation/devicetree/bindings/arm/apple.yaml index da60e9de1cfb..5c2629ec3d4c 100644 --- a/Documentation/devicetree/bindings/arm/apple.yaml +++ b/Documentation/devicetree/bindings/arm/apple.yaml @@ -92,10 +92,11 @@ description: | Devices based on the "M2" SoC: - MacBook Air (M2, 2022) + - MacBook Air (15-inch, M2, 2023) - MacBook Pro (13-inch, M2, 2022) - Mac mini (M2, 2023) - And devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: + Devices based on the "M1 Pro", "M1 Max" and "M1 Ultra" SoCs: - MacBook Pro (14-inch, M1 Pro, 2021) - MacBook Pro (14-inch, M1 Max, 2021) @@ -104,6 +105,17 @@ description: | - Mac Studio (M1 Max, 2022) - Mac Studio (M1 Ultra, 2022) + Devices based on the "M2 Pro", "M2 Max" and "M2 Ultra" SoCs: + + - MacBook Pro (14-inch, M2 Pro, 2023) + - MacBook Pro (14-inch, M2 Max, 2023) + - MacBook Pro (16-inch, M2 Pro, 2023) + - MacBook Pro (16-inch, M2 Max, 2023) + - Mac mini (M2 Pro, 2023) + - Mac Studio (M2 Max, 2023) + - Mac Studio (M2 Ultra, 2023) + - Mac Pro (M2 Ultra, 2023) + The compatible property should follow this format: compatible = "apple,<targettype>", "apple,<socid>", "apple,arm-platform"; @@ -279,6 +291,7 @@ properties: items: - enum: - apple,j413 # MacBook Air (M2, 2022) + - apple,j415 # MacBook Air (15-inch, M2, 2023) - apple,j473 # Mac mini (M2, 2023) - apple,j493 # MacBook Pro (13-inch, M2, 2022) - const: apple,t8112 @@ -308,6 +321,32 @@ properties: - const: apple,t6002 - const: apple,arm-platform + - description: Apple M2 Pro SoC based platforms + items: + - enum: + - apple,j414s # MacBook Pro (14-inch, M2 Pro, 2023) + - apple,j416s # MacBook Pro (16-inch, M2 Pro, 2023) + - apple,j474s # Mac mini (M2 Pro, 2023) + - const: apple,t6020 + - const: apple,arm-platform + + - description: Apple M2 Max SoC based platforms + items: + - enum: + - apple,j414c # MacBook Pro (14-inch, M2 Max, 2023) + - apple,j416c # MacBook Pro (16-inch, M2 Max, 2023) + - apple,j475c # Mac Studio (M2 Max, 2023) + - const: apple,t6021 + - const: apple,arm-platform + + - description: Apple M2 Ultra SoC based platforms + items: + - enum: + - apple,j180d # Mac Pro (M2 Ultra, 2023) + - apple,j475d # Mac Studio (M2 Ultra, 2023) + - const: apple,t6022 + - const: apple,arm-platform + additionalProperties: true ... diff --git a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml index 5001f4d5a0dc..b88f41a225a3 100644 --- a/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml +++ b/Documentation/devicetree/bindings/arm/apple/apple,pmgr.yaml @@ -20,19 +20,26 @@ properties: pattern: "^power-management@[0-9a-f]+$" compatible: - items: - - enum: - - apple,s5l8960x-pmgr - - apple,t7000-pmgr - - apple,s8000-pmgr - - apple,t8010-pmgr - - apple,t8015-pmgr - - apple,t8103-pmgr - - apple,t8112-pmgr - - apple,t6000-pmgr - - const: apple,pmgr - - const: syscon - - const: simple-mfd + oneOf: + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-pmgr + - apple,t7000-pmgr + - apple,s8000-pmgr + - apple,t8010-pmgr + - apple,t8015-pmgr + - apple,t8103-pmgr + - apple,t8112-pmgr + - apple,t6000-pmgr + - const: apple,pmgr + - const: syscon + - const: simple-mfd + - items: + - const: apple,t6020-pmgr + - const: apple,t8103-pmgr + - const: syscon + - const: simple-mfd reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml index 8dd6b6446394..4cdca5320544 100644 --- a/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml +++ b/Documentation/devicetree/bindings/arm/arm,vexpress-juno.yaml @@ -103,8 +103,9 @@ properties: - const: arm,juno-r2 - const: arm,juno - const: arm,vexpress - - description: Arm AEMv8a Versatile Express Real-Time System Model - (VE RTSM) is a programmers view of the Versatile Express with Arm + - description: Arm AEMv8a (Architecture Envelope Model) + Versatile Express Real-Time System Model (VE RTSM) + is a programmers view of the Versatile Express with Arm v8A hardware. See ARM DUI 0575D. items: - const: arm,rtsm_ve,aemv8a @@ -139,7 +140,7 @@ patternProperties: the connection between the motherboard and any tiles. Sometimes the compatible is placed directly under this node, sometimes it is placed in a subnode named "motherboard-bus". Sometimes the compatible includes - "arm,vexpress,v2?-p1" sometimes (on software models) is is just + "arm,vexpress,v2?-p1" sometimes (on software models) it is just "simple-bus". If the compatible is placed in the "motherboard-bus" node, it is stricter and always has two compatibles. type: object diff --git a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml index 456dbf7b5ec8..aedefca7cf4a 100644 --- a/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml +++ b/Documentation/devicetree/bindings/arm/aspeed/aspeed.yaml @@ -46,6 +46,7 @@ properties: - facebook,yamp-bmc - facebook,yosemitev2-bmc - facebook,wedge400-bmc + - facebook,wedge400-data64-bmc - hxt,stardragon4800-rep2-bmc - ibm,mihawk-bmc - ibm,mowgli-bmc @@ -81,9 +82,12 @@ properties: - asus,x4tf-bmc - facebook,bletchley-bmc - facebook,catalina-bmc + - facebook,clemente-bmc - facebook,cloudripper-bmc + - facebook,darwin-bmc - facebook,elbert-bmc - facebook,fuji-bmc + - facebook,fuji-data64-bmc - facebook,greatlakes-bmc - facebook,harma-bmc - facebook,minerva-cmc diff --git a/Documentation/devicetree/bindings/arm/axis.txt b/Documentation/devicetree/bindings/arm/axis.txt deleted file mode 100644 index ebd33a88776f..000000000000 --- a/Documentation/devicetree/bindings/arm/axis.txt +++ /dev/null @@ -1,13 +0,0 @@ -Axis Communications AB -ARTPEC series SoC Device Tree Bindings - -ARTPEC-6 ARM SoC -================ - -Required root node properties: -- compatible = "axis,artpec6"; - -ARTPEC-6 Development board: ---------------------------- -Required root node properties: -- compatible = "axis,artpec6-dev-board", "axis,artpec6"; diff --git a/Documentation/devicetree/bindings/arm/axis.yaml b/Documentation/devicetree/bindings/arm/axis.yaml new file mode 100644 index 000000000000..63e9aca85db7 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/axis.yaml @@ -0,0 +1,36 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/axis.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Axis ARTPEC platforms + +maintainers: + - Jesper Nilsson <jesper.nilsson@axis.com> + - Lars Persson <lars.persson@axis.com> + - linux-arm-kernel@axis.com + +description: | + ARM platforms using SoCs designed by Axis branded as "ARTPEC". + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - description: Axis ARTPEC-6 SoC board + items: + - enum: + - axis,artpec6-dev-board + - const: axis,artpec6 + + - description: Axis ARTPEC-8 SoC board + items: + - enum: + - axis,artpec8-grizzly + - const: axis,artpec8 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml index d925e7a3b5ef..f47d74a5b0b6 100644 --- a/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml +++ b/Documentation/devicetree/bindings/arm/bcm/brcm,bcm4708.yaml @@ -25,6 +25,7 @@ properties: - enum: - asus,rt-ac56u - asus,rt-ac68u + - buffalo,wxr-1750dhp - buffalo,wzr-1166dhp - buffalo,wzr-1166dhp2 - buffalo,wzr-1750dhp diff --git a/Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml b/Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml new file mode 100644 index 000000000000..d7c813118c1c --- /dev/null +++ b/Documentation/devicetree/bindings/arm/cavium,thunder-88xx.yaml @@ -0,0 +1,19 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/cavium,thunder-88xx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Cavium Thunder 88xx SoC + +maintainers: + - Robert Richter <rric@kernel.org> + +properties: + $nodename: + const: '/' + compatible: + items: + - const: cavium,thunder-88xx + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder.txt b/Documentation/devicetree/bindings/arm/cavium-thunder.txt deleted file mode 100644 index 6f63a5866902..000000000000 --- a/Documentation/devicetree/bindings/arm/cavium-thunder.txt +++ /dev/null @@ -1,10 +0,0 @@ -Cavium Thunder platform device tree bindings --------------------------------------------- - -Boards with Cavium's Thunder SoC shall have following properties. - -Root Node ---------- -Required root node properties: - - - compatible = "cavium,thunder-88xx"; diff --git a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt b/Documentation/devicetree/bindings/arm/cavium-thunder2.txt deleted file mode 100644 index dc5dd65cbce7..000000000000 --- a/Documentation/devicetree/bindings/arm/cavium-thunder2.txt +++ /dev/null @@ -1,8 +0,0 @@ -Cavium ThunderX2 CN99XX platform tree bindings ----------------------------------------------- - -Boards with Cavium ThunderX2 CN99XX SoC shall have the root property: - compatible = "cavium,thunderx2-cn9900", "brcm,vulcan-soc"; - -These SoC uses the "cavium,thunder2" core which will be compatible -with "brcm,vulcan". diff --git a/Documentation/devicetree/bindings/arm/cpus.yaml b/Documentation/devicetree/bindings/arm/cpus.yaml index 5bd517befb68..736b7ab1bd0a 100644 --- a/Documentation/devicetree/bindings/arm/cpus.yaml +++ b/Documentation/devicetree/bindings/arm/cpus.yaml @@ -80,6 +80,8 @@ properties: compatible: enum: + - apm,potenza + - apm,strega - apple,avalanche - apple,blizzard - apple,cyclone @@ -121,6 +123,10 @@ properties: - arm,arm1176jzf-s - arm,arm11mpcore - arm,armv8 # Only for s/w models + - arm,c1-nano + - arm,c1-premium + - arm,c1-pro + - arm,c1-ultra - arm,cortex-a5 - arm,cortex-a7 - arm,cortex-a8 @@ -143,11 +149,14 @@ properties: - arm,cortex-a78 - arm,cortex-a78ae - arm,cortex-a78c + - arm,cortex-a320 - arm,cortex-a510 - arm,cortex-a520 + - arm,cortex-a520ae - arm,cortex-a710 - arm,cortex-a715 - arm,cortex-a720 + - arm,cortex-a720ae - arm,cortex-a725 - arm,cortex-m0 - arm,cortex-m0+ @@ -345,14 +354,37 @@ properties: deprecated: true description: Use 'cpu-supply' instead + pu-supply: + deprecated: true + description: Only for i.MX6Q/DL/SL SoCs. + + soc-supply: + deprecated: true + description: Only for i.MX6/7 Soc. + sram-supply: deprecated: true description: Use 'mem-supply' instead + fsl,soc-operating-points: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + description: FSL i.MX6 Soc operation-points when change cpu frequency + deprecated: true + items: + items: + - description: Frequency in kHz + - description: Voltage for OPP in uV + mediatek,cci: $ref: /schemas/types.yaml#/definitions/phandle description: Link to Mediatek Cache Coherent Interconnect + edac-enabled: + $ref: /schemas/types.yaml#/definitions/flag + description: + A72 CPUs support Error Detection And Correction (EDAC) on their L1 and + L2 caches. This flag marks this function as usable. + qcom,saw: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -400,6 +432,17 @@ allOf: - $ref: /schemas/cpu.yaml# - $ref: /schemas/opp/opp-v1.yaml# - if: + not: + properties: + compatible: + contains: + const: arm,cortex-a72 + then: + # Allow edac-enabled only for Cortex A72 + properties: + edac-enabled: false + + - if: # If the enable-method property contains one of those values properties: enable-method: diff --git a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml index 3b26040f8f18..9d377e193c12 100644 --- a/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml +++ b/Documentation/devicetree/bindings/arm/freescale/fsl,imx7ulp-pm.yaml @@ -28,6 +28,14 @@ properties: reg: maxItems: 1 + clocks: + maxItems: 2 + + clock-names: + items: + - const: divcore + - const: hsrun_divcore + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/arm/fsl.yaml b/Documentation/devicetree/bindings/arm/fsl.yaml index a3e9f9e0735a..00cdf490b062 100644 --- a/Documentation/devicetree/bindings/arm/fsl.yaml +++ b/Documentation/devicetree/bindings/arm/fsl.yaml @@ -1112,6 +1112,7 @@ properties: - skov,imx8mp-skov-revb-mi1010ait-1cp1 # SKOV i.MX8MP climate control with 10.1" panel - skov,imx8mp-skov-revc-bd500 # SKOV i.MX8MP climate control with LED frontplate - skov,imx8mp-skov-revc-tian-g07017 # SKOV i.MX8MP climate control with 7" panel + - ultratronik,imx8mp-ultra-mach-sbc # Ultratronik SBC i.MX8MP based board - ysoft,imx8mp-iota2-lumpy # Y Soft i.MX8MP IOTA2 Lumpy Board - const: fsl,imx8mp @@ -1200,6 +1201,24 @@ properties: - const: polyhex,imx8mp-debix-som-a # Polyhex Debix SOM A - const: fsl,imx8mp + - description: SolidRun i.MX8MP SoM based boards + items: + - enum: + - solidrun,imx8mp-cubox-m # SolidRun i.MX8MP SoM on CuBox-M + - solidrun,imx8mp-hummingboard-mate # SolidRun i.MX8MP SoM on HummingBoard Mate + - solidrun,imx8mp-hummingboard-pro # SolidRun i.MX8MP SoM on HummingBoard Pro + - solidrun,imx8mp-hummingboard-pulse # SolidRun i.MX8MP SoM on HummingBoard Pulse + - solidrun,imx8mp-hummingboard-ripple # SolidRun i.MX8MP SoM on HummingBoard Ripple + - const: solidrun,imx8mp-sr-som + - const: fsl,imx8mp + + - description: TechNexion EDM-G-IMX8M-PLUS SoM based boards + items: + - enum: + - technexion,edm-g-imx8mp-wb # TechNexion EDM-G-IMX8MP SOM on WB-EDM-G + - const: technexion,edm-g-imx8mp # TechNexion EDM-G-IMX8MP SOM + - const: fsl,imx8mp + - description: Toradex Boards with SMARC iMX8M Plus Modules items: - const: toradex,smarc-imx8mp-dev # Toradex SMARC iMX8M Plus on Toradex SMARC Development Board @@ -1382,9 +1401,16 @@ properties: - description: i.MX8ULP based Boards items: - enum: + - fsl,imx8ulp-9x9-evk # i.MX8ULP EVK9 Board - fsl,imx8ulp-evk # i.MX8ULP EVK Board - const: fsl,imx8ulp + - description: i.MX91 based Boards + items: + - enum: + - fsl,imx91-11x11-evk # i.MX91 11x11 EVK Board + - const: fsl,imx91 + - description: i.MX93 based Boards items: - enum: @@ -1426,6 +1452,24 @@ properties: - const: fsl,imxrt1170 - description: + TQMa91xxLA and TQMa91xxCA are two series of feature compatible SOM + using NXP i.MX91 SOC in 11x11 mm package. + TQMa91xxLA is designed to be soldered on different carrier boards. + TQMa91xxCA is a compatible variant using board to board connectors. + All SOM and CPU variants use the same device tree hence only one + compatible is needed. Bootloader disables all features not present + in the assembled SOC. + MBa91xxCA mainboard can be used as starterkit for the SOM + soldered on an adapter board or for the connector variant + MBa91xxLA mainboard is a single board computer using the solderable + SOM variant + items: + - enum: + - tq,imx91-tqma9131-mba91xxca # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM on MBa91xxCA + - const: tq,imx91-tqma9131 # TQ-Systems GmbH i.MX91 TQMa91xxCA/LA SOM + - const: fsl,imx91 + + - description: TQMa93xxLA and TQMa93xxCA are two series of feature compatible SOM using NXP i.MX93 SOC in 11x11 mm package. TQMa93xxLA is designed to be soldered on different carrier boards. @@ -1537,6 +1581,12 @@ properties: - fsl,ls1012a-qds - const: fsl,ls1012a + - description: TQ Systems TQMLS12AL SoM on MBLS1012AL board + items: + - const: tq,ls1012a-tqmls1012al-mbls1012al + - const: tq,ls1012a-tqmls1012al + - const: fsl,ls1012a + - description: LS1021A based Boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml index d60792b1d995..b7b430896596 100644 --- a/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml +++ b/Documentation/devicetree/bindings/arm/intel-ixp4xx.yaml @@ -16,6 +16,8 @@ properties: oneOf: - items: - enum: + - actiontec,mi424wr-ac + - actiontec,mi424wr-d - adieng,coyote - arcom,vulcan - dlink,dsm-g600-a diff --git a/Documentation/devicetree/bindings/arm/keystone/keystone.txt b/Documentation/devicetree/bindings/arm/keystone/keystone.txt deleted file mode 100644 index f310bad04483..000000000000 --- a/Documentation/devicetree/bindings/arm/keystone/keystone.txt +++ /dev/null @@ -1,42 +0,0 @@ -TI Keystone Platforms Device Tree Bindings ------------------------------------------------ - -Boards with Keystone2 based devices (TCI66xxK2H) SOC shall have the -following properties. - -Required properties: - - compatible: All TI specific devices present in Keystone SOC should be in - the form "ti,keystone-*". Generic devices like gic, arch_timers, ns16550 - type UART should use the specified compatible for those devices. - -SoC families: - -- Keystone 2 generic SoC: - compatible = "ti,keystone" - -SoCs: - -- Keystone 2 Hawking/Kepler - compatible = "ti,k2hk", "ti,keystone" -- Keystone 2 Lamarr - compatible = "ti,k2l", "ti,keystone" -- Keystone 2 Edison - compatible = "ti,k2e", "ti,keystone" -- K2G - compatible = "ti,k2g", "ti,keystone" - -Boards: -- Keystone 2 Hawking/Kepler EVM - compatible = "ti,k2hk-evm", "ti,k2hk", "ti,keystone" - -- Keystone 2 Lamarr EVM - compatible = "ti,k2l-evm", "ti, k2l", "ti,keystone" - -- Keystone 2 Edison EVM - compatible = "ti,k2e-evm", "ti,k2e", "ti,keystone" - -- K2G EVM - compatible = "ti,k2g-evm", "ti,k2g", "ti-keystone" - -- K2G Industrial Communication Engine EVM - compatible = "ti,k2g-ice", "ti,k2g", "ti-keystone" diff --git a/Documentation/devicetree/bindings/arm/marvell,berlin.yaml b/Documentation/devicetree/bindings/arm/marvell,berlin.yaml new file mode 100644 index 000000000000..4e8442980dcb --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell,berlin.yaml @@ -0,0 +1,45 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell,berlin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Synaptics/Marvell Berlin SoC + +maintainers: + - Jisheng Zhang <jszhang@kernel.org> + +description: + According to https://www.synaptics.com/company/news/conexant-marvell + Synaptics has acquired the Multimedia Solutions Business of Marvell, so + Berlin SoCs are now Synaptics' SoCs. + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sony,nsz-gs7 + - const: marvell,berlin2 + - const: marvell,berlin + - items: + - enum: + - google,chromecast + - valve,steamlink + - const: marvell,berlin2cd + - const: marvell,berlin + - items: + - enum: + - marvell,berlin2q-dmp + - const: marvell,berlin2q + - const: marvell,berlin + - items: + - enum: + - marvell,berlin4ct-dmp + - marvell,berlin4ct-stb + - const: marvell,berlin4ct + - const: marvell,berlin + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt b/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt deleted file mode 100644 index 64e8c73fc5ab..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/98dx3236.txt +++ /dev/null @@ -1,23 +0,0 @@ -Marvell 98DX3236, 98DX3336 and 98DX4251 Platforms Device Tree Bindings ----------------------------------------------------------------------- - -Boards with a SoC of the Marvell 98DX3236, 98DX3336 and 98DX4251 families -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx3236" - -In addition, boards using the Marvell 98DX3336 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx3336" - -In addition, boards using the Marvell 98DX4251 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp-98dx4251" diff --git a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt index c83245065d44..72de11bd2ef0 100644 --- a/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt @@ -115,45 +115,6 @@ ap_syscon: system-controller@6f4000 { SYSTEM CONTROLLER 1 =================== -Thermal: --------- - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal*.yaml - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -It is possible to setup an overheat interrupt by giving at least one -critical point to any subnode of the thermal-zone node. - -Required properties: -- compatible: must be one of: - * marvell,armada-ap806-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- interrupts: overheat interrupt handle. Should point to line 18 of the - SEI irqchip. See interrupt-controller/interrupts.txt -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel, while positive - IDs refer to each CPU. - -Example: -ap_syscon1: system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - ap_thermal: thermal-sensor@80 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x80 0x10>; - interrupt-parent = <&sei>; - interrupts = <18>; - #thermal-sensor-cells = <1>; - }; -}; - Cluster clocks: --------------- diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt b/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt deleted file mode 100644 index c6ed90ea6e17..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-370-xp.txt +++ /dev/null @@ -1,24 +0,0 @@ -Marvell Armada 370 and Armada XP Platforms Device Tree Bindings ---------------------------------------------------------------- - -Boards with a SoC of the Marvell Armada 370 and Armada XP families -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,armada-370-xp" - -In addition, boards using the Marvell Armada 370 SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armada370" - -In addition, boards using the Marvell Armada XP SoC shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armadaxp" - diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt b/Documentation/devicetree/bindings/arm/marvell/armada-375.txt deleted file mode 100644 index 867d0b80cb8f..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-375.txt +++ /dev/null @@ -1,9 +0,0 @@ -Marvell Armada 375 Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 375 family shall have the -following property: - -Required root node property: - -compatible: must contain "marvell,armada375" diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml index 51e1386f0e01..b2f4fe81b97c 100644 --- a/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml +++ b/Documentation/devicetree/bindings/arm/marvell/armada-37xx.yaml @@ -23,6 +23,7 @@ properties: - marvell,armada-3720-db - methode,edpu - methode,udpu + - ripe,atlas-v5 - const: marvell,armada3720 - const: marvell,armada3710 diff --git a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt b/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt deleted file mode 100644 index 89468664f6ea..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/armada-39x.txt +++ /dev/null @@ -1,31 +0,0 @@ -Marvell Armada 39x Platforms Device Tree Bindings -------------------------------------------------- - -Boards with a SoC of the Marvell Armada 39x family shall have the -following property: - -Required root node property: - - - compatible: must contain "marvell,armada390" - -In addition, boards using the Marvell Armada 395 SoC shall have the -following property before the common "marvell,armada390" one: - -Required root node property: - -compatible: must contain "marvell,armada395" - -Example: - -compatible = "marvell,a395-gp", "marvell,armada395", "marvell,armada390"; - -Boards using the Marvell Armada 398 SoC shall have the following -property before the common "marvell,armada390" one: - -Required root node property: - -compatible: must contain "marvell,armada398" - -Example: - -compatible = "marvell,a398-db", "marvell,armada398", "marvell,armada390"; diff --git a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt index 9d5d70c98058..54ff9f218328 100644 --- a/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt +++ b/Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt @@ -189,46 +189,3 @@ CP110_LABEL(syscon0): system-controller@440000 { }; }; - -SYSTEM CONTROLLER 1 -=================== - -Thermal: --------- - -The thermal IP can probe the temperature all around the processor. It -may feature several channels, each of them wired to one sensor. - -It is possible to setup an overheat interrupt by giving at least one -critical point to any subnode of the thermal-zone node. - -For common binding part and usage, refer to -Documentation/devicetree/bindings/thermal/thermal*.yaml - -Required properties: -- compatible: must be one of: - * marvell,armada-cp110-thermal -- reg: register range associated with the thermal functions. - -Optional properties: -- interrupts-extended: overheat interrupt handle. Should point to - a line of the ICU-SEI irqchip (116 is what is usually used by the - firmware). The ICU-SEI will redirect towards interrupt line #37 of the - AP SEI which is shared across all CPs. - See interrupt-controller/interrupts.txt -- #thermal-sensor-cells: shall be <1> when thermal-zones subnodes refer - to this IP and represents the channel ID. There is one sensor per - channel. O refers to the thermal IP internal channel. - -Example: -CP110_LABEL(syscon1): system-controller@6f8000 { - compatible = "syscon", "simple-mfd"; - reg = <0x6f8000 0x1000>; - - CP110_LABEL(thermal): thermal-sensor@70 { - compatible = "marvell,armada-cp110-thermal"; - reg = <0x70 0x10>; - interrupts-extended = <&CP110_LABEL(icu_sei) 116 IRQ_TYPE_LEVEL_HIGH>; - #thermal-sensor-cells = <1>; - }; -}; diff --git a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt deleted file mode 100644 index 98cce9a653eb..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/kirkwood.txt +++ /dev/null @@ -1,27 +0,0 @@ -Marvell Kirkwood Platforms Device Tree Bindings ------------------------------------------------ - -Boards with a SoC of the Marvell Kirkwood -shall have the following property: - -Required root node property: - -compatible: must contain "marvell,kirkwood"; - -In order to support the kirkwood cpufreq driver, there must be a node -cpus/cpu@0 with three clocks, "cpu_clk", "ddrclk" and "powersave", -where the "powersave" clock is a gating clock used to switch the CPU -between the "cpu_clk" and the "ddrclk". - -Example: - - cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - device_type = "cpu"; - compatible = "marvell,sheeva-88SV131"; - clocks = <&core_clk 1>, <&core_clk 3>, <&gate_clk 11>; - clock-names = "cpu_clk", "ddrclk", "powersave"; - }; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml new file mode 100644 index 000000000000..e65eadfbd097 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,armada-370-xp.yaml @@ -0,0 +1,78 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,armada-370-xp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 370 and Armada XP platforms + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - ctera,c200-v2 + - dlink,dns327l + - globalscale,mirabox + - netgear,readynas-102 + - netgear,readynas-104 + - marvell,a370-db + - marvell,a370-rd + - seagate,dart-2 + - seagate,dart-4 + - seagate,cumulus-max + - seagate,cumulus + - synology,ds213j + - const: marvell,armada370 + - const: marvell,armada-370-xp + + - items: + - enum: + - mikrotik,crs305-1g-4s + - mikrotik,crs326-24g-2s + - mikrotik,crs328-4c-20s-4s + - const: marvell,armadaxp-98dx3236 + - const: marvell,armada-370-xp + + - items: + - const: marvell,db-xc3-24g4xg + - const: marvell,armadaxp-98dx3336 + - const: marvell,armada-370-xp + + - items: + - const: marvell,db-dxbc2 + - const: marvell,armadaxp-98dx4251 + - const: marvell,armada-370-xp + + - items: + - enum: + - lenovo,ix4-300d + - linksys,mamba + - marvell,rd-axpwifiap + - netgear,readynas-2120 + - synology,ds414 + - const: marvell,armadaxp-mv78230 + - const: marvell,armadaxp + - const: marvell,armada-370-xp + + - items: + - const: plathome,openblocks-ax3-4 + - const: marvell,armadaxp-mv78260 + - const: marvell,armadaxp + - const: marvell,armada-370-xp + + - items: + - enum: + - marvell,axp-db + - marvell,axp-gp + - marvell,axp-matrix + - const: marvell,armadaxp-mv78460 + - const: marvell,armadaxp + - const: marvell,armada-370-xp + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml new file mode 100644 index 000000000000..81c33e46fecc --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,armada375.yaml @@ -0,0 +1,21 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,armada375.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 375 Platform + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + items: + - const: marvell,a375-db + - const: marvell,armada375 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml new file mode 100644 index 000000000000..5ff6a5439525 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,armada390.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,armada390.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 39x Platforms + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - const: marvell,a390-db + - const: marvell,armada390 + - items: + - enum: + - marvell,a398-db + - const: marvell,armada398 + - const: marvell,armada390 + - items: + - enum: + - marvell,a395-gp + - const: marvell,armada395 + - const: marvell,armada390 + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt deleted file mode 100644 index e10e8525eabd..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.txt +++ /dev/null @@ -1,7 +0,0 @@ -Marvell Dove Platforms Device Tree Bindings ------------------------------------------------ - -Boards with a Marvell Dove SoC shall have the following properties: - -Required root node property: -- compatible: must contain "marvell,dove"; diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml new file mode 100644 index 000000000000..a37804fb30c4 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,dove.yaml @@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,dove.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Dove SoC + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - compulab,cm-a510 + - solidrun,cubox + - globalscale,d2plug + - globalscale,d3plug + - marvell,dove-db + - const: marvell,dove + - items: + - const: solidrun,cubox-es + - const: solidrun,cubox + - const: marvell,dove + - items: + - const: compulab,sbc-a510 + - const: compulab,cm-a510 + - const: marvell,dove + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt deleted file mode 100644 index 7d28fe4bf654..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.txt +++ /dev/null @@ -1,105 +0,0 @@ -Marvell Kirkwood SoC Family Device Tree Bindings ------------------------------------------------- - -Boards with a SoC of the Marvell Kirkwook family, eg 88f6281 - -* Required root node properties: -compatible: must contain "marvell,kirkwood" - -In addition, the above compatible shall be extended with the specific -SoC. Currently known SoC compatibles are: - -"marvell,kirkwood-88f6192" -"marvell,kirkwood-88f6281" -"marvell,kirkwood-88f6282" -"marvell,kirkwood-88f6283" -"marvell,kirkwood-88f6702" -"marvell,kirkwood-98DX4122" - -And in addition, the compatible shall be extended with the specific -board. Currently known boards are: - -"buffalo,linkstation-lsqvl" -"buffalo,linkstation-lsvl" -"buffalo,linkstation-lswsxl" -"buffalo,linkstation-lswxl" -"buffalo,linkstation-lswvl" -"buffalo,lschlv2" -"buffalo,lsxhl" -"buffalo,lsxl" -"cloudengines,pogo02" -"cloudengines,pogoplugv4" -"dlink,dns-320" -"dlink,dns-320-a1" -"dlink,dns-325" -"dlink,dns-325-a1" -"dlink,dns-kirkwood" -"excito,b3" -"globalscale,dreamplug-003-ds2001" -"globalscale,guruplug" -"globalscale,guruplug-server-plus" -"globalscale,sheevaplug" -"globalscale,sheevaplug" -"globalscale,sheevaplug-esata" -"globalscale,sheevaplug-esata-rev13" -"iom,iconnect" -"iom,iconnect-1.1" -"iom,ix2-200" -"keymile,km_kirkwood" -"lacie,cloudbox" -"lacie,inetspace_v2" -"lacie,laplug" -"lacie,nas2big" -"lacie,netspace_lite_v2" -"lacie,netspace_max_v2" -"lacie,netspace_mini_v2" -"lacie,netspace_v2" -"marvell,db-88f6281-bp" -"marvell,db-88f6282-bp" -"marvell,mv88f6281gtw-ge" -"marvell,rd88f6281" -"marvell,rd88f6281" -"marvell,rd88f6281-a0" -"marvell,rd88f6281-a1" -"mpl,cec4" -"mpl,cec4-10" -"netgear,readynas" -"netgear,readynas" -"netgear,readynas-duo-v2" -"netgear,readynas-nv+-v2" -"plathome,openblocks-a6" -"plathome,openblocks-a7" -"raidsonic,ib-nas6210" -"raidsonic,ib-nas6210-b" -"raidsonic,ib-nas6220" -"raidsonic,ib-nas6220-b" -"raidsonic,ib-nas62x0" -"seagate,dockstar" -"seagate,goflexnet" -"synology,ds109" -"synology,ds110jv10" -"synology,ds110jv20" -"synology,ds110jv30" -"synology,ds111" -"synology,ds209" -"synology,ds210jv10" -"synology,ds210jv20" -"synology,ds212" -"synology,ds212jv10" -"synology,ds212jv20" -"synology,ds212pv10" -"synology,ds409" -"synology,ds409slim" -"synology,ds410j" -"synology,ds411" -"synology,ds411j" -"synology,ds411slim" -"synology,ds413jv10" -"synology,rs212" -"synology,rs409" -"synology,rs411" -"synology,rs812" -"usi,topkick" -"usi,topkick-1281P2" -"zyxel,nsa310" -"zyxel,nsa310a" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml new file mode 100644 index 000000000000..120784066833 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,kirkwood.yaml @@ -0,0 +1,266 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,kirkwood.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Kirkwood SoC Family + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - qnap,ts219 + - qnap,ts419 + - synology,ds110 + - synology,ds111 + - synology,ds209 + - synology,ds409slim + - synology,ds411j + - synology,ds411slim + - synology,rs212 + - synology,rs409 + - const: marvell,kirkwood + + - items: + - const: synology,ds109 + - const: synology,ds110jv20 + - const: synology,ds110 + - const: marvell,kirkwood + + - items: + - const: synology,ds110jv10 + - const: synology,ds110jv30 + - const: marvell,kirkwood + + - items: + - const: synology,ds210jv10 + - const: synology,ds210jv20 + - const: synology,ds210jv30 + - const: synology,ds211j + - const: marvell,kirkwood + + - items: + - const: synology,ds212jv10 + - const: synology,ds212jv20 + - const: marvell,kirkwood + + - items: + - const: synology,ds212 + - const: synology,ds212pv10 + - const: synology,ds212pv10 + - const: synology,ds212pv20 + - const: synology,ds213airv10 + - const: synology,ds213v10 + - const: marvell,kirkwood + + - items: + - const: synology,ds409 + - const: synology,ds410j + - const: marvell,kirkwood + + - items: + - const: synology,ds411 + - const: synology,ds413jv10 + - const: marvell,kirkwood + + - items: + - const: synology,rs411 + - const: synology,rs812 + - const: marvell,kirkwood + + - items: + - enum: + - cloudengines,pogoplugv4 + - lacie,laplug + - lacie,netspace_lite_v2 + - lacie,netspace_mini_v2 + - marvell,rd88f6192 + - seagate,blackarmor-nas220 + - enum: + - marvell,kirkwood-88f6192 + - const: marvell,kirkwood + + - items: + - enum: + - buffalo,lswsxl + - buffalo,lswxl + - checkpoint,l-50 + - cloudengines,pogoe02 + - ctera,c200-v1 + - dlink,dir-665 + - endian,4i-edge-200 + - excito,b3 + - globalscale,sheevaplug + - hp,t5325 + - iom,ix2-200 + - lacie,inetspace_v2 + - lacie,netspace_v2 + - lacie,netspace_max_v2 + - marvell,db-88f6281-bp + - marvell,mv88f6281gtw-ge + - seagate,dockstar + - seagate,goflexnet + - zyxel,nsa310 + - zyxel,nsa320 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - buffalo,lschlv2 + - buffalo,lsxhl + - const: buffalo,lsxl + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: dlink,dns-320-a1 + - const: dlink,dns-320 + - const: dlink,dns-kirkwood + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: dlink,dns-325-a1 + - const: dlink,dns-325 + - const: dlink,dns-kirkwood + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: globalscale,dreamplug-003-ds2001 + - const: globalscale,dreamplug + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: globalscale,guruplug-server-plus + - const: globalscale,guruplug + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: globalscale,sheevaplug-esata-rev13 + - const: globalscale,sheevaplug-esata + - const: globalscale,sheevaplug + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: iom,iconnect-1.1 + - const: iom,iconnect + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: lacie,d2net_v2 + - const: lacie,netxbig + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + - items: + - enum: + - lacie,net2big_v2 + - lacie,net5big_v2 + - const: lacie,netxbig + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - marvell,openrd-base + - marvell,openrd-client + - marvell,openrd-ultimate + - const: marvell,openrd + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - marvell,rd88f6281-a + - marvell,rd88f6281-z0 + - const: marvell,rd88f6281 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: mpl,cec4-10 + - const: mpl,cec4 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: raidsonic,ib-nas6210-b + - const: raidsonic,ib-nas6220-b + - const: raidsonic,ib-nas6210 + - const: raidsonic,ib-nas6220 + - const: raidsonic,ib-nas62x0 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - const: zyxel,nsa310a + - const: zyxel,nsa310 + - const: marvell,kirkwood-88f6281 + - const: marvell,kirkwood + + - items: + - enum: + - buffalo,lsqvl + - buffalo,lsvl + - buffalo,lswvl + - linksys,viper + - marvell,db-88f6282-bp + - zyxel,nsa325 + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - const: lacie,nas2big + - const: lacie,netxbig + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - enum: + - netgear,readynas-duo-v2 + - netgear,readynas-nv+-v2 + - const: netgear,readynas + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - const: usi,topkick-1281P2 + - const: usi,topkick + - const: marvell,kirkwood-88f6282 + - const: marvell,kirkwood + + - items: + - enum: + - plathome,openblocks-a6 + - plathome,openblocks-a7 + - const: marvell,kirkwood-88f6283 + - const: marvell,kirkwood + + - items: + - enum: + - lacie,cloudbox + - zyxel,nsa310s + - const: marvell,kirkwood-88f6702 + - const: marvell,kirkwood + + - items: + - enum: + - keymile,km_fixedeth + - keymile,km_kirkwood + - const: marvell,kirkwood-98DX4122 + - const: marvell,kirkwood + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt deleted file mode 100644 index 748a8f287462..000000000000 --- a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.txt +++ /dev/null @@ -1,25 +0,0 @@ -Marvell Orion SoC Family Device Tree Bindings ---------------------------------------------- - -Boards with a SoC of the Marvell Orion family, eg 88f5181 - -* Required root node properties: -compatible: must contain "marvell,orion5x" - -In addition, the above compatible shall be extended with the specific -SoC. Currently known SoC compatibles are: - -"marvell,orion5x-88f5181" -"marvell,orion5x-88f5182" - -And in addition, the compatible shall be extended with the specific -board. Currently known boards are: - -"buffalo,lsgl" -"buffalo,lswsgl" -"buffalo,lswtgl" -"lacie,ethernet-disk-mini-v2" -"lacie,d2-network" -"marvell,rd-88f5182-nas" -"maxtor,shared-storage-2" -"netgear,wnr854t" diff --git a/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml new file mode 100644 index 000000000000..c0417591b2be --- /dev/null +++ b/Documentation/devicetree/bindings/arm/marvell/marvell,orion5x.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/marvell/marvell,orion5x.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Orion5x SoC Family + +maintainers: + - Andrew Lunn <andrew@lunn.ch> + - Gregory Clement <gregory.clement@bootlin.com> + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - netgear,wnr854t + - const: marvell,orion5x-88f5181 + - const: marvell,orion5x + - items: + - enum: + - buffalo,kurobox-pro + - buffalo,lschl + - buffalo,lsgl + - buffalo,lswsgl + - buffalo,lswtgl + - lacie,ethernet-disk-mini-v2 + - lacie,d2-network + - marvell,rd-88f5182-nas + - maxtor,shared-storage-2 + - const: marvell,orion5x-88f5182 + - const: marvell,orion5x + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..f04277873694 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,11 +431,13 @@ properties: - const: mediatek,mt8365 - items: - enum: + - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 - items: - enum: + - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml index 45d4a6620041..f3a761cbd0fd 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,audsys.yaml @@ -23,6 +23,7 @@ properties: - mediatek,mt7622-audsys - mediatek,mt8167-audsys - mediatek,mt8173-audsys + - mediatek,mt8183-audiosys - mediatek,mt8183-audsys - mediatek,mt8186-audsys - mediatek,mt8192-audsys @@ -41,13 +42,26 @@ properties: const: 1 audio-controller: - $ref: /schemas/sound/mediatek,mt2701-audio.yaml# type: object required: - compatible - '#clock-cells' +if: + properties: + compatible: + contains: + const: mediatek,mt8183-audiosys +then: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt8183-audio.yaml# +else: + properties: + audio-controller: + $ref: /schemas/sound/mediatek,mt2701-audio.yaml# + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml index f1bd6f50e726..6b7f5e6f99cf 100644 --- a/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml +++ b/Documentation/devicetree/bindings/arm/nxp/lpc32xx.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NXP LPC32xx Platforms maintainers: - - Roland Stigge <stigge@antcom.de> + - Vladimir Zapolskiy <vz@mleia.com> properties: compatible: diff --git a/Documentation/devicetree/bindings/arm/pmu.yaml b/Documentation/devicetree/bindings/arm/pmu.yaml index 295963a3cae7..f47baaefcdac 100644 --- a/Documentation/devicetree/bindings/arm/pmu.yaml +++ b/Documentation/devicetree/bindings/arm/pmu.yaml @@ -28,6 +28,10 @@ properties: - arm,arm1136-pmu - arm,arm1176-pmu - arm,arm11mpcore-pmu + - arm,c1-nano-pmu + - arm,c1-premium-pmu + - arm,c1-pro-pmu + - arm,c1-ultra-pmu - arm,cortex-a5-pmu - arm,cortex-a7-pmu - arm,cortex-a8-pmu @@ -48,11 +52,14 @@ properties: - arm,cortex-a76-pmu - arm,cortex-a77-pmu - arm,cortex-a78-pmu + - arm,cortex-a320-pmu - arm,cortex-a510-pmu - arm,cortex-a520-pmu + - arm,cortex-a520ae-pmu - arm,cortex-a710-pmu - arm,cortex-a715-pmu - arm,cortex-a720-pmu + - arm,cortex-a720ae-pmu - arm,cortex-a725-pmu - arm,cortex-x1-pmu - arm,cortex-x2-pmu diff --git a/Documentation/devicetree/bindings/arm/qcom-soc.yaml b/Documentation/devicetree/bindings/arm/qcom-soc.yaml index a77d68dcad4e..27261039d56f 100644 --- a/Documentation/devicetree/bindings/arm/qcom-soc.yaml +++ b/Documentation/devicetree/bindings/arm/qcom-soc.yaml @@ -23,7 +23,9 @@ description: | select: properties: compatible: - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + oneOf: + - pattern: "^qcom,.*(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sar|sc|sd[amx]|sm|x1[ep])[0-9]+.*$" + - pattern: "^qcom,.*(glymur|milos).*$" required: - compatible @@ -34,6 +36,7 @@ properties: - pattern: "^qcom,(apq|ipq|mdm|msm|qcm|qcs|q[dr]u|sa|sc|sd[amx]|sm|x1[ep])[0-9]+(pro)?-.*$" - pattern: "^qcom,sar[0-9]+[a-z]?-.*$" - pattern: "^qcom,(sa|sc)8[0-9]+[a-z][a-z]?-.*$" + - pattern: "^qcom,(glymur|milos)-.*$" # Legacy namings - variations of existing patterns/compatibles are OK, # but do not add completely new entries to these: diff --git a/Documentation/devicetree/bindings/arm/qcom.yaml b/Documentation/devicetree/bindings/arm/qcom.yaml index ae43b3556580..18b5ed044f9f 100644 --- a/Documentation/devicetree/bindings/arm/qcom.yaml +++ b/Documentation/devicetree/bindings/arm/qcom.yaml @@ -10,100 +10,6 @@ maintainers: - Bjorn Andersson <bjorn.andersson@linaro.org> description: | - For devices using the Qualcomm SoC the "compatible" properties consists of - one or several "manufacturer,model" strings, describing the device itself, - followed by one or several "qcom,<SoC>" strings, describing the SoC used in - the device. - - The 'SoC' element must be one of the following strings: - - apq8016 - apq8026 - apq8064 - apq8074 - apq8084 - apq8094 - apq8096 - ipq4018 - ipq4019 - ipq5018 - ipq5332 - ipq5424 - ipq6018 - ipq8064 - ipq8074 - ipq9574 - mdm9615 - msm8226 - msm8660 - msm8916 - msm8917 - msm8926 - msm8929 - msm8939 - msm8953 - msm8956 - msm8960 - msm8974 - msm8974pro - msm8976 - msm8992 - msm8994 - msm8996 - msm8996pro - msm8998 - qcs404 - qcs615 - qcs8300 - qcs8550 - qcm2290 - qcm6490 - qcs9100 - qdu1000 - qrb2210 - qrb4210 - qru1000 - sa8155p - sa8540p - sa8775p - sar2130p - sc7180 - sc7280 - sc8180x - sc8280xp - sda660 - sdm450 - sdm630 - sdm632 - sdm636 - sdm660 - sdm670 - sdm845 - sdx55 - sdx65 - sdx75 - sm4250 - sm4450 - sm6115 - sm6115p - sm6125 - sm6350 - sm6375 - sm7125 - sm7150 - sm7225 - sm7325 - sm8150 - sm8250 - sm8350 - sm8450 - sm8550 - sm8650 - sm8750 - x1e78100 - x1e80100 - x1p42100 - There are many devices in the list below that run the standard ChromeOS bootloader setup and use the open source depthcharge bootloader to boot the OS. These devices use the bootflow explained at @@ -205,6 +111,12 @@ properties: - items: - enum: + - sony,huashan + - const: qcom,msm8960t + - const: qcom,msm8960 + + - items: + - enum: - lge,hammerhead - samsung,hlte - sony,xperia-amami @@ -281,6 +193,7 @@ properties: - items: - enum: + - flipkart,rimob - motorola,potter - xiaomi,daisy - xiaomi,mido @@ -424,6 +337,7 @@ properties: - items: - enum: - fairphone,fp5 + - particle,tachyon - qcom,qcm6490-idp - qcom,qcs6490-rb3gen2 - shift,otter @@ -942,6 +856,7 @@ properties: - items: - enum: + - qcom,monaco-evk - qcom,qcs8300-ride - const: qcom,qcs8300 @@ -949,6 +864,7 @@ properties: - enum: - qcom,qcs615-ride - const: qcom,qcs615 + - const: qcom,sm6150 - items: - enum: @@ -969,6 +885,7 @@ properties: - items: - enum: + - qcom,lemans-evk - qcom,qcs9100-ride - qcom,qcs9100-ride-r3 - const: qcom,qcs9100 @@ -976,9 +893,6 @@ properties: - items: - enum: - - google,cheza - - google,cheza-rev1 - - google,cheza-rev2 - lenovo,yoga-c630 - lg,judyln - lg,judyp @@ -1076,6 +990,8 @@ properties: - qcom,qrb5165-rb5 - qcom,sm8250-hdk - qcom,sm8250-mtp + - samsung,r8q + - samsung,x1q - sony,pdx203-generic - sony,pdx206-generic - xiaomi,elish @@ -1095,6 +1011,7 @@ properties: - enum: - qcom,sm8450-hdk - qcom,sm8450-qrd + - samsung,r0q - sony,pdx223 - sony,pdx224 - const: qcom,sm8450 @@ -1146,6 +1063,8 @@ properties: - enum: - asus,vivobook-s15 - asus,zenbook-a14-ux3407ra + - dell,inspiron-14-plus-7441 + - dell,latitude-7455 - dell,xps13-9345 - hp,elitebook-ultra-g1q - hp,omnibook-x14 @@ -1158,7 +1077,15 @@ properties: - items: - enum: + - qcom,hamoa-iot-evk + - const: qcom,hamoa-iot-som + - const: qcom,x1e80100 + + - items: + - enum: - asus,zenbook-a14-ux3407qa + - hp,omnibook-x14-fe1 + - lenovo,thinkbook-16 - qcom,x1p42100-crd - const: qcom,x1p42100 diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml index 28db6bd6aa5b..6aceaa8acbb2 100644 --- a/Documentation/devicetree/bindings/arm/rockchip.yaml +++ b/Documentation/devicetree/bindings/arm/rockchip.yaml @@ -54,6 +54,11 @@ properties: - const: ariaboard,photonicat - const: rockchip,rk3568 + - description: ArmSoM Sige1 board + items: + - const: armsom,sige1 + - const: rockchip,rk3528 + - description: ArmSoM Sige5 board items: - const: armsom,sige5 @@ -253,6 +258,11 @@ properties: - const: firefly,roc-rk3576-pc - const: rockchip,rk3576 + - description: Firefly ROC-RK3588-RT + items: + - const: firefly,roc-rk3588-rt + - const: rockchip,rk3588 + - description: Firefly Station M2 items: - const: firefly,rk3566-roc-pc @@ -320,6 +330,11 @@ properties: - friendlyarm,nanopi-r6s - const: rockchip,rk3588s + - description: FriendlyElec NanoPi Zero2 + items: + - const: friendlyarm,nanopi-zero2 + - const: rockchip,rk3528 + - description: FriendlyElec NanoPC T6 series boards items: - enum: @@ -683,6 +698,13 @@ properties: - const: hardkernel,odroid-m2 - const: rockchip,rk3588s + - description: HINLINK H66K / H68K + items: + - enum: + - hinlink,h66k + - hinlink,h68k + - const: rockchip,rk3568 + - description: Hugsun X99 TV Box items: - const: hugsun,x99 @@ -881,6 +903,13 @@ properties: - const: radxa,rock - const: rockchip,rk3188 + - description: Radxa ROCK 2A/2F + items: + - enum: + - radxa,rock-2a + - radxa,rock-2f + - const: rockchip,rk3528 + - description: Radxa ROCK Pi 4A/A+/B/B+/C items: - enum: diff --git a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml index 26fe899badc5..f8e20e602c20 100644 --- a/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml +++ b/Documentation/devicetree/bindings/arm/samsung/samsung-boards.yaml @@ -14,12 +14,6 @@ properties: const: '/' compatible: oneOf: - - description: S3C2416 based boards - items: - - enum: - - samsung,smdk2416 # Samsung SMDK2416 - - const: samsung,s3c2416 - - description: S3C6410 based boards items: - enum: diff --git a/Documentation/devicetree/bindings/arm/sti.yaml b/Documentation/devicetree/bindings/arm/sti.yaml index 842def3e3f2b..177358895fe1 100644 --- a/Documentation/devicetree/bindings/arm/sti.yaml +++ b/Documentation/devicetree/bindings/arm/sti.yaml @@ -15,11 +15,7 @@ properties: compatible: oneOf: - items: - - const: st,stih407-b2120 - - const: st,stih407 - - items: - enum: - - st,stih410-b2120 - st,stih410-b2260 - const: st,stih410 - items: diff --git a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml index ed97652c8492..95d2319afe23 100644 --- a/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/st,stm32-syscon.yaml @@ -36,20 +36,31 @@ properties: clocks: maxItems: 1 + "#clock-cells": + const: 0 + required: - compatible - reg -if: - properties: - compatible: - contains: - enum: - - st,stm32mp157-syscfg - - st,stm32f4-gcan -then: - required: - - clocks +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp157-syscfg + - st,stm32f4-gcan + then: + required: + - clocks + - if: + properties: + compatible: + const: st,stm32mp25-syscfg + then: + required: + - "#clock-cells" additionalProperties: false diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentation/devicetree/bindings/arm/sunxi.yaml index c25a22fe4d25..9e4627f97d7e 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -595,6 +595,14 @@ properties: - const: netcube,kumquat - const: allwinner,sun8i-v3s + - description: NetCube Systems Nagami SoM based boards + items: + - enum: + - netcube,nagami-basic-carrier + - netcube,nagami-keypad-carrier + - const: netcube,nagami + - const: allwinner,sun8i-t113s + - description: NextThing Co. CHIP items: - const: nextthing,chip @@ -963,6 +971,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 + - description: X96Q + items: + - const: amediatech,x96q + - const: allwinner,sun50i-h616 + - description: X96Q Pro+ items: - const: amediatech,x96q-pro-plus diff --git a/Documentation/devicetree/bindings/arm/syna.txt b/Documentation/devicetree/bindings/arm/syna.txt deleted file mode 100644 index f53c430f648c..000000000000 --- a/Documentation/devicetree/bindings/arm/syna.txt +++ /dev/null @@ -1,89 +0,0 @@ -Synaptics SoC Device Tree Bindings - -According to https://www.synaptics.com/company/news/conexant-marvell -Synaptics has acquired the Multimedia Solutions Business of Marvell, so -berlin SoCs are now Synaptics' SoCs now. - ---------------------------------------------------------------- - -Boards with a SoC of the Marvell Berlin family, e.g. Armada 1500 -shall have the following properties: - -* Required root node properties: -compatible: must contain "marvell,berlin" - -In addition, the above compatible shall be extended with the specific -SoC and board used. Currently known SoC compatibles are: - "marvell,berlin2" for Marvell Armada 1500 (BG2, 88DE3100), - "marvell,berlin2cd" for Marvell Armada 1500-mini (BG2CD, 88DE3005) - "marvell,berlin2ct" for Marvell Armada ? (BG2CT, 88DE????) - "marvell,berlin2q" for Marvell Armada 1500-pro (BG2Q, 88DE3114) - "marvell,berlin3" for Marvell Armada ? (BG3, 88DE????) - -* Example: - -/ { - model = "Sony NSZ-GS7"; - compatible = "sony,nsz-gs7", "marvell,berlin2", "marvell,berlin"; - - ... -} - -* Marvell Berlin CPU control bindings - -CPU control register allows various operations on CPUs, like resetting them -independently. - -Required properties: -- compatible: should be "marvell,berlin-cpu-ctrl" -- reg: address and length of the register set - -Example: - -cpu-ctrl@f7dd0000 { - compatible = "marvell,berlin-cpu-ctrl"; - reg = <0xf7dd0000 0x10000>; -}; - -* Marvell Berlin2 chip control binding - -Marvell Berlin SoCs have a chip control register set providing several -individual registers dealing with pinmux, padmux, clock, reset, and secondary -CPU boot address. Unfortunately, the individual registers are spread among the -chip control registers, so there should be a single DT node only providing the -different functions which are described below. - -Required properties: -- compatible: - * the first and second values must be: - "simple-mfd", "syscon" -- reg: address and length of following register sets for - BG2/BG2CD: chip control register set - BG2Q: chip control register set and cpu pll registers - -* Marvell Berlin2 system control binding - -Marvell Berlin SoCs have a system control register set providing several -individual registers dealing with pinmux, padmux, and reset. - -Required properties: -- compatible: - * the first and second values must be: - "simple-mfd", "syscon" -- reg: address and length of the system control register set - -Example: - -chip: chip-control@ea0000 { - compatible = "simple-mfd", "syscon"; - reg = <0xea0000 0x400>; - - /* sub-device nodes */ -}; - -sysctrl: system-controller@d000 { - compatible = "simple-mfd", "syscon"; - reg = <0xd000 0x100>; - - /* sub-device nodes */ -}; diff --git a/Documentation/devicetree/bindings/arm/tegra.yaml b/Documentation/devicetree/bindings/arm/tegra.yaml index 1634dab53269..6139407c2cbf 100644 --- a/Documentation/devicetree/bindings/arm/tegra.yaml +++ b/Documentation/devicetree/bindings/arm/tegra.yaml @@ -36,8 +36,12 @@ properties: - toradex,colibri_t20-iris - const: toradex,colibri_t20 - const: nvidia,tegra20 - - items: - - const: asus,tf101 + - description: ASUS Transformers T20 Device family + items: + - enum: + - asus,sl101 + - asus,tf101 + - asus,tf101g - const: nvidia,tegra20 - items: - const: acer,picasso @@ -174,6 +178,10 @@ properties: - const: google,nyan-big - const: google,nyan - const: nvidia,tegra124 + - description: Xiaomi Mi Pad (A0101) + items: + - const: xiaomi,mocha + - const: nvidia,tegra124 - items: - enum: - nvidia,darcy diff --git a/Documentation/devicetree/bindings/arm/ti/k3.yaml b/Documentation/devicetree/bindings/arm/ti/k3.yaml index e80c653fa438..0105dcda6e04 100644 --- a/Documentation/devicetree/bindings/arm/ti/k3.yaml +++ b/Documentation/devicetree/bindings/arm/ti/k3.yaml @@ -58,6 +58,13 @@ properties: - ti,am62-lp-sk - const: ti,am625 + - description: K3 AM6254atl SiP + items: + - enum: + - ti,am6254atl-sk + - const: ti,am6254atl + - const: ti,am625 + - description: K3 AM62x SoC Toradex Verdin Modules and Carrier Boards items: - enum: @@ -106,6 +113,12 @@ properties: - const: toradex,verdin-am62p # Verdin AM62P Module - const: ti,am62p5 + - description: K3 AM62P5 SoC Variscite SOM and Carrier Boards + items: + - const: variscite,var-som-am62p-symphony + - const: variscite,var-som-am62p + - const: ti,am62p5 + - description: K3 AM642 SoC items: - enum: diff --git a/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml b/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml new file mode 100644 index 000000000000..20d4084f4506 --- /dev/null +++ b/Documentation/devicetree/bindings/arm/ti/ti,keystone.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/arm/ti/ti,keystone.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI Keystone Platforms + +maintainers: + - Nishanth Menon <nm@ti.com> + - Santosh Shilimkar <ssantosh@kernel.org> + +properties: + compatible: + oneOf: + - description: K2G + items: + - enum: + - ti,k2g-evm + - ti,k2g-ice + - const: ti,k2g + - const: ti,keystone + - description: Keystone 2 Edison + items: + - enum: + - ti,k2e-evm + - const: ti,k2e + - const: ti,keystone + - description: Keystone 2 Lamarr + items: + - enum: + - ti,k2l-evm + - const: ti,k2l + - const: ti,keystone + - description: Keystone 2 Hawking/Kepler + items: + - enum: + - ti,k2hk-evm + - const: ti,k2hk + - const: ti,keystone + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml index 4de5bb2e5f24..b135ffa4ab6b 100644 --- a/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml +++ b/Documentation/devicetree/bindings/cache/andestech,ax45mp-cache.yaml @@ -47,7 +47,7 @@ properties: const: 2 cache-sets: - const: 1024 + enum: [1024, 2048] cache-size: enum: [131072, 262144, 524288, 1048576, 2097152] @@ -81,6 +81,10 @@ allOf: const: 2048 cache-size: const: 2097152 + else: + properties: + cache-sets: + const: 1024 examples: - | diff --git a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml index f5f62e9a10a1..58be701a720e 100644 --- a/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml +++ b/Documentation/devicetree/bindings/clock/allwinner,sun55i-a523-ccu.yaml @@ -19,6 +19,7 @@ properties: compatible: enum: - allwinner,sun55i-a523-ccu + - allwinner,sun55i-a523-mcu-ccu - allwinner,sun55i-a523-r-ccu reg: @@ -26,11 +27,11 @@ properties: clocks: minItems: 4 - maxItems: 5 + maxItems: 9 clock-names: minItems: 4 - maxItems: 5 + maxItems: 9 required: - "#clock-cells" @@ -67,6 +68,38 @@ allOf: properties: compatible: enum: + - allwinner,sun55i-a523-mcu-ccu + + then: + properties: + clocks: + items: + - description: High Frequency Oscillator (usually at 24MHz) + - description: Low Frequency Oscillator (usually at 32kHz) + - description: Internal Oscillator + - description: Audio PLL (4x) + - description: Peripherals PLL 0 (300 MHz output) + - description: DSP module clock + - description: MBUS clock + - description: PRCM AHB clock + - description: PRCM APB0 clock + + clock-names: + items: + - const: hosc + - const: losc + - const: iosc + - const: pll-audio0-4x + - const: pll-periph0-300m + - const: dsp + - const: mbus + - const: r-ahb + - const: r-apb0 + + - if: + properties: + compatible: + enum: - allwinner,sun55i-a523-r-ccu then: diff --git a/Documentation/devicetree/bindings/clock/apple,nco.yaml b/Documentation/devicetree/bindings/clock/apple,nco.yaml index 8b8411dc42f6..080454f56721 100644 --- a/Documentation/devicetree/bindings/clock/apple,nco.yaml +++ b/Documentation/devicetree/bindings/clock/apple,nco.yaml @@ -19,12 +19,17 @@ description: | properties: compatible: - items: - - enum: - - apple,t6000-nco - - apple,t8103-nco - - apple,t8112-nco - - const: apple,nco + oneOf: + - items: + - const: apple,t6020-nco + - const: apple,t8103-nco + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-nco + - apple,t8103-nco + - apple,t8112-nco + - const: apple,nco clocks: description: diff --git a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml index 4e78933232b6..6f3a8578fe2a 100644 --- a/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml +++ b/Documentation/devicetree/bindings/clock/marvell,pxa1908.yaml @@ -19,11 +19,14 @@ description: | properties: compatible: - enum: - - marvell,pxa1908-apbc - - marvell,pxa1908-apbcp - - marvell,pxa1908-mpmu - - marvell,pxa1908-apmu + oneOf: + - enum: + - marvell,pxa1908-apbc + - marvell,pxa1908-apbcp + - marvell,pxa1908-mpmu + - items: + - const: marvell,pxa1908-apmu + - const: syscon reg: maxItems: 1 @@ -31,6 +34,9 @@ properties: '#clock-cells': const: 1 + '#power-domain-cells': + const: 1 + required: - compatible - reg @@ -38,11 +44,23 @@ required: additionalProperties: false +if: + not: + properties: + compatible: + contains: + const: marvell,pxa1908-apmu + +then: + properties: + '#power-domain-cells': false + examples: # APMU block: - | clock-controller@d4282800 { - compatible = "marvell,pxa1908-apmu"; + compatible = "marvell,pxa1908-apmu", "syscon"; reg = <0xd4282800 0x400>; #clock-cells = <1>; + #power-domain-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml new file mode 100644 index 000000000000..def739fa0a8c --- /dev/null +++ b/Documentation/devicetree/bindings/clock/qcom,ipq5424-apss-clk.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,ipq5424-apss-clk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm APSS IPQ5424 Clock Controller + +maintainers: + - Varadarajan Narayanan <quic_varada@quicinc.com> + +description: + The CPU core in ipq5424 is clocked by a huayra PLL with RCG support. + The RCG and PLL have a separate register space from the GCC. + +properties: + compatible: + enum: + - qcom,ipq5424-apss-clk + + reg: + maxItems: 1 + + clocks: + items: + - description: Reference to the XO clock. + - description: Reference to the GPLL0 clock. + + '#clock-cells': + const: 1 + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - '#clock-cells' + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq5424-gcc.h> + + apss_clk: clock-controller@fa80000 { + compatible = "qcom,ipq5424-apss-clk"; + reg = <0x0fa80000 0x20000>; + clocks = <&xo_board>, + <&gcc GPLL0>; + #clock-cells = <1>; + #interconnect-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml b/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml index 896276b8c6bb..b51913a81791 100644 --- a/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml +++ b/Documentation/devicetree/bindings/cpufreq/apple,cluster-cpufreq.yaml @@ -35,6 +35,9 @@ properties: - const: apple,t7000-cluster-cpufreq - const: apple,s5l8960x-cluster-cpufreq - const: apple,s5l8960x-cluster-cpufreq + - items: + - const: apple,t6020-cluster-cpufreq + - const: apple,t8112-cluster-cpufreq reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt b/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt deleted file mode 100644 index 1d7e49167666..000000000000 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-dt.txt +++ /dev/null @@ -1,61 +0,0 @@ -Generic cpufreq driver - -It is a generic DT based cpufreq driver for frequency management. It supports -both uniprocessor (UP) and symmetric multiprocessor (SMP) systems which share -clock and voltage across all CPUs. - -Both required and optional properties listed below must be defined -under node /cpus/cpu@0. - -Required properties: -- None - -Optional properties: -- operating-points: Refer to Documentation/devicetree/bindings/opp/opp-v1.yaml for - details. OPPs *must* be supplied either via DT, i.e. this property, or - populated at runtime. -- clock-latency: Specify the possible maximum transition latency for clock, - in unit of nanoseconds. -- voltage-tolerance: Specify the CPU voltage tolerance in percentage. -- #cooling-cells: - Please refer to - Documentation/devicetree/bindings/thermal/thermal-cooling-devices.yaml. - -Examples: - -cpus { - #address-cells = <1>; - #size-cells = <0>; - - cpu@0 { - compatible = "arm,cortex-a9"; - reg = <0>; - next-level-cache = <&L2>; - operating-points = < - /* kHz uV */ - 792000 1100000 - 396000 950000 - 198000 850000 - >; - clock-latency = <61036>; /* two CLK32 periods */ - #cooling-cells = <2>; - }; - - cpu@1 { - compatible = "arm,cortex-a9"; - reg = <1>; - next-level-cache = <&L2>; - }; - - cpu@2 { - compatible = "arm,cortex-a9"; - reg = <2>; - next-level-cache = <&L2>; - }; - - cpu@3 { - compatible = "arm,cortex-a9"; - reg = <3>; - next-level-cache = <&L2>; - }; -}; diff --git a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml index e0242bed3342..2d42fc3d8ef8 100644 --- a/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml +++ b/Documentation/devicetree/bindings/cpufreq/cpufreq-qcom-hw.yaml @@ -22,6 +22,7 @@ properties: items: - enum: - qcom,qcm2290-cpufreq-hw + - qcom,qcs615-cpufreq-hw - qcom,sc7180-cpufreq-hw - qcom,sc8180x-cpufreq-hw - qcom,sdm670-cpufreq-hw @@ -132,6 +133,7 @@ allOf: compatible: contains: enum: + - qcom,qcs615-cpufreq-hw - qcom,qdu1000-cpufreq-epss - qcom,sa8255p-cpufreq-epss - qcom,sa8775p-cpufreq-epss diff --git a/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml new file mode 100644 index 000000000000..5f3c7db3f3aa --- /dev/null +++ b/Documentation/devicetree/bindings/cpufreq/mediatek,mt8196-cpufreq-hw.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/cpufreq/mediatek,mt8196-cpufreq-hw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek Hybrid CPUFreq for MT8196/MT6991 series SoCs + +maintainers: + - Nicolas Frattaroli <nicolas.frattaroli@collabora.com> + +description: + MT8196 uses CPUFreq management hardware that supports dynamic voltage + frequency scaling (dvfs), and can support several performance domains. + +properties: + compatible: + const: mediatek,mt8196-cpufreq-hw + + reg: + items: + - description: FDVFS control register region + - description: OPP tables and control for performance domain 0 + - description: OPP tables and control for performance domain 1 + - description: OPP tables and control for performance domain 2 + + "#performance-domain-cells": + const: 1 + +required: + - compatible + - reg + - "#performance-domain-cells" + +additionalProperties: false + +examples: + - | + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a720"; + enable-method = "psci"; + performance-domains = <&performance 0>; + reg = <0x000>; + }; + + /* ... */ + + cpu6: cpu@600 { + device_type = "cpu"; + compatible = "arm,cortex-x4"; + enable-method = "psci"; + performance-domains = <&performance 1>; + reg = <0x600>; + }; + + cpu7: cpu@700 { + device_type = "cpu"; + compatible = "arm,cortex-x925"; + enable-method = "psci"; + performance-domains = <&performance 2>; + reg = <0x700>; + }; + }; + + /* ... */ + + soc { + #address-cells = <2>; + #size-cells = <2>; + + performance: performance-controller@c2c2034 { + compatible = "mediatek,mt8196-cpufreq-hw"; + reg = <0 0xc220400 0 0x20>, <0 0xc2c0f20 0 0x120>, + <0 0xc2c1040 0 0x120>, <0 0xc2c1160 0 0x120>; + #performance-domain-cells = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml index 0b27df429bdc..84df3cf239d5 100644 --- a/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ingenic,jz4780-hdmi.yaml @@ -26,6 +26,9 @@ properties: clocks: maxItems: 2 + clock-names: + maxItems: 2 + ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml index 0a10e10d80ff..b98d942bbe19 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it6263.yaml @@ -28,6 +28,7 @@ description: | allOf: - $ref: /schemas/display/lvds-dual-ports.yaml# + - $ref: /schemas/sound/dai-common.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml index a7eb2603691f..ba644c30dcf4 100644 --- a/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ite,it66121.yaml @@ -84,7 +84,10 @@ required: - interrupts - ports -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml b/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml index 5b9d36f7af30..655db8cfdc25 100644 --- a/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml +++ b/Documentation/devicetree/bindings/display/bridge/lontium,lt9611.yaml @@ -69,7 +69,10 @@ required: - vcc-supply - ports -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml b/Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml new file mode 100644 index 000000000000..dfa6ff6f115e --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/megachips,stdp2690-ge-b850v3-fw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: GE B850v3 video bridge + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: | + STDP4028-ge-b850v3-fw bridges (LVDS-DP) + STDP2690-ge-b850v3-fw bridges (DP-DP++) + + The video processing pipeline on the second output on the GE B850v3: + + Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output + + Each bridge has a dedicated flash containing firmware for supporting the custom + design. The result is that, in this design, neither the STDP4028 nor the + STDP2690 behave as the stock bridges would. The compatible strings include the + suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with + the firmware specific for the GE B850v3. + + The hardware do not provide control over the video processing pipeline, as the + two bridges behaves as a single one. The only interfaces exposed by the + hardware are EDID, HPD, and interrupts. + +properties: + compatible: + enum: + - megachips,stdp4028-ge-b850v3-fw + - megachips,stdp2690-ge-b850v3-fw + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + properties: + port@0: + description: sink port + $ref: /schemas/graph.yaml#/properties/port + + port@1: + description: source port + $ref: /schemas/graph.yaml#/properties/port + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + +allOf: + - if: + properties: + compatible: + contains: + const: megachips,stdp4028-ge-b850v3-fw + then: + required: + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@73 { + compatible = "megachips,stdp4028-ge-b850v3-fw"; + reg = <0x73>; + interrupt-parent = <&gpio2>; + interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&lvds0_out>; + }; + + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&stdp2690_in>; + }; + }; + }; + }; + }; + diff --git a/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt b/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt deleted file mode 100644 index 09e0a21f705e..000000000000 --- a/Documentation/devicetree/bindings/display/bridge/megachips-stdpxxxx-ge-b850v3-fw.txt +++ /dev/null @@ -1,91 +0,0 @@ -Drivers for the second video output of the GE B850v3: - STDP4028-ge-b850v3-fw bridges (LVDS-DP) - STDP2690-ge-b850v3-fw bridges (DP-DP++) - -The video processing pipeline on the second output on the GE B850v3: - - Host -> LVDS|--(STDP4028)--|DP -> DP|--(STDP2690)--|DP++ -> Video output - -Each bridge has a dedicated flash containing firmware for supporting the custom -design. The result is that, in this design, neither the STDP4028 nor the -STDP2690 behave as the stock bridges would. The compatible strings include the -suffix "-ge-b850v3-fw" to make it clear that the driver is for the bridges with -the firmware specific for the GE B850v3. - -The hardware do not provide control over the video processing pipeline, as the -two bridges behaves as a single one. The only interfaces exposed by the -hardware are EDID, HPD, and interrupts. - -stdp4028-ge-b850v3-fw required properties: - - compatible : "megachips,stdp4028-ge-b850v3-fw" - - reg : I2C bus address - - interrupts : one interrupt should be described here, as in - <0 IRQ_TYPE_LEVEL_HIGH> - - ports : One input port(reg = <0>) and one output port(reg = <1>) - -stdp2690-ge-b850v3-fw required properties: - compatible : "megachips,stdp2690-ge-b850v3-fw" - - reg : I2C bus address - - ports : One input port(reg = <0>) and one output port(reg = <1>) - -Example: - -&mux2_i2c2 { - clock-frequency = <100000>; - - stdp4028@73 { - compatible = "megachips,stdp4028-ge-b850v3-fw"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0x73>; - - interrupt-parent = <&gpio2>; - interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stdp4028_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - port@1 { - reg = <1>; - stdp4028_out: endpoint { - remote-endpoint = <&stdp2690_in>; - }; - }; - }; - }; - - stdp2690@72 { - compatible = "megachips,stdp2690-ge-b850v3-fw"; - #address-cells = <1>; - #size-cells = <0>; - - reg = <0x72>; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - stdp2690_in: endpoint { - remote-endpoint = <&stdp4028_out>; - }; - }; - - port@1 { - reg = <1>; - stdp2690_out: endpoint { - /* Connector for external display */ - }; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml index b8e9cf6ce4e6..3fce9e698ea1 100644 --- a/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml +++ b/Documentation/devicetree/bindings/display/bridge/nxp,tda998x.yaml @@ -81,7 +81,10 @@ oneOf: - required: - ports -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml index 1acad99f3965..ad279f0993fa 100644 --- a/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml +++ b/Documentation/devicetree/bindings/display/bridge/samsung,mipi-dsim.yaml @@ -24,6 +24,7 @@ properties: - samsung,exynos5410-mipi-dsi - samsung,exynos5422-mipi-dsi - samsung,exynos5433-mipi-dsi + - samsung,exynos7870-mipi-dsi - fsl,imx8mm-mipi-dsim - fsl,imx8mp-mipi-dsim - items: @@ -148,6 +149,32 @@ allOf: properties: compatible: contains: + const: samsung,exynos7870-mipi-dsi + + then: + properties: + clocks: + minItems: 4 + maxItems: 4 + + clock-names: + items: + - const: bus + - const: pll + - const: byte + - const: esc + + ports: + required: + - port@0 + + required: + - ports + + - if: + properties: + compatible: + contains: const: samsung,exynos5433-mipi-dsi then: diff --git a/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml index 1509c4535e53..17ea06719b56 100644 --- a/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml +++ b/Documentation/devicetree/bindings/display/bridge/sil,sii9022.yaml @@ -109,7 +109,10 @@ required: - compatible - reg -additionalProperties: false +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +unevaluatedProperties: false examples: - | diff --git a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml index 43cf4df9811a..9ef587d46506 100644 --- a/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml +++ b/Documentation/devicetree/bindings/display/bridge/simple-bridge.yaml @@ -28,6 +28,8 @@ properties: - enum: - adi,adv7123 - dumb-vga-dac + - radxa,ra620 + - realtek,rtd2171 - ti,opa362 - ti,ths8134 - ti,ths8135 diff --git a/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml new file mode 100644 index 000000000000..e2d293d623b8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/solomon,ssd2825.yaml @@ -0,0 +1,141 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/solomon,ssd2825.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Solomon SSD2825 RGB to MIPI-DSI bridge + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: solomon,ssd2825 + + reg: + maxItems: 1 + + reset-gpios: true + + dvdd-supply: + description: Regulator for 1.2V digital power supply. + + avdd-supply: + description: Regulator for 1.2V analog power supply. + + vddio-supply: + description: Regulator for 1.8V IO power supply. + + spi-max-frequency: + maximum: 1000000 + + spi-cpha: true + spi-cpol: true + + clocks: + maxItems: 1 + description: Reference TX_CLK used before PLL is locked. + + solomon,hs-zero-delay-ns: + description: + HS zero delay period + minimum: 0 + maximum: 1700 + default: 133 + + solomon,hs-prep-delay-ns: + description: + HS prep delay period + minimum: 0 + maximum: 1728 + default: 40 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Video port for RGB input + + properties: + endpoint: + $ref: /schemas/graph.yaml#/$defs/endpoint-base + unevaluatedProperties: false + + properties: + bus-width: + enum: [ 16, 18, 24 ] + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for DSI output (panel or connector) + + required: + - port@0 + - port@1 + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + dsi@2 { + compatible = "solomon,ssd2825"; + reg = <2>; + + spi-max-frequency = <1000000>; + + spi-cpha; + spi-cpol; + + reset-gpios = <&gpio 114 GPIO_ACTIVE_LOW>; + + dvdd-supply = <&vdd_1v2>; + avdd-supply = <&vdd_1v2>; + vddio-supply = <&vdd_1v8_io>; + + solomon,hs-zero-delay-ns = <300>; + solomon,hs-prep-delay-ns = <65>; + + clocks = <&ssd2825_tx_clk>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + bridge_input: endpoint { + remote-endpoint = <&dpi_output>; + bus-width = <24>; + }; + }; + + port@1 { + reg = <1>; + + bridge_output: endpoint { + remote-endpoint = <&panel_input>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml b/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml index 1c522f72c4ba..721da44054e1 100644 --- a/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml +++ b/Documentation/devicetree/bindings/display/bridge/ti,tdp158.yaml @@ -17,6 +17,7 @@ properties: # The reg property is required if and only if the device is connected # to an I2C bus. In pin strap mode, reg must not be specified. reg: + maxItems: 1 description: I2C address of the device # Pin 36 = Operation Enable / Reset Pin diff --git a/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml new file mode 100644 index 000000000000..5e8498c8303d --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/waveshare,dsi2dpi.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/waveshare,dsi2dpi.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Waveshare MIPI-DSI to DPI Converter bridge + +maintainers: + - Joseph Guo <qijian.guo@nxp.com> + +description: + Waveshare bridge board is part of Waveshare panel which converts DSI to DPI. + +properties: + compatible: + const: waveshare,dsi2dpi + + reg: + maxItems: 1 + description: base I2C address of the device + + power-supply: true + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Video port for MIPI DSI input + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + description: array of physical DSI data lane indexes. + items: + - const: 1 + - const: 2 + + required: + - data-lanes + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: + Video port for MIPI DPI output panel. + + required: + - port@0 + - port@1 + +required: + - compatible + - reg + - ports + - power-supply + +additionalProperties: false + +examples: + - | + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bridge@45 { + compatible = "waveshare,dsi2dpi"; + reg = <0x45>; + power-supply = <®_3p3v>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + waveshare_from_dsim: endpoint { + data-lanes = <1 2>; + remote-endpoint = <&dsim_to_waveshare>; + }; + }; + + port@1 { + reg = <1>; + + waveshare_to_panel: endpoint { + remote-endpoint = <&panel_to_waveshare>; + }; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/connector/dp-connector.yaml b/Documentation/devicetree/bindings/display/connector/dp-connector.yaml index 22792a79e7ce..1f2b449dc910 100644 --- a/Documentation/devicetree/bindings/display/connector/dp-connector.yaml +++ b/Documentation/devicetree/bindings/display/connector/dp-connector.yaml @@ -31,10 +31,32 @@ properties: $ref: /schemas/graph.yaml#/properties/port description: Connection to controller providing DP signals + ports: + $ref: /schemas/graph.yaml#/properties/ports + description: OF graph representation of signales routed to DP connector + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to controller providing DP signals + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Connection to controller providing AUX signals + + required: + - port@0 + - port@1 + required: - compatible - type - - port + +oneOf: + - required: + - port + - required: + - ports additionalProperties: false @@ -52,4 +74,32 @@ examples: }; }; + - | + /* DP connecttor being driven by the USB+DP combo PHY */ + connector { + compatible = "dp-connector"; + label = "dp0"; + type = "full-size"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + endpoint { + remote-endpoint = <&phy_ss_out>; + }; + }; + + port@1 { + reg = <1>; + + endpoint { + remote-endpoint = <&phy_sbu_out>; + }; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/display/dsi-controller.yaml b/Documentation/devicetree/bindings/display/dsi-controller.yaml index 67ce10307ee0..bb4d6e9e7d0c 100644 --- a/Documentation/devicetree/bindings/display/dsi-controller.yaml +++ b/Documentation/devicetree/bindings/display/dsi-controller.yaml @@ -46,7 +46,7 @@ properties: const: 0 patternProperties: - "^panel@[0-3]$": + "^(panel|bridge)@[0-3]$": description: Panels connected to the DSI link type: object diff --git a/Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml b/Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml new file mode 100644 index 000000000000..cd27f8ba5ae1 --- /dev/null +++ b/Documentation/devicetree/bindings/display/mayqueen,pixpaper.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/mayqueen,pixpaper.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mayqueen Pixpaper e-ink display panel + +maintainers: + - LiangCheng Wang <zaq14760@gmail.com> + +description: + The Pixpaper is an e-ink display panel controlled via an SPI interface. + The panel has a resolution of 122x250 pixels and requires GPIO pins for + reset, busy, and data/command control. + +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + +properties: + compatible: + const: mayqueen,pixpaper + + reg: + maxItems: 1 + + spi-max-frequency: + maximum: 1000000 + default: 1000000 + + reset-gpios: + maxItems: 1 + + busy-gpios: + maxItems: 1 + + dc-gpios: + maxItems: 1 + +required: + - compatible + - reg + - reset-gpios + - busy-gpios + - dc-gpios + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + spi { + #address-cells = <1>; + #size-cells = <0>; + display@0 { + compatible = "mayqueen,pixpaper"; + reg = <0>; + spi-max-frequency = <1000000>; + reset-gpios = <&gpio1 17 GPIO_ACTIVE_HIGH>; + busy-gpios = <&gpio1 18 GPIO_ACTIVE_HIGH>; + dc-gpios = <&gpio1 19 GPIO_ACTIVE_HIGH>; + }; + }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml index b659d79393a8..eb4f276e8dc4 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,dpi.yaml @@ -102,6 +102,13 @@ properties: - port@0 - port@1 + resets: + maxItems: 1 + + reset-names: + items: + - const: dpi + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml index 71534febd49c..930c088a722a 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,od.yaml @@ -60,6 +60,18 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the GCE client register + items: + - items: + - description: Phandle reference to a Mediatek GCE Mailbox + - description: + GCE subsys id mapping to a client defined in header + include/dt-bindings/gce/<chip>-gce.h. + - description: offset for the GCE register offset + - description: size of the GCE register offset + required: - compatible - reg @@ -70,6 +82,7 @@ additionalProperties: false examples: - | #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/gce/mt8173-gce.h> soc { #address-cells = <2>; @@ -79,5 +92,6 @@ examples: compatible = "mediatek,mt8173-disp-od"; reg = <0 0x14023000 0 0x1000>; clocks = <&mmsys CLK_MM_DISP_OD>; + mediatek,gce-client-reg = <&gce SUBSYS_1402XXXX 0x3000 0x1000>; }; }; diff --git a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml index 61a5e22effbf..036a66ed42e7 100644 --- a/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml +++ b/Documentation/devicetree/bindings/display/mediatek/mediatek,ufoe.yaml @@ -64,6 +64,18 @@ properties: - port@0 - port@1 + mediatek,gce-client-reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: describes how to locate the GCE client register + items: + - items: + - description: Phandle reference to a Mediatek GCE Mailbox + - description: + GCE subsys id mapping to a client defined in header + include/dt-bindings/gce/<chip>-gce.h. + - description: offset for the GCE register offset + - description: size of the GCE register offset + required: - compatible - reg @@ -77,7 +89,9 @@ examples: - | #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/gce/mt8173-gce.h> #include <dt-bindings/power/mt8173-power.h> + soc { #address-cells = <2>; #size-cells = <2>; @@ -88,5 +102,6 @@ examples: interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_LOW>; power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>; clocks = <&mmsys CLK_MM_DISP_UFOE>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xa000 0x1000>; }; }; diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index 9923b065323b..aeb4e4f36044 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -29,15 +29,30 @@ properties: - qcom,sdm845-dp - qcom,sm8350-dp - qcom,sm8650-dp + - qcom,x1e80100-dp + + - items: + - enum: + - qcom,sm6350-dp + - const: qcom,sc7180-dp + + # deprecated entry for compatibility with old DT - items: - enum: - - qcom,sar2130p-dp - qcom,sm6350-dp + - const: qcom,sm8350-dp + deprecated: true + + - items: + - enum: + - qcom,sar2130p-dp + - qcom,sm7150-dp - qcom,sm8150-dp - qcom,sm8250-dp - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: - enum: - qcom,sm8750-dp @@ -51,35 +66,37 @@ properties: - description: link register block - description: p0 register block - description: p1 register block + - description: p2 register block + - description: p3 register block + - description: mst2link register block + - description: mst3link register block interrupts: maxItems: 1 clocks: + minItems: 5 items: - description: AHB clock to enable register access - description: Display Port AUX clock - description: Display Port Link clock - description: Link interface clock between DP and PHY - - description: Display Port Pixel clock + - description: Display Port stream 0 Pixel clock + - description: Display Port stream 1 Pixel clock + - description: Display Port stream 2 Pixel clock + - description: Display Port stream 3 Pixel clock clock-names: + minItems: 5 items: - const: core_iface - const: core_aux - const: ctrl_link - const: ctrl_link_iface - const: stream_pixel - - assigned-clocks: - items: - - description: link clock source - - description: pixel clock source - - assigned-clock-parents: - items: - - description: phy 0 parent - - description: phy 1 parent + - const: stream_1_pixel + - const: stream_2_pixel + - const: stream_3_pixel phys: maxItems: 1 @@ -161,7 +178,6 @@ required: allOf: # AUX BUS does not exist on DP controllers # Audio output also is present only on DP output - # p1 regions is present on DP, but not on eDP - if: properties: compatible: @@ -174,12 +190,110 @@ allOf: properties: "#sound-dai-cells": false else: + if: + properties: + compatible: + contains: + enum: + - qcom,sa8775p-dp + - qcom,x1e80100-dp + then: + oneOf: + - required: + - aux-bus + - required: + - "#sound-dai-cells" + else: + properties: + aux-bus: false + required: + - "#sound-dai-cells" + + - if: + properties: + compatible: + contains: + enum: + # these platforms support SST only + - qcom,sc7180-dp + - qcom,sc7280-dp + - qcom,sc7280-edp + - qcom,sc8180x-edp + - qcom,sc8280xp-edp + then: properties: - aux-bus: false reg: minItems: 5 - required: - - "#sound-dai-cells" + maxItems: 5 + clocks: + minItems: 5 + maxItems: 5 + clocks-names: + minItems: 5 + maxItems: 5 + + - if: + properties: + compatible: + contains: + enum: + # these platforms support 2 streams MST on some interfaces, + # others are SST only + - qcom,sc8280xp-dp + - qcom,x1e80100-dp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 5 + maxItems: 6 + clocks-names: + minItems: 5 + maxItems: 6 + + - if: + properties: + compatible: + contains: + # 2 streams MST + enum: + - qcom,sc8180x-dp + - qcom,sdm845-dp + - qcom,sm8350-dp + - qcom,sm8650-dp + then: + properties: + reg: + minItems: 5 + maxItems: 5 + clocks: + minItems: 6 + maxItems: 6 + clocks-names: + minItems: 6 + maxItems: 6 + + - if: + properties: + compatible: + contains: + enum: + # these platforms support 4 stream MST on first DP, + # 2 streams MST on the second one. + - qcom,sa8775p-dp + then: + properties: + reg: + minItems: 9 + maxItems: 9 + clocks: + minItems: 6 + maxItems: 8 + clocks-names: + minItems: 6 + maxItems: 8 additionalProperties: false diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml index d4bb65c660af..4400d4cce072 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -27,6 +27,7 @@ properties: - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sc8180x-dsi-ctrl - qcom,sdm660-dsi-ctrl - qcom,sdm670-dsi-ctrl - qcom,sdm845-dsi-ctrl @@ -332,6 +333,7 @@ allOf: - qcom,sar2130p-dsi-ctrl - qcom,sc7180-dsi-ctrl - qcom,sc7280-dsi-ctrl + - qcom,sc8180x-dsi-ctrl - qcom,sdm845-dsi-ctrl - qcom,sm6115-dsi-ctrl - qcom,sm6125-dsi-ctrl diff --git a/Documentation/devicetree/bindings/display/msm/gmu.yaml b/Documentation/devicetree/bindings/display/msm/gmu.yaml index 4392aa7a4ffe..afc187935744 100644 --- a/Documentation/devicetree/bindings/display/msm/gmu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gmu.yaml @@ -124,6 +124,40 @@ allOf: contains: enum: - qcom,adreno-gmu-623.0 + then: + properties: + reg: + items: + - description: Core GMU registers + - description: Resource controller registers + - description: GMU PDC registers + reg-names: + items: + - const: gmu + - const: rscc + - const: gmu_pdc + clocks: + items: + - description: GMU clock + - description: GPU CX clock + - description: GPU AXI clock + - description: GPU MEMNOC clock + - description: GPU AHB clock + - description: GPU HUB CX clock + clock-names: + items: + - const: gmu + - const: cxo + - const: axi + - const: memnoc + - const: ahb + - const: hub + + - if: + properties: + compatible: + contains: + enum: - qcom,adreno-gmu-635.0 - qcom,adreno-gmu-660.1 - qcom,adreno-gmu-663.0 diff --git a/Documentation/devicetree/bindings/display/msm/gpu.yaml b/Documentation/devicetree/bindings/display/msm/gpu.yaml index 6ddc72fd85b0..3696b083e353 100644 --- a/Documentation/devicetree/bindings/display/msm/gpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/gpu.yaml @@ -146,39 +146,209 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[3-5][0-9][0-9]\.[0-9]+$' + oneOf: + - pattern: '^qcom,adreno-305\.[0-9]+$' + - pattern: '^qcom,adreno-330\.[0-9]+$' + then: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-306\.[0-9]+$' then: properties: clocks: - minItems: 2 - maxItems: 7 + minItems: 5 + maxItems: 6 + clock-names: + oneOf: + - items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-320\.[0-9]+$' + then: + properties: + clocks: + minItems: 4 + maxItems: 4 clock-names: items: - anyOf: - - const: core - description: GPU Core clock - - const: iface - description: GPU Interface clock - - const: mem - description: GPU Memory clock - - const: mem_iface - description: GPU Memory Interface clock - - const: alt_mem_iface - description: GPU Alternative Memory Interface clock - - const: gfx3d - description: GPU 3D engine clock - - const: rbbmtimer - description: GPU RBBM Timer for Adreno 5xx series - - const: rbcpr - description: GPU RB Core Power Reduction clock - minItems: 2 + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-405\.[0-9]+$' + then: + properties: + clocks: + minItems: 7 maxItems: 7 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: gfx3d + description: GPU 3D engine clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series - required: - - clocks - - clock-names + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-50[56]\.[0-9]+$' + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem_iface + description: GPU Memory Interface clock + - const: alt_mem_iface + description: GPU Alternative Memory Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: alwayson + description: GPU AON clock + + - if: + properties: + compatible: + contains: + oneOf: + - pattern: '^qcom,adreno-508\.[0-9]+$' + - pattern: '^qcom,adreno-509\.[0-9]+$' + - pattern: '^qcom,adreno-512\.[0-9]+$' + - pattern: '^qcom,adreno-540\.[0-9]+$' + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: iface + description: GPU Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: rbcpr + description: GPU RB Core Power Reduction clock + - const: core + description: GPU Core clock + + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-510\.[0-9]+$' + then: + properties: + clocks: + minItems: 6 + maxItems: 6 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: alwayson + description: GPU AON clock + + - if: + properties: + compatible: + contains: + pattern: '^qcom,adreno-530\.[0-9]+$' + then: + properties: + clocks: + minItems: 5 + maxItems: 5 + clock-names: + items: + - const: core + description: GPU Core clock + - const: iface + description: GPU Interface clock + - const: rbbmtimer + description: GPU RBBM Timer for Adreno 5xx series + - const: mem + description: GPU Memory clock + - const: mem_iface + description: GPU Memory Interface clock - if: properties: @@ -187,6 +357,7 @@ allOf: enum: - qcom,adreno-610.0 - qcom,adreno-619.1 + - qcom,adreno-07000200 then: properties: clocks: @@ -222,7 +393,9 @@ allOf: properties: compatible: contains: - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' + oneOf: + - pattern: '^qcom,adreno-[67][0-9][0-9]\.[0-9]+$' + - pattern: '^qcom,adreno-[0-9a-f]{8}$' then: # Starting with A6xx, the clocks are usually defined in the GMU node properties: diff --git a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml index e153f8d26e7a..2735c78b0b67 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,mdp5.yaml @@ -60,7 +60,6 @@ properties: - const: bus - const: core - const: vsync - - const: lut - const: tbu - const: tbu_rt # MSM8996 has additional iommu clock diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml index 1053b3bc4908..e2730a2f25cf 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sa8775p-mdss.yaml @@ -375,7 +375,11 @@ examples: <0xaf54200 0x0c0>, <0xaf55000 0x770>, <0xaf56000 0x09c>, - <0xaf57000 0x09c>; + <0xaf57000 0x09c>, + <0xaf58000 0x09c>, + <0xaf59000 0x09c>, + <0xaf5a000 0x23c>, + <0xaf5b000 0x23c>; interrupt-parent = <&mdss0>; interrupts = <12>; @@ -384,16 +388,28 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>, + <&dispcc_dptx0_pixel2_clk>, + <&dispcc_dptx0_pixel3_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel", + "stream_2_pixel", + "stream_3_pixel"; assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; - assigned-clock-parents = <&mdss0_dp0_phy 0>, <&mdss0_dp0_phy 1>; + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>, + <&dispcc_mdss_dptx0_pixel2_clk_src>, + <&dispcc_mdss_dptx0_pixel3_clk_src>; + assigned-clock-parents = <&mdss0_dp0_phy 0>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>, + <&mdss0_dp0_phy 1>; phys = <&mdss0_dp0_phy>; phy-names = "dp"; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml index 870144b53cec..44c1bb9e4109 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sar2130p-mdss.yaml @@ -207,16 +207,20 @@ examples: <&dispcc_disp_cc_mdss_dptx0_aux_clk>, <&dispcc_disp_cc_mdss_dptx0_link_clk>, <&dispcc_disp_cc_mdss_dptx0_link_intf_clk>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_disp_cc_mdss_dptx0_link_clk_src>, - <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>; + <&dispcc_disp_cc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_disp_cc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents = <&usb_dp_qmpphy_QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy_QMP_USB43DP_DP_VCO_DIV_CLK>; phys = <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml index 2947f27e0585..b643d3adf669 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc7280-mdss.yaml @@ -281,7 +281,8 @@ examples: reg = <0xaea0000 0x200>, <0xaea0200 0x200>, <0xaea0400 0xc00>, - <0xaea1000 0x400>; + <0xaea1000 0x400>, + <0xaea1400 0x400>; interrupt-parent = <&mdss>; interrupts = <14>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml new file mode 100644 index 000000000000..a411126708b8 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-dpu.yaml @@ -0,0 +1,103 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-dpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180X Display DPU + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +$ref: /schemas/display/msm/dpu-common.yaml# + +properties: + compatible: + const: qcom,sc8180x-dpu + + reg: + items: + - description: Address offset and size for mdp register set + - description: Address offset and size for vbif register set + + reg-names: + items: + - const: mdp + - const: vbif + + clocks: + items: + - description: Display AHB clock + - description: Display HF AXI clock + - description: Display core clock + - description: Display vsync clock + - description: Display rotator clock + - description: Display LUT clock + + clock-names: + items: + - const: iface + - const: bus + - const: core + - const: vsync + - const: rot + - const: lut + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> + #include <dt-bindings/clock/qcom,gcc-sc8180x.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc8180x.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-controller@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "rot", + "lut"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml new file mode 100644 index 000000000000..00e82bdbbcc7 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sc8180x-mdss.yaml @@ -0,0 +1,359 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sc8180x-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SC8180X Display MDSS + +maintainers: + - Dmitry Baryshkov <dmitry.baryshkov@linaro.org> + +description: + Device tree bindings for MSM Mobile Display Subsystem(MDSS) that encapsulates + sub-blocks like DPU display controller, DSI and DP interfaces etc. Device tree + bindings of MDSS are mentioned for SC8180X target. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + items: + - const: qcom,sc8180x-mdss + + clocks: + items: + - description: Display AHB clock from gcc + - description: Display hf axi clock + - description: Display sf axi clock + - description: Display core clock + + clock-names: + items: + - const: iface + - const: bus + - const: nrt_bus + - const: core + + iommus: + maxItems: 1 + + interconnects: + maxItems: 3 + + interconnect-names: + maxItems: 3 + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,sc8180x-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + enum: + - qcom,sc8180x-dp + - qcom,sc8180x-edp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + contains: + const: qcom,sc8180x-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + + properties: + compatible: + const: qcom,dsi-phy-7nm + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,dispcc-sm8250.h> + #include <dt-bindings/clock/qcom,gcc-sc8180x.h> + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,sc8180x.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + display-subsystem@ae00000 { + compatible = "qcom,sc8180x-mdss"; + reg = <0x0ae00000 0x1000>; + reg-names = "mdss"; + + interconnects = <&mmss_noc MASTER_MDP_PORT0 &mc_virt SLAVE_EBI_CH0>, + <&mmss_noc MASTER_MDP_PORT1 &mc_virt SLAVE_EBI_CH0>, + <&gem_noc MASTER_AMPSS_M0 &config_noc SLAVE_DISPLAY_CFG>; + interconnect-names = "mdp0-mem", + "mdp1-mem", + "cpu-cfg"; + + power-domains = <&dispcc MDSS_GDSC>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&gcc GCC_DISP_SF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>; + clock-names = "iface", "bus", "nrt_bus", "core"; + + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + #interrupt-cells = <1>; + + iommus = <&apps_smmu 0x800 0x420>; + + #address-cells = <1>; + #size-cells = <1>; + ranges; + + display-controller@ae01000 { + compatible = "qcom,sc8180x-dpu"; + reg = <0x0ae01000 0x8f000>, + <0x0aeb0000 0x2008>; + reg-names = "mdp", "vbif"; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>, + <&dispcc DISP_CC_MDSS_MDP_CLK>, + <&dispcc DISP_CC_MDSS_VSYNC_CLK>, + <&dispcc DISP_CC_MDSS_ROT_CLK>, + <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>; + clock-names = "iface", + "bus", + "core", + "vsync", + "rot", + "lut"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; + assigned-clock-rates = <19200000>; + + operating-points-v2 = <&mdp_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + interrupt-parent = <&mdss>; + interrupts = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dpu_intf1_out: endpoint { + remote-endpoint = <&dsi0_in>; + }; + }; + + port@1 { + reg = <1>; + dpu_intf2_out: endpoint { + remote-endpoint = <&dsi1_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-171428571 { + opp-hz = /bits/ 64 <171428571>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-345000000 { + opp-hz = /bits/ 64 <345000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + + opp-460000000 { + opp-hz = /bits/ 64 <460000000>; + required-opps = <&rpmhpd_opp_nom>; + }; + }; + }; + + dsi@ae94000 { + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae94000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <4>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, + <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK>, + <&dispcc DISP_CC_MDSS_ESC0_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; + assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi0_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi0_in: endpoint { + remote-endpoint = <&dpu_intf1_out>; + }; + }; + + port@1 { + reg = <1>; + dsi0_out: endpoint { + }; + }; + }; + + dsi_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-187500000 { + opp-hz = /bits/ 64 <187500000>; + required-opps = <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz = /bits/ 64 <300000000>; + required-opps = <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz = /bits/ 64 <358000000>; + required-opps = <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + dsi0_phy: phy@ae94400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae94400 0x200>, + <0x0ae94600 0x280>, + <0x0ae94900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + + dsi@ae96000 { + compatible = "qcom,sc8180x-dsi-ctrl", + "qcom,mdss-dsi-ctrl"; + reg = <0x0ae96000 0x400>; + reg-names = "dsi_ctrl"; + + interrupt-parent = <&mdss>; + interrupts = <5>; + + clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK>, + <&dispcc DISP_CC_MDSS_BYTE1_INTF_CLK>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK>, + <&dispcc DISP_CC_MDSS_ESC1_CLK>, + <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&gcc GCC_DISP_HF_AXI_CLK>; + clock-names = "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus"; + + assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE1_CLK_SRC>, + <&dispcc DISP_CC_MDSS_PCLK1_CLK_SRC>; + assigned-clock-parents = <&dsi1_phy 0>, <&dsi1_phy 1>; + + operating-points-v2 = <&dsi_opp_table>; + power-domains = <&rpmhpd SC8180X_MMCX>; + + phys = <&dsi1_phy>; + phy-names = "dsi"; + + #address-cells = <1>; + #size-cells = <0>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + dsi1_in: endpoint { + remote-endpoint = <&dpu_intf2_out>; + }; + }; + + port@1 { + reg = <1>; + dsi1_out: endpoint { + }; + }; + }; + }; + + dsi1_phy: phy@ae96400 { + compatible = "qcom,dsi-phy-7nm"; + reg = <0x0ae96400 0x200>, + <0x0ae96600 0x280>, + <0x0ae96900 0x260>; + reg-names = "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + #clock-cells = <1>; + #phy-cells = <0>; + + clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names = "iface", "ref"; + vdds-supply = <&vreg_dsi_phy>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml index 13c5d5ffabde..9b0621d88d50 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm7150-mdss.yaml @@ -61,7 +61,8 @@ patternProperties: additionalProperties: true properties: compatible: - const: qcom,sm7150-dp + contains: + const: qcom,sm7150-dp "^dsi@[0-9a-f]+$": type: object @@ -378,7 +379,8 @@ examples: }; displayport-controller@ae90000 { - compatible = "qcom,sm7150-dp"; + compatible = "qcom,sm7150-dp", + "qcom,sm8350-dp"; reg = <0xae90000 0x200>, <0xae90200 0x200>, <0xae90400 0xc00>, @@ -392,16 +394,20 @@ examples: <&dispcc_mdss_dp_aux_clk>, <&dispcc_mdss_dp_link_clk>, <&dispcc_mdss_dp_link_intf_clk>, - <&dispcc_mdss_dp_pixel_clk>; + <&dispcc_mdss_dp_pixel_clk>, + <&dispcc_mdss_dp_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_mdss_dp_link_clk_src>, - <&dispcc_mdss_dp_pixel_clk_src>; + <&dispcc_mdss_dp_pixel_clk_src>, + <&dispcc_mdss_dp_pixel1_clk_src>; assigned-clock-parents = <&dp_phy 0>, + <&dp_phy 1>, <&dp_phy 1>; operating-points-v2 = <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml index 72c70edc1fb0..4151f475f3bc 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -401,16 +401,20 @@ examples: <&disp_cc_mdss_dptx0_aux_clk>, <&disp_cc_mdss_dptx0_link_clk>, <&disp_cc_mdss_dptx0_link_intf_clk>, - <&disp_cc_mdss_dptx0_pixel0_clk>; + <&disp_cc_mdss_dptx0_pixel0_clk>, + <&disp_cc_mdss_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&disp_cc_mdss_dptx0_link_clk_src>, - <&disp_cc_mdss_dptx0_pixel0_clk_src>; + <&disp_cc_mdss_dptx0_pixel0_clk_src>, + <&disp_cc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents = <&usb_dp_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_dp_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&dp_opp_table>; diff --git a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml index 3b01a0e47333..8d698a2e055a 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,x1e80100-mdss.yaml @@ -170,11 +170,11 @@ examples: displayport-controller@ae90000 { compatible = "qcom,x1e80100-dp"; - reg = <0 0xae90000 0 0x200>, - <0 0xae90200 0 0x200>, - <0 0xae90400 0 0x600>, - <0 0xae91000 0 0x400>, - <0 0xae91400 0 0x400>; + reg = <0xae90000 0x200>, + <0xae90200 0x200>, + <0xae90400 0x600>, + <0xae91000 0x400>, + <0xae91400 0x400>; interrupt-parent = <&mdss>; interrupts = <12>; @@ -183,15 +183,19 @@ examples: <&dispcc_dptx0_aux_clk>, <&dispcc_dptx0_link_clk>, <&dispcc_dptx0_link_intf_clk>, - <&dispcc_dptx0_pixel0_clk>; + <&dispcc_dptx0_pixel0_clk>, + <&dispcc_dptx0_pixel1_clk>; clock-names = "core_iface", "core_aux", "ctrl_link", "ctrl_link_iface", - "stream_pixel"; + "stream_pixel", + "stream_1_pixel"; assigned-clocks = <&dispcc_mdss_dptx0_link_clk_src>, - <&dispcc_mdss_dptx0_pixel0_clk_src>; + <&dispcc_mdss_dptx0_pixel0_clk_src>, + <&dispcc_mdss_dptx0_pixel1_clk_src>; assigned-clock-parents = <&usb_1_ss0_qmpphy QMP_USB43DP_DP_LINK_CLK>, + <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, <&usb_1_ss0_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; operating-points-v2 = <&mdss_dp0_opp_table>; diff --git a/Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml b/Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml new file mode 100644 index 000000000000..f429e84ee65d --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/hydis,hv101hd1.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/hydis,hv101hd1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hydis HV101HD1 DSI Display Panel + +maintainers: + - Svyatoslav Ryhel <clamor95@gmail.com> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: hydis,hv101hd1 + + reg: + maxItems: 1 + + vdd-supply: true + vio-supply: true + + backlight: true + port: true + +required: + - compatible + - vdd-supply + - vio-supply + - backlight + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "hydis,hv101hd1"; + reg = <0>; + + vdd-supply = <&vdd_lcd>; + vio-supply = <&vddio_lcd>; + + backlight = <&backlight>; + + port { + panel_in: endpoint { + remote-endpoint = <&dsi_out>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml index a51af61d4846..434cc6af9c95 100644 --- a/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml +++ b/Documentation/devicetree/bindings/display/panel/ilitek,ili9881c.yaml @@ -18,6 +18,7 @@ properties: - enum: - ampire,am8001280g - bananapi,lhr050h41 + - bestar,bsd1218-a101kl68 - feixin,k101-im2byl02 - raspberrypi,dsi-7inch - startek,kd050hdfia020 diff --git a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml index fcb5834f799a..4388d5375851 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-lvds.yaml @@ -41,11 +41,15 @@ properties: - enum: # Admatec 9904379 10.1" 1024x600 LVDS panel - admatec,9904379 + # Ampire AMP19201200B5TZQW-T03 10.1" WUXGA (1920x1200) color TFT LCD panel + - ampire,amp19201200b5tzqw-t03 - auo,b101ew05 # AUO G084SN05 V9 8.4" 800x600 LVDS panel - auo,g084sn05 # Chunghwa Picture Tubes Ltd. 7" WXGA (800x1280) TFT LCD LVDS panel - chunghwa,claa070wp03xg + # EDT ETML0700Z8DHA 7.0" Full HD (1920x1080) color TFT LCD LVDS panel + - edt,etml0700z8dha # EDT ETML0700Z9NDHA 7.0" WSVGA (1024x600) color TFT LCD LVDS panel - edt,etml0700z9ndha # HannStar Display Corp. HSD101PWW2 10.1" WXGA (1280x800) LVDS panel diff --git a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml index 1ac1f0219079..2017428d8828 100644 --- a/Documentation/devicetree/bindings/display/panel/panel-simple.yaml +++ b/Documentation/devicetree/bindings/display/panel/panel-simple.yaml @@ -178,6 +178,8 @@ properties: - innolux,g121xce-l01 # InnoLux 15.6" FHD (1920x1080) TFT LCD panel - innolux,g156hce-l01 + # InnoLux 13.3" FHD (1920x1080) TFT LCD panel + - innolux,n133hse-ea1 # InnoLux 15.6" WXGA TFT LCD panel - innolux,n156bge-l21 # Innolux Corporation 7.0" WSVGA (1024x600) TFT LCD panel @@ -228,6 +230,8 @@ properties: - netron-dy,e231732 # Newhaven Display International 480 x 272 TFT LCD panel - newhaven,nhd-4.3-480272ef-atxl + # NLT Technologies, Ltd. 12.1" WXGA (1280 x 800) LVDS TFT LCD panel + - nlt,nl12880bc20-spwg-24 # NLT Technologies, Ltd. 15.6" WXGA (1366×768) LVDS TFT LCD panel - nlt,nl13676bc25-03f # New Vision Display 7.0" 800 RGB x 480 TFT LCD panel @@ -236,6 +240,8 @@ properties: - okaya,rs800480t-7x0gp # Olimex 4.3" TFT LCD panel - olimex,lcd-olinuxino-43-ts + # Olimex 5.0" TFT LCD panel + - olimex,lcd-olinuxino-5-cts # On Tat Industrial Company 5" DPI TFT panel. - ontat,kd50g21-40nt-a1 # On Tat Industrial Company 7" DPI TFT panel. @@ -321,6 +327,10 @@ properties: - vivax,tpc9150-panel # VXT 800x480 color TFT LCD panel - vxt,vl050-8048nt-c01 + # Waveshare 13.3" FHD (1920x1080) LCD panel + - waveshare,13.3inch-panel + # Waveshare 7.0" WSVGA (1024x600) LCD panel + - waveshare,7.0inch-c-panel # Winstar Display Corporation 3.5" QVGA (320x240) TFT LCD panel - winstar,wf35ltiacd # Yes Optoelectronics YTC700TLAG-05-201C 7" TFT LCD panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml index e36659340ef3..ccb574caed28 100644 --- a/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml +++ b/Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml @@ -21,6 +21,10 @@ properties: - enum: # Samsung 13" 3K (2880×1920 pixels) eDP AMOLED panel - samsung,atna30dw01 + # Samsung 14" FHD+ (1920x1200 pixels) eDP AMOLED panel + - samsung,atna40ct06 + # Samsung 14" WQXGA+ (2880x1800 pixels) eDP AMOLED panel + - samsung,atna40cu11 # Samsung 14" WQXGA+ (2880×1800 pixels) eDP AMOLED panel - samsung,atna40yk20 # Samsung 14.5" WQXGA+ (2880x1800 pixels) eDP AMOLED panel diff --git a/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml new file mode 100644 index 000000000000..eccfc66d7fe2 --- /dev/null +++ b/Documentation/devicetree/bindings/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/panel/samsung,s6e8aa5x01-ams561ra01.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung AMS561RA01 panel with S6E8AA5X01 controller + +maintainers: + - Kaustabh Chakraborty <kauschluss@disroot.org> + +allOf: + - $ref: panel-common.yaml# + +properties: + compatible: + const: samsung,s6e8aa5x01-ams561ra01 + + reg: + maxItems: 1 + + vdd-supply: + description: core voltage supply + + vci-supply: + description: voltage supply for analog circuits + + reset-gpios: true + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + dsi { + #address-cells = <1>; + #size-cells = <0>; + + panel@0 { + compatible = "samsung,s6e8aa5x01-ams561ra01"; + reg = <0>; + + vdd-supply = <&panel_vdd_reg>; + vci-supply = <&panel_vci_reg>; + + reset-gpios = <&gpd3 4 GPIO_ACTIVE_HIGH>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml new file mode 100644 index 000000000000..a8a008717997 --- /dev/null +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-dp.yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/rockchip/rockchip,dw-dp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip DW DisplayPort Transmitter + +maintainers: + - Andy Yan <andy.yan@rock-chips.com> + +description: | + The Rockchip RK3588 SoC integrates the Synopsys DesignWare DPTX controller + which is compliant with the DisplayPort Specification Version 1.4 with the + following features: + + * DisplayPort 1.4a + * Main Link: 1/2/4 lanes + * Main Link Support 1.62Gbps, 2.7Gbps, 5.4Gbps and 8.1Gbps + * AUX channel 1Mbps + * Single Stream Transport(SST) + * Multistream Transport (MST) + * Type-C support (alternate mode) + * HDCP 2.2, HDCP 1.3 + * Supports up to 8/10 bits per color component + * Supports RBG, YCbCr4:4:4, YCbCr4:2:2, YCbCr4:2:0 + * Pixel clock up to 594MHz + * I2S, SPDIF audio interface + +allOf: + - $ref: /schemas/sound/dai-common.yaml# + +properties: + compatible: + enum: + - rockchip,rk3588-dp + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: Peripheral/APB bus clock + - description: DisplayPort AUX clock + - description: HDCP clock + - description: I2S interface clock + - description: SPDIF interfce clock + + clock-names: + items: + - const: apb + - const: aux + - const: hdcp + - const: i2s + - const: spdif + + phys: + maxItems: 1 + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for RGB/YUV input. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Video port for DP output. + + required: + - port@0 + - port@1 + + power-domains: + maxItems: 1 + + resets: + maxItems: 1 + + "#sound-dai-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + - phys + - ports + - resets + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/phy/phy.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/rk3588-power.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + dp@fde50000 { + compatible = "rockchip,rk3588-dp"; + reg = <0x0 0xfde50000 0x0 0x4000>; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH 0>; + clocks = <&cru PCLK_DP0>, <&cru CLK_AUX16M_0>, + <&cru CLK_DP0>, <&cru MCLK_I2S4_8CH_TX>, + <&cru MCLK_SPDIF2_DP0>; + clock-names = "apb", "aux", "hdcp", "i2s", "spdif"; + assigned-clocks = <&cru CLK_AUX16M_0>; + assigned-clock-rates = <16000000>; + resets = <&cru SRST_DP0>; + phys = <&usbdp_phy0 PHY_TYPE_DP>; + power-domains = <&power RK3588_PD_VO0>; + #sound-dai-cells = <0>; + + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + + dp0_in_vp2: endpoint { + remote-endpoint = <&vp2_out_dp0>; + }; + }; + + port@1 { + reg = <1>; + + dp0_out_con0: endpoint { + remote-endpoint = <&dp_con0_in>; + }; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml index 0881e82deb11..c59df3c1a3f7 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,dw-mipi-dsi.yaml @@ -97,9 +97,11 @@ allOf: then: properties: clocks: + minItems: 2 maxItems: 2 clock-names: + minItems: 2 maxItems: 2 - if: diff --git a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml index 53384e47b507..75cd1c13fa52 100644 --- a/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml +++ b/Documentation/devicetree/bindings/display/rockchip/rockchip,rk3588-mipi-dsi2.yaml @@ -12,6 +12,7 @@ maintainers: properties: compatible: enum: + - rockchip,rk3576-mipi-dsi2 - rockchip,rk3588-mipi-dsi2 reg: diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml index 53916e4c95d8..14b954718008 100644 --- a/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml +++ b/Documentation/devicetree/bindings/display/samsung/samsung,exynos7-decon.yaml @@ -80,6 +80,21 @@ properties: - const: vsync - const: lcd_sys + iommus: + maxItems: 1 + + memory-region: + maxItems: 1 + description: + A phandle to a node describing a reserved framebuffer memory region. + For example, the splash memory region set up by the bootloader. + + port: + $ref: /schemas/graph.yaml#/properties/port + description: + Output port which is connected to either a Mobile Image Compressor + (MIC) or a DSI Master device. + power-domains: maxItems: 1 @@ -92,6 +107,7 @@ required: - clock-names - interrupts - interrupt-names + - port - reg additionalProperties: false @@ -118,4 +134,9 @@ examples: "decon0_vclk"; pinctrl-0 = <&lcd_clk &pwm1_out>; pinctrl-names = "default"; + port { + decon_to_dsi: endpoint { + remote-endpoint = <&dsi_to_decon>; + }; + }; }; diff --git a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml index 075231716b2f..ff685031bb2c 100644 --- a/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml +++ b/Documentation/devicetree/bindings/display/samsung/samsung,fimd.yaml @@ -15,7 +15,6 @@ maintainers: properties: compatible: enum: - - samsung,s3c2443-fimd - samsung,s3c6400-fimd - samsung,s5pv210-fimd - samsung,exynos3250-fimd diff --git a/Documentation/devicetree/bindings/display/sitronix,st7567.yaml b/Documentation/devicetree/bindings/display/sitronix,st7567.yaml index e8a5b8ad18fe..2eb6d00b5a25 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7567.yaml +++ b/Documentation/devicetree/bindings/display/sitronix,st7567.yaml @@ -23,6 +23,11 @@ properties: reg: maxItems: 1 + sitronix,inverted: + type: boolean + description: + Display pixels are inverted, i.e. 0 is white and 1 is black. + width-mm: true height-mm: true panel-timing: true diff --git a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml index 4fea782fccd7..b83721eb4b7f 100644 --- a/Documentation/devicetree/bindings/display/sitronix,st7571.yaml +++ b/Documentation/devicetree/bindings/display/sitronix,st7571.yaml @@ -28,6 +28,11 @@ properties: description: Display supports 4-level grayscale. + sitronix,inverted: + type: boolean + description: + Display pixels are inverted, i.e. 0 is white and 1 is black. + reset-gpios: true width-mm: true height-mm: true diff --git a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml index d6ea4d62a2cf..77058a5ccf68 100644 --- a/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32-ltdc.yaml @@ -12,7 +12,10 @@ maintainers: properties: compatible: - const: st,stm32-ltdc + enum: + - st,stm32-ltdc + - st,stm32mp251-ltdc + - st,stm32mp255-ltdc reg: maxItems: 1 @@ -24,15 +27,23 @@ properties: minItems: 1 clocks: - maxItems: 1 + minItems: 1 + maxItems: 4 clock-names: items: - const: lcd + - const: bus + - const: ref + - const: lvds + minItems: 1 resets: maxItems: 1 + access-controllers: + maxItems: 1 + port: $ref: /schemas/graph.yaml#/properties/port description: | @@ -51,6 +62,46 @@ required: - resets - port +allOf: + - if: + properties: + compatible: + contains: + enum: + - st,stm32-ltdc + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp251-ltdc + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + minItems: 2 + maxItems: 2 + - if: + properties: + compatible: + contains: + enum: + - st,stm32mp255-ltdc + then: + properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml index 6736f93256b5..14e042156179 100644 --- a/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml +++ b/Documentation/devicetree/bindings/display/st,stm32mp25-lvds.yaml @@ -31,7 +31,12 @@ description: | properties: compatible: - const: st,stm32mp25-lvds + oneOf: + - items: + - enum: + - st,stm32mp255-lvds + - const: st,stm32mp25-lvds + - const: st,stm32mp25-lvds "#clock-cells": const: 0 @@ -54,6 +59,12 @@ properties: resets: maxItems: 1 + access-controllers: + maxItems: 1 + + power-domains: + maxItems: 1 + ports: $ref: /schemas/graph.yaml#/properties/ports diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml index 2181855a0920..644f42b942ad 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-vi.yaml @@ -70,9 +70,6 @@ properties: ranges: maxItems: 1 - avdd-dsi-csi-supply: - description: DSI/CSI power supply. Must supply 1.2 V. - vip: $ref: /schemas/display/tegra/nvidia,tegra20-vip.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml index fa07a40d1004..37f6129c9c92 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra210-csi.yaml @@ -37,6 +37,9 @@ properties: - const: cile - const: csi_tpg + avdd-dsi-csi-supply: + description: DSI/CSI power supply. Must supply 1.2 V. + power-domains: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/ti/ti,opa362.txt b/Documentation/devicetree/bindings/display/ti/ti,opa362.txt deleted file mode 100644 index f96083c0bd17..000000000000 --- a/Documentation/devicetree/bindings/display/ti/ti,opa362.txt +++ /dev/null @@ -1,38 +0,0 @@ -OPA362 analog video amplifier - -Required properties: -- compatible: "ti,opa362" -- enable-gpios: enable/disable output gpio - -Required node: -- Video port 0 for opa362 input -- Video port 1 for opa362 output - -Example: - -tv_amp: opa362 { - compatible = "ti,opa362"; - enable-gpios = <&gpio1 23 0>; /* GPIO to enable video out amplifier */ - - ports { - #address-cells = <1>; - #size-cells = <0>; - - port@0 { - reg = <0>; - opa_in: endpoint@0 { - remote-endpoint = <&venc_out>; - }; - }; - - port@1 { - reg = <1>; - opa_out: endpoint@0 { - remote-endpoint = <&tv_connector_in>; - }; - }; - }; -}; - - - diff --git a/Documentation/devicetree/bindings/dma/apple,admac.yaml b/Documentation/devicetree/bindings/dma/apple,admac.yaml index ab193bc8bdbb..6a200cbd7d02 100644 --- a/Documentation/devicetree/bindings/dma/apple,admac.yaml +++ b/Documentation/devicetree/bindings/dma/apple,admac.yaml @@ -22,12 +22,17 @@ allOf: properties: compatible: - items: - - enum: - - apple,t6000-admac - - apple,t8103-admac - - apple,t8112-admac - - const: apple,admac + oneOf: + - items: + - const: apple,t6020-admac + - const: apple,t8103-admac + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-admac + - apple,t8103-admac + - apple,t8112-admac + - const: apple,admac reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml index f2f87f0f545b..6493a6968bb4 100644 --- a/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml +++ b/Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml @@ -92,8 +92,12 @@ required: anyOf: - required: - qcom,powered-remotely + - num-channels + - qcom,num-ees - required: - qcom,controlled-remotely + - num-channels + - qcom,num-ees - required: - clocks - clock-names diff --git a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml index ec4634c5fa89..3d787dea0f14 100644 --- a/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml +++ b/Documentation/devicetree/bindings/edac/altr,socfpga-ecc-manager.yaml @@ -53,6 +53,7 @@ properties: properties: compatible: enum: + - altr,sdram-edac - altr,sdram-edac-a10 - altr,sdram-edac-s10 diff --git a/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml b/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml new file mode 100644 index 000000000000..9afc78254cc0 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/apm,xgene-edac.yaml @@ -0,0 +1,203 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/apm,xgene-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC EDAC + +maintainers: + - Khuong Dinh <khuong@os.amperecomputing.com> + +description: > + EDAC node is defined to describe on-chip error detection and correction. + + The following error types are supported: + + memory controller - Memory controller + PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache + L3 - L3 cache controller + SoC - SoC IPs such as Ethernet, SATA, etc + +properties: + compatible: + const: apm,xgene-edac + + reg: + items: + - description: CPU bus (PCP) resource + + '#address-cells': + const: 2 + + '#size-cells': + const: 2 + + ranges: true + + interrupts: + description: Interrupt-specifier for MCU, PMD, L3, or SoC error IRQ(s). + items: + - description: MCU error IRQ + - description: PMD error IRQ + - description: L3 error IRQ + - description: SoC error IRQ + minItems: 1 + + regmap-csw: + description: Regmap of the CPU switch fabric (CSW) resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcba: + description: Regmap of the MCB-A (memory bridge) resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcbb: + description: Regmap of the MCB-B (memory bridge) resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-efuse: + description: Regmap of the PMD efuse resource. + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-rb: + description: Regmap of the register bus resource (optional for compatibility). + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - regmap-csw + - regmap-mcba + - regmap-mcbb + - regmap-efuse + - reg + - interrupts + +# Child-node bindings +patternProperties: + '^edacmc@': + description: Memory controller subnode + type: object + additionalProperties: false + + properties: + compatible: + const: apm,xgene-edac-mc + + reg: + maxItems: 1 + + memory-controller: + description: Instance number of the memory controller. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + required: + - compatible + - reg + - memory-controller + + + '^edacpmd@': + description: PMD subnode + type: object + additionalProperties: false + + properties: + compatible: + const: apm,xgene-edac-pmd + + reg: + maxItems: 1 + + pmd-controller: + description: Instance number of the PMD controller. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 3 + + required: + - compatible + - reg + - pmd-controller + + '^edacl3@': + description: L3 subnode + type: object + additionalProperties: false + + properties: + compatible: + enum: + - apm,xgene-edac-l3 + - apm,xgene-edac-l3-v2 + + reg: + maxItems: 1 + + required: + - compatible + - reg + + '^edacsoc@': + description: SoC subnode + type: object + additionalProperties: false + + properties: + compatible: + enum: + - apm,xgene-edac-soc + - apm,xgene-edac-soc-v1 + + reg: + maxItems: 1 + + required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + edac@78800000 { + compatible = "apm,xgene-edac"; + reg = <0x0 0x78800000 0x0 0x100>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + interrupts = <0x0 0x20 0x4>, <0x0 0x21 0x4>, <0x0 0x27 0x4>; + + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + regmap-efuse = <&efuse>; + regmap-rb = <&rb>; + + edacmc@7e800000 { + compatible = "apm,xgene-edac-mc"; + reg = <0x0 0x7e800000 0x0 0x1000>; + memory-controller = <0>; + }; + + edacpmd@7c000000 { + compatible = "apm,xgene-edac-pmd"; + reg = <0x0 0x7c000000 0x0 0x200000>; + pmd-controller = <0>; + }; + + edacl3@7e600000 { + compatible = "apm,xgene-edac-l3"; + reg = <0x0 0x7e600000 0x0 0x1000>; + }; + + edacsoc@7e930000 { + compatible = "apm,xgene-edac-soc-v1"; + reg = <0x0 0x7e930000 0x0 0x1000>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt b/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt deleted file mode 100644 index 1006b0489464..000000000000 --- a/Documentation/devicetree/bindings/edac/apm-xgene-edac.txt +++ /dev/null @@ -1,112 +0,0 @@ -* APM X-Gene SoC EDAC node - -EDAC node is defined to describe on-chip error detection and correction. -The follow error types are supported: - - memory controller - Memory controller - PMD (L1/L2) - Processor module unit (PMD) L1/L2 cache - L3 - L3 cache controller - SoC - SoC IP's such as Ethernet, SATA, and etc - -The following section describes the EDAC DT node binding. - -Required properties: -- compatible : Shall be "apm,xgene-edac". -- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. -- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. -- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. -- regmap-efuse : Regmap of the PMD efuse resource. -- regmap-rb : Regmap of the register bus resource. This property - is optional only for compatibility. If the RB - error conditions are not cleared, it will - continuously generate interrupt. -- reg : First resource shall be the CPU bus (PCP) resource. -- interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error - IRQ(s). - -Required properties for memory controller subnode: -- compatible : Shall be "apm,xgene-edac-mc". -- reg : First resource shall be the memory controller unit - (MCU) resource. -- memory-controller : Instance number of the memory controller. - -Required properties for PMD subnode: -- compatible : Shall be "apm,xgene-edac-pmd" or - "apm,xgene-edac-pmd-v2". -- reg : First resource shall be the PMD resource. -- pmd-controller : Instance number of the PMD controller. - -Required properties for L3 subnode: -- compatible : Shall be "apm,xgene-edac-l3" or - "apm,xgene-edac-l3-v2". -- reg : First resource shall be the L3 EDAC resource. - -Required properties for SoC subnode: -- compatible : Shall be "apm,xgene-edac-soc-v1" for revision 1 or - "apm,xgene-edac-l3-soc" for general value reporting - only. -- reg : First resource shall be the SoC EDAC resource. - -Example: - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - efuse: efuse@1054a000 { - compatible = "apm,xgene-efuse", "syscon"; - reg = <0x0 0x1054a000 0x0 0x20>; - }; - - rb: rb@7e000000 { - compatible = "apm,xgene-rb", "syscon"; - reg = <0x0 0x7e000000 0x0 0x10>; - }; - - edac@78800000 { - compatible = "apm,xgene-edac"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - regmap-efuse = <&efuse>; - regmap-rb = <&rb>; - reg = <0x0 0x78800000 0x0 0x100>; - interrupts = <0x0 0x20 0x4>, - <0x0 0x21 0x4>, - <0x0 0x27 0x4>; - - edacmc@7e800000 { - compatible = "apm,xgene-edac-mc"; - reg = <0x0 0x7e800000 0x0 0x1000>; - memory-controller = <0>; - }; - - edacpmd@7c000000 { - compatible = "apm,xgene-edac-pmd"; - reg = <0x0 0x7c000000 0x0 0x200000>; - pmd-controller = <0>; - }; - - edacl3@7e600000 { - compatible = "apm,xgene-edac-l3"; - reg = <0x0 0x7e600000 0x0 0x1000>; - }; - - edacsoc@7e930000 { - compatible = "apm,xgene-edac-soc-v1"; - reg = <0x0 0x7e930000 0x0 0x1000>; - }; - }; diff --git a/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml new file mode 100644 index 000000000000..09735826d707 --- /dev/null +++ b/Documentation/devicetree/bindings/edac/aspeed,ast2400-sdram-edac.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/edac/aspeed,ast2400-sdram-edac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Aspeed BMC SoC SDRAM EDAC controller + +maintainers: + - Stefan Schaeckeler <sschaeck@cisco.com> + +description: > + The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error + correction check). + + The memory controller supports SECDED (single bit error correction, double bit + error detection) and single bit error auto scrubbing by reserving 8 bits for + every 64 bit word (effectively reducing available memory to 8/9). + + Note, the bootloader must configure ECC mode in the memory controller. + +properties: + compatible: + enum: + - aspeed,ast2400-sdram-edac + - aspeed,ast2500-sdram-edac + - aspeed,ast2600-sdram-edac + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + sdram@1e6e0000 { + compatible = "aspeed,ast2500-sdram-edac"; + reg = <0x1e6e0000 0x174>; + interrupts = <0>; + }; diff --git a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt b/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt deleted file mode 100644 index 8ca9e0a049d8..000000000000 --- a/Documentation/devicetree/bindings/edac/aspeed-sdram-edac.txt +++ /dev/null @@ -1,28 +0,0 @@ -Aspeed BMC SoC EDAC node - -The Aspeed BMC SoC supports DDR3 and DDR4 memory with and without ECC (error -correction check). - -The memory controller supports SECDED (single bit error correction, double bit -error detection) and single bit error auto scrubbing by reserving 8 bits for -every 64 bit word (effectively reducing available memory to 8/9). - -Note, the bootloader must configure ECC mode in the memory controller. - - -Required properties: -- compatible: should be one of - - "aspeed,ast2400-sdram-edac" - - "aspeed,ast2500-sdram-edac" - - "aspeed,ast2600-sdram-edac" -- reg: sdram controller register set should be <0x1e6e0000 0x174> -- interrupts: should be AVIC interrupt #0 - - -Example: - - edac: sdram@1e6e0000 { - compatible = "aspeed,ast2500-sdram-edac"; - reg = <0x1e6e0000 0x174>; - interrupts = <0>; - }; diff --git a/Documentation/devicetree/bindings/eeprom/at24.yaml b/Documentation/devicetree/bindings/eeprom/at24.yaml index 0ac68646c077..50af7ccf6e21 100644 --- a/Documentation/devicetree/bindings/eeprom/at24.yaml +++ b/Documentation/devicetree/bindings/eeprom/at24.yaml @@ -143,6 +143,7 @@ properties: - const: atmel,24c128 - items: - enum: + - giantec,gt24c256c - puya,p24c256c - const: atmel,24c256 - items: diff --git a/Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/acer,aspire1-ec.yaml index 7cb0134134ff..01ee61768527 100644 --- a/Documentation/devicetree/bindings/platform/acer,aspire1-ec.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/acer,aspire1-ec.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/platform/acer,aspire1-ec.yaml# +$id: http://devicetree.org/schemas/embedded-controller/acer,aspire1-ec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Acer Aspire 1 Embedded Controller diff --git a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml index 50f457090066..3ab5737c9a8f 100644 --- a/Documentation/devicetree/bindings/mfd/google,cros-ec.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/mfd/google,cros-ec.yaml# +$id: http://devicetree.org/schemas/embedded-controller/google,cros-ec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: ChromeOS Embedded Controller diff --git a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml b/Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml index dc379f3ebf24..82d4b2dadbae 100644 --- a/Documentation/devicetree/bindings/mfd/gateworks-gsc.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/gw,gsc.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause %YAML 1.2 --- -$id: http://devicetree.org/schemas/mfd/gateworks-gsc.yaml# +$id: http://devicetree.org/schemas/embedded-controller/gw,gsc.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Gateworks System Controller diff --git a/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml index 4a03b0ee3149..cd9e65b6c2ea 100644 --- a/Documentation/devicetree/bindings/platform/huawei,gaokun-ec.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/huawei,gaokun3-ec.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/platform/huawei,gaokun-ec.yaml# +$id: http://devicetree.org/schemas/embedded-controller/huawei,gaokun3-ec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Huawei Matebook E Go Embedded Controller diff --git a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml index 37207a97e06c..a77e67f6cb82 100644 --- a/Documentation/devicetree/bindings/mfd/kontron,sl28cpld.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/kontron,sl28cpld.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/mfd/kontron,sl28cpld.yaml# +$id: http://devicetree.org/schemas/embedded-controller/kontron,sl28cpld.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Kontron's sl28cpld board management controller @@ -16,7 +16,12 @@ description: | properties: compatible: - const: kontron,sl28cpld + oneOf: + - items: + - enum: + - kontron,sa67mcu + - const: kontron,sl28cpld + - const: kontron,sl28cpld reg: description: diff --git a/Documentation/devicetree/bindings/platform/lenovo,yoga-c630-ec.yaml b/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-c630-ec.yaml index 3180ce1a22d4..a029b38e8dc0 100644 --- a/Documentation/devicetree/bindings/platform/lenovo,yoga-c630-ec.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/lenovo,yoga-c630-ec.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/platform/lenovo,yoga-c630-ec.yaml# +$id: http://devicetree.org/schemas/embedded-controller/lenovo,yoga-c630-ec.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Lenovo Yoga C630 Embedded Controller. diff --git a/Documentation/devicetree/bindings/platform/microsoft,surface-sam.yaml b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-sam.yaml index b33d26f15b2a..9202cfca0b35 100644 --- a/Documentation/devicetree/bindings/platform/microsoft,surface-sam.yaml +++ b/Documentation/devicetree/bindings/embedded-controller/microsoft,surface-sam.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/platform/microsoft,surface-sam.yaml# +$id: http://devicetree.org/schemas/embedded-controller/microsoft,surface-sam.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Surface System Aggregator Module (SAM, SSAM) diff --git a/Documentation/devicetree/bindings/example-schema.yaml b/Documentation/devicetree/bindings/example-schema.yaml index c731d5045e80..b04f3cc4312c 100644 --- a/Documentation/devicetree/bindings/example-schema.yaml +++ b/Documentation/devicetree/bindings/example-schema.yaml @@ -223,7 +223,7 @@ required: # # For multiple 'if' schema, group them under an 'allOf'. # -# If the conditionals become too unweldy, then it may be better to just split +# If the conditionals become too unwieldy, then it may be better to just split # the binding into separate schema documents. allOf: - if: diff --git a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml index abbd62f1fed0..be817fd9cc34 100644 --- a/Documentation/devicetree/bindings/firmware/arm,scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/arm,scmi.yaml @@ -27,7 +27,7 @@ anyOf: properties: $nodename: - const: scmi + pattern: '^scmi(-[0-9]+)?$' compatible: oneOf: diff --git a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml index 2bda2e0e1369..7a5a02da2719 100644 --- a/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml +++ b/Documentation/devicetree/bindings/firmware/nxp,imx95-scmi.yaml @@ -24,13 +24,19 @@ properties: const: 0x80 protocol@81: - $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' - unevaluatedProperties: false + type: object + allOf: + - $ref: '/schemas/firmware/arm,scmi.yaml#/$defs/protocol-node' + - $ref: /schemas/input/input.yaml# + additionalProperties: false properties: reg: const: 0x81 + linux,code: + default: 116 # KEY_POWER + protocol@82: description: SCMI CPU Protocol which allows an agent to start or stop a CPU. It is diff --git a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml index b913192219e4..ef97faac7e47 100644 --- a/Documentation/devicetree/bindings/firmware/qcom,scm.yaml +++ b/Documentation/devicetree/bindings/firmware/qcom,scm.yaml @@ -36,6 +36,7 @@ properties: - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -134,6 +135,7 @@ allOf: - qcom,scm-msm8226 - qcom,scm-msm8660 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8960 - qcom,scm-msm8974 @@ -177,6 +179,7 @@ allOf: - qcom,scm-mdm9607 - qcom,scm-msm8226 - qcom,scm-msm8916 + - qcom,scm-msm8937 - qcom,scm-msm8953 - qcom,scm-msm8974 - qcom,scm-msm8976 diff --git a/Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml b/Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml new file mode 100644 index 000000000000..690b6c936f18 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/aspeed,ast2400-cf-fsi-master.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/aspeed,ast2400-cf-fsi-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASpeed ColdFire offloaded GPIO-based FSI master + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +allOf: + - $ref: /schemas/fsi/fsi-controller.yaml# + +properties: + compatible: + enum: + - aspeed,ast2400-cf-fsi-master + - aspeed,ast2500-cf-fsi-master + + clock-gpios: + maxItems: 1 + description: GPIO for FSI clock + + data-gpios: + maxItems: 1 + description: GPIO for FSI data signal + + enable-gpios: + maxItems: 1 + description: GPIO for enable signal + + trans-gpios: + maxItems: 1 + description: GPIO for voltage translator enable + + mux-gpios: + maxItems: 1 + description: + GPIO for pin multiplexing with other functions (eg, external FSI masters) + + memory-region: + maxItems: 1 + description: + Reference to the reserved memory for the ColdFire. Must be 2M aligned on + AST2400 and 1M aligned on AST2500. + + aspeed,cvic: + description: Reference to the CVIC node. + $ref: /schemas/types.yaml#/definitions/phandle + + aspeed,sram: + description: Reference to the SRAM node. + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - clock-gpios + - data-gpios + - enable-gpios + - trans-gpios + - mux-gpios + - memory-region + - aspeed,cvic + - aspeed,sram + +unevaluatedProperties: false + +examples: + - | + fsi-master { + compatible = "aspeed,ast2500-cf-fsi-master"; + clock-gpios = <&gpio 0>; + data-gpios = <&gpio 1>; + enable-gpios = <&gpio 2>; + trans-gpios = <&gpio 3>; + mux-gpios = <&gpio 4>; + memory-region = <&coldfire_memory>; + aspeed,cvic = <&cvic>; + aspeed,sram = <&sram>; + }; diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt b/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt deleted file mode 100644 index 3dc752db748b..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-ast-cf.txt +++ /dev/null @@ -1,36 +0,0 @@ -Device-tree bindings for ColdFire offloaded gpio-based FSI master driver ------------------------------------------------------------------------- - -Required properties: - - compatible = - "aspeed,ast2400-cf-fsi-master" for an AST2400 based system - or - "aspeed,ast2500-cf-fsi-master" for an AST2500 based system - - - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock - - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal - - enable-gpios = <gpio-descriptor>; : GPIO for enable signal - - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable - - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other - functions (eg, external FSI masters) - - memory-region = <phandle>; : Reference to the reserved memory for - the ColdFire. Must be 2M aligned on - AST2400 and 1M aligned on AST2500 - - aspeed,sram = <phandle>; : Reference to the SRAM node. - - aspeed,cvic = <phandle>; : Reference to the CVIC node. - -Examples: - - fsi-master { - compatible = "aspeed,ast2500-cf-fsi-master", "fsi-master"; - - clock-gpios = <&gpio 0>; - data-gpios = <&gpio 1>; - enable-gpios = <&gpio 2>; - trans-gpios = <&gpio 3>; - mux-gpios = <&gpio 4>; - - memory-region = <&coldfire_memory>; - aspeed,sram = <&sram>; - aspeed,cvic = <&cvic>; - } diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt deleted file mode 100644 index 1e442450747f..000000000000 --- a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.txt +++ /dev/null @@ -1,28 +0,0 @@ -Device-tree bindings for gpio-based FSI master driver ------------------------------------------------------ - -Required properties: - - compatible = "fsi-master-gpio"; - - clock-gpios = <gpio-descriptor>; : GPIO for FSI clock - - data-gpios = <gpio-descriptor>; : GPIO for FSI data signal - -Optional properties: - - enable-gpios = <gpio-descriptor>; : GPIO for enable signal - - trans-gpios = <gpio-descriptor>; : GPIO for voltage translator enable - - mux-gpios = <gpio-descriptor>; : GPIO for pin multiplexing with other - functions (eg, external FSI masters) - - no-gpio-delays; : Don't add extra delays between GPIO - accesses. This is useful when the HW - GPIO block is running at a low enough - frequency. - -Examples: - - fsi-master { - compatible = "fsi-master-gpio", "fsi-master"; - clock-gpios = <&gpio 0>; - data-gpios = <&gpio 1>; - enable-gpios = <&gpio 2>; - trans-gpios = <&gpio 3>; - mux-gpios = <&gpio 4>; - } diff --git a/Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml new file mode 100644 index 000000000000..21bfbad595b3 --- /dev/null +++ b/Documentation/devicetree/bindings/fsi/fsi-master-gpio.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/fsi/fsi-master-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: fsi-master-gpio + +maintainers: + - Eddie James <eajames@linux.ibm.com> + +allOf: + - $ref: /schemas/fsi/fsi-controller.yaml + +properties: + compatible: + items: + - const: fsi-master-gpio + + clock-gpios: + description: GPIO for FSI clock + maxItems: 1 + + data-gpios: + description: GPIO for FSI data signal + maxItems: 1 + + enable-gpios: + description: GPIO for enable signal + maxItems: 1 + + trans-gpios: + description: GPIO for voltage translator enable + maxItems: 1 + + mux-gpios: + description: GPIO for pin multiplexing with other functions (eg, external + FSI masters) + maxItems: 1 + + no-gpio-delays: + description: + Don't add extra delays between GPIO accesses. This is useful when the HW + GPIO block is running at a low enough frequency. + type: boolean + +required: + - compatible + - clock-gpios + - data-gpios + +unevaluatedProperties: false + +examples: + - | + fsi-master { + compatible = "fsi-master-gpio"; + clock-gpios = <&gpio 0>; + data-gpios = <&gpio 1>; + enable-gpios = <&gpio 2>; + trans-gpios = <&gpio 3>; + mux-gpios = <&gpio 4>; + }; diff --git a/Documentation/devicetree/bindings/goldfish/pipe.txt b/Documentation/devicetree/bindings/goldfish/pipe.txt index e417a31a1ee3..5637ce701788 100644 --- a/Documentation/devicetree/bindings/goldfish/pipe.txt +++ b/Documentation/devicetree/bindings/goldfish/pipe.txt @@ -1,6 +1,6 @@ Android Goldfish QEMU Pipe -Andorid pipe virtual device generated by android emulator. +Android pipe virtual device generated by android emulator. Required properties: diff --git a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml index 87e986386f32..b4d55bf6a285 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mmio.yaml @@ -22,6 +22,7 @@ properties: - brcm,bcm6345-gpio - ni,169445-nand-gpio - wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller + - intel,ixp4xx-expansion-bus-mmio-gpio big-endian: true @@ -89,6 +90,20 @@ properties: description: If this property is present, the controller cannot drive the GPIO lines. +if: + properties: + compatible: + contains: + const: intel,ixp4xx-expansion-bus-mmio-gpio +then: + $ref: /schemas/memory-controllers/intel,ixp4xx-expansion-peripheral-props.yaml# + +patternProperties: + "^.+-hog(-[0-9]+)?$": + type: object + required: + - gpio-hog + required: - compatible - reg @@ -96,7 +111,7 @@ required: - '#gpio-cells' - gpio-controller -additionalProperties: false +unevaluatedProperties: false examples: - | @@ -126,3 +141,22 @@ examples: gpio-controller; #gpio-cells = <2>; }; + + bus@c4000000 { + compatible = "intel,ixp42x-expansion-bus-controller", "syscon"; + reg = <0xc4000000 0x30>; + native-endian; + #address-cells = <2>; + #size-cells = <1>; + ranges = <0 0x0 0x50000000 0x01000000>; + dma-ranges = <0 0x0 0x50000000 0x01000000>; + gpio@1,0 { + compatible = "intel,ixp4xx-expansion-bus-mmio-gpio"; + gpio-controller; + #gpio-cells = <2>; + big-endian; + reg = <1 0x00000000 0x2>; + reg-names = "dat"; + intel,ixp4xx-eb-write-enable = <1>; + }; + }; diff --git a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml index b58e08c8ecd8..aaf97124803f 100644 --- a/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml +++ b/Documentation/devicetree/bindings/gpio/gpio-mxs.yaml @@ -18,9 +18,13 @@ description: | properties: compatible: - enum: - - fsl,imx23-pinctrl - - fsl,imx28-pinctrl + items: + - enum: + - fsl,imx23-pinctrl + - fsl,imx28-pinctrl + # Over 10 years old devices, driver use simple-bus to probe child gpio + # Devices. Keep it as it to be compatible existed dts files. + - const: simple-bus '#address-cells': const: 1 @@ -31,7 +35,65 @@ properties: maxItems: 1 patternProperties: - "gpio@[0-9]+$": + "^(?!gpio@)[^@]+@[0-9]+$": + type: object + properties: + fsl,pinmux-ids: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + An integer array. Each integer in the array specify a pin + with given mux function, with bank, pin and mux packed as below. + + [15..12] : bank number + [11..4] : pin number + [3..0] : mux selection + + This integer with mux selection packed is used as an entity by both group + and config nodes to identify a pin. The mux selection in the integer takes + effects only on group node, and will get ignored by driver with config node, + since config node is only meant to set up pin configurations. + + Valid values for these integers are listed below. + + reg: + items: + - description: | + pin group index. NOTE: it is supposed wrong use reg property + here. But it is over 10 years devices. Just keep it as it. + + fsl,drive-strength: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + description: | + 0: MXS_DRIVE_4mA + 1: MXS_DRIVE_8mA + 2: MXS_DRIVE_12mA + 3: MXS_DRIVE_16mA + + fsl,voltage: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + 0: MXS_VOLTAGE_LOW - 1.8 V + 1: MXS_VOLTAGE_HIGH - 3.3 V + + fsl,pull-up: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: | + 0: MXS_PULL_DISABLE - Disable the internal pull-up + 1: MXS_PULL_ENABLE - Enable the internal pull-up + + Note that when enabling the pull-up, the internal pad keeper gets disabled. + Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up + will only disable the internal pad keeper. + + required: + - fsl,pinmux-ids + + additionalProperties: false + + "^gpio@[0-9]+$": type: object properties: compatible: @@ -80,7 +142,7 @@ examples: pinctrl@80018000 { #address-cells = <1>; #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; + compatible = "fsl,imx28-pinctrl", "simple-bus"; reg = <0x80018000 0x2000>; gpio@0 { @@ -132,4 +194,12 @@ examples: interrupt-controller; #interrupt-cells = <2>; }; + + lcdif-apx4@5 { + reg = <5>; + fsl,pinmux-ids = <0x1181 0x1191>; + fsl,drive-strength = <0>; + fsl,voltage = <0>; + fsl,pull-up = <0>; + }; }; diff --git a/Documentation/devicetree/bindings/gpio/gpio.txt b/Documentation/devicetree/bindings/gpio/gpio.txt index d82c32217fff..b37dbb1edc62 100644 --- a/Documentation/devicetree/bindings/gpio/gpio.txt +++ b/Documentation/devicetree/bindings/gpio/gpio.txt @@ -35,8 +35,8 @@ and bit-banged data signals: <&gpio1 15 0>; In the above example, &gpio1 uses 2 cells to specify a gpio. The first cell is -a local offset to the GPIO line and the second cell represent consumer flags, -such as if the consumer desire the line to be active low (inverted) or open +a local offset to the GPIO line and the second cell represents consumer flags, +such as if the consumer desires the line to be active low (inverted) or open drain. This is the recommended practice. The exact meaning of each specifier cell is controller specific, and must be @@ -59,7 +59,7 @@ GPIO pin number, and GPIO flags as accepted by the "qe_pio_e" gpio-controller. Optional standard bitfield specifiers for the last cell: - Bit 0: 0 means active high, 1 means active low -- Bit 1: 0 mean push-pull wiring, see: +- Bit 1: 0 means push-pull wiring, see: https://en.wikipedia.org/wiki/Push-pull_output 1 means single-ended wiring, see: https://en.wikipedia.org/wiki/Single-ended_triode @@ -176,7 +176,7 @@ example of a name from an SoC's reference manual) would not be desirable. In either case placeholders are discouraged: rather use the "" (blank string) if the use of the GPIO line is undefined in your design. Ideally, -try to add comments to the dts file describing the naming the convention +try to add comments to the dts file describing the naming convention you have chosen, and specifying from where the names are derived. The names are assigned starting from line offset 0, from left to right, @@ -304,7 +304,7 @@ pins 50..69. It is also possible to use pin groups for gpio ranges when pin groups are the easiest and most convenient mapping. -Both both <pinctrl-base> and <count> must set to 0 when using named pin groups +Both <pinctrl-base> and <count> must be set to 0 when using named pin groups names. The property gpio-ranges-group-names must contain exactly one string for each @@ -313,7 +313,7 @@ range. Elements of gpio-ranges-group-names must contain the name of a pin group defined in the respective pin controller. The number of pins/GPIO lines in the range is the number of pins in that pin group. The number of pins of that -group is defined int the implementation and not in the device tree. +group is defined in the implementation and not in the device tree. If numerical and named pin groups are mixed, the string corresponding to a numerical pin range in gpio-ranges-group-names must be empty. diff --git a/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml b/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml index b032471831e7..02663d67eac7 100644 --- a/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/kontron,sl28cpld-gpio.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. There are three flavors of the GPIO controller, one full featured input/output with interrupt support (kontron,sl28cpld-gpio), one diff --git a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml index b68159600e2b..69852444df23 100644 --- a/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/loongson,ls-gpio.yaml @@ -14,6 +14,7 @@ properties: oneOf: - enum: - loongson,ls2k-gpio + - loongson,ls2k0300-gpio - loongson,ls2k0500-gpio0 - loongson,ls2k0500-gpio1 - loongson,ls2k2000-gpio0 @@ -36,7 +37,7 @@ properties: ngpios: minimum: 1 - maximum: 64 + maximum: 128 "#gpio-cells": const: 2 @@ -49,6 +50,14 @@ properties: minItems: 1 maxItems: 64 + "#interrupt-cells": + const: 2 + + interrupt-controller: true + + resets: + maxItems: 1 + required: - compatible - reg @@ -58,6 +67,23 @@ required: - gpio-ranges - interrupts +allOf: + - if: + properties: + compatible: + contains: + const: loongson,ls2k0300-gpio + then: + required: + - "#interrupt-cells" + - interrupt-controller + - resets + else: + properties: + "#interrupts-cells": false + interrupt-controller: false + resets: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml b/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml index 82a190a715f9..4d200f9dffd5 100644 --- a/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml +++ b/Documentation/devicetree/bindings/gpio/maxim,max31910.yaml @@ -95,9 +95,9 @@ examples: #gpio-cells = <2>; maxim,modesel-gpios = <&gpio2 23>; - maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; - maxim,db0-gpios = <&gpio2 25>; - maxim,db1-gpios = <&gpio2 26>; + maxim,fault-gpios = <&gpio2 24 GPIO_ACTIVE_LOW>; + maxim,db0-gpios = <&gpio2 25>; + maxim,db1-gpios = <&gpio2 26>; spi-max-frequency = <25000000>; }; diff --git a/Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml b/Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml new file mode 100644 index 000000000000..c5c3fc4c816f --- /dev/null +++ b/Documentation/devicetree/bindings/gpio/maxim,max7360-gpio.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpio/maxim,max7360-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX7360 GPIO controller + +maintainers: + - Kamel Bouhara <kamel.bouhara@bootlin.com> + - Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> + +description: | + Maxim MAX7360 GPIO controller, in MAX7360 chipset + https://www.analog.com/en/products/max7360.html + + The device provides two series of GPIOs, referred here as GPIOs and GPOs. + + PORT0 to PORT7 pins can be used as GPIOs, with support for interrupts and + constant-current mode. These pins will also be used by the rotary encoder and + PWM functionalities. + + COL2 to COL7 pins can be used as GPOs, there is no input capability. COL pins + will be partitioned, with the first pins being affected to the keypad + functionality and the last ones as GPOs. + +properties: + compatible: + enum: + - maxim,max7360-gpio + - maxim,max7360-gpo + + gpio-controller: true + + "#gpio-cells": + const: 2 + + interrupt-controller: true + + "#interrupt-cells": + const: 2 + + maxim,constant-current-disable: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Bit field, each bit disables constant-current output of the associated + GPIO, starting from the least significant bit for the first GPIO. + maximum: 0xff + +required: + - compatible + - gpio-controller + +allOf: + - if: + properties: + compatible: + contains: + enum: + - maxim,max7360-gpio + ngpios: false + then: + required: + - interrupt-controller + else: + properties: + interrupt-controller: false + maxim,constant-current-disable: false + +additionalProperties: false + +examples: + - | + gpio { + compatible = "maxim,max7360-gpio"; + + gpio-controller; + #gpio-cells = <2>; + maxim,constant-current-disable = <0x06>; + + interrupt-controller; + #interrupt-cells = <2>; + }; diff --git a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml index 065f5761a93f..2bd620a1099b 100644 --- a/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml @@ -85,6 +85,7 @@ properties: - nvidia,tegra194-gpio-aon - nvidia,tegra234-gpio - nvidia,tegra234-gpio-aon + - nvidia,tegra256-gpio reg-names: items: @@ -155,6 +156,7 @@ allOf: - nvidia,tegra186-gpio - nvidia,tegra194-gpio - nvidia,tegra234-gpio + - nvidia,tegra256-gpio then: properties: interrupts: diff --git a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml index ec0232e72c71..83e0b2d14c9f 100644 --- a/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml @@ -80,7 +80,7 @@ examples: gpio@d4019000 { compatible = "spacemit,k1-gpio"; reg = <0xd4019000 0x800>; - clocks =<&ccu 9>, <&ccu 61>; + clocks = <&ccu 9>, <&ccu 61>; clock-names = "core", "bus"; gpio-controller; #gpio-cells = <3>; diff --git a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml index 0299d4a25086..c994177de940 100644 --- a/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml +++ b/Documentation/devicetree/bindings/gpio/trivial-gpio.yaml @@ -1,7 +1,7 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) %YAML 1.2 --- -$id: http://devicetree.org/schemas/trivial-gpio.yaml# +$id: http://devicetree.org/schemas/gpio/trivial-gpio.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# title: Trivial 2-cell GPIO controllers diff --git a/Documentation/devicetree/bindings/gpu/apple,agx.yaml b/Documentation/devicetree/bindings/gpu/apple,agx.yaml index 51629b3833b0..05af942ad174 100644 --- a/Documentation/devicetree/bindings/gpu/apple,agx.yaml +++ b/Documentation/devicetree/bindings/gpu/apple,agx.yaml @@ -16,11 +16,17 @@ properties: - apple,agx-g13g - apple,agx-g13s - apple,agx-g14g + - apple,agx-g14s - items: - enum: - apple,agx-g13c - apple,agx-g13d - const: apple,agx-g13s + - items: + - enum: + - apple,agx-g14c + - apple,agx-g14d + - const: apple,agx-g14s reg: items: diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml index 48daba21a890..a7192622e120 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml +++ b/Documentation/devicetree/bindings/gpu/arm,mali-midgard.yaml @@ -53,8 +53,10 @@ properties: - enum: - rockchip,rk3399-mali - const: arm,mali-t860 - - # "arm,mali-t880" + - items: + - enum: + - samsung,exynos8890-mali + - const: arm,mali-t880 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml b/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml new file mode 100644 index 000000000000..20a4e00086ee --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/aspeed,ast2400-gfx.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/aspeed,ast2400-gfx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ASPEED GFX Display Controller + +maintainers: + - Joel Stanley <joel@jms.id.au> + +properties: + compatible: + items: + - enum: + - aspeed,ast2400-gfx + - aspeed,ast2500-gfx + - aspeed,ast2600-gfx + - const: syscon + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + interrupts: + maxItems: 1 + + memory-region: + maxItems: 1 + description: + a reserved-memory region to use for the framebuffer. + + syscon: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to SCU + +required: + - compatible + - reg + - interrupts + - clocks + - resets + - memory-region + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/aspeed-clock.h> + + display@1e6e6000 { + compatible = "aspeed,ast2500-gfx", "syscon"; + reg = <0x1e6e6000 0x1000>; + clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; + resets = <&syscon ASPEED_RESET_CRT1>; + interrupts = <0x19>; + memory-region = <&gfx_memory>; + }; diff --git a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt b/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt deleted file mode 100644 index 958bdf962339..000000000000 --- a/Documentation/devicetree/bindings/gpu/aspeed-gfx.txt +++ /dev/null @@ -1,41 +0,0 @@ -Device tree configuration for the GFX display device on the ASPEED SoCs - -Required properties: - - compatible - * Must be one of the following: - + aspeed,ast2500-gfx - + aspeed,ast2400-gfx - * In addition, the ASPEED pinctrl bindings require the 'syscon' property to - be present - - - reg: Physical base address and length of the GFX registers - - - interrupts: interrupt number for the GFX device - - - clocks: clock number used to generate the pixel clock - - - resets: reset line that must be released to use the GFX device - - - memory-region: - Phandle to a memory region to allocate from, as defined in - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt - - -Example: - -gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; - reg-io-width = <4>; - clocks = <&syscon ASPEED_CLK_GATE_D1CLK>; - resets = <&syscon ASPEED_RESET_CRT1>; - interrupts = <0x19>; - memory-region = <&gfx_memory>; -}; - -gfx_memory: framebuffer { - size = <0x01000000>; - alignment = <0x01000000>; - compatible = "shared-dma-pool"; - reusable; -}; diff --git a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml index 4450e2e73b3c..c87d7bece0ec 100644 --- a/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml +++ b/Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml @@ -23,6 +23,11 @@ properties: - const: img,img-rogue - items: - enum: + - thead,th1520-gpu + - const: img,img-bxm-4-64 + - const: img,img-rogue + - items: + - enum: - ti,j721s2-gpu - const: img,img-bxs-4-64 - const: img,img-rogue @@ -77,14 +82,18 @@ required: additionalProperties: false allOf: - # Constraints added alongside the new compatible strings that would otherwise - # create an ABI break. - if: properties: compatible: contains: - const: img,img-rogue + const: img,img-axe-1-16m then: + properties: + power-domains: + items: + - description: Power domain A + power-domain-names: + maxItems: 1 required: - power-domains - power-domain-names @@ -93,13 +102,20 @@ allOf: properties: compatible: contains: - const: img,img-axe-1-16m + const: thead,th1520-gpu then: properties: + clocks: + minItems: 3 + clock-names: + minItems: 3 power-domains: - maxItems: 1 - power-domain-names: - maxItems: 1 + items: + - description: The single, unified power domain for the GPU on the + TH1520 SoC, integrating all internal IP power domains. + power-domain-names: false + required: + - power-domains - if: properties: @@ -109,9 +125,14 @@ allOf: then: properties: power-domains: - minItems: 2 + items: + - description: Power domain A + - description: Power domain B power-domain-names: minItems: 2 + required: + - power-domains + - power-domain-names - if: properties: diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt deleted file mode 100644 index cc6ce5221a38..000000000000 --- a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.txt +++ /dev/null @@ -1,115 +0,0 @@ -NVIDIA Tegra Graphics Processing Units - -Required properties: -- compatible: "nvidia,<gpu>" - Currently recognized values: - - nvidia,gk20a - - nvidia,gm20b - - nvidia,gp10b - - nvidia,gv11b -- reg: Physical base address and length of the controller's registers. - Must contain two entries: - - first entry for bar0 - - second entry for bar1 -- interrupts: Must contain an entry for each entry in interrupt-names. - See ../interrupt-controller/interrupts.txt for details. -- interrupt-names: Must include the following entries: - - stall - - nonstall -- vdd-supply: regulator for supply voltage. Only required for GPUs not using - power domains. -- clocks: Must contain an entry for each entry in clock-names. - See ../clocks/clock-bindings.txt for details. -- clock-names: Must include the following entries: - - gpu - - pwr -If the compatible string is "nvidia,gm20b", then the following clock -is also required: - - ref -If the compatible string is "nvidia,gv11b", then the following clock is also -required: - - fuse -- resets: Must contain an entry for each entry in reset-names. - See ../reset/reset.txt for details. -- reset-names: Must include the following entries: - - gpu -- power-domains: GPUs that make use of power domains can define this property - instead of vdd-supply. Currently "nvidia,gp10b" makes use of this. - -Optional properties: -- iommus: A reference to the IOMMU. See ../iommu/iommu.txt for details. - -Example for GK20A: - - gpu@57000000 { - compatible = "nvidia,gk20a"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "stall", "nonstall"; - vdd-supply = <&vdd_gpu>; - clocks = <&tegra_car TEGRA124_CLK_GPU>, - <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; - clock-names = "gpu", "pwr"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - iommus = <&mc TEGRA_SWGROUP_GPU>; - }; - -Example for GM20B: - - gpu@57000000 { - compatible = "nvidia,gm20b"; - reg = <0x0 0x57000000 0x0 0x01000000>, - <0x0 0x58000000 0x0 0x01000000>; - interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "stall", "nonstall"; - clocks = <&tegra_car TEGRA210_CLK_GPU>, - <&tegra_car TEGRA210_CLK_PLL_P_OUT5>, - <&tegra_car TEGRA210_CLK_PLL_G_REF>; - clock-names = "gpu", "pwr", "ref"; - resets = <&tegra_car 184>; - reset-names = "gpu"; - iommus = <&mc TEGRA_SWGROUP_GPU>; - }; - -Example for GP10B: - - gpu@17000000 { - compatible = "nvidia,gp10b"; - reg = <0x0 0x17000000 0x0 0x1000000>, - <0x0 0x18000000 0x0 0x1000000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH - GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA186_CLK_GPCCLK>, - <&bpmp TEGRA186_CLK_GPU>; - clock-names = "gpu", "pwr"; - resets = <&bpmp TEGRA186_RESET_GPU>; - reset-names = "gpu"; - power-domains = <&bpmp TEGRA186_POWER_DOMAIN_GPU>; - iommus = <&smmu TEGRA186_SID_GPU>; - }; - -Example for GV11B: - - gpu@17000000 { - compatible = "nvidia,gv11b"; - reg = <0x17000000 0x1000000>, - <0x18000000 0x1000000>; - interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "stall", "nonstall"; - clocks = <&bpmp TEGRA194_CLK_GPCCLK>, - <&bpmp TEGRA194_CLK_GPU_PWR>, - <&bpmp TEGRA194_CLK_FUSE>; - clock-names = "gpu", "pwr", "fuse"; - resets = <&bpmp TEGRA194_RESET_GPU>; - reset-names = "gpu"; - dma-coherent; - - power-domains = <&bpmp TEGRA194_POWER_DOMAIN_GPU>; - iommus = <&smmu TEGRA194_SID_GPU>; - }; diff --git a/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml new file mode 100644 index 000000000000..4d856a8b674c --- /dev/null +++ b/Documentation/devicetree/bindings/gpu/nvidia,gk20a.yaml @@ -0,0 +1,171 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/gpu/nvidia,gk20a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Graphics Processing Units + +maintainers: + - Alexandre Courbot <acourbot@nvidia.com> + - Jon Hunter <jonathanh@nvidia.com> + - Thierry Reding <treding@nvidia.com> + +properties: + compatible: + enum: + - nvidia,gk20a + - nvidia,gm20b + - nvidia,gp10b + - nvidia,gv11b + + reg: + items: + - description: Bar0 register window + - description: Bar1 register window + + interrupts: + items: + - description: Stall interrupt + - description: Nonstall interrupt + + interrupt-names: + items: + - const: stall + - const: nonstall + + vdd-supply: + description: + Regulator for GPU supply voltage + + clocks: + minItems: 2 + items: + - description: GPU clock + - description: Power clock + - description: Reference or fuse clock + + clock-names: + minItems: 2 + items: + - const: gpu + - const: pwr + - enum: [ ref, fuse ] + + resets: + maxItems: 1 + + reset-names: + items: + - const: gpu + + power-domains: + maxItems: 1 + + interconnects: + minItems: 4 + maxItems: 12 + + interconnect-names: + minItems: 4 + maxItems: 12 + + iommus: + maxItems: 1 + + dma-coherent: true + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + - resets + - reset-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - nvidia,gp10b + - nvidia,gv11b + then: + required: + - power-domains + else: + properties: + interconnects: false + interconnect-names: false + + required: + - vdd-supply + - if: + properties: + compatible: + contains: + enum: + - nvidia,gp10b + then: + properties: + interconnects: + maxItems: 4 + + interconnect-names: + items: + - const: dma-mem + - const: write-0 + - const: read-1 + - const: write-1 + - if: + properties: + compatible: + contains: + enum: + - nvidia,gv11b + then: + properties: + interconnects: + minItems: 12 + + interconnect-names: + items: + - const: dma-mem + - const: read-0-hp + - const: write-0 + - const: read-1 + - const: read-1-hp + - const: write-1 + - const: read-2 + - const: read-2-hp + - const: write-2 + - const: read-3 + - const: read-3-hp + - const: write-3 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/tegra124-car-common.h> + #include <dt-bindings/memory/tegra124-mc.h> + + gpu@57000000 { + compatible = "nvidia,gk20a"; + reg = <0x57000000 0x01000000>, + <0x58000000 0x01000000>; + interrupts = <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "stall", "nonstall"; + vdd-supply = <&vdd_gpu>; + clocks = <&tegra_car TEGRA124_CLK_GPU>, + <&tegra_car TEGRA124_CLK_PLL_P_OUT5>; + clock-names = "gpu", "pwr"; + resets = <&tegra_car 184>; + reset-names = "gpu"; + iommus = <&mc TEGRA_SWGROUP_GPU>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml index ddb72857c846..d6a7517f2a50 100644 --- a/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml +++ b/Documentation/devicetree/bindings/hwmon/adi,adm1275.yaml @@ -18,6 +18,13 @@ description: | Datasheets: https://www.analog.com/en/products/adm1294.html + The SQ24905C is also a Hot-swap controller compatibility to the ADM1278, + the PMBUS_MFR_MODEL is MC09C + + Datasheets: + https://www.silergy.com/ + download/downloadFile?id=5669&type=product&ftype=note + properties: compatible: enum: @@ -30,6 +37,7 @@ properties: - adi,adm1281 - adi,adm1293 - adi,adm1294 + - silergy,mc09c reg: maxItems: 1 @@ -96,6 +104,7 @@ allOf: - adi,adm1281 - adi,adm1293 - adi,adm1294 + - silergy,mc09c then: properties: adi,volt-curr-sample-average: diff --git a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml index 010333cb25c0..966b221b6caa 100644 --- a/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml +++ b/Documentation/devicetree/bindings/hwmon/kontron,sl28cpld-hwmon.yaml @@ -11,11 +11,12 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. properties: compatible: enum: + - kontron,sa67mcu-hwmon - kontron,sl28cpld-fan reg: diff --git a/Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml b/Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml new file mode 100644 index 000000000000..9419b481ff35 --- /dev/null +++ b/Documentation/devicetree/bindings/hwmon/lantiq,cputemp.yaml @@ -0,0 +1,30 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/hwmon/lantiq,cputemp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Lantiq cpu temperature sensor + +maintainers: + - Florian Eckert <fe@dev.tdt.de> + +properties: + compatible: + const: lantiq,cputemp + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + cputemp@103040 { + compatible = "lantiq,cputemp"; + reg = <0x103040 0x4>; + }; diff --git a/Documentation/devicetree/bindings/hwmon/lm75.yaml b/Documentation/devicetree/bindings/hwmon/lm75.yaml index c38255243f57..0b9fda81e3ec 100644 --- a/Documentation/devicetree/bindings/hwmon/lm75.yaml +++ b/Documentation/devicetree/bindings/hwmon/lm75.yaml @@ -28,6 +28,7 @@ properties: - maxim,max31725 - maxim,max31726 - maxim,mcp980x + - nxp,p3t1750 - nxp,p3t1755 - nxp,pct2075 - st,stds75 @@ -69,6 +70,7 @@ allOf: - ti,tmp100 - ti,tmp101 - ti,tmp112 + - ti,tmp75 then: properties: interrupts: false diff --git a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt b/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt deleted file mode 100644 index 473b34c876dd..000000000000 --- a/Documentation/devicetree/bindings/hwmon/ltq-cputemp.txt +++ /dev/null @@ -1,10 +0,0 @@ -Lantiq cpu temperature sensor - -Requires node properties: -- compatible value : - "lantiq,cputemp" - -Example: - cputemp@0 { - compatible = "lantiq,cputemp"; - }; diff --git a/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml b/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml index 3dc7f15484d2..ae23a05375cb 100644 --- a/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml +++ b/Documentation/devicetree/bindings/hwmon/pmbus/isil,isl68137.yaml @@ -54,6 +54,8 @@ properties: - renesas,raa228004 - renesas,raa228006 - renesas,raa228228 + - renesas,raa228244 + - renesas,raa228246 - renesas,raa229001 - renesas,raa229004 - renesas,raa229621 diff --git a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml index 8b4ed5ee962f..a84cc3a4cfdc 100644 --- a/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml +++ b/Documentation/devicetree/bindings/hwmon/pwm-fan.yaml @@ -31,6 +31,15 @@ properties: it must be self resetting edge interrupts. maxItems: 1 + fan-shutdown-percent: + description: + Fan RPM in percent set during shutdown. This is used to keep the fan + running at fixed RPM after the kernel shut down, which is useful on + hardware that does keep heating itself even after the kernel did shut + down, for example from some sort of management core. + minimum: 0 + maximum: 100 + fan-stop-to-start-percent: description: Minimum fan RPM in percent to start when stopped. diff --git a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml index fa68b99ef2e2..d3cde8936686 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml @@ -32,6 +32,8 @@ properties: - ti,ina237 - ti,ina238 - ti,ina260 + - ti,ina700 + - ti,ina780 reg: maxItems: 1 @@ -114,10 +116,42 @@ allOf: - ti,ina237 - ti,ina238 - ti,ina260 + - ti,ina700 + - ti,ina780 then: properties: ti,maximum-expected-current-microamp: false + - if: + properties: + compatible: + contains: + enum: + - silergy,sy24655 + - ti,ina209 + - ti,ina219 + - ti,ina220 + - ti,ina226 + - ti,ina230 + - ti,ina231 + - ti,ina260 + - ti,ina700 + - ti,ina780 + then: + properties: + ti,shunt-gain: false + + - if: + properties: + compatible: + contains: + enum: + - ti,ina700 + - ti,ina780 + then: + properties: + shunt-resistor: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml b/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml index 4c89448eba0d..96b2e4969f78 100644 --- a/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml +++ b/Documentation/devicetree/bindings/hwmon/ti,tmp102.yaml @@ -20,6 +20,10 @@ properties: reg: maxItems: 1 + label: + description: + A descriptive name for this channel, like "ambient" or "psu". + "#thermal-sensor-cells": const: 1 @@ -45,6 +49,7 @@ examples: reg = <0x48>; interrupt-parent = <&gpio7>; interrupts = <16 IRQ_TYPE_LEVEL_LOW>; + label = "somelabel"; vcc-supply = <&supply>; #thermal-sensor-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml index fed3e1b8c43f..500a965bdb7a 100644 --- a/Documentation/devicetree/bindings/i2c/apple,i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/apple,i2c.yaml @@ -20,17 +20,22 @@ allOf: properties: compatible: - items: - - enum: - - apple,s5l8960x-i2c - - apple,t7000-i2c - - apple,s8000-i2c - - apple,t8010-i2c - - apple,t8015-i2c - - apple,t8103-i2c - - apple,t8112-i2c - - apple,t6000-i2c - - const: apple,i2c + oneOf: + - items: + - const: apple,t6020-i2c + - const: apple,t8103-i2c + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-i2c + - apple,t7000-i2c + - apple,s8000-i2c + - apple,t8010-i2c + - apple,t8015-i2c + - apple,t8103-i2c + - apple,t8112-i2c + - apple,t6000-i2c + - const: apple,i2c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml index 7ae8c7b1d006..32269239bae4 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-exynos5.yaml @@ -35,9 +35,14 @@ properties: - const: samsung,exynos7-hsi2c - items: - enum: + - samsung,exynos8890-hsi2c + - const: samsung,exynos8895-hsi2c + - items: + - enum: - google,gs101-hsi2c - samsung,exynos2200-hsi2c - samsung,exynos850-hsi2c + - samsung,exynos990-hsi2c - const: samsung,exynosautov9-hsi2c - const: samsung,exynos5-hsi2c # Exynos5250 and Exynos5420 deprecated: true diff --git a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml index 23fe8ff76645..3562ce0c0f7e 100644 --- a/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml +++ b/Documentation/devicetree/bindings/i2c/i2c-mt65xx.yaml @@ -52,6 +52,12 @@ properties: - const: mediatek,mt8173-i2c - items: - enum: + - mediatek,mt6878-i2c + - mediatek,mt6991-i2c + - mediatek,mt8196-i2c + - const: mediatek,mt8188-i2c + - items: + - enum: - mediatek,mt6893-i2c - mediatek,mt8195-i2c - const: mediatek,mt8192-i2c diff --git a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml index 6b6f6762d122..51241c1293e3 100644 --- a/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/nvidia,tegra20-i2c.yaml @@ -80,6 +80,17 @@ properties: support for 64 KiB transactions whereas earlier chips supported no more than 4 KiB per transactions. const: nvidia,tegra194-i2c + - description: | + Tegra256 has 8 generic I2C controllers. The controllers are similar to + the previous generations, but have a different parent clock and hence + the timing parameters are configured differently. + const: nvidia,tegra256-i2c + - description: + Tegra264 has 17 generic I2C controllers, two of which are in the AON + (always-on) partition of the SoC. In addition to the features from + Tegra194, a SW mutex register is added to support use of the same I2C + instance across multiple firmwares. + const: nvidia,tegra264-i2c reg: maxItems: 1 @@ -186,6 +197,8 @@ allOf: contains: enum: - nvidia,tegra194-i2c + - nvidia,tegra256-i2c + - nvidia,tegra264-i2c then: required: - resets diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml index 73144473b9b2..9bc99d736343 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml @@ -25,6 +25,8 @@ properties: - items: - enum: + - qcom,qcm2290-cci + - qcom,sa8775p-cci - qcom,sc7280-cci - qcom,sc8280xp-cci - qcom,sdm670-cci @@ -44,11 +46,11 @@ properties: const: 0 clocks: - minItems: 3 + minItems: 2 maxItems: 6 clock-names: - minItems: 3 + minItems: 2 maxItems: 6 interrupts: @@ -113,6 +115,7 @@ allOf: then: properties: clocks: + minItems: 3 maxItems: 3 clock-names: items: @@ -123,6 +126,22 @@ allOf: - if: properties: compatible: + contains: + enum: + - qcom,qcm2290-cci + then: + properties: + clocks: + minItems: 2 + maxItems: 2 + clock-names: + items: + - const: ahb + - const: cci + + - if: + properties: + compatible: oneOf: - contains: enum: @@ -223,6 +242,7 @@ allOf: compatible: contains: enum: + - qcom,sa8775p-cci - qcom,sm8550-cci - qcom,sm8650-cci - qcom,x1e80100-cci @@ -292,7 +312,8 @@ examples: clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; clock-names = "xvclk"; - clock-frequency = <19200000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK0_CLK>; + assigned-clock-rates = <19200000>; dovdd-supply = <&vreg_lvs1a_1p8>; avdd-supply = <&cam0_avdd_2v8>; @@ -324,7 +345,8 @@ examples: clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; clock-names = "xclk"; - clock-frequency = <24000000>; + assigned-clocks = <&clock_camcc CAM_CC_MCLK3_CLK>; + assigned-clock-rates = <24000000>; vdddo-supply = <&vreg_lvs1a_1p8>; vdda-supply = <&cam3_avdd_2v8>; diff --git a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml index 9f66a3bb1f80..51534953a69c 100644 --- a/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/i2c/qcom,i2c-geni-qcom.yaml @@ -75,6 +75,7 @@ required: allOf: - $ref: /schemas/i2c/i2c-controller.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml index 6ba7d793504c..a2ddc6803617 100644 --- a/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/samsung,s3c2410-i2c.yaml @@ -13,7 +13,6 @@ properties: compatible: oneOf: - enum: - - samsung,s3c2410-i2c - samsung,s3c2440-i2c # For s3c2440-like I2C used inside HDMIPHY block found on several SoCs: - samsung,s3c2440-hdmiphy-i2c @@ -93,7 +92,6 @@ allOf: compatible: contains: enum: - - samsung,s3c2410-i2c - samsung,s3c2440-i2c - samsung,s3c2440-hdmiphy-i2c then: diff --git a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml index 3d6aefb0d0f1..b7220fff2235 100644 --- a/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml +++ b/Documentation/devicetree/bindings/i2c/spacemit,k1-i2c.yaml @@ -9,6 +9,9 @@ title: I2C controller embedded in SpacemiT's K1 SoC maintainers: - Troy Mitchell <troymitchell988@gmail.com> +allOf: + - $ref: /schemas/i2c/i2c-controller.yaml# + properties: compatible: const: spacemit,k1-i2c @@ -53,7 +56,7 @@ examples: reg = <0xd4010800 0x38>; interrupt-parent = <&plic>; interrupts = <36>; - clocks =<&ccu 32>, <&ccu 84>; + clocks = <&ccu 32>, <&ccu 84>; clock-names = "func", "bus"; clock-frequency = <100000>; }; diff --git a/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml b/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml new file mode 100644 index 000000000000..2498672d2654 --- /dev/null +++ b/Documentation/devicetree/bindings/i3c/adi,i3c-master.yaml @@ -0,0 +1,72 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/i3c/adi,i3c-master.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices I3C Controller + +description: + FPGA-based I3C controller designed to interface with I3C and I2C peripherals, + implementing a subset of the I3C-basic specification. The IP core is tested + on arm, microblaze, and arm64 architectures. + + https://analogdevicesinc.github.io/hdl/library/i3c_controller + +maintainers: + - Jorge Marques <jorge.marques@analog.com> + +properties: + compatible: + const: adi,i3c-master-v1 + + reg: + maxItems: 1 + + clocks: + minItems: 1 + items: + - description: The AXI interconnect clock, drives the register map. + - description: + The secondary clock, drives the internal logic asynchronously to the + register map. The presence of this entry states that the IP Core was + synthesized with a second clock input, and the absence of this entry + indicates a topology where a single clock input drives all the + internal logic. + + clock-names: + minItems: 1 + items: + - const: axi + - const: i3c + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - interrupts + +allOf: + - $ref: i3c.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i3c@44a00000 { + compatible = "adi,i3c-master-v1"; + reg = <0x44a00000 0x1000>; + interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clkc 15>, <&clkc 15>; + clock-names = "axi", "i3c"; + #address-cells = <3>; + #size-cells = <0>; + + /* I3C and I2C devices */ + }; diff --git a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml index fe2e9633c46f..a20d875086d4 100644 --- a/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml +++ b/Documentation/devicetree/bindings/i3c/renesas,i3c.yaml @@ -4,7 +4,7 @@ $id: http://devicetree.org/schemas/i3c/renesas,i3c.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/G3S and RZ/G3E I3C Bus Interface +title: Renesas I3C Bus Interface maintainers: - Wolfram Sang <wsa+renesas@sang-engineering.com> @@ -12,10 +12,16 @@ maintainers: properties: compatible: - items: - - enum: - - renesas,r9a08g045-i3c # RZ/G3S - - renesas,r9a09g047-i3c # RZ/G3E + oneOf: + - items: + - enum: + - renesas,r9a08g045-i3c # RZ/G3S + - renesas,r9a09g047-i3c # RZ/G3E + - items: + - enum: + - renesas,r9a09g056-i3c # RZ/V2N + - renesas,r9a09g057-i3c # RZ/V2H(P) + - const: renesas,r9a09g047-i3c reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml index 2bde6cc6fe0a..ee5a0dfff437 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/apple,aic2.yaml @@ -34,6 +34,7 @@ properties: - enum: - apple,t8112-aic - apple,t6000-aic + - apple,t6020-aic - const: apple,aic2 interrupt-controller: true diff --git a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml index 7173c4b5a228..ee4c77dac201 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/arm,gic.yaml @@ -59,6 +59,7 @@ properties: - nvidia,tegra186-agic - nvidia,tegra194-agic - nvidia,tegra234-agic + - nvidia,tegra264-agic - const: nvidia,tegra210-agic interrupt-controller: true diff --git a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml index d5287a2bf866..d998a9d69b91 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/aspeed,ast2500-scu-ic.yaml @@ -5,7 +5,7 @@ $id: http://devicetree.org/schemas/interrupt-controller/aspeed,ast2500-scu-ic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Aspeed AST25XX and AST26XX SCU Interrupt Controller +title: Aspeed AST25XX, AST26XX, AST27XX SCU Interrupt Controller maintainers: - Eddie James <eajames@linux.ibm.com> @@ -16,6 +16,10 @@ properties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml index f0d9bbd7d510..642738512f3c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/chrp,open-pic.yaml @@ -36,12 +36,27 @@ properties: const: 0 '#interrupt-cells': - const: 2 + description: + A value of 4 means that interrupt specifiers contain the interrupt-type or + type-specific information cells. + enum: [ 2, 4 ] pic-no-reset: description: Indicates the PIC shall not be reset during runtime initialization. type: boolean + single-cpu-affinity: + description: + If present, non-IPI interrupts will be routed to a single CPU at a time. + type: boolean + + last-interrupt-source: + description: + Some MPICs do not correctly report the number of hardware sources in the + global feature registers. This value, if specified, overrides the value + read from MPIC_GREG_FEATURE_LAST_SRC. + $ref: /schemas/types.yaml#/definitions/uint32 + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt deleted file mode 100644 index a6813a071f15..000000000000 --- a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.txt +++ /dev/null @@ -1,84 +0,0 @@ -Hisilicon mbigen device tree bindings. -======================================= - -Mbigen means: message based interrupt generator. - -MBI is kind of msi interrupt only used on Non-PCI devices. - -To reduce the wired interrupt number connected to GIC, -Hisilicon designed mbigen to collect and generate interrupt. - - -Non-pci devices can connect to mbigen and generate the -interrupt by writing ITS register. - -The mbigen chip and devices connect to mbigen have the following properties: - -Mbigen main node required properties: -------------------------------------------- -- compatible: Should be "hisilicon,mbigen-v2" - -- reg: Specifies the base physical address and size of the Mbigen - registers. - -Mbigen sub node required properties: ------------------------------------------- -- interrupt controller: Identifies the node as an interrupt controller - -- msi-parent: Specifies the MSI controller this mbigen use. - For more detail information,please refer to the generic msi-parent binding in - Documentation/devicetree/bindings/interrupt-controller/msi.txt. - -- num-pins: the total number of pins implemented in this Mbigen - instance. - -- #interrupt-cells : Specifies the number of cells needed to encode an - interrupt source. The value must be 2. - - The 1st cell is hardware pin number of the interrupt.This number is local to - each mbigen chip and in the range from 0 to the maximum interrupts number - of the mbigen. - - The 2nd cell is the interrupt trigger type. - The value of this cell should be: - 1: rising edge triggered - or - 4: high level triggered - -Examples: - - mbigen_chip_dsa { - compatible = "hisilicon,mbigen-v2"; - reg = <0x0 0xc0080000 0x0 0x10000>; - - mbigen_gmac:intc_gmac { - interrupt-controller; - msi-parent = <&its_dsa 0x40b1c>; - num-pins = <9>; - #interrupt-cells = <2>; - }; - - mbigen_i2c:intc_i2c { - interrupt-controller; - msi-parent = <&its_dsa 0x40b0e>; - num-pins = <2>; - #interrupt-cells = <2>; - }; - }; - -Devices connect to mbigen required properties: ----------------------------------------------------- --interrupts:Specifies the interrupt source. - For the specific information of each cell in this property,please refer to - the "interrupt-cells" description mentioned above. - -Examples: - gmac0: ethernet@c2080000 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0 0xc2080000 0 0x20000>, - <0 0xc0000000 0 0x1000>; - interrupt-parent = <&mbigen_device_gmac>; - interrupts = <656 1>, - <657 1>; - }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml new file mode 100644 index 000000000000..326424e6e02a --- /dev/null +++ b/Documentation/devicetree/bindings/interrupt-controller/hisilicon,mbigen-v2.yaml @@ -0,0 +1,76 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interrupt-controller/hisilicon,mbigen-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Hisilicon mbigen v2 + +maintainers: + - Wei Xu <xuwei5@hisilicon.com> + +description: > + Mbigen means: message based interrupt generator. + + MBI is kind of msi interrupt only used on Non-PCI devices. + + To reduce the wired interrupt number connected to GIC, Hisilicon designed + mbigen to collect and generate interrupt. + + Non-pci devices can connect to mbigen and generate the interrupt by writing + ITS register. + +properties: + compatible: + const: hisilicon,mbigen-v2 + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: + type: object + additionalProperties: false + + properties: + interrupt-controller: true + + '#interrupt-cells': + const: 2 + + msi-parent: + maxItems: 1 + + num-pins: + description: The total number of pins implemented in this Mbigen instance. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - interrupt-controller + - "#interrupt-cells" + - msi-parent + - num-pins + +examples: + - | + mbigen@c0080000 { + compatible = "hisilicon,mbigen-v2"; + reg = <0xc0080000 0x10000>; + + mbigen_gmac: intc_gmac { + interrupt-controller; + #interrupt-cells = <2>; + msi-parent = <&its_dsa 0x40b1c>; + num-pins = <9>; + }; + + mbigen_i2c: intc_i2c { + interrupt-controller; + #interrupt-cells = <2>; + msi-parent = <&its_dsa 0x40b0e>; + num-pins = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml index e8dfa6507f64..87df07beda59 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/kontron,sl28cpld-intc.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. The following interrupts are available. All types and levels are fixed and handled by the board management controller. diff --git a/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml index 9d4f06f45372..ddfce217e119 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/marvell,cp110-icu.yaml @@ -49,6 +49,9 @@ patternProperties: reg: maxItems: 1 + '#address-cells': + const: 0 + '#interrupt-cells': const: 2 diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml index f06b40f88778..38d0c2d57dd6 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.yaml @@ -26,6 +26,7 @@ properties: compatible: items: - enum: + - qcom,glymur-pdc - qcom,qcs615-pdc - qcom,qcs8300-pdc - qcom,qdu1000-pdc diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml index 5b827bc24301..f683d696909b 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.0.0.yaml @@ -59,6 +59,7 @@ properties: - items: - enum: - canaan,k210-plic + - eswin,eic7700-plic - sifive,fu540-c000-plic - spacemit,k1-plic - starfive,jh7100-plic diff --git a/Documentation/devicetree/bindings/iommu/apple,dart.yaml b/Documentation/devicetree/bindings/iommu/apple,dart.yaml index 7adb1de455a5..47ec7fa52c3a 100644 --- a/Documentation/devicetree/bindings/iommu/apple,dart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,dart.yaml @@ -22,11 +22,15 @@ description: |+ properties: compatible: - enum: - - apple,t8103-dart - - apple,t8103-usb4-dart - - apple,t8110-dart - - apple,t6000-dart + oneOf: + - enum: + - apple,t8103-dart + - apple,t8103-usb4-dart + - apple,t8110-dart + - apple,t6000-dart + - items: + - const: apple,t6020-dart + - const: apple,t8110-dart reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/iommu/apple,sart.yaml b/Documentation/devicetree/bindings/iommu/apple,sart.yaml index e87c1520fea6..88e66d4b13c6 100644 --- a/Documentation/devicetree/bindings/iommu/apple,sart.yaml +++ b/Documentation/devicetree/bindings/iommu/apple,sart.yaml @@ -30,10 +30,13 @@ properties: compatible: oneOf: - items: - - const: apple,t8112-sart + - enum: + - apple,t6020-sart + - apple,t8112-sart - const: apple,t6000-sart - enum: - apple,t6000-sart + - apple,t8015-sart - apple,t8103-sart reg: diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml index 75750c64157c..f49ed8ac4776 100644 --- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml +++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml @@ -52,7 +52,7 @@ description: |+ As above, The Multimedia HW will go through SMI and M4U while it access EMI. SMI is a bridge between m4u and the Multimedia HW. It contain smi local arbiter and smi common. It will control whether the Multimedia - HW should go though the m4u for translation or bypass it and talk + HW should go through the m4u for translation or bypass it and talk directly with EMI. And also SMI help control the power domain and clocks for each local arbiter. diff --git a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml index 129e32c4c774..610c79863208 100644 --- a/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml +++ b/Documentation/devicetree/bindings/ipmi/aspeed,ast2400-kcs-bmc.yaml @@ -40,6 +40,9 @@ properties: - description: ODR register - description: STR register + clocks: + maxItems: 1 + aspeed,lpc-io-reg: $ref: /schemas/types.yaml#/definitions/uint32-array minItems: 1 diff --git a/Documentation/devicetree/bindings/leds/ams,as3645a.txt b/Documentation/devicetree/bindings/leds/ams,as3645a.txt deleted file mode 100644 index 4af2987b25e9..000000000000 --- a/Documentation/devicetree/bindings/leds/ams,as3645a.txt +++ /dev/null @@ -1,85 +0,0 @@ -Analog devices AS3645A device tree bindings - -The AS3645A flash LED controller can drive two LEDs, one high current -flash LED and one indicator LED. The high current flash LED can be -used in torch mode as well. - -Ranges below noted as [a, b] are closed ranges between a and b, i.e. a -and b are included in the range. - -Please also see common.txt in the same directory. - - -Required properties -=================== - -compatible : Must be "ams,as3645a". -reg : The I2C address of the device. Typically 0x30. -#address-cells : 1 -#size-cells : 0 - - -Required properties of the flash child node (0) -=============================================== - -reg: 0 -flash-timeout-us: Flash timeout in microseconds. The value must be in - the range [100000, 850000] and divisible by 50000. -flash-max-microamp: Maximum flash current in microamperes. Has to be - in the range between [200000, 500000] and - divisible by 20000. -led-max-microamp: Maximum torch (assist) current in microamperes. The - value must be in the range between [20000, 160000] and - divisible by 20000. -ams,input-max-microamp: Maximum flash controller input current. The - value must be in the range [1250000, 2000000] - and divisible by 50000. - - -Optional properties of the flash child node -=========================================== - -function : See Documentation/devicetree/bindings/leds/common.txt. -color : See Documentation/devicetree/bindings/leds/common.txt. -label : See Documentation/devicetree/bindings/leds/common.txt (deprecated). - - -Required properties of the indicator child node (1) -=================================================== - -reg: 1 -led-max-microamp: Maximum indicator current. The allowed values are - 2500, 5000, 7500 and 10000. - -Optional properties of the indicator child node -=============================================== - -function : See Documentation/devicetree/bindings/leds/common.txt. -color : See Documentation/devicetree/bindings/leds/common.txt. -label : See Documentation/devicetree/bindings/leds/common.txt (deprecated). - - -Example -======= - -#include <dt-bindings/leds/common.h> - - as3645a@30 { - #address-cells = <1>; - #size-cells = <0>; - reg = <0x30>; - compatible = "ams,as3645a"; - led@0 { - reg = <0x0>; - flash-timeout-us = <150000>; - flash-max-microamp = <320000>; - led-max-microamp = <60000>; - ams,input-max-microamp = <1750000>; - function = LED_FUNCTION_FLASH; - }; - led@1 { - reg = <0x1>; - led-max-microamp = <10000>; - function = LED_FUNCTION_INDICATOR; - }; - }; diff --git a/Documentation/devicetree/bindings/leds/ams,as3645a.yaml b/Documentation/devicetree/bindings/leds/ams,as3645a.yaml new file mode 100644 index 000000000000..250a4b275d8a --- /dev/null +++ b/Documentation/devicetree/bindings/leds/ams,as3645a.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/ams,as3645a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Analog Devices AS3645A LED Controller + +maintainers: + - Sakari Ailus <sakari.ailus@iki.fi> + +description: + The AS3645A flash LED controller can drive two LEDs, one + high current flash LED and one indicator LED. The high + current flash LED can be used in torch mode as well. + +properties: + compatible: + const: ams,as3645a + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + maxItems: 1 + + led@0: + description: led0 describes the 'flash' feature + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + const: 0 + + flash-timeout-us: + minimum: 100000 + maximum: 850000 + multipleOf: 50000 + + flash-max-microamp: + minimum: 200000 + maximum: 500000 + multipleOf: 20000 + + led-max-microamp: + minimum: 20000 + maximum: 160000 + multipleOf: 20000 + description: + Maximum current when in torch (assist) mode. + + ams,input-max-microamp: + minimum: 1250000 + maximum: 2000000 + multipleOf: 50000 + + required: + - reg + - flash-timeout-us + - flash-max-microamp + - led-max-microamp + - ams,input-max-microamp + + led@1: + description: led1 describes the 'indicator' feature + type: object + $ref: common.yaml# + unevaluatedProperties: false + + properties: + reg: + const: 1 + + led-max-microamp: + enum: + - 2500 + - 5000 + - 7500 + - 10000 + description: + Maximum indicator current. + + required: + - reg + - led-max-microamp + +required: + - compatible + - reg + - "#size-cells" + - "#address-cells" + +additionalProperties: false + +examples: + - | + #include <dt-bindings/leds/common.h> + + i2c{ + #address-cells = <1>; + #size-cells = <0>; + + led-controller@30 { + compatible = "ams,as3645a"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x30>; + + led@0 { + reg = <0>; + flash-timeout-us = <150000>; + flash-max-microamp = <320000>; + led-max-microamp = <60000>; + ams,input-max-microamp = <1750000>; + function = LED_FUNCTION_FLASH; + }; + + led@1 { + reg = <1>; + led-max-microamp = <10000>; + function = LED_FUNCTION_INDICATOR; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml b/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml index f5554da6bc6c..8fc5af8f27f9 100644 --- a/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml +++ b/Documentation/devicetree/bindings/leds/backlight/led-backlight.yaml @@ -23,11 +23,7 @@ properties: compatible: const: led-backlight - leds: - description: A list of LED nodes - $ref: /schemas/types.yaml#/definitions/phandle-array - items: - maxItems: 1 + leds: true required: - compatible diff --git a/Documentation/devicetree/bindings/leds/common.yaml b/Documentation/devicetree/bindings/leds/common.yaml index 3e8319e44339..274f83288a92 100644 --- a/Documentation/devicetree/bindings/leds/common.yaml +++ b/Documentation/devicetree/bindings/leds/common.yaml @@ -62,7 +62,7 @@ properties: default-state: description: The initial state of the LED. If the LED is already on or off and the - default-state property is set the to same value, then no glitch should be + default-state property is set to the same value, then no glitch should be produced where the LED momentarily turns off (or on). The "keep" setting will keep the LED at whatever its current state is, without producing a glitch. diff --git a/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml b/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml index 3c0431c51159..906735acfbaf 100644 --- a/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml +++ b/Documentation/devicetree/bindings/leds/issi,is31fl319x.yaml @@ -42,7 +42,6 @@ properties: description: GPIO attached to the SDB pin. audio-gain-db: - $ref: /schemas/types.yaml#/definitions/uint32 default: 0 description: Audio gain selection for external analog modulation input. enum: [0, 3, 6, 9, 12, 15, 18, 21] diff --git a/Documentation/devicetree/bindings/leds/leds-consumer.yaml b/Documentation/devicetree/bindings/leds/leds-consumer.yaml new file mode 100644 index 000000000000..fe6a0faa1d3b --- /dev/null +++ b/Documentation/devicetree/bindings/leds/leds-consumer.yaml @@ -0,0 +1,67 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/leds/leds-consumer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Common leds consumer + +maintainers: + - Aleksandrs Vinarskis <alex@vinarskis.com> + +description: + Some LED defined in DT are required by other DT consumers, for example + v4l2 subnode may require privacy or flash LED. Unlike trigger-source + approach which is typically used as 'soft' binding, referencing LED + devices by phandle makes things simpler when 'hard' binding is desired. + + Document LED properties that its consumers may define. + +select: true + +properties: + leds: + oneOf: + - type: object + - $ref: /schemas/types.yaml#/definitions/phandle-array + description: + A list of LED device(s) required by a particular consumer. + items: + maxItems: 1 + + led-names: + description: + A list of device name(s). Used to map LED devices to their respective + functions, when consumer requires more than one LED. + +additionalProperties: true + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/leds/common.h> + + leds { + compatible = "gpio-leds"; + + privacy_led: privacy-led { + color = <LED_COLOR_ID_RED>; + default-state = "off"; + function = LED_FUNCTION_INDICATOR; + gpios = <&tlmm 110 GPIO_ACTIVE_HIGH>; + }; + }; + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + v4l2_node: camera@36 { + reg = <0x36>; + + leds = <&privacy_led>; + led-names = "privacy"; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml b/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml index 8ed059a5a724..5c9cfa39396b 100644 --- a/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml +++ b/Documentation/devicetree/bindings/leds/leds-group-multicolor.yaml @@ -17,10 +17,7 @@ properties: compatible: const: leds-group-multicolor - leds: - description: - An aray of monochromatic leds - $ref: /schemas/types.yaml#/definitions/phandle-array + leds: true required: - leds diff --git a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml index 474c1a0f99f3..28985cc62c25 100644 --- a/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/apple,mailbox.yaml @@ -31,9 +31,17 @@ properties: - apple,t8103-asc-mailbox - apple,t8112-asc-mailbox - apple,t6000-asc-mailbox + - apple,t6020-asc-mailbox - const: apple,asc-mailbox-v4 - description: + An older ASC mailbox interface found on T2 and A11 that is also + used for the NVMe coprocessor and the system management + controller. + items: + - const: apple,t8015-asc-mailbox + + - description: M3 mailboxes are an older variant with a slightly different MMIO interface still found on the M1. It is used for the Thunderbolt co-processors. diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt deleted file mode 100644 index bf0c998b8603..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.txt +++ /dev/null @@ -1,59 +0,0 @@ -Broadcom FlexRM Ring Manager -============================ -The Broadcom FlexRM ring manager provides a set of rings which can be -used to submit work to offload engines. An SoC may have multiple FlexRM -hardware blocks. There is one device tree entry per FlexRM block. The -FlexRM driver will create a mailbox-controller instance for given FlexRM -hardware block where each mailbox channel is a separate FlexRM ring. - -Required properties: --------------------- -- compatible: Should be "brcm,iproc-flexrm-mbox" -- reg: Specifies base physical address and size of the FlexRM - ring registers -- msi-parent: Phandles (and potential Device IDs) to MSI controllers - The FlexRM engine will send MSIs (instead of wired - interrupts) to CPU. There is one MSI for each FlexRM ring. - Refer devicetree/bindings/interrupt-controller/msi.txt -- #mbox-cells: Specifies the number of cells needed to encode a mailbox - channel. This should be 3. - - The 1st cell is the mailbox channel number. - - The 2nd cell contains MSI completion threshold. This is the - number of completion messages for which FlexRM will inject - one MSI interrupt to CPU. - - The 3rd cell contains MSI timer value representing time for - which FlexRM will wait to accumulate N completion messages - where N is the value specified by 2nd cell above. If FlexRM - does not get required number of completion messages in time - specified by this cell then it will inject one MSI interrupt - to CPU provided at least one completion message is available. - -Optional properties: --------------------- -- dma-coherent: Present if DMA operations made by the FlexRM engine (such - as DMA descriptor access, access to buffers pointed by DMA - descriptors and read/write pointer updates to DDR) are - cache coherent with the CPU. - -Example: --------- -crypto_mbox: mbox@67000000 { - compatible = "brcm,iproc-flexrm-mbox"; - reg = <0x67000000 0x200000>; - msi-parent = <&gic_its 0x7f00>; - #mbox-cells = <3>; -}; - -crypto@672c0000 { - compatible = "brcm,spu2-v2-crypto"; - reg = <0x672c0000 0x1000>; - mboxes = <&crypto_mbox 0 0x1 0xffff>, - <&crypto_mbox 1 0x1 0xffff>, - <&crypto_mbox 16 0x1 0xffff>, - <&crypto_mbox 17 0x1 0xffff>, - <&crypto_mbox 30 0x1 0xffff>, - <&crypto_mbox 31 0x1 0xffff>; -}; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml new file mode 100644 index 000000000000..c801bd2e95f3 --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-flexrm-mbox.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/brcm,iproc-flexrm-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom FlexRM Ring Manager + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +description: + The Broadcom FlexRM ring manager provides a set of rings which can be used to + submit work to offload engines. An SoC may have multiple FlexRM hardware + blocks. There is one device tree entry per FlexRM block. The FlexRM driver + will create a mailbox-controller instance for given FlexRM hardware block + where each mailbox channel is a separate FlexRM ring. + +properties: + compatible: + const: brcm,iproc-flexrm-mbox + + reg: + maxItems: 1 + + msi-parent: + maxItems: 1 + + '#mbox-cells': + description: > + The 1st cell is the mailbox channel number. + + The 2nd cell contains MSI completion threshold. This is the number of + completion messages for which FlexRM will inject one MSI interrupt to CPU. + + The 3rd cell contains MSI timer value representing time for which FlexRM + will wait to accumulate N completion messages where N is the value + specified by 2nd cell above. If FlexRM does not get required number of + completion messages in time specified by this cell then it will inject one + MSI interrupt to CPU provided at least one completion message is + available. + const: 3 + + dma-coherent: true + +required: + - compatible + - reg + - msi-parent + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + mailbox@67000000 { + compatible = "brcm,iproc-flexrm-mbox"; + reg = <0x67000000 0x200000>; + msi-parent = <&gic_its 0x7f00>; + #mbox-cells = <3>; + dma-coherent; + }; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt deleted file mode 100644 index 9bcdf2087625..000000000000 --- a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.txt +++ /dev/null @@ -1,25 +0,0 @@ -The PDC driver manages data transfer to and from various offload engines -on some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is -one device tree entry per block. On some chips, the PDC functionality is -handled by the FA2 (Northstar Plus). - -Required properties: -- compatible : Should be "brcm,iproc-pdc-mbox" or "brcm,iproc-fa2-mbox" for - FA2/Northstar Plus. -- reg: Should contain PDC registers location and length. -- interrupts: Should contain the IRQ line for the PDC. -- #mbox-cells: 1 -- brcm,rx-status-len: Length of metadata preceding received frames, in bytes. - -Optional properties: -- brcm,use-bcm-hdr: present if a BCM header precedes each frame. - -Example: - pdc0: iproc-pdc0@612c0000 { - compatible = "brcm,iproc-pdc-mbox"; - reg = <0 0x612c0000 0 0x445>; /* PDC FS0 regs */ - interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; /* one cell per mailbox channel */ - brcm,rx-status-len = <32>; - brcm,use-bcm-hdr; - }; diff --git a/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml new file mode 100644 index 000000000000..5534ae07c9fa --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/brcm,iproc-pdc-mbox.yaml @@ -0,0 +1,66 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/brcm,iproc-pdc-mbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc PDC mailbox + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +description: + The PDC driver manages data transfer to and from various offload engines on + some Broadcom SoCs. An SoC may have multiple PDC hardware blocks. There is one + device tree entry per block. On some chips, the PDC functionality is handled + by the FA2 (Northstar Plus). + +properties: + compatible: + enum: + - brcm,iproc-pdc-mbox + - brcm,iproc-fa2-mbox + + reg: + maxItems: 1 + + dma-coherent: true + + interrupts: + maxItems: 1 + + '#mbox-cells': + const: 1 + + brcm,rx-status-len: + description: + Length of metadata preceding received frames, in bytes. + $ref: /schemas/types.yaml#/definitions/uint32 + + brcm,use-bcm-hdr: + type: boolean + description: + Present if a BCM header precedes each frame. + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + - brcm,rx-status-len + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox0@612c0000 { + compatible = "brcm,iproc-pdc-mbox"; + reg = <0x612c0000 0x445>; + interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + brcm,rx-status-len = <32>; + brcm,use-bcm-hdr; + }; diff --git a/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt b/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt deleted file mode 100644 index 282ab81a4ea6..000000000000 --- a/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.txt +++ /dev/null @@ -1,16 +0,0 @@ -* rWTM BIU Mailbox driver for Armada 37xx - -Required properties: -- compatible: must be "marvell,armada-3700-rwtm-mailbox" -- reg: physical base address of the mailbox and length of memory mapped - region -- interrupts: the IRQ line for the mailbox -- #mbox-cells: must be 1 - -Example: - rwtm: mailbox@b0000 { - compatible = "marvell,armada-3700-rwtm-mailbox"; - reg = <0xb0000 0x100>; - interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; - }; diff --git a/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml new file mode 100644 index 000000000000..0a07ed1b1beb --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/marvell,armada-3700-rwtm-mailbox.yaml @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/marvell,armada-3700-rwtm-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 3700 rWTM Mailbox + +maintainers: + - Marek Behún <kabel@kernel.org> + +properties: + compatible: + const: marvell,armada-3700-rwtm-mailbox + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@b0000 { + compatible = "marvell,armada-3700-rwtm-mailbox"; + reg = <0xb0000 0x100>; + interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml index 73d6db34d64a..587126d03fc6 100644 --- a/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml +++ b/Documentation/devicetree/bindings/mailbox/mediatek,gce-mailbox.yaml @@ -60,17 +60,6 @@ required: - interrupts - clocks -allOf: - - if: - not: - properties: - compatible: - contains: - const: mediatek,mt8195-gce - then: - required: - - clock-names - additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml b/Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml new file mode 100644 index 000000000000..107bc96a8f3d --- /dev/null +++ b/Documentation/devicetree/bindings/mailbox/rockchip,rk3368-mailbox.yaml @@ -0,0 +1,56 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mailbox/rockchip,rk3368-mailbox.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Rockchip RK3368 Mailbox Controller + +maintainers: + - Heiko Stuebner <heiko@sntech.de> + +description: + The Rockchip mailbox is used by the Rockchip CPU cores to communicate + requests to MCU processor. + +properties: + compatible: + const: rockchip,rk3368-mailbox + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + const: pclk_mailbox + + interrupts: + description: One interrupt for each channel + maxItems: 4 + + '#mbox-cells': + const: 1 + +required: + - compatible + - reg + - interrupts + - '#mbox-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + mailbox@ff6b0000 { + compatible = "rockchip,rk3368-mailbox"; + reg = <0xff6b0000 0x1000>; + interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; + #mbox-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt b/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt deleted file mode 100644 index b6bb84acf5be..000000000000 --- a/Documentation/devicetree/bindings/mailbox/rockchip-mailbox.txt +++ /dev/null @@ -1,32 +0,0 @@ -Rockchip mailbox - -The Rockchip mailbox is used by the Rockchip CPU cores to communicate -requests to MCU processor. - -Refer to ./mailbox.txt for generic information about mailbox device-tree -bindings. - -Required properties: - - - compatible: should be one of the following. - - "rockchip,rk3368-mbox" for rk3368 - - reg: physical base address of the controller and length of memory mapped - region. - - interrupts: The interrupt number to the cpu. The interrupt specifier format - depends on the interrupt controller. - - #mbox-cells: Common mailbox binding property to identify the number - of cells required for the mailbox specifier. Should be 1 - -Example: --------- - -/* RK3368 */ -mbox: mbox@ff6b0000 { - compatible = "rockchip,rk3368-mailbox"; - reg = <0x0 0xff6b0000 0x0 0x1000>, - interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>; - #mbox-cells = <1>; -}; diff --git a/Documentation/devicetree/bindings/media/cec/cec-common.yaml b/Documentation/devicetree/bindings/media/cec/cec-common.yaml index af6ee5f1c73f..6d5017d9bf55 100644 --- a/Documentation/devicetree/bindings/media/cec/cec-common.yaml +++ b/Documentation/devicetree/bindings/media/cec/cec-common.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: HDMI CEC Adapters Common Properties maintainers: - - Hans Verkuil <hverkuil@xs4all.nl> + - Hans Verkuil <hverkuil@kernel.org> properties: $nodename: diff --git a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml index 64d7ec057672..582c6c9cae48 100644 --- a/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml +++ b/Documentation/devicetree/bindings/media/cec/cec-gpio.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: HDMI CEC GPIO maintainers: - - Hans Verkuil <hverkuil-cisco@xs4all.nl> + - Hans Verkuil <hverkuil@kernel.org> description: | The HDMI CEC GPIO module supports CEC implementations where the CEC line is diff --git a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml index 4b46aa755ccd..6ef545b1d622 100644 --- a/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml +++ b/Documentation/devicetree/bindings/media/cec/nvidia,tegra114-cec.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: NVIDIA Tegra HDMI CEC maintainers: - - Hans Verkuil <hverkuil-cisco@xs4all.nl> + - Hans Verkuil <hverkuil@kernel.org> allOf: - $ref: cec-common.yaml# diff --git a/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml index 6c403003cdda..2dc2829d42a0 100644 --- a/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml +++ b/Documentation/devicetree/bindings/media/i2c/adi,adv7604.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Analog Devices ADV7604/10/11/12 video decoder with HDMI receiver maintainers: - - Hans Verkuil <hverkuil-cisco@xs4all.nl> + - Hans Verkuil <hverkuil@kernel.org> description: The ADV7604 and ADV7610/11/12 are multiformat video decoders with diff --git a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml index bc664a016396..217b08c8cbbd 100644 --- a/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml +++ b/Documentation/devicetree/bindings/media/i2c/mipi-ccs.yaml @@ -55,6 +55,7 @@ properties: clock-frequency: description: Frequency of the external clock to the sensor in Hz. + deprecated: true reset-gpios: description: Reset GPIO. Also commonly called XSHUTDOWN in hardware @@ -93,7 +94,6 @@ properties: required: - compatible - reg - - clock-frequency - clocks additionalProperties: false @@ -114,8 +114,11 @@ examples: reg = <0x10>; reset-gpios = <&gpio3 20 GPIO_ACTIVE_LOW>; vana-supply = <&vaux3>; + clocks = <&omap3_isp 0>; - clock-frequency = <9600000>; + assigned-clocks = <&omap3_isp 0>; + assigned-clock-rates = <9600000>; + port { ccs_ep: endpoint { data-lanes = <1 2>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml new file mode 100644 index 000000000000..bd2f1ae23e65 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,og0ve1b.yaml @@ -0,0 +1,97 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,og0ve1b.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OG0VE1B Image Sensor + +description: + OmniVision OG0VE1B image sensor is a low power consuming monochrome + image sensor. The sensor is controlled over a serial camera control + bus protocol (SCCB), the widest supported image size is 640x480 at + 120 frames per second rate, data output format is 8/10-bit RAW + transferred over one-lane MIPI D-PHY at up to 800 Mbps. + +maintainers: + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,og0ve1b + + reg: + maxItems: 1 + + clocks: + description: XVCLK supply clock, 6MHz to 27MHz frequency. + maxItems: 1 + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + maxItems: 1 + + strobe-gpios: + description: Input GPIO connected to strobe pad of the sensor. + maxItems: 1 + + avdd-supply: + description: Analog voltage supply, 2.6 to 3.0 volts. + + dovdd-supply: + description: Digital I/O voltage supply, 1.7 to 3.0 volts. + + dvdd-supply: + description: Digital core voltage supply. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - link-frequencies + +required: + - compatible + - reg + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@3e { + compatible = "ovti,og0ve1b"; + reg = <0x3e>; + clocks = <&camera_clk 0>; + assigned-clocks = <&camera_clk 0>; + assigned-clock-rates = <24000000>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + avdd-supply = <&vreg_2p8>; + dovdd-supply = <&vreg_1p8>; + dvdd-supply = <&vreg_1p2>; + + port { + endpoint { + link-frequencies = /bits/ 64 <500000000>; + remote-endpoint = <&mipi_csi2_ep>; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml index 67c1c291327b..0e1d9c390180 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov02a10.yaml @@ -39,6 +39,7 @@ properties: clock-frequency: description: Frequency of the eclk clock in Hz. + deprecated: true dovdd-supply: description: @@ -100,7 +101,6 @@ required: - reg - clocks - clock-names - - clock-frequency - dovdd-supply - avdd-supply - dvdd-supply @@ -127,7 +127,6 @@ examples: clocks = <&ov02a10_clk>; clock-names = "eclk"; - clock-frequency = <24000000>; rotation = <180>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml new file mode 100644 index 000000000000..bb34f21519c8 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov2735.yaml @@ -0,0 +1,108 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov2735.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV2735 Image Sensor + +maintainers: + - Himanshu Bhavani <himanshu.bhavani@siliconsignals.io> + +description: + The OmniVision OV2735 is a 2MP (1920x1080) color CMOS image sensor controlled + through an I2C-compatible SCCB bus. it outputs RAW10 format and uses a 1/2.7" + optical format. + +properties: + compatible: + const: ovti,ov2735 + + reg: + maxItems: 1 + + clocks: + items: + - description: XVCLK clock + + avdd-supply: + description: Analog Domain Power Supply + + dovdd-supply: + description: I/O Domain Power Supply + + dvdd-supply: + description: Digital Domain Power Supply + + reset-gpios: + maxItems: 1 + description: Reset Pin GPIO Control (active low) + + enable-gpios: + maxItems: 1 + description: + Active-low enable pin. Labeled as 'PWDN' in the datasheet, but acts as + an enable signal. During power rail ramp-up, the device remains powered + down. Once power rails are stable, pulling this pin low powers on the + device. + + port: + description: MIPI CSI-2 transmitter port + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + items: + - const: 1 + - const: 2 + + required: + - data-lanes + - link-frequencies + +required: + - compatible + - reg + - clocks + - avdd-supply + - dovdd-supply + - dvdd-supply + - port + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera-sensor@3c { + compatible = "ovti,ov2735"; + reg = <0x3c>; + clocks = <&ov2735_clk>; + + avdd-supply = <&ov2735_avdd>; + dovdd-supply = <&ov2735_dovdd>; + dvdd-supply = <&ov2735_dvdd>; + + reset-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; + enable-gpios = <&gpio2 11 GPIO_ACTIVE_LOW>; + + port { + cam_out: endpoint { + remote-endpoint = <&mipi_in_cam>; + data-lanes = <1 2>; + link-frequencies = /bits/ 64 <420000000>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml index bc9b27afe3ea..a583714b1ac7 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov5645.yaml @@ -21,6 +21,7 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz. + deprecated: true vdda-supply: description: Analog voltage supply, 2.8 volts @@ -83,8 +84,11 @@ examples: camera@3c { compatible = "ovti,ov5645"; reg = <0x3c>; + clocks = <&clks 1>; - clock-frequency = <24000000>; + assigned-clocks = <&clks 1>; + assigned-clock-rates = <24000000>; + vdddo-supply = <&ov5645_vdddo_1v8>; vdda-supply = <&ov5645_vdda_2v8>; vddd-supply = <&ov5645_vddd_1v5>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml new file mode 100644 index 000000000000..5a857fa2f371 --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov6211.yaml @@ -0,0 +1,96 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ov6211.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: OmniVision OV6211 Image Sensor + +description: + OmniVision OV6211 image sensor is a high performance monochrome image + sensor. The sensor is controlled over a serial camera control bus + protocol (SCCB), the widest supported output image frame size is 400x400 + at 120 frames per second rate, data output format is 8/10-bit RAW + transferred over one-lane MIPI D-PHY interface. + +maintainers: + - Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + const: ovti,ov6211 + + reg: + maxItems: 1 + + clocks: + description: XVCLK supply clock, 6MHz to 27MHz frequency. + maxItems: 1 + + reset-gpios: + description: Active low GPIO connected to XSHUTDOWN pad of the sensor. + maxItems: 1 + + strobe-gpios: + description: Input GPIO connected to strobe pad of the sensor. + maxItems: 1 + + avdd-supply: + description: Analogue voltage supply, 2.6 to 3.0 volts. + + dovdd-supply: + description: Digital I/O voltage supply, 1.8 volts. + + dvdd-supply: + description: Digital core voltage supply. + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + required: + - link-frequencies + +required: + - compatible + - reg + - port + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + camera@60 { + compatible = "ovti,ov6211"; + reg = <0x60>; + clocks = <&camera_clk 0>; + assigned-clocks = <&camera_clk 0>; + assigned-clock-rates = <24000000>; + reset-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>; + avdd-supply = <&vreg_2p8>; + dovdd-supply = <&vreg_1p8>; + dvdd-supply = <&vreg_1p2>; + + port { + endpoint { + link-frequencies = /bits/ 64 <480000000>; + remote-endpoint = <&mipi_csi2_ep>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml index 2e5187acbbb8..922996da59b2 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov7251.yaml @@ -29,6 +29,7 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz. + deprecated: true vdda-supply: description: Analog voltage supply, 2.8 volts @@ -89,8 +90,11 @@ examples: camera@3c { compatible = "ovti,ov7251"; reg = <0x3c>; + clocks = <&clks 1>; - clock-frequency = <24000000>; + assigned-clocks = <&clks 1>; + assigned-clock-rates = <24000000>; + vdddo-supply = <&ov7251_vdddo_1v8>; vdda-supply = <&ov7251_vdda_2v8>; vddd-supply = <&ov7251_vddd_1v5>; diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml b/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml index 3f6f72c35485..fa71f24823f2 100644 --- a/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ov8856.yaml @@ -37,6 +37,7 @@ properties: clock-frequency: description: Frequency of the xvclk clock in Hertz. + deprecated: true dovdd-supply: description: @@ -87,7 +88,6 @@ required: - reg - clocks - clock-names - - clock-frequency - dovdd-supply - avdd-supply - dvdd-supply @@ -114,7 +114,6 @@ examples: clocks = <&cam_osc>; clock-names = "xvclk"; - clock-frequency = <19200000>; avdd-supply = <&mt6358_vcama2_reg>; dvdd-supply = <&mt6358_vcamd_reg>; diff --git a/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml b/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml index c8f2955e0825..ebd95a8d9b2f 100644 --- a/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml +++ b/Documentation/devicetree/bindings/media/i2c/samsung,s5k5baf.yaml @@ -26,6 +26,7 @@ properties: clock-frequency: default: 24000000 description: mclk clock frequency + deprecated: true rstn-gpios: maxItems: 1 @@ -82,9 +83,12 @@ examples: sensor@2d { compatible = "samsung,s5k5baf"; reg = <0x2d>; + clocks = <&camera 0>; + assigned-clocks = <&camera 0>; + assigned-clock-rates = <24000000>; + clock-names = "mclk"; - clock-frequency = <24000000>; rstn-gpios = <&gpl2 1 GPIO_ACTIVE_LOW>; stbyn-gpios = <&gpl2 0 GPIO_ACTIVE_LOW>; vdda-supply = <&cam_io_en_reg>; diff --git a/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml b/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml index 7e83a94124b5..e563e35920c4 100644 --- a/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml +++ b/Documentation/devicetree/bindings/media/i2c/samsung,s5k6a3.yaml @@ -30,6 +30,7 @@ properties: clock-frequency: default: 24000000 description: extclk clock frequency + deprecated: true gpios: maxItems: 1 @@ -80,8 +81,11 @@ examples: sensor@10 { compatible = "samsung,s5k6a3"; reg = <0x10>; - clock-frequency = <24000000>; + clocks = <&camera 1>; + assigned-clocks = <&camera 1>; + assigned-clock-rates = <24000000>; + clock-names = "extclk"; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; afvdd-supply = <&ldo19_reg>; diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml index 421b935b52bc..d105bd357dbb 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx258.yaml @@ -81,6 +81,7 @@ properties: required: - compatible - reg + - clocks - port unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml index b397a730ee94..b06a6e75ba97 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx274.yaml @@ -46,6 +46,8 @@ properties: required: - compatible - reg + - clocks + - clock-names - port additionalProperties: false @@ -59,6 +61,8 @@ examples: imx274: camera-sensor@1a { compatible = "sony,imx274"; reg = <0x1a>; + clocks = <&imx274_clk>; + clock-names = "inck"; reset-gpios = <&gpio_sensor 0 0>; port { diff --git a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml index 990acf89af8f..484039671cd1 100644 --- a/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml +++ b/Documentation/devicetree/bindings/media/i2c/sony,imx290.yaml @@ -51,6 +51,7 @@ properties: clock-frequency: description: Frequency of the xclk clock in Hz + deprecated: true vdda-supply: description: Analog power supply (2.9V) @@ -100,7 +101,6 @@ required: - reg - clocks - clock-names - - clock-frequency - vdda-supply - vddd-supply - vdddo-supply @@ -125,7 +125,8 @@ examples: clocks = <&gcc 90>; clock-names = "xclk"; - clock-frequency = <37125000>; + assigned-clocks = <&clks 1>; + assigned-clock-rates = <37125000>; vdddo-supply = <&camera_vdddo_1v8>; vdda-supply = <&camera_vdda_2v8>; diff --git a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml index 4dcbd2b039a5..0539d52de422 100644 --- a/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml +++ b/Documentation/devicetree/bindings/media/i2c/ti,ds90ub960.yaml @@ -361,6 +361,9 @@ examples: compatible = "sony,imx274"; reg = <0x1a>; + clocks = <&serializer>; + clock-names = "inck"; + reset-gpios = <&serializer1 0 GPIO_ACTIVE_LOW>; port { diff --git a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt index e80d5891b7ed..8d8e40c56872 100644 --- a/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt +++ b/Documentation/devicetree/bindings/media/i2c/toshiba,et8ek8.txt @@ -13,9 +13,6 @@ Mandatory properties - reg: I2C address (0x3e, or an alternative address) - vana-supply: Analogue voltage supply (VANA), 2.8 volts - clocks: External clock to the sensor -- clock-frequency: Frequency of the external clock to the sensor. Camera - driver will set this frequency on the external clock. The clock frequency is - a pre-determined frequency known to be suitable to the board. - reset-gpios: XSHUTDOWN GPIO. The XSHUTDOWN signal is active low. The sensor is in hardware standby mode when the signal is in the low state. @@ -43,8 +40,11 @@ Example compatible = "toshiba,et8ek8"; reg = <0x3e>; vana-supply = <&vaux4>; + clocks = <&isp 0>; - clock-frequency = <9600000>; + assigned-clocks = <&isp 0>; + assigned-clock-rates = <9600000>; + reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>; /* 102 */ port { csi_cam1: endpoint { diff --git a/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml b/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml new file mode 100644 index 000000000000..8a47761f1e6b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/mediatek,mt8173-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8173 Video Processor Unit + +maintainers: + - Ariel D'Alessandro <ariel.dalessandro@collabora.com> + +description: + Video Processor Unit is a HW video controller. It controls HW Codec including + H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color + convert). + +properties: + compatible: + const: mediatek,mt8173-vpu + + reg: + maxItems: 2 + + reg-names: + items: + - const: tcm + - const: cfg_reg + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-names: + items: + - const: main + + memory-region: + maxItems: 1 + +required: + - compatible + - reg + - reg-names + - interrupts + - clocks + - clock-names + - memory-region + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8173-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + vpu: vpu@10020000 { + compatible = "mediatek,mt8173-vpu"; + reg = <0 0x10020000 0 0x30000>, + <0 0x10050000 0 0x100>; + reg-names = "tcm", "cfg_reg"; + interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&topckgen CLK_TOP_SCP_SEL>; + clock-names = "main"; + memory-region = <&vpu_dma_reserved>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/media/mediatek-mdp.txt b/Documentation/devicetree/bindings/media/mediatek-mdp.txt index 53ef26e2c857..253a93eabb5e 100644 --- a/Documentation/devicetree/bindings/media/mediatek-mdp.txt +++ b/Documentation/devicetree/bindings/media/mediatek-mdp.txt @@ -5,7 +5,8 @@ Media Data Path is used for scaling and color space conversion. Required properties (controller node): - compatible: "mediatek,mt8173-mdp" - mediatek,vpu: the node of video processor unit, see - Documentation/devicetree/bindings/media/mediatek-vpu.txt for details. + Documentation/devicetree/bindings/media/mediatek,mt8173-vpu.yaml for + details. Required properties (all function blocks, child node): - compatible: Should be one of diff --git a/Documentation/devicetree/bindings/media/mediatek-vpu.txt b/Documentation/devicetree/bindings/media/mediatek-vpu.txt deleted file mode 100644 index 2a5bac37f9a2..000000000000 --- a/Documentation/devicetree/bindings/media/mediatek-vpu.txt +++ /dev/null @@ -1,31 +0,0 @@ -* Mediatek Video Processor Unit - -Video Processor Unit is a HW video controller. It controls HW Codec including -H.264/VP8/VP9 Decode, H.264/VP8 Encode and Image Processor (scale/rotate/color convert). - -Required properties: - - compatible: "mediatek,mt8173-vpu" - - reg: Must contain an entry for each entry in reg-names. - - reg-names: Must include the following entries: - "tcm": tcm base - "cfg_reg": Main configuration registers base - - interrupts: interrupt number to the cpu. - - clocks : clock name from clock manager - - clock-names: must be main. It is the main clock of VPU - -Optional properties: - - memory-region: phandle to a node describing memory (see - Documentation/devicetree/bindings/reserved-memory/reserved-memory.txt) - to be used for VPU extended memory; if not present, VPU may be located - anywhere in the memory - -Example: - vpu: vpu@10020000 { - compatible = "mediatek,mt8173-vpu"; - reg = <0 0x10020000 0 0x30000>, - <0 0x10050000 0 0x100>; - reg-names = "tcm", "cfg_reg"; - interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&topckgen TOP_SCP_SEL>; - clock-names = "main"; - }; diff --git a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml index 03a23a26c4f3..41ad5b84eaeb 100644 --- a/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml +++ b/Documentation/devicetree/bindings/media/nxp,imx-mipi-csi2.yaml @@ -66,6 +66,14 @@ properties: clock-frequency: description: The desired external clock ("wrap") frequency, in Hz default: 166000000 + deprecated: true + + fsl,num-channels: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Number of output channels + minimum: 1 + maximum: 4 + default: 1 ports: $ref: /schemas/graph.yaml#/properties/ports @@ -147,7 +155,9 @@ examples: <&clks IMX7D_MIPI_CSI_ROOT_CLK>, <&clks IMX7D_MIPI_DPHY_ROOT_CLK>; clock-names = "pclk", "wrap", "phy"; - clock-frequency = <166000000>; + + assigned-clocks = <&clks IMX7D_MIPI_CSI_ROOT_CLK>; + assigned-clock-rates = <166000000>; power-domains = <&pgc_mipi_phy>; phy-supply = <®_1p0d>; @@ -185,12 +195,16 @@ examples: compatible = "fsl,imx8mm-mipi-csi2"; reg = <0x32e30000 0x1000>; interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; - clock-frequency = <333000000>; + clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>, <&clk IMX8MM_CLK_CSI1_ROOT>, <&clk IMX8MM_CLK_CSI1_PHY_REF>, <&clk IMX8MM_CLK_DISP_AXI_ROOT>; clock-names = "pclk", "wrap", "phy", "axi"; + + assigned-clocks = <&clk IMX8MM_CLK_CSI1_ROOT>; + assigned-clock-rates = <250000000>; + power-domains = <&mipi_pd>; ports { diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml new file mode 100644 index 000000000000..391d0f6f67ef --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-camss.yaml @@ -0,0 +1,243 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcm2290-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Camera Subsystem (CAMSS) + +maintainers: + - Loic Poulain <loic.poulain@oss.qualcomm.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,qcm2290-camss + + reg: + maxItems: 9 + + reg-names: + items: + - const: top + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: csitpg0 + - const: csitpg1 + - const: vfe0 + - const: vfe1 + + clocks: + maxItems: 15 + + clock-names: + items: + - const: ahb + - const: axi + - const: camnoc_nrt_axi + - const: camnoc_rt_axi + - const: csi0 + - const: csi1 + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: top_ahb + - const: vfe0 + - const: vfe0_cphy_rx + - const: vfe1 + - const: vfe1_cphy_rx + + interrupts: + maxItems: 8 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csiphy0 + - const: csiphy1 + - const: csitpg0 + - const: csitpg1 + - const: vfe0 + - const: vfe1 + + interconnects: + maxItems: 3 + + interconnect-names: + items: + - const: ahb + - const: hf_mnoc + - const: sf_mnoc + + iommus: + maxItems: 4 + + power-domains: + items: + - description: GDSC CAMSS Block, Global Distributed Switch Controller. + + vdd-csiphy-1p2-supply: + description: + Phandle to a 1.2V regulator supply to CSI PHYs. + + vdd-csiphy-1p8-supply: + description: + Phandle to 1.8V regulator supply to CSI PHYs pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + + description: + Input port for receiving CSI data from a CSIPHY. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - vdd-csiphy-1p2-supply + - vdd-csiphy-1p8-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/interconnect/qcom,rpm-icc.h> + #include <dt-bindings/interconnect/qcom,qcm2290.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + camss: camss@5c6e000 { + compatible = "qcom,qcm2290-camss"; + + reg = <0x0 0x5c11000 0x0 0x1000>, + <0x0 0x5c6e000 0x0 0x1000>, + <0x0 0x5c75000 0x0 0x1000>, + <0x0 0x5c52000 0x0 0x1000>, + <0x0 0x5c53000 0x0 0x1000>, + <0x0 0x5c66000 0x0 0x400>, + <0x0 0x5c68000 0x0 0x400>, + <0x0 0x5c6f000 0x0 0x4000>, + <0x0 0x5c76000 0x0 0x4000>; + reg-names = "top", + "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + clocks = <&gcc GCC_CAMERA_AHB_CLK>, + <&gcc GCC_CAMSS_AXI_CLK>, + <&gcc GCC_CAMSS_NRT_AXI_CLK>, + <&gcc GCC_CAMSS_RT_AXI_CLK>, + <&gcc GCC_CAMSS_TFE_0_CSID_CLK>, + <&gcc GCC_CAMSS_TFE_1_CSID_CLK>, + <&gcc GCC_CAMSS_CPHY_0_CLK>, + <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>, + <&gcc GCC_CAMSS_CPHY_1_CLK>, + <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>, + <&gcc GCC_CAMSS_TOP_AHB_CLK>, + <&gcc GCC_CAMSS_TFE_0_CLK>, + <&gcc GCC_CAMSS_TFE_0_CPHY_RX_CLK>, + <&gcc GCC_CAMSS_TFE_1_CLK>, + <&gcc GCC_CAMSS_TFE_1_CPHY_RX_CLK>; + clock-names = "ahb", + "axi", + "camnoc_nrt_axi", + "camnoc_rt_axi", + "csi0", + "csi1", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "top_ahb", + "vfe0", + "vfe0_cphy_rx", + "vfe1", + "vfe1_cphy_rx"; + + interrupts = <GIC_SPI 210 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 212 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 309 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 310 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 211 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 213 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csiphy0", + "csiphy1", + "csitpg0", + "csitpg1", + "vfe0", + "vfe1"; + + interconnects = <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_CAMERA_CFG RPM_ACTIVE_TAG>, + <&mmrt_virt MASTER_CAMNOC_HF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&mmnrt_virt MASTER_CAMNOC_SF RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>; + interconnect-names = "ahb", + "hf_mnoc", + "sf_mnoc"; + + iommus = <&apps_smmu 0x400 0x0>, + <&apps_smmu 0x800 0x0>, + <&apps_smmu 0x820 0x0>, + <&apps_smmu 0x840 0x0>; + + power-domains = <&gcc GCC_CAMSS_TOP_GDSC>; + + vdd-csiphy-1p2-supply = <&pm4125_l5>; + vdd-csiphy-1p8-supply = <&pm4125_l13>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml new file mode 100644 index 000000000000..3f3ee82fc878 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcm2290-venus.yaml @@ -0,0 +1,130 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcm2290-venus.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCM2290 Venus video encode and decode accelerators + +maintainers: + - Jorge Ramirez-Ortiz <jorge.ramirez@oss.qualcomm.com> + +description: + The Venus AR50_LITE IP is a video encode and decode accelerator present + on Qualcomm platforms. + +allOf: + - $ref: qcom,venus-common.yaml# + +properties: + compatible: + const: qcom,qcm2290-venus + + power-domains: + maxItems: 3 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: cx + + clocks: + maxItems: 6 + + clock-names: + items: + - const: core + - const: iface + - const: bus + - const: throttle + - const: vcodec0_core + - const: vcodec0_bus + + iommus: + maxItems: 5 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: video-mem + - const: cpu-cfg + + operating-points-v2: true + opp-table: + type: object + +required: + - compatible + - power-domain-names + - iommus + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-qcm2290.h> + #include <dt-bindings/interconnect/qcom,qcm2290.h> + #include <dt-bindings/interconnect/qcom,rpm-icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + venus: video-codec@5a00000 { + compatible = "qcom,qcm2290-venus"; + reg = <0x5a00000 0xf0000>; + + interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>; + + power-domains = <&gcc GCC_VENUS_GDSC>, + <&gcc GCC_VCODEC0_GDSC>, + <&rpmpd QCM2290_VDDCX>; + power-domain-names = "venus", + "vcodec0", + "cx"; + + operating-points-v2 = <&venus_opp_table>; + + clocks = <&gcc GCC_VIDEO_VENUS_CTL_CLK>, + <&gcc GCC_VIDEO_AHB_CLK>, + <&gcc GCC_VENUS_CTL_AXI_CLK>, + <&gcc GCC_VIDEO_THROTTLE_CORE_CLK>, + <&gcc GCC_VIDEO_VCODEC0_SYS_CLK>, + <&gcc GCC_VCODEC0_AXI_CLK>; + clock-names = "core", + "iface", + "bus", + "throttle", + "vcodec0_core", + "vcodec0_bus"; + + memory-region = <&pil_video_mem>; + + iommus = <&apps_smmu 0x860 0x0>, + <&apps_smmu 0x880 0x0>, + <&apps_smmu 0x861 0x04>, + <&apps_smmu 0x863 0x0>, + <&apps_smmu 0x804 0xe0>; + + interconnects = <&mmnrt_virt MASTER_VIDEO_P0 RPM_ALWAYS_TAG + &bimc SLAVE_EBI1 RPM_ALWAYS_TAG>, + <&bimc MASTER_APPSS_PROC RPM_ACTIVE_TAG + &config_noc SLAVE_VENUS_CFG RPM_ACTIVE_TAG>; + interconnect-names = "video-mem", + "cpu-cfg"; + + venus_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-133333333 { + opp-hz = /bits/ 64 <133333333>; + required-opps = <&rpmpd_opp_low_svs>; + }; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmpd_opp_svs>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml new file mode 100644 index 000000000000..80a4540a22dc --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,qcs8300-camss.yaml @@ -0,0 +1,336 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,qcs8300-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm QCS8300 CAMSS ISP + +maintainers: + - Vikram Sharma <quic_vikramsa@quicinc.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,qcs8300-camss + + reg: + maxItems: 21 + + reg-names: + items: + - const: csid_wrapper + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + clocks: + maxItems: 26 + + clock-names: + items: + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_vfe_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: icp_ahb + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 20 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: top + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-2]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 0-2. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sa8775p-camcc.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@ac78000 { + compatible = "qcom,qcs8300-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0x0f00>, + <0x0 0xac7c000 0x0 0x0f00>, + <0x0 0xac84000 0x0 0x0f00>, + <0x0 0xac88000 0x0 0x0f00>, + <0x0 0xac8c000 0x0 0x0f00>, + <0x0 0xac90000 0x0 0x0f00>, + <0x0 0xac94000 0x0 0x0f00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac60000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x2400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml new file mode 100644 index 000000000000..019caa2b09c3 --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sa8775p-camss.yaml @@ -0,0 +1,361 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sa8775p-camss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SA8775P CAMSS ISP + +maintainers: + - Vikram Sharma <quic_vikramsa@quicinc.com> + +description: + The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms. + +properties: + compatible: + const: qcom,sa8775p-camss + + reg: + maxItems: 22 + + reg-names: + items: + - const: csid_wrapper + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + clocks: + maxItems: 28 + + clock-names: + items: + - const: camnoc_axi + - const: core_ahb + - const: cpas_ahb + - const: cpas_fast_ahb_clk + - const: cpas_vfe_lite + - const: cpas_vfe0 + - const: cpas_vfe1 + - const: csid + - const: csiphy0 + - const: csiphy0_timer + - const: csiphy1 + - const: csiphy1_timer + - const: csiphy2 + - const: csiphy2_timer + - const: csiphy3 + - const: csiphy3_timer + - const: csiphy_rx + - const: gcc_axi_hf + - const: gcc_axi_sf + - const: icp_ahb + - const: vfe0 + - const: vfe0_fast_ahb + - const: vfe1 + - const: vfe1_fast_ahb + - const: vfe_lite + - const: vfe_lite_ahb + - const: vfe_lite_cphy_rx + - const: vfe_lite_csid + + interrupts: + maxItems: 21 + + interrupt-names: + items: + - const: csid0 + - const: csid1 + - const: csid_lite0 + - const: csid_lite1 + - const: csid_lite2 + - const: csid_lite3 + - const: csid_lite4 + - const: csiphy0 + - const: csiphy1 + - const: csiphy2 + - const: csiphy3 + - const: tpg0 + - const: tpg1 + - const: tpg2 + - const: vfe0 + - const: vfe1 + - const: vfe_lite0 + - const: vfe_lite1 + - const: vfe_lite2 + - const: vfe_lite3 + - const: vfe_lite4 + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: ahb + - const: hf_0 + + iommus: + maxItems: 1 + + power-domains: + items: + - description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller. + + power-domain-names: + items: + - const: top + + vdda-phy-supply: + description: + Phandle to a regulator supply to PHY core block. + + vdda-pll-supply: + description: + Phandle to 1.8V regulator supply to PHY refclk pll block. + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + description: + CSI input ports. + + patternProperties: + "^port@[0-3]+$": + $ref: /schemas/graph.yaml#/$defs/port-base + unevaluatedProperties: false + description: + Input port for receiving CSI data on CSIPHY 0-3. + + properties: + endpoint: + $ref: video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + minItems: 1 + maxItems: 4 + + required: + - data-lanes + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - interrupt-names + - interconnects + - interconnect-names + - iommus + - power-domains + - power-domain-names + - vdda-phy-supply + - vdda-pll-supply + - ports + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,sa8775p-camcc.h> + #include <dt-bindings/clock/qcom,sa8775p-gcc.h> + #include <dt-bindings/interconnect/qcom,sa8775p-rpmh.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/qcom-rpmpd.h> + + soc { + #address-cells = <2>; + #size-cells = <2>; + + isp@ac78000 { + compatible = "qcom,sa8775p-camss"; + + reg = <0x0 0xac78000 0x0 0x1000>, + <0x0 0xac7a000 0x0 0x0f00>, + <0x0 0xac7c000 0x0 0x0f00>, + <0x0 0xac84000 0x0 0x0f00>, + <0x0 0xac88000 0x0 0x0f00>, + <0x0 0xac8c000 0x0 0x0f00>, + <0x0 0xac90000 0x0 0x0f00>, + <0x0 0xac94000 0x0 0x0f00>, + <0x0 0xac9c000 0x0 0x2000>, + <0x0 0xac9e000 0x0 0x2000>, + <0x0 0xaca0000 0x0 0x2000>, + <0x0 0xaca2000 0x0 0x2000>, + <0x0 0xacac000 0x0 0x0400>, + <0x0 0xacad000 0x0 0x0400>, + <0x0 0xacae000 0x0 0x0400>, + <0x0 0xac4d000 0x0 0xd000>, + <0x0 0xac5a000 0x0 0xd000>, + <0x0 0xac85000 0x0 0x0d00>, + <0x0 0xac89000 0x0 0x0d00>, + <0x0 0xac8d000 0x0 0x0d00>, + <0x0 0xac91000 0x0 0x0d00>, + <0x0 0xac95000 0x0 0x0d00>; + reg-names = "csid_wrapper", + "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, + <&camcc CAM_CC_CORE_AHB_CLK>, + <&camcc CAM_CC_CPAS_AHB_CLK>, + <&camcc CAM_CC_CPAS_FAST_AHB_CLK>, + <&camcc CAM_CC_CPAS_IFE_LITE_CLK>, + <&camcc CAM_CC_CPAS_IFE_0_CLK>, + <&camcc CAM_CC_CPAS_IFE_1_CLK>, + <&camcc CAM_CC_CSID_CLK>, + <&camcc CAM_CC_CSIPHY0_CLK>, + <&camcc CAM_CC_CSI0PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY1_CLK>, + <&camcc CAM_CC_CSI1PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY2_CLK>, + <&camcc CAM_CC_CSI2PHYTIMER_CLK>, + <&camcc CAM_CC_CSIPHY3_CLK>, + <&camcc CAM_CC_CSI3PHYTIMER_CLK>, + <&camcc CAM_CC_CSID_CSIPHY_RX_CLK>, + <&gcc GCC_CAMERA_HF_AXI_CLK>, + <&gcc GCC_CAMERA_SF_AXI_CLK>, + <&camcc CAM_CC_ICP_AHB_CLK>, + <&camcc CAM_CC_IFE_0_CLK>, + <&camcc CAM_CC_IFE_0_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_1_CLK>, + <&camcc CAM_CC_IFE_1_FAST_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CLK>, + <&camcc CAM_CC_IFE_LITE_AHB_CLK>, + <&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>, + <&camcc CAM_CC_IFE_LITE_CSID_CLK>; + clock-names = "camnoc_axi", + "core_ahb", + "cpas_ahb", + "cpas_fast_ahb_clk", + "cpas_vfe_lite", + "cpas_vfe0", + "cpas_vfe1", + "csid", + "csiphy0", + "csiphy0_timer", + "csiphy1", + "csiphy1_timer", + "csiphy2", + "csiphy2_timer", + "csiphy3", + "csiphy3_timer", + "csiphy_rx", + "gcc_axi_hf", + "gcc_axi_sf", + "icp_ahb", + "vfe0", + "vfe0_fast_ahb", + "vfe1", + "vfe1_fast_ahb", + "vfe_lite", + "vfe_lite_ahb", + "vfe_lite_cphy_rx", + "vfe_lite_csid"; + + interrupts = <GIC_SPI 565 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 564 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 759 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 758 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 545 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 546 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 547 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 761 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 760 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 605 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "csid0", + "csid1", + "csid_lite0", + "csid_lite1", + "csid_lite2", + "csid_lite3", + "csid_lite4", + "csiphy0", + "csiphy1", + "csiphy2", + "csiphy3", + "tpg0", + "tpg1", + "tpg2", + "vfe0", + "vfe1", + "vfe_lite0", + "vfe_lite1", + "vfe_lite2", + "vfe_lite3", + "vfe_lite4"; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "ahb", + "hf_0"; + + iommus = <&apps_smmu 0x3400 0x20>; + + power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; + power-domain-names = "top"; + + vdda-phy-supply = <&vreg_l4a_0p88>; + vdda-pll-supply = <&vreg_l1c_1p2>; + + ports { + #address-cells = <1>; + #size-cells = <0>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index c79bf2101812..9c4b760508b5 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -8,7 +8,7 @@ title: Qualcomm iris video encode and decode accelerators maintainers: - Vikash Garodia <quic_vgarodia@quicinc.com> - - Dikshita Agarwal <quic_dikshita@quicinc.com> + - Dikshita Agarwal <dikshita.agarwal@oss.qualcomm.com> description: The iris video processing unit is a video encode and decode accelerator @@ -20,12 +20,16 @@ properties: - items: - enum: - qcom,sa8775p-iris + - qcom,x1e80100-iris - const: qcom,sm8550-iris - enum: - qcom,qcs8300-iris - qcom,sm8550-iris - qcom,sm8650-iris + reg: + maxItems: 1 + power-domains: maxItems: 4 @@ -45,6 +49,12 @@ properties: - const: core - const: vcodec0_core + firmware-name: + maxItems: 1 + + interrupts: + maxItems: 1 + interconnects: maxItems: 2 @@ -69,6 +79,9 @@ properties: dma-coherent: true + memory-region: + maxItems: 1 + operating-points-v2: true opp-table: @@ -85,7 +98,6 @@ required: - dma-coherent allOf: - - $ref: qcom,venus-common.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml new file mode 100644 index 000000000000..c9a0fcafe53f --- /dev/null +++ b/Documentation/devicetree/bindings/media/qcom,sm8750-iris.yaml @@ -0,0 +1,186 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/qcom,sm8750-iris.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 SoC Iris video encoder and decoder + +maintainers: + - Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> + +description: + The Iris video processing unit on Qualcomm SM8750 SoC is a video encode and + decode accelerator. + +properties: + compatible: + enum: + - qcom,sm8750-iris + + clocks: + maxItems: 6 + + clock-names: + items: + - const: iface # AXI0 + - const: core + - const: vcodec0_core + - const: iface1 # AXI1 + - const: core_freerun + - const: vcodec0_core_freerun + + dma-coherent: true + + interconnects: + maxItems: 2 + + interconnect-names: + items: + - const: cpu-cfg + - const: video-mem + + iommus: + maxItems: 2 + + operating-points-v2: true + opp-table: + type: object + + power-domains: + maxItems: 4 + + power-domain-names: + items: + - const: venus + - const: vcodec0 + - const: mxc + - const: mmcx + + resets: + maxItems: 4 + + reset-names: + items: + - const: bus0 + - const: bus1 + - const: core + - const: vcodec0_core + +required: + - compatible + - dma-coherent + - interconnects + - interconnect-names + - iommus + - power-domain-names + - resets + - reset-names + +allOf: + - $ref: qcom,venus-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,rpmh.h> + #include <dt-bindings/clock/qcom,sm8750-gcc.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interconnect/qcom,icc.h> + #include <dt-bindings/interconnect/qcom,sm8750-rpmh.h> + #include <dt-bindings/power/qcom-rpmpd.h> + #include <dt-bindings/power/qcom,rpmhpd.h> + + video-codec@aa00000 { + compatible = "qcom,sm8750-iris"; + reg = <0x0aa00000 0xf0000>; + + clocks = <&gcc GCC_VIDEO_AXI0_CLK>, + <&videocc_mvs0c_clk>, + <&videocc_mvs0_clk>, + <&gcc GCC_VIDEO_AXI1_CLK>, + <&videocc_mvs0c_freerun_clk>, + <&videocc_mvs0_freerun_clk>; + clock-names = "iface", + "core", + "vcodec0_core", + "iface1", + "core_freerun", + "vcodec0_core_freerun"; + + dma-coherent; + iommus = <&apps_smmu 0x1940 0>, + <&apps_smmu 0x1947 0>; + + interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY + &config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, + <&mmss_noc MASTER_VIDEO_MVP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "cpu-cfg", + "video-mem"; + + interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; + + operating-points-v2 = <&iris_opp_table>; + + memory-region = <&video_mem>; + + power-domains = <&videocc_mvs0c_gdsc>, + <&videocc_mvs0_gdsc>, + <&rpmhpd RPMHPD_MXC>, + <&rpmhpd RPMHPD_MMCX>; + power-domain-names = "venus", + "vcodec0", + "mxc", + "mmcx"; + + resets = <&gcc GCC_VIDEO_AXI0_CLK_ARES>, + <&gcc GCC_VIDEO_AXI1_CLK_ARES>, + <&videocc_mvs0c_freerun_clk_ares>, + <&videocc_mvs0_freerun_clk_ares>; + reset-names = "bus0", + "bus1", + "core", + "vcodec0_core"; + + iris_opp_table: opp-table { + compatible = "operating-points-v2"; + + opp-240000000 { + opp-hz = /bits/ 64 <240000000>; + required-opps = <&rpmhpd_opp_low_svs_d1>, + <&rpmhpd_opp_low_svs_d1>; + }; + + opp-338000000 { + opp-hz = /bits/ 64 <338000000>; + required-opps = <&rpmhpd_opp_low_svs>, + <&rpmhpd_opp_low_svs>; + }; + + opp-420000000 { + opp-hz = /bits/ 64 <420000000>; + required-opps = <&rpmhpd_opp_svs>, + <&rpmhpd_opp_svs>; + }; + + opp-444000000 { + opp-hz = /bits/ 64 <444000000>; + required-opps = <&rpmhpd_opp_svs_l1>, + <&rpmhpd_opp_svs_l1>; + }; + + opp-533333334 { + opp-hz = /bits/ 64 <533333334>; + required-opps = <&rpmhpd_opp_nom>, + <&rpmhpd_opp_nom>; + }; + + opp-630000000 { + opp-hz = /bits/ 64 <630000000>; + required-opps = <&rpmhpd_opp_turbo>, + <&rpmhpd_opp_turbo>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml index 6be00aca4181..477c21417e75 100644 --- a/Documentation/devicetree/bindings/media/rockchip-isp1.yaml +++ b/Documentation/devicetree/bindings/media/rockchip-isp1.yaml @@ -71,7 +71,16 @@ properties: const: dphy power-domains: - maxItems: 1 + minItems: 1 + items: + - description: ISP power domain + - description: MIPI CSI-2 power domain + + power-domain-names: + minItems: 1 + items: + - const: isp + - const: csi2 ports: $ref: /schemas/graph.yaml#/properties/ports @@ -155,14 +164,26 @@ allOf: const: fsl,imx8mp-isp then: properties: + clocks: + minItems: 4 + clock-names: + minItems: 4 iommus: false phys: false phy-names: false + power-domains: + minItems: 2 + power-domain-names: + minItems: 2 required: - fsl,blk-ctrl + - power-domain-names else: properties: fsl,blk-ctrl: false + power-domains: + maxItems: 1 + power-domain-names: false required: - iommus - phys diff --git a/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml b/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml index 3a5ff3f47060..71d63bb9abb5 100644 --- a/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml +++ b/Documentation/devicetree/bindings/media/samsung,exynos4212-fimc-is.yaml @@ -209,9 +209,10 @@ examples: svdda-supply = <&cam_io_reg>; svddio-supply = <&ldo19_reg>; afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; clocks = <&camera 1>; clock-names = "extclk"; + assigned-clocks = <&camera 1>; + assigned-clock-rates = <24000000>; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { diff --git a/Documentation/devicetree/bindings/media/samsung,fimc.yaml b/Documentation/devicetree/bindings/media/samsung,fimc.yaml index 7808d61f1fa3..2a54379d9509 100644 --- a/Documentation/devicetree/bindings/media/samsung,fimc.yaml +++ b/Documentation/devicetree/bindings/media/samsung,fimc.yaml @@ -259,10 +259,11 @@ examples: svdda-supply = <&cam_io_reg>; svddio-supply = <&ldo19_reg>; afvdd-supply = <&ldo19_reg>; - clock-frequency = <24000000>; /* CAM_B_CLKOUT */ clocks = <&camera 1>; clock-names = "extclk"; + assigned-clocks = <&camera 1>; + assigned-clock-rates = <24000000>; gpios = <&gpm1 6 GPIO_ACTIVE_LOW>; port { diff --git a/Documentation/devicetree/bindings/media/silabs,si470x.yaml b/Documentation/devicetree/bindings/media/silabs,si470x.yaml index a3d19c562ca3..db22b88fc5bb 100644 --- a/Documentation/devicetree/bindings/media/silabs,si470x.yaml +++ b/Documentation/devicetree/bindings/media/silabs,si470x.yaml @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml# title: Silicon Labs Si470x FM Radio Receiver maintainers: - - Hans Verkuil <hverkuil@xs4all.nl> + - Hans Verkuil <hverkuil@kernel.org> - Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com> properties: diff --git a/Documentation/devicetree/bindings/media/video-interface-devices.yaml b/Documentation/devicetree/bindings/media/video-interface-devices.yaml index cf7712ad297c..3ad1590b0496 100644 --- a/Documentation/devicetree/bindings/media/video-interface-devices.yaml +++ b/Documentation/devicetree/bindings/media/video-interface-devices.yaml @@ -17,6 +17,14 @@ properties: An array of phandles, each referring to a flash LED, a sub-node of the LED driver device node. + leds: + minItems: 1 + maxItems: 1 + + led-names: + enum: + - privacy + lens-focus: $ref: /schemas/types.yaml#/definitions/phandle description: diff --git a/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml b/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml index b935894bd4fc..3328c8df8190 100644 --- a/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/brcm,brcmstb-memc-ddr.yaml @@ -42,6 +42,10 @@ properties: items: - const: brcm,brcmstb-memc-ddr-rev-b.1.x - const: brcm,brcmstb-memc-ddr + - description: Revision 0.x controllers + items: + - const: brcm,brcmstb-memc-ddr-rev-a.0.0 + - const: brcm,brcmstb-memc-ddr reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml index bc8477e7ab19..4e4fb4acd7f9 100644 --- a/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml +++ b/Documentation/devicetree/bindings/memory-controllers/nvidia,tegra210-emc.yaml @@ -33,6 +33,9 @@ properties: items: - description: EMC general interrupt + "#interconnect-cells": + const: 0 + memory-region: maxItems: 1 description: @@ -44,6 +47,11 @@ properties: description: phandle of the memory controller node + operating-points-v2: + description: + Should contain freqs and voltages and opp-supported-hw property, which + is a bitfield indicating SoC speedo ID mask. + required: - compatible - reg @@ -79,4 +87,7 @@ examples: interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; memory-region = <&emc_table>; nvidia,memory-controller = <&mc>; + operating-points-v2 = <&dvfs_opp_table>; + + #interconnect-cells = <0>; }; diff --git a/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml new file mode 100644 index 000000000000..d65313b33a3e --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/starfive,jh7110-dmc.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/starfive,jh7110-dmc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: StarFive JH7110 DMC + +maintainers: + - E Shattow <e@freeshell.de> + +description: + JH7110 DDR external memory interface LPDDR4/DDR4/DDR3/LPDDR3 32-bit at + 2133Mbps (up to 2800Mbps). + +properties: + compatible: + items: + - const: starfive,jh7110-dmc + + reg: + items: + - description: controller registers + - description: phy registers + + clocks: + maxItems: 1 + + clock-names: + items: + - const: pll + + resets: + items: + - description: axi + - description: osc + - description: apb + + reset-names: + items: + - const: axi + - const: osc + - const: apb + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/starfive,jh7110-crg.h> + #include <dt-bindings/reset/starfive,jh7110-crg.h> + soc { + #address-cells = <2>; + #size-cells = <2>; + + memory-controller@15700000 { + compatible = "starfive,jh7110-dmc"; + reg = <0x0 0x15700000 0x0 0x10000>, + <0x0 0x13000000 0x0 0x10000>; + clocks = <&syscrg JH7110_PLLCLK_PLL1_OUT>; + clock-names = "pll"; + resets = <&syscrg JH7110_SYSRST_DDR_AXI>, + <&syscrg JH7110_SYSRST_DDR_OSC>, + <&syscrg JH7110_SYSRST_DDR_APB>; + reset-names = "axi", "osc", "apb"; + }; + }; diff --git a/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml new file mode 100644 index 000000000000..479288567d0b --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/xlnx,versal-net-ddrmc5.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/xlnx,versal-net-ddrmc5.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Xilinx Versal NET Memory Controller + +maintainers: + - Shubhrajyoti Datta <shubhrajyoti.datta@amd.com> + +description: + The integrated DDR Memory Controllers (DDRMCs) support both DDR5 and LPDDR5 + compact and extended memory interfaces. Versal NET DDR memory controller + has an optional ECC support which correct single bit ECC errors and detect + double bit ECC errors. It also has support for reporting other errors like + MMCM (Mixed-Mode Clock Manager) errors and General software errors. + +properties: + compatible: + const: xlnx,versal-net-ddrmc5 + + amd,rproc: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the remoteproc_r5 rproc node using which APU interacts + with remote processor. APU primarily communicates with the RPU for + accessing the DDRMC address space and getting error notification. + +required: + - compatible + - amd,rproc + +additionalProperties: false + +examples: + - | + memory-controller { + compatible = "xlnx,versal-net-ddrmc5"; + amd,rproc = <&remoteproc_r5>; + }; diff --git a/Documentation/devicetree/bindings/mfd/act8945a.txt b/Documentation/devicetree/bindings/mfd/act8945a.txt deleted file mode 100644 index 5ca75d888b4a..000000000000 --- a/Documentation/devicetree/bindings/mfd/act8945a.txt +++ /dev/null @@ -1,82 +0,0 @@ -Device-Tree bindings for Active-semi ACT8945A MFD driver - -Required properties: - - compatible: "active-semi,act8945a". - - reg: the I2C slave address for the ACT8945A chip - -The chip exposes two subdevices: - - a regulators: see ../regulator/act8945a-regulator.txt - - a charger: see ../power/act8945a-charger.txt - -Example: - pmic@5b { - compatible = "active-semi,act8945a"; - reg = <0x5b>; - - active-semi,vsel-high; - - regulators { - vdd_1v35_reg: REG_DCDC1 { - regulator-name = "VDD_1V35"; - regulator-min-microvolt = <1350000>; - regulator-max-microvolt = <1350000>; - regulator-always-on; - }; - - vdd_1v2_reg: REG_DCDC2 { - regulator-name = "VDD_1V2"; - regulator-min-microvolt = <1100000>; - regulator-max-microvolt = <1300000>; - regulator-always-on; - }; - - vdd_3v3_reg: REG_DCDC3 { - regulator-name = "VDD_3V3"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_fuse_reg: REG_LDO1 { - regulator-name = "VDD_FUSE"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - vdd_3v3_lp_reg: REG_LDO2 { - regulator-name = "VDD_3V3_LP"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_led_reg: REG_LDO3 { - regulator-name = "VDD_LED"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; - - vdd_sdhc_1v8_reg: REG_LDO4 { - regulator-name = "VDD_SDHC_1V8"; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - regulator-always-on; - }; - }; - - charger { - compatible = "active-semi,act8945a-charger"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_charger_chglev &pinctrl_charger_lbo &pinctrl_charger_irq>; - interrupt-parent = <&pioA>; - interrupts = <45 IRQ_TYPE_LEVEL_LOW>; - - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/mfd/apple,smc.yaml b/Documentation/devicetree/bindings/mfd/apple,smc.yaml index 8a10e270d421..5429538f7e2e 100644 --- a/Documentation/devicetree/bindings/mfd/apple,smc.yaml +++ b/Documentation/devicetree/bindings/mfd/apple,smc.yaml @@ -15,12 +15,17 @@ description: properties: compatible: - items: - - enum: - - apple,t6000-smc - - apple,t8103-smc - - apple,t8112-smc - - const: apple,smc + oneOf: + - items: + - const: apple,t6020-smc + - const: apple,t8103-smc + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-smc + - apple,t8103-smc + - apple,t8112-smc + - const: apple,smc reg: items: diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml index 5eccd10d95ce..da1887d7a8fe 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml @@ -48,8 +48,34 @@ properties: patternProperties: '^p2a-control@[0-9a-f]+$': - description: See Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt + description: > + PCI-to-AHB Bridge Control + + The bridge is available on platforms with the VGA enabled on the Aspeed + device. In this case, the host has access to a 64KiB window into all of + the BMC's memory. The BMC can disable this bridge. If the bridge is + enabled, the host has read access to all the regions of memory, however + the host only has read and write access depending on a register + controlled by the BMC. type: object + additionalProperties: false + + properties: + compatible: + enum: + - aspeed,ast2400-p2a-ctrl + - aspeed,ast2500-p2a-ctrl + reg: + maxItems: 1 + + memory-region: + maxItems: 1 + description: + A reserved_memory region to be used for the PCI to AHB mapping + + required: + - compatible + - reg '^pinctrl(@[0-9a-f]+)?$': type: object @@ -75,6 +101,10 @@ patternProperties: - aspeed,ast2500-scu-ic - aspeed,ast2600-scu-ic0 - aspeed,ast2600-scu-ic1 + - aspeed,ast2700-scu-ic0 + - aspeed,ast2700-scu-ic1 + - aspeed,ast2700-scu-ic2 + - aspeed,ast2700-scu-ic3 '^silicon-id@[0-9a-f]+$': description: Unique hardware silicon identifiers within the SoC @@ -123,6 +153,11 @@ examples: #size-cells = <1>; ranges = <0x0 0x1e6e2000 0x1000>; + p2a-control@2c { + compatible = "aspeed,ast2400-p2a-ctrl"; + reg = <0x2c 0x4>; + }; + silicon-id@7c { compatible = "aspeed,ast2500-silicon-id", "aspeed,silicon-id"; reg = <0x7c 0x4>, <0x150 0x8>; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt b/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt deleted file mode 100644 index aea5370efd97..000000000000 --- a/Documentation/devicetree/bindings/mfd/aspeed-gfx.txt +++ /dev/null @@ -1,17 +0,0 @@ -* Device tree bindings for Aspeed SoC Display Controller (GFX) - -The Aspeed SoC Display Controller primarily does as its name suggests, but also -participates in pinmux requests on the g5 SoCs. It is therefore considered a -syscon device. - -Required properties: -- compatible: "aspeed,ast2500-gfx", "syscon" -- reg: contains offset/length value of the GFX memory - region. - -Example: - -gfx: display@1e6e6000 { - compatible = "aspeed,ast2500-gfx", "syscon"; - reg = <0x1e6e6000 0x1000>; -}; diff --git a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml index d88854e60b7f..f329223cec07 100644 --- a/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml +++ b/Documentation/devicetree/bindings/mfd/aspeed-lpc.yaml @@ -137,6 +137,9 @@ patternProperties: reg: maxItems: 1 + clocks: + maxItems: 1 + interrupts: maxItems: 1 diff --git a/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml b/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml new file mode 100644 index 000000000000..d2886f2686a8 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/fsl,mc13xxx.yaml @@ -0,0 +1,288 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/fsl,mc13xxx.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MC13xxx Power Management Integrated Circuits (PMIC) + +maintainers: + - Alexander Kurz <akurz@blala.de> + +description: > + The MC13xxx PMIC series consists of the three models MC13783, MC13892 + and MC34708 and provide regulators and other features like RTC, ADC, + LED, touchscreen, codec and input buttons. + + Link to datasheets + https://www.nxp.com/docs/en/data-sheet/MC13783.pdf + https://www.nxp.com/docs/en/data-sheet/MC13892.pdf + https://www.nxp.com/docs/en/data-sheet/MC34708.pdf + +properties: + compatible: + enum: + - fsl,mc13783 + - fsl,mc13892 + - fsl,mc34708 + + reg: + description: I2C slave address or SPI chip select number. + maxItems: 1 + + spi-max-frequency: true + + spi-cs-high: true + + system-power-controller: true + + interrupts: + maxItems: 1 + + buttons: + type: object + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + "^onkey@[0-2]$": + $ref: /schemas/input/input.yaml# + unevaluatedProperties: false + type: object + + properties: + reg: + description: | + One of + MC13783 BUTTON IDs: + 0: ONOFD1 + 1: ONOFD2 + 2: ONOFD3 + + MC13892 BUTTON IDs: + 0: PWRON1 + 1: PWRON2 + 2: PWRON3 + + MC34708 BUTTON IDs: + 0: PWRON1 + 1: PWRON2 + maximum: 2 + + debounce-delay-ms: + enum: [0, 30, 150, 750] + default: 30 + description: + Sets the debouncing delay in milliseconds. + + active-low: + description: Set active when pin is pulled low. + + linux,code: true + + fsl,enable-reset: + description: + Setting of the global reset option. + type: boolean + + unevaluatedProperties: false + + leds: + type: object + $ref: /schemas/leds/common.yaml# + + properties: + reg: + description: | + One of + MC13783 LED IDs + 0: Main display + 1: AUX display + 2: Keypad + 3: Red 1 + 4: Green 1 + 5: Blue 1 + 6: Red 2 + 7: Green 2 + 8: Blue 2 + 9: Red 3 + 10: Green 3 + 11: Blue 3 + + MC13892 LED IDs + 0: Main display + 1: AUX display + 2: Keypad + 3: Red + 4: Green + 5: Blue + + MC34708 LED IDs + 0: Charger Red + 1: Charger Green + maxItems: 1 + + led-control: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Setting for LED-Control register array length depends on model, + mc13783: 6, mc13892: 4, mc34708: 1 + + regulators: + type: object + + additionalProperties: + type: object + + description: | + List of child nodes specifying the regulators, depending on chip variant. + Each child node is defined using the standard binding for regulators and + the optional regulator properties defined below. + + fsl,mc13xxx-uses-adc: + type: boolean + description: Indicate the ADC is being used + + fsl,mc13xxx-uses-codec: + type: boolean + description: Indicate the Audio Codec is being used + + fsl,mc13xxx-uses-rtc: + type: boolean + description: Indicate the RTC is being used + + fsl,mc13xxx-uses-touch: + type: boolean + description: Indicate the touchscreen controller is being used + +required: + - compatible + - reg + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,mc13783 + then: + properties: + leds: + properties: + led-control: + minItems: 6 + maxItems: 6 + regulators: + patternProperties: + "^gpo[1-4]|pwgt[12]spi|sw[12][ab]|sw3|vaudio|vcam|vdig|vesim|vgen|viohi|violo|vmmc[12]|vrf[12]|vrfbg|vrfcp|vrfdig|vrfref|vsim|vvib$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: fsl,mc13892 + then: + properties: + leds: + properties: + led-control: + minItems: 4 + maxItems: 4 + regulators: + patternProperties: + "^gpo[1-4]|pwgt[12]spi|sw[1-4]|swbst|vaudio|vcam|vcoincell|vdig|vgen[1-3]|viohi|vpll|vsd|vusb|vusb2|vvideo$": + type: object + $ref: /schemas/regulator/regulator.yaml# + + unevaluatedProperties: false + + - if: + properties: + compatible: + contains: + const: fsl,mc34708 + then: + properties: + buttons: + patternProperties: + "^onkey@[0-2]$": + properties: + reg: + maximum: 1 + leds: + properties: + led-control: + minItems: 1 + maxItems: 1 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/leds/common.h> + + spi { + #address-cells = <1>; + #size-cells = <0>; + + pmic: mc13892@0 { + compatible = "fsl,mc13892"; + reg = <0>; + spi-max-frequency = <1000000>; + spi-cs-high; + interrupt-parent = <&gpio0>; + interrupts = <8 IRQ_TYPE_LEVEL_HIGH>; + fsl,mc13xxx-uses-rtc; + fsl,mc13xxx-uses-adc; + + buttons { + #address-cells = <1>; + #size-cells = <0>; + + onkey@0 { + reg = <0>; + debounce-delay-ms = <30>; + active-low; + fsl,enable-reset; + }; + }; + + leds { + #address-cells = <1>; + #size-cells = <0>; + led-control = <0x000 0x000 0x0e0 0x000>; + + sysled@3 { + reg = <3>; + label = "system:red:live"; + linux,default-trigger = "heartbeat"; + }; + }; + + regulators { + sw1_reg: sw1 { + regulator-min-microvolt = <600000>; + regulator-max-microvolt = <1375000>; + regulator-boot-on; + regulator-always-on; + }; + + sw2_reg: sw2 { + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1850000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/maxim,max7360.yaml b/Documentation/devicetree/bindings/mfd/maxim,max7360.yaml new file mode 100644 index 000000000000..3fc920c8639d --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/maxim,max7360.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/maxim,max7360.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim MAX7360 Keypad, Rotary encoder, PWM and GPIO controller + +maintainers: + - Kamel Bouhara <kamel.bouhara@bootlin.com> + - Mathieu Dubois-Briand <mathieu.dubois-briand@bootlin.com> + +description: | + Maxim MAX7360 device, with following functions: + - keypad controller + - rotary controller + - GPIO and GPO controller + - PWM controller + + https://www.analog.com/en/products/max7360.html + +allOf: + - $ref: /schemas/input/matrix-keymap.yaml# + - $ref: /schemas/input/input.yaml# + +properties: + compatible: + enum: + - maxim,max7360 + + reg: + maxItems: 1 + + interrupts: + maxItems: 2 + + interrupt-names: + items: + - const: inti + - const: intk + + keypad-debounce-delay-ms: + description: Keypad debounce delay in ms + minimum: 9 + maximum: 40 + default: 9 + + rotary-debounce-delay-ms: + description: Rotary encoder debounce delay in ms + minimum: 0 + maximum: 15 + default: 0 + + linux,axis: + $ref: /schemas/input/rotary-encoder.yaml#/properties/linux,axis + + rotary-encoder,relative-axis: + $ref: /schemas/types.yaml#/definitions/flag + description: + Register a relative axis rather than an absolute one. + + rotary-encoder,steps: + $ref: /schemas/types.yaml#/definitions/uint32 + default: 24 + description: + Number of steps in a full turnaround of the + encoder. Only relevant for absolute axis. Defaults to 24 which is a + typical value for such devices. + + rotary-encoder,rollover: + $ref: /schemas/types.yaml#/definitions/flag + description: + Automatic rollover when the rotary value becomes + greater than the specified steps or smaller than 0. For absolute axis only. + + "#pwm-cells": + const: 3 + + gpio: + $ref: /schemas/gpio/maxim,max7360-gpio.yaml# + description: + PORT0 to PORT7 general purpose input/output pins configuration. + + gpo: + $ref: /schemas/gpio/maxim,max7360-gpio.yaml# + description: > + COL2 to COL7 general purpose output pins configuration. Allows to use + unused keypad columns as outputs. + + The MAX7360 has 8 column lines and 6 of them can be used as GPOs. GPIOs + numbers used for this gpio-controller node do correspond to the column + numbers: values 0 and 1 are never valid, values from 2 to 7 might be valid + depending on the value of the keypad,num-column property. + +patternProperties: + '-pins$': + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: /schemas/pinctrl/pincfg-node.yaml + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: '^(PORT[0-7]|ROTARY)$' + minItems: 1 + maxItems: 8 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [gpio, pwm, rotary] + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - interrupt-names + - linux,keymap + - linux,axis + - "#pwm-cells" + - gpio + - gpo + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/input/input.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + io-expander@38 { + compatible = "maxim,max7360"; + reg = <0x38>; + + interrupt-parent = <&gpio1>; + interrupts = <23 IRQ_TYPE_LEVEL_LOW>, + <24 IRQ_TYPE_LEVEL_LOW>; + interrupt-names = "inti", "intk"; + + keypad,num-rows = <8>; + keypad,num-columns = <4>; + linux,keymap = < + MATRIX_KEY(0x00, 0x00, KEY_F5) + MATRIX_KEY(0x01, 0x00, KEY_F4) + MATRIX_KEY(0x02, 0x01, KEY_F6) + >; + keypad-debounce-delay-ms = <10>; + autorepeat; + + rotary-debounce-delay-ms = <2>; + linux,axis = <0>; /* REL_X */ + rotary-encoder,relative-axis; + + #pwm-cells = <3>; + + max7360_gpio: gpio { + compatible = "maxim,max7360-gpio"; + + gpio-controller; + #gpio-cells = <2>; + maxim,constant-current-disable = <0x06>; + + interrupt-controller; + #interrupt-cells = <0x2>; + }; + + max7360_gpo: gpo { + compatible = "maxim,max7360-gpo"; + + gpio-controller; + #gpio-cells = <2>; + }; + + backlight_pins: backlight-pins { + pins = "PORT2"; + function = "pwm"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/mc13xxx.txt b/Documentation/devicetree/bindings/mfd/mc13xxx.txt deleted file mode 100644 index 8261ea73278a..000000000000 --- a/Documentation/devicetree/bindings/mfd/mc13xxx.txt +++ /dev/null @@ -1,156 +0,0 @@ -* Freescale MC13783/MC13892 Power Management Integrated Circuit (PMIC) - -Required properties: -- compatible : Should be "fsl,mc13783" or "fsl,mc13892" - -Optional properties: -- fsl,mc13xxx-uses-adc : Indicate the ADC is being used -- fsl,mc13xxx-uses-codec : Indicate the Audio Codec is being used -- fsl,mc13xxx-uses-rtc : Indicate the RTC is being used -- fsl,mc13xxx-uses-touch : Indicate the touchscreen controller is being used - -Sub-nodes: -- codec: Contain the Audio Codec node. - - adc-port: Contain PMIC SSI port number used for ADC. - - dac-port: Contain PMIC SSI port number used for DAC. -- leds : Contain the led nodes and initial register values in property - "led-control". Number of register depends of used IC, for MC13783 is 6, - for MC13892 is 4, for MC34708 is 1. See datasheet for bits definitions of - these registers. - - #address-cells: Must be 1. - - #size-cells: Must be 0. - Each led node should contain "reg", which used as LED ID (described below). - Optional properties "label" and "linux,default-trigger" is described in - Documentation/devicetree/bindings/leds/common.txt. -- regulators : Contain the regulator nodes. The regulators are bound using - their names as listed below with their registers and bits for enabling. - -MC13783 LED IDs: - 0 : Main display - 1 : AUX display - 2 : Keypad - 3 : Red 1 - 4 : Green 1 - 5 : Blue 1 - 6 : Red 2 - 7 : Green 2 - 8 : Blue 2 - 9 : Red 3 - 10 : Green 3 - 11 : Blue 3 - -MC13892 LED IDs: - 0 : Main display - 1 : AUX display - 2 : Keypad - 3 : Red - 4 : Green - 5 : Blue - -MC34708 LED IDs: - 0 : Charger Red - 1 : Charger Green - -MC13783 regulators: - sw1a : regulator SW1A (register 24, bit 0) - sw1b : regulator SW1B (register 25, bit 0) - sw2a : regulator SW2A (register 26, bit 0) - sw2b : regulator SW2B (register 27, bit 0) - sw3 : regulator SW3 (register 29, bit 20) - vaudio : regulator VAUDIO (register 32, bit 0) - viohi : regulator VIOHI (register 32, bit 3) - violo : regulator VIOLO (register 32, bit 6) - vdig : regulator VDIG (register 32, bit 9) - vgen : regulator VGEN (register 32, bit 12) - vrfdig : regulator VRFDIG (register 32, bit 15) - vrfref : regulator VRFREF (register 32, bit 18) - vrfcp : regulator VRFCP (register 32, bit 21) - vsim : regulator VSIM (register 33, bit 0) - vesim : regulator VESIM (register 33, bit 3) - vcam : regulator VCAM (register 33, bit 6) - vrfbg : regulator VRFBG (register 33, bit 9) - vvib : regulator VVIB (register 33, bit 11) - vrf1 : regulator VRF1 (register 33, bit 12) - vrf2 : regulator VRF2 (register 33, bit 15) - vmmc1 : regulator VMMC1 (register 33, bit 18) - vmmc2 : regulator VMMC2 (register 33, bit 21) - gpo1 : regulator GPO1 (register 34, bit 6) - gpo2 : regulator GPO2 (register 34, bit 8) - gpo3 : regulator GPO3 (register 34, bit 10) - gpo4 : regulator GPO4 (register 34, bit 12) - pwgt1spi : regulator PWGT1SPI (register 34, bit 15) - pwgt2spi : regulator PWGT2SPI (register 34, bit 16) - -MC13892 regulators: - vcoincell : regulator VCOINCELL (register 13, bit 23) - sw1 : regulator SW1 (register 24, bit 0) - sw2 : regulator SW2 (register 25, bit 0) - sw3 : regulator SW3 (register 26, bit 0) - sw4 : regulator SW4 (register 27, bit 0) - swbst : regulator SWBST (register 29, bit 20) - vgen1 : regulator VGEN1 (register 32, bit 0) - viohi : regulator VIOHI (register 32, bit 3) - vdig : regulator VDIG (register 32, bit 9) - vgen2 : regulator VGEN2 (register 32, bit 12) - vpll : regulator VPLL (register 32, bit 15) - vusb2 : regulator VUSB2 (register 32, bit 18) - vgen3 : regulator VGEN3 (register 33, bit 0) - vcam : regulator VCAM (register 33, bit 6) - vvideo : regulator VVIDEO (register 33, bit 12) - vaudio : regulator VAUDIO (register 33, bit 15) - vsd : regulator VSD (register 33, bit 18) - gpo1 : regulator GPO1 (register 34, bit 6) - gpo2 : regulator GPO2 (register 34, bit 8) - gpo3 : regulator GPO3 (register 34, bit 10) - gpo4 : regulator GPO4 (register 34, bit 12) - pwgt1spi : regulator PWGT1SPI (register 34, bit 15) - pwgt2spi : regulator PWGT2SPI (register 34, bit 16) - vusb : regulator VUSB (register 50, bit 3) - - The bindings details of individual regulator device can be found in: - Documentation/devicetree/bindings/regulator/regulator.txt - -Examples: - -ecspi@70010000 { /* ECSPI1 */ - cs-gpios = <&gpio4 24 0>, /* GPIO4_24 */ - <&gpio4 25 0>; /* GPIO4_25 */ - - pmic: mc13892@0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,mc13892"; - spi-max-frequency = <6000000>; - reg = <0>; - interrupt-parent = <&gpio0>; - interrupts = <8>; - - leds { - #address-cells = <1>; - #size-cells = <0>; - led-control = <0x000 0x000 0x0e0 0x000>; - - sysled@3 { - reg = <3>; - label = "system:red:live"; - linux,default-trigger = "heartbeat"; - }; - }; - - regulators { - sw1_reg: mc13892__sw1 { - regulator-min-microvolt = <600000>; - regulator-max-microvolt = <1375000>; - regulator-boot-on; - regulator-always-on; - }; - - sw2_reg: mc13892__sw2 { - regulator-min-microvolt = <900000>; - regulator-max-microvolt = <1850000>; - regulator-boot-on; - regulator-always-on; - }; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml b/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml index 877078ac172f..5454d9403cad 100644 --- a/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml +++ b/Documentation/devicetree/bindings/mfd/qnap,ts433-mcu.yaml @@ -16,8 +16,12 @@ description: properties: compatible: enum: + - qnap,ts233-mcu - qnap,ts433-mcu + nvmem-layout: + $ref: /schemas/nvmem/layouts/nvmem-layout.yaml + patternProperties: "^fan-[0-9]+$": $ref: /schemas/hwmon/fan-common.yaml# diff --git a/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml new file mode 100644 index 000000000000..c6593ac6ef6a --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/spacemit,p1.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/spacemit,p1.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT P1 Power Management Integrated Circuit + +maintainers: + - Troy Mitchell <troy.mitchell@linux.spacemit.com> + +description: + P1 is an I2C-controlled PMIC produced by SpacemiT. It implements six + constant-on-time buck converters and twelve low-dropout regulators. + It also contains a load switch, watchdog timer, real-time clock, eight + 12-bit ADC channels, and six GPIOs. Additional details are available + in the "Power Stone/P1" section at the following link. + https://developer.spacemit.com/documentation + +properties: + compatible: + const: spacemit,p1 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + vin-supply: + description: Input supply phandle. + + regulators: + type: object + + patternProperties: + "^(buck[1-6]|aldo[1-4]|dldo[1-7])$": + type: object + $ref: /schemas/regulator/regulator.yaml# + unevaluatedProperties: false + + unevaluatedProperties: false + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@41 { + compatible = "spacemit,p1"; + reg = <0x41>; + interrupts = <64>; + + regulators { + buck1 { + regulator-name = "buck1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3450000>; + regulator-ramp-delay = <5000>; + regulator-always-on; + }; + + aldo1 { + regulator-name = "aldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + + dldo1 { + regulator-name = "dldo1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3400000>; + regulator-boot-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/mfd/syscon.yaml b/Documentation/devicetree/bindings/mfd/syscon.yaml index 27672adeb1fe..657c38175fba 100644 --- a/Documentation/devicetree/bindings/mfd/syscon.yaml +++ b/Documentation/devicetree/bindings/mfd/syscon.yaml @@ -79,6 +79,7 @@ select: - marvell,armada-3700-cpu-misc - marvell,armada-3700-nb-pm - marvell,armada-3700-avs + - marvell,armada-3700-usb2-host-device-misc - marvell,armada-3700-usb2-host-misc - marvell,dove-global-config - mediatek,mt2701-pctl-a-syscfg @@ -90,6 +91,7 @@ select: - mediatek,mt8173-pctl-a-syscfg - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy @@ -185,6 +187,7 @@ properties: - marvell,armada-3700-cpu-misc - marvell,armada-3700-nb-pm - marvell,armada-3700-avs + - marvell,armada-3700-usb2-host-device-misc - marvell,armada-3700-usb2-host-misc - marvell,dove-global-config - mediatek,mt2701-pctl-a-syscfg @@ -197,6 +200,7 @@ properties: - mediatek,mt8365-infracfg-nao - mediatek,mt8365-syscfg - microchip,lan966x-cpu-syscon + - microchip,mpfs-control-scb - microchip,mpfs-sysreg-scb - microchip,sam9x60-sfr - microchip,sama7d65-ddr3phy diff --git a/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml new file mode 100644 index 000000000000..ba14663c9266 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/ti,bq25703a.yaml @@ -0,0 +1,117 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/ti,bq25703a.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: BQ25703A Charger Manager/Buck/Boost Converter + +maintainers: + - Chris Morgan <macromorgan@hotmail.com> + +allOf: + - $ref: /schemas/power/supply/power-supply.yaml# + +properties: + compatible: + const: ti,bq25703a + + reg: + const: 0x6b + + input-current-limit-microamp: + description: + Maximum total input current allowed used for both charging and + powering the device. + minimum: 50000 + maximum: 6400000 + default: 3250000 + + interrupts: + maxItems: 1 + + monitored-battery: + description: + A minimum of constant-charge-current-max-microamp, + constant-charge-voltage-max-microvolt, and + voltage-min-design-microvolt are required. + + regulators: + type: object + additionalProperties: false + description: + Boost converter regulator output of bq257xx. + + properties: + vbus: + type: object + $ref: /schemas/regulator/regulator.yaml + additionalProperties: false + + properties: + regulator-name: true + regulator-min-microamp: + minimum: 0 + maximum: 6350000 + regulator-max-microamp: + minimum: 0 + maximum: 6350000 + regulator-min-microvolt: + minimum: 4480000 + maximum: 20800000 + regulator-max-microvolt: + minimum: 4480000 + maximum: 20800000 + enable-gpios: + description: + The BQ25703 may require both a register write and a GPIO + toggle to enable the boost regulator. + + required: + - regulator-name + - regulator-min-microamp + - regulator-max-microamp + - regulator-min-microvolt + - regulator-max-microvolt + +unevaluatedProperties: false + +required: + - compatible + - reg + - input-current-limit-microamp + - monitored-battery + - power-supplies + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/pinctrl/rockchip.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + bq25703: charger@6b { + compatible = "ti,bq25703a"; + reg = <0x6b>; + input-current-limit-microamp = <5000000>; + interrupt-parent = <&gpio0>; + interrupts = <RK_PD5 IRQ_TYPE_LEVEL_LOW>; + monitored-battery = <&battery>; + power-supplies = <&fusb302>; + + regulators { + usb_otg_vbus: vbus { + enable-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; + regulator-max-microamp = <960000>; + regulator-max-microvolt = <5088000>; + regulator-min-microamp = <512000>; + regulator-min-microvolt = <4992000>; + regulator-name = "usb_otg_vbus"; + }; + }; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml b/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml index ae149eb8593d..ca72786b0e0d 100644 --- a/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,lp87524-q1.yaml @@ -26,7 +26,7 @@ properties: '#gpio-cells': description: The first cell is the pin number. - The second cell is is used to specify flags. + The second cell is used to specify flags. See ../gpio/gpio.txt for more information. const: 2 diff --git a/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml b/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml index 5167d6eb904a..885e33276b1b 100644 --- a/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,lp87561-q1.yaml @@ -26,7 +26,7 @@ properties: '#gpio-cells': description: The first cell is the pin number. - The second cell is is used to specify flags. + The second cell is used to specify flags. See ../gpio/gpio.txt for more information. const: 2 diff --git a/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml b/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml index eca430edf608..2b5b54aa6c73 100644 --- a/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,lp87565-q1.yaml @@ -28,7 +28,7 @@ properties: '#gpio-cells': description: The first cell is the pin number. - The second cell is is used to specify flags. + The second cell is used to specify flags. See ../gpio/gpio.txt for more information. const: 2 diff --git a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml index a48cb00afe43..ca17fbdea691 100644 --- a/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,tps6594.yaml @@ -41,6 +41,7 @@ properties: system-power-controller: true gpio-controller: true + gpio-line-names: true '#gpio-cells': const: 2 diff --git a/Documentation/devicetree/bindings/mfd/ti,twl.yaml b/Documentation/devicetree/bindings/mfd/ti,twl.yaml index f162ab60c09b..776b04e182cb 100644 --- a/Documentation/devicetree/bindings/mfd/ti,twl.yaml +++ b/Documentation/devicetree/bindings/mfd/ti,twl.yaml @@ -11,9 +11,9 @@ maintainers: description: | The TWLs are Integrated Power Management Chips. - Some version might contain much more analog function like + Some versions might contain much more analog functions like USB transceiver or Audio amplifier. - These chips are connected to an i2c bus. + These chips are connected to an I2C bus. allOf: - if: @@ -49,33 +49,14 @@ allOf: ti,retain-on-reset: false properties: - madc: - type: object - $ref: /schemas/iio/adc/ti,twl4030-madc.yaml - unevaluatedProperties: false - charger: - type: object $ref: /schemas/power/supply/twl4030-charger.yaml unevaluatedProperties: false - pwrbutton: - type: object - additionalProperties: false - properties: - compatible: - const: ti,twl4030-pwrbutton - interrupts: - items: - - items: - const: 8 - - watchdog: - type: object - additionalProperties: false - properties: - compatible: - const: ti,twl4030-wdt + gpadc: false + + usb-comparator: false + - if: properties: compatible: @@ -106,15 +87,30 @@ allOf: properties: charger: - type: object - properties: - compatible: - const: ti,twl6030-charger + $ref: /schemas/power/supply/ti,twl6030-charger.yaml + unevaluatedProperties: false + gpadc: - type: object properties: compatible: const: ti,twl6030-gpadc + + pwrbutton: false + + madc: false + + watchdog: false + + audio: false + + keypad: false + + twl4030-usb: false + + gpio: false + + power: false + - if: properties: compatible: @@ -142,23 +138,36 @@ allOf: properties: charger: - type: object - properties: - compatible: - items: - - const: ti,twl6032-charger - - const: ti,twl6030-charger + $ref: /schemas/power/supply/ti,twl6030-charger.yaml + unevaluatedProperties: false + gpadc: - type: object properties: compatible: const: ti,twl6032-gpadc + pwrbutton: false + + madc: false + + watchdog: false + + audio: false + + keypad: false + + twl4030-usb: false + + gpio: false + + power: false + properties: compatible: - description: - TWL4030 for integrated power-management/audio CODEC device used in OMAP3 - based boards + description: > + TWL4030 for integrated power-management/audio CODEC device used in + OMAP3 based boards. + TWL6030/32 for integrated power-management used in OMAP4 based boards enum: - ti,twl4030 @@ -181,28 +190,221 @@ properties: "#clock-cells": const: 1 + clocks: + maxItems: 1 + + clock-names: + const: fck + charger: type: object - additionalProperties: true + properties: compatible: true + required: - compatible rtc: type: object additionalProperties: false + properties: compatible: const: ti,twl4030-rtc interrupts: maxItems: 1 + madc: + type: object + $ref: /schemas/iio/adc/ti,twl4030-madc.yaml + unevaluatedProperties: false + + pwrbutton: + type: object + additionalProperties: false + + properties: + compatible: + const: ti,twl4030-pwrbutton + interrupts: + items: + - items: + const: 8 + + watchdog: + type: object + additionalProperties: false + + properties: + compatible: + const: ti,twl4030-wdt + + audio: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-audio + + required: + - compatible + + keypad: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-keypad + + required: + - compatible + + twl4030-usb: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-usb + + required: + - compatible + + gpio: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl4030-gpio + + required: + - compatible + + power: + type: object + additionalProperties: false + description: > + The power management module inside the TWL4030 provides several + facilities to control the power resources, including power scripts. + + For now, the binding only supports the complete shutdown of the + system after poweroff. + + Board-specific compatible strings may be used for platform-specific + power configurations. + + A board-specific compatible string (e.g., ti,twl4030-power-omap3-evm) + may be paired with a generic fallback (generally for power saving mode). + + properties: + compatible: + oneOf: + # Case 1: A single compatible string is provided. + - enum: + - ti,twl4030-power + - ti,twl4030-power-reset + - ti,twl4030-power-idle + - ti,twl4030-power-idle-osc-off + - ti,twl4030-power-omap3-sdp + - ti,twl4030-power-omap3-ldp + - ti,twl4030-power-omap3-evm + + # Case 2: The specific, valid fallback for 'idle-osc-off'. + - items: + - const: ti,twl4030-power-idle-osc-off + - const: ti,twl4030-power-idle + + # Case 3: The specific, valid fallback for 'omap3-evm'. + - items: + - const: ti,twl4030-power-omap3-evm + - const: ti,twl4030-power-idle + + ti,system-power-controller: + type: boolean + deprecated: true + description: > + DEPRECATED. The standard 'system-power-controller' + property on the parent node should be used instead. + + ti,use_poweroff: + type: boolean + deprecated: true + description: DEPRECATED, to be removed. + + required: + - compatible + + gpadc: + type: object + $ref: /schemas/iio/adc/ti,twl6030-gpadc.yaml + unevaluatedProperties: false + + properties: + compatible: true + + usb-comparator: + type: object + additionalProperties: true + + properties: + compatible: + const: ti,twl6030-usb + + required: + - compatible + + pwm: + type: object + $ref: /schemas/pwm/pwm.yaml# + unevaluatedProperties: false + description: + PWM controllers (PWM1 and PWM2 on TWL4030, PWM0 and PWM1 on TWL6030/32). + + properties: + compatible: + enum: + - ti,twl4030-pwm + - ti,twl6030-pwm + + '#pwm-cells': + const: 2 + + required: + - compatible + - '#pwm-cells' + + pwmled: + type: object + $ref: /schemas/pwm/pwm.yaml# + unevaluatedProperties: false + description: > + PWM controllers connected to LED terminals (PWMA and PWMB on TWL4030. + + LED PWM on TWL6030/32, mainly used as charging indicator LED). + + properties: + compatible: + enum: + - ti,twl4030-pwmled + - ti,twl6030-pwmled + + '#pwm-cells': + const: 2 + + required: + - compatible + - '#pwm-cells' + patternProperties: "^regulator-": type: object unevaluatedProperties: false $ref: /schemas/regulator/regulator.yaml + properties: compatible: true regulator-initial-mode: @@ -211,12 +413,13 @@ patternProperties: # with low power consumption with low load current capability - 0x0e # Active mode, the regulator can deliver its nominal output # voltage with full-load current capability + ti,retain-on-reset: - description: - Does not turn off the supplies during warm - reset. Could be needed for VMMC, as TWL6030 - reset sequence for this signal does not comply - with the SD specification. + description: > + Does not turn off the supplies during warm reset. + + Could be needed for VMMC, as TWL6030 reset sequence for + this signal does not comply with the SD specification. type: boolean unevaluatedProperties: false @@ -271,6 +474,16 @@ examples: compatible = "ti,twl6030-vmmc"; ti,retain-on-reset; }; + + pwm { + compatible = "ti,twl6030-pwm"; + #pwm-cells = <2>; + }; + + pwmled { + compatible = "ti,twl6030-pwmled"; + #pwm-cells = <2>; + }; }; }; @@ -325,6 +538,20 @@ examples: watchdog { compatible = "ti,twl4030-wdt"; }; + + power { + compatible = "ti,twl4030-power"; + }; + + pwm { + compatible = "ti,twl4030-pwm"; + #pwm-cells = <2>; + }; + + pwmled { + compatible = "ti,twl4030-pwmled"; + #pwm-cells = <2>; + }; }; }; ... diff --git a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt b/Documentation/devicetree/bindings/mfd/twl4030-audio.txt deleted file mode 100644 index 414d2ae0adf6..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-audio.txt +++ /dev/null @@ -1,46 +0,0 @@ -Texas Instruments TWL family (twl4030) audio module - -The audio module inside the TWL family consist of an audio codec and a vibra -driver. - -Required properties: -- compatible : must be "ti,twl4030-audio" - -Optional properties, nodes: - -Audio functionality: -- codec { }: Need to be present if the audio functionality is used. Within this - section the following options can be used: -- ti,digimic_delay: Delay need after enabling the digimic to reduce artifacts - from the start of the recorded sample (in ms) --ti,ramp_delay_value: HS ramp delay configuration to reduce pop noise --ti,hs_extmute: Use external mute for HS pop reduction --ti,hs_extmute_gpio: Use external GPIO to control the external mute --ti,offset_cncl_path: Offset cancellation path selection, refer to TRM for the - valid values. - -Vibra functionality -- ti,enable-vibra: Need to be set to <1> if the vibra functionality is used. if - missing or it is 0, the vibra functionality is disabled. - -Example: -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_audio: audio { - compatible = "ti,twl4030-audio"; - - ti,enable-vibra = <1>; - - codec { - ti,ramp_delay_value = <3>; - }; - - }; - }; -}; diff --git a/Documentation/devicetree/bindings/mfd/twl4030-power.txt b/Documentation/devicetree/bindings/mfd/twl4030-power.txt deleted file mode 100644 index 3d19963312ce..000000000000 --- a/Documentation/devicetree/bindings/mfd/twl4030-power.txt +++ /dev/null @@ -1,48 +0,0 @@ -Texas Instruments TWL family (twl4030) reset and power management module - -The power management module inside the TWL family provides several facilities -to control the power resources, including power scripts. For now, the -binding only supports the complete shutdown of the system after poweroff. - -Required properties: -- compatible : must be one of the following - "ti,twl4030-power" - "ti,twl4030-power-reset" - "ti,twl4030-power-idle" - "ti,twl4030-power-idle-osc-off" - -The use of ti,twl4030-power-reset is recommended at least on -3530 that needs a special configuration for warm reset to work. - -When using ti,twl4030-power-idle, the TI recommended configuration -for idle modes is loaded to the tlw4030 PMIC. - -When using ti,twl4030-power-idle-osc-off, the TI recommended -configuration is used with the external oscillator being shut -down during off-idle. Note that this does not work on all boards -depending on how the external oscillator is wired. - -Optional properties: - -- ti,system-power-controller: This indicates that TWL4030 is the - power supply master of the system. With this flag, the chip will - initiate an ACTIVE-to-OFF or SLEEP-to-OFF transition when the - system poweroffs. - -- ti,use_poweroff: Deprecated name for ti,system-power-controller - -Example: -&i2c1 { - clock-frequency = <2600000>; - - twl: twl@48 { - reg = <0x48>; - interrupts = <7>; /* SYS_NIRQ cascaded to intc */ - interrupt-parent = <&intc>; - - twl_power: power { - compatible = "ti,twl4030-power"; - ti,use_poweroff; - }; - }; -}; diff --git a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt b/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt deleted file mode 100644 index f2e2e28b317c..000000000000 --- a/Documentation/devicetree/bindings/misc/aspeed-p2a-ctrl.txt +++ /dev/null @@ -1,46 +0,0 @@ -====================================================================== -Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver -====================================================================== - -The bridge is available on platforms with the VGA enabled on the Aspeed device. -In this case, the host has access to a 64KiB window into all of the BMC's -memory. The BMC can disable this bridge. If the bridge is enabled, the host -has read access to all the regions of memory, however the host only has read -and write access depending on a register controlled by the BMC. - -Required properties: -=================== - - - compatible: must be one of: - - "aspeed,ast2400-p2a-ctrl" - - "aspeed,ast2500-p2a-ctrl" - -Optional properties: -=================== - -- reg: A hint for the memory regions associated with the P2A controller -- memory-region: A phandle to a reserved_memory region to be used for the PCI - to AHB mapping - -The p2a-control node should be the child of a syscon node with the required -property: - -- compatible : Should be one of the following: - "aspeed,ast2400-scu", "syscon", "simple-mfd" - "aspeed,ast2500-scu", "syscon", "simple-mfd" - -Example -=================== - -g4 Example ----------- - -syscon: scu@1e6e2000 { - compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd"; - reg = <0x1e6e2000 0x1a8>; - - p2a: p2a-control { - compatible = "aspeed,ast2400-p2a-ctrl"; - memory-region = <&reserved_memory>; - }; -}; diff --git a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml index eee6be7a7867..493655a38b37 100644 --- a/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml +++ b/Documentation/devicetree/bindings/mmc/brcm,sdhci-brcmstb.yaml @@ -61,7 +61,7 @@ properties: description: Specifies that controller should use auto CMD12 allOf: - - $ref: mmc-controller.yaml# + - $ref: sdhci-common.yaml# - if: properties: clock-names: diff --git a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml index 62087cf920df..f45e592901e2 100644 --- a/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml +++ b/Documentation/devicetree/bindings/mmc/fsl,esdhc.yaml @@ -90,6 +90,7 @@ required: allOf: - $ref: sdhci-common.yaml# + - $ref: mmc-controller-common.yaml# unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml index 9a7235439759..ebde06173578 100644 --- a/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml +++ b/Documentation/devicetree/bindings/mmc/mmc-controller-common.yaml @@ -57,7 +57,7 @@ properties: # latter case. We choose to use the XOR logic for GPIO CD and WP # lines. This means, the two properties are "superimposed," for # example leaving the GPIO_ACTIVE_LOW flag clear and specifying the - # respective *-inverted property property results in a + # respective *-inverted property results in a # double-inversion and actually means the "normal" line polarity is # in effect. wp-inverted: @@ -93,6 +93,14 @@ properties: minimum: 400000 maximum: 384000000 + max-sd-hs-hz: + description: | + Maximum frequency (in Hz) to be used for SD cards operating in + High-Speed (HS) mode. + minimum: 400000 + maximum: 50000000 + default: 50000000 + disable-wp: $ref: /schemas/types.yaml#/definitions/flag description: @@ -264,7 +272,7 @@ properties: mmc-pwrseq-simple.yaml. But now it\'s reused as a tunable delay waiting for I/O signalling and card power supply to be stable, regardless of whether pwrseq-simple is used. Default to 10ms if - no available. + not available. default: 10 supports-cqe: diff --git a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml index e8bd49d46794..27c4060f2f91 100644 --- a/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml +++ b/Documentation/devicetree/bindings/mmc/samsung,exynos-dw-mshc.yaml @@ -31,6 +31,7 @@ properties: - samsung,exynos5433-dw-mshc-smu - samsung,exynos7885-dw-mshc-smu - samsung,exynos850-dw-mshc-smu + - samsung,exynos8890-dw-mshc-smu - samsung,exynos8895-dw-mshc-smu - const: samsung,exynos7-dw-mshc-smu diff --git a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml index 22d1f50c3fd1..594bd174ff21 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-msm.yaml @@ -48,6 +48,7 @@ properties: - qcom,qcs615-sdhci - qcom,qcs8300-sdhci - qcom,qdu1000-sdhci + - qcom,sa8775p-sdhci - qcom,sar2130p-sdhci - qcom,sc7180-sdhci - qcom,sc7280-sdhci diff --git a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml index e7c06032048a..186ce8ff4626 100644 --- a/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml +++ b/Documentation/devicetree/bindings/mmc/sdhci-pxa.yaml @@ -44,12 +44,29 @@ allOf: items: - const: default - const: state_cmd_gpio - pinctrl-0: - description: - Should contain default pinctrl. + minItems: 1 + pinctrl-1: description: Should switch CMD pin to GPIO mode as a high output. + - if: + properties: + compatible: + contains: + const: mrvl,pxav3-mmc + then: + properties: + pinctrl-names: + description: + Optional for increasing stability of the controller at fast bus clocks. + items: + - const: default + - const: state_uhs + minItems: 1 + + pinctrl-1: + description: + Should switch the drive strength of the data pins to high. properties: compatible: @@ -82,6 +99,14 @@ properties: - const: io - const: core + pinctrl-names: true + + pinctrl-0: + description: + Should contain default pinctrl. + + pinctrl-1: true + mrvl,clk-delay-cycles: description: Specify a number of cycles to delay for tuning. $ref: /schemas/types.yaml#/definitions/uint32 diff --git a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml index 76dd97c3fb40..c7644e6586d3 100644 --- a/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml +++ b/Documentation/devicetree/bindings/net/airoha,en7581-npu.yaml @@ -41,9 +41,21 @@ properties: - description: wlan irq line5 memory-region: - maxItems: 1 - description: - Memory used to store NPU firmware binary. + oneOf: + - items: + - description: NPU firmware binary region + - items: + - description: NPU firmware binary region + - description: NPU wlan offload RX buffers region + - description: NPU wlan offload TX buffers region + - description: NPU wlan offload TX packet identifiers region + + memory-region-names: + items: + - const: firmware + - const: pkt + - const: tx-pkt + - const: tx-bufid required: - compatible @@ -79,6 +91,8 @@ examples: <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>; - memory-region = <&npu_binary>; + memory-region = <&npu_firmware>, <&npu_pkt>, <&npu_txpkt>, + <&npu_txbufid>; + memory-region-names = "firmware", "pkt", "tx-pkt", "tx-bufid"; }; }; diff --git a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml index eb26623dab51..d4d8f3a7918e 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun4i-a10-emac.yaml @@ -33,6 +33,15 @@ properties: - items: - description: phandle to SRAM - description: register value for device + dmas: + items: + - description: RX DMA Channel + - description: TX DMA Channel + + dma-names: + items: + - const: rx + - const: tx required: - compatible diff --git a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml index 2ac709a4c472..fc62fb2a68ac 100644 --- a/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml +++ b/Documentation/devicetree/bindings/net/allwinner,sun8i-a83t-emac.yaml @@ -10,6 +10,21 @@ maintainers: - Chen-Yu Tsai <wens@csie.org> - Maxime Ripard <mripard@kernel.org> +# We need a select here so we don't match all nodes with 'snps,dwmac' +select: + properties: + compatible: + contains: + enum: + - allwinner,sun8i-a83t-emac + - allwinner,sun8i-h3-emac + - allwinner,sun8i-r40-gmac + - allwinner,sun8i-v3s-emac + - allwinner,sun50i-a64-emac + - allwinner,sun55i-a523-gmac200 + required: + - compatible + properties: compatible: oneOf: @@ -26,6 +41,9 @@ properties: - allwinner,sun50i-h616-emac0 - allwinner,sun55i-a523-gmac0 - const: allwinner,sun50i-a64-emac + - items: + - const: allwinner,sun55i-a523-gmac200 + - const: snps,dwmac-4.20a reg: maxItems: 1 @@ -37,14 +55,21 @@ properties: const: macirq clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 clock-names: - const: stmmaceth + minItems: 1 + items: + - const: stmmaceth + - const: mbus phy-supply: description: PHY regulator + power-domains: + maxItems: 1 + syscon: $ref: /schemas/types.yaml#/definitions/phandle description: @@ -191,6 +216,42 @@ allOf: - mdio-parent-bus - mdio@1 + - if: + properties: + compatible: + contains: + const: allwinner,sun55i-a523-gmac200 + then: + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + tx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 700 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + rx-internal-delay-ps: + default: 0 + minimum: 0 + maximum: 3100 + multipleOf: 100 + description: + External RGMII PHY TX clock delay chain value in ps. + required: + - power-domains + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + power-domains: false + + unevaluatedProperties: false examples: @@ -323,4 +384,34 @@ examples: }; }; + - | + ethernet@4510000 { + compatible = "allwinner,sun55i-a523-gmac200", + "snps,dwmac-4.20a"; + reg = <0x04510000 0x10000>; + clocks = <&ccu 117>, <&ccu 79>; + clock-names = "stmmaceth", "mbus"; + resets = <&ccu 43>; + reset-names = "stmmaceth"; + interrupts = <0 47 4>; + interrupt-names = "macirq"; + pinctrl-names = "default"; + pinctrl-0 = <&rgmii1_pins>; + power-domains = <&pck600 4>; + syscon = <&syscon>; + phy-handle = <&ext_rgmii_phy_1>; + phy-mode = "rgmii-id"; + snps,fixed-burst; + snps,axi-config = <&gmac1_stmmac_axi_setup>; + + mdio { + compatible = "snps,dwmac-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + ext_rgmii_phy_1: ethernet-phy@1 { + reg = <1>; + }; + }; + }; ... diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml index 3a22d35db778..fc445ad5a1f1 100644 --- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml +++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml @@ -62,6 +62,13 @@ properties: - const: stmmaceth - const: ptp_ref + interrupts: + maxItems: 1 + + interrupt-names: + items: + - const: macirq + iommus: minItems: 1 maxItems: 2 diff --git a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml index 0cd78d71768c..5c91716d1f21 100644 --- a/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/amlogic,meson-dwmac.yaml @@ -149,7 +149,7 @@ properties: - description: The first register range should be the one of the DWMAC controller - description: - The second range is is for the Amlogic specific configuration + The second range is for the Amlogic specific configuration (for example the PRG_ETHERNET register range on Meson8b and newer) interrupts: diff --git a/Documentation/devicetree/bindings/net/apm,xgene-enet.yaml b/Documentation/devicetree/bindings/net/apm,xgene-enet.yaml new file mode 100644 index 000000000000..1c767ef8fcc5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/apm,xgene-enet.yaml @@ -0,0 +1,115 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/apm,xgene-enet.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC Ethernet + +maintainers: + - Iyappan Subramanian <iyappan@os.amperecomputing.com> + - Keyur Chudgar <keyur@os.amperecomputing.com> + - Quan Nguyen <quan@os.amperecomputing.com> + +allOf: + - $ref: ethernet-controller.yaml# + +properties: + compatible: + enum: + - apm,xgene-enet + - apm,xgene1-sgenet + - apm,xgene1-xgenet + - apm,xgene2-sgenet + - apm,xgene2-xgenet + + reg: + maxItems: 3 + + reg-names: + items: + - const: enet_csr + - const: ring_csr + - const: ring_cmd + + clocks: + maxItems: 1 + + dma-coherent: true + + interrupts: + description: An rx and tx completion interrupt pair per queue + minItems: 1 + maxItems: 16 + + channel: + description: Ethernet to CPU start channel number + $ref: /schemas/types.yaml#/definitions/uint32 + + port-id: + description: Port number + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 1 + + tx-delay: + description: Delay value for RGMII bridge TX clock + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 7 + default: 4 + + rx-delay: + description: Delay value for RGMII bridge RX clock + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 7 + default: 2 + + rxlos-gpios: + description: Input GPIO from SFP+ module indicating incoming signal + maxItems: 1 + + mdio: + description: MDIO bus subnode + $ref: mdio.yaml# + unevaluatedProperties: false + + properties: + compatible: + const: apm,xgene-mdio + + required: + - compatible + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + ethernet@17020000 { + compatible = "apm,xgene-enet"; + reg = <0x17020000 0xd100>, + <0x17030000 0x400>, + <0x10000000 0x200>; + reg-names = "enet_csr", "ring_csr", "ring_cmd"; + interrupts = <0x0 0x3c 0x4>; + channel = <0>; + port-id = <0>; + clocks = <&menetclk 0>; + local-mac-address = [00 01 73 00 00 01]; + phy-connection-type = "rgmii"; + phy-handle = <&menetphy>; + + mdio { + compatible = "apm,xgene-mdio"; + #address-cells = <1>; + #size-cells = <0>; + + menetphy: ethernet-phy@3 { + compatible = "ethernet-phy-id001c.c915"; + reg = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml b/Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml new file mode 100644 index 000000000000..470fb5f7f7b5 --- /dev/null +++ b/Documentation/devicetree/bindings/net/apm,xgene-mdio-rgmii.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/apm,xgene-mdio-rgmii.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC MDIO + +maintainers: + - Iyappan Subramanian <iyappan@os.amperecomputing.com> + - Keyur Chudgar <keyur@os.amperecomputing.com> + - Quan Nguyen <quan@os.amperecomputing.com> + +allOf: + - $ref: mdio.yaml# + +properties: + compatible: + enum: + - apm,xgene-mdio-rgmii + - apm,xgene-mdio-xfi + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + +unevaluatedProperties: false + +required: + - compatible + - reg + - clocks + +examples: + - | + mdio@17020000 { + compatible = "apm,xgene-mdio-rgmii"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x17020000 0xd100>; + clocks = <&menetclk 0>; + + phy@3 { + reg = <0x3>; + }; + phy@4 { + reg = <0x4>; + }; + phy@5 { + reg = <0x5>; + }; + }; diff --git a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt b/Documentation/devicetree/bindings/net/apm-xgene-enet.txt deleted file mode 100644 index f591ab782dbc..000000000000 --- a/Documentation/devicetree/bindings/net/apm-xgene-enet.txt +++ /dev/null @@ -1,91 +0,0 @@ -APM X-Gene SoC Ethernet nodes - -Ethernet nodes are defined to describe on-chip ethernet interfaces in -APM X-Gene SoC. - -Required properties for all the ethernet interfaces: -- compatible: Should state binding information from the following list, - - "apm,xgene-enet": RGMII based 1G interface - - "apm,xgene1-sgenet": SGMII based 1G interface - - "apm,xgene1-xgenet": XFI based 10G interface -- reg: Address and length of the register set for the device. It contains the - information of registers in the same order as described by reg-names -- reg-names: Should contain the register set names - - "enet_csr": Ethernet control and status register address space - - "ring_csr": Descriptor ring control and status register address space - - "ring_cmd": Descriptor ring command register address space -- interrupts: Two interrupt specifiers can be specified. - - First is the Rx interrupt. This irq is mandatory. - - Second is the Tx completion interrupt. - This is supported only on SGMII based 1GbE and 10GbE interfaces. -- channel: Ethernet to CPU, start channel (prefetch buffer) number - - Must map to the first irq and irqs must be sequential -- port-id: Port number (0 or 1) -- clocks: Reference to the clock entry. -- local-mac-address: MAC address assigned to this device -- phy-connection-type: Interface type between ethernet device and PHY device - -Required properties for ethernet interfaces that have external PHY: -- phy-handle: Reference to a PHY node connected to this device - -- mdio: Device tree subnode with the following required properties: - - compatible: Must be "apm,xgene-mdio". - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - For the phy on the mdio bus, there must be a node with the following fields: - - compatible: PHY identifier. Please refer ./phy.txt for the format. - - reg: The ID number for the phy. - -Optional properties: -- status: Should be "ok" or "disabled" for enabled/disabled. Default is "ok". -- tx-delay: Delay value for RGMII bridge TX clock. - Valid values are between 0 to 7, that maps to - 417, 717, 1020, 1321, 1611, 1913, 2215, 2514 ps - Default value is 4, which corresponds to 1611 ps -- rx-delay: Delay value for RGMII bridge RX clock. - Valid values are between 0 to 7, that maps to - 273, 589, 899, 1222, 1480, 1806, 2147, 2464 ps - Default value is 2, which corresponds to 899 ps -- rxlos-gpios: Input gpio from SFP+ module to indicate availability of - incoming signal. - - -Example: - menetclk: menetclk { - compatible = "apm,xgene-device-clock"; - clock-output-names = "menetclk"; - status = "ok"; - }; - - menet: ethernet@17020000 { - compatible = "apm,xgene-enet"; - status = "disabled"; - reg = <0x0 0x17020000 0x0 0xd100>, - <0x0 0x17030000 0x0 0x400>, - <0x0 0x10000000 0x0 0x200>; - reg-names = "enet_csr", "ring_csr", "ring_cmd"; - interrupts = <0x0 0x3c 0x4>; - port-id = <0>; - clocks = <&menetclk 0>; - local-mac-address = [00 01 73 00 00 01]; - phy-connection-type = "rgmii"; - phy-handle = <&menetphy>; - mdio { - compatible = "apm,xgene-mdio"; - #address-cells = <1>; - #size-cells = <0>; - menetphy: menetphy@3 { - compatible = "ethernet-phy-id001c.c915"; - reg = <0x3>; - }; - - }; - }; - -/* Board-specific peripheral configurations */ -&menet { - tx-delay = <4>; - rx-delay = <2>; - status = "ok"; -}; diff --git a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt b/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt deleted file mode 100644 index 78722d74cea8..000000000000 --- a/Documentation/devicetree/bindings/net/apm-xgene-mdio.txt +++ /dev/null @@ -1,37 +0,0 @@ -APM X-Gene SoC MDIO node - -MDIO node is defined to describe on-chip MDIO controller. - -Required properties: - - compatible: Must be "apm,xgene-mdio-rgmii" or "apm,xgene-mdio-xfi" - - #address-cells: Must be <1>. - - #size-cells: Must be <0>. - - reg: Address and length of the register set - - clocks: Reference to the clock entry - -For the phys on the mdio bus, there must be a node with the following fields: - - compatible: PHY identifier. Please refer ./phy.txt for the format. - - reg: The ID number for the phy. - -Example: - - mdio: mdio@17020000 { - compatible = "apm,xgene-mdio-rgmii"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x17020000 0x0 0xd100>; - clocks = <&menetclk 0>; - }; - - /* Board-specific peripheral configurations */ - &mdio { - menetphy: phy@3 { - reg = <0x3>; - }; - sgenet0phy: phy@4 { - reg = <0x4>; - }; - sgenet1phy: phy@5 { - reg = <0x5>; - }; - }; diff --git a/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml b/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml index 37cb39a3a62e..fd78258d71b4 100644 --- a/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml +++ b/Documentation/devicetree/bindings/net/bluetooth/brcm,bcm4377-bluetooth.yaml @@ -23,6 +23,7 @@ properties: - pci14e4,5fa0 # BCM4377 - pci14e4,5f69 # BCM4378 - pci14e4,5f71 # BCM4387 + - pci14e4,5f72 # BCM4388 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt b/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt deleted file mode 100644 index 284cddb3118e..000000000000 --- a/Documentation/devicetree/bindings/net/brcm,bcm7445-switch-v4.0.txt +++ /dev/null @@ -1,50 +0,0 @@ -* Broadcom Starfighter 2 integrated switch - -See dsa/brcm,bcm7445-switch-v4.0.yaml for the documentation. - -*Deprecated* binding required properties: - -- dsa,mii-bus: phandle to the MDIO bus controller, see dsa/dsa.txt -- dsa,ethernet: phandle to the CPU network interface controller, see dsa/dsa.txt -- #address-cells: must be 2, see dsa/dsa.txt - -Example using the old DSA DeviceTree binding: - -switch_top@f0b00000 { - compatible = "simple-bus"; - #size-cells = <1>; - #address-cells = <1>; - ranges = <0 0xf0b00000 0x40804>; - - ethernet_switch@0 { - compatible = "brcm,bcm7445-switch-v4.0"; - #size-cells = <0>; - #address-cells = <2>; - reg = <0x0 0x40000 - 0x40000 0x110 - 0x40340 0x30 - 0x40380 0x30 - 0x40400 0x34 - 0x40600 0x208>; - interrupts = <0 0x18 0 - 0 0x19 0>; - brcm,num-gphy = <1>; - brcm,num-rgmii-ports = <2>; - brcm,fcb-pause-override; - brcm,acb-packets-inflight; - - ... - switch@0 { - reg = <0 0>; - #size-cells = <0>; - #address-cells = <1>; - - port@0 { - label = "gphy"; - reg = <0>; - brcm,use-bcm-hdr; - }; - ... - }; - }; -}; diff --git a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml index c4887522e8fe..61ef60d8f1c7 100644 --- a/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml +++ b/Documentation/devicetree/bindings/net/can/bosch,m_can.yaml @@ -50,6 +50,9 @@ properties: - const: hclk - const: cclk + resets: + maxItems: 1 + bosch,mram-cfg: description: | Message RAM configuration data. diff --git a/Documentation/devicetree/bindings/net/cdns,macb.yaml b/Documentation/devicetree/bindings/net/cdns,macb.yaml index 559d0f733e7e..1029786a855c 100644 --- a/Documentation/devicetree/bindings/net/cdns,macb.yaml +++ b/Documentation/devicetree/bindings/net/cdns,macb.yaml @@ -54,6 +54,7 @@ properties: - cdns,np4-macb # NP4 SoC devices - microchip,sama7g5-emac # Microchip SAMA7G5 ethernet interface - microchip,sama7g5-gem # Microchip SAMA7G5 gigabit ethernet interface + - raspberrypi,rp1-gem # Raspberry Pi RP1 gigabit ethernet interface - sifive,fu540-c000-gem # SiFive FU540-C000 SoC - cdns,emac # Generic - cdns,gem # Generic @@ -85,7 +86,7 @@ properties: items: - enum: [ ether_clk, hclk, pclk ] - enum: [ hclk, pclk ] - - const: tx_clk + - enum: [ tx_clk, tsu_clk ] - enum: [ rx_clk, tsu_clk ] - const: tsu_clk diff --git a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml index eb4607460db7..a8c8009414ae 100644 --- a/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml +++ b/Documentation/devicetree/bindings/net/dsa/microchip,ksz.yaml @@ -10,9 +10,6 @@ maintainers: - Marek Vasut <marex@denx.de> - Woojung Huh <Woojung.Huh@microchip.com> -allOf: - - $ref: /schemas/spi/spi-peripheral-props.yaml# - properties: # See Documentation/devicetree/bindings/net/dsa/dsa.yaml for a list of additional # required and optional properties. @@ -37,6 +34,13 @@ properties: - microchip,ksz8567 - microchip,lan9646 + pinctrl-names: + items: + - const: default + - const: reset + description: + Used during reset for strap configuration. + reset-gpios: description: Should be a gpio specifier for a reset line. @@ -107,38 +111,53 @@ required: - compatible - reg -if: - not: - properties: - compatible: - enum: - - microchip,ksz8863 - - microchip,ksz8873 -then: - $ref: dsa.yaml#/$defs/ethernet-ports -else: - patternProperties: - "^(ethernet-)?ports$": +allOf: + - $ref: /schemas/spi/spi-peripheral-props.yaml# + + - if: + not: + properties: + compatible: + enum: + - microchip,ksz8863 + - microchip,ksz8873 + then: + $ref: dsa.yaml#/$defs/ethernet-ports + else: patternProperties: - "^(ethernet-)?port@[0-2]$": - $ref: dsa-port.yaml# - unevaluatedProperties: false - properties: - microchip,rmii-clk-internal: - $ref: /schemas/types.yaml#/definitions/flag - description: - When ksz88x3 is acting as clock provier (via REFCLKO) it - can select between internal and external RMII reference - clock. Internal reference clock means that the clock for - the RMII of ksz88x3 is provided by the ksz88x3 internally - and the REFCLKI pin is unconnected. For the external - reference clock, the clock needs to be fed back to ksz88x3 - via REFCLKI. - If microchip,rmii-clk-internal is set, ksz88x3 will provide - rmii reference clock internally, otherwise reference clock - should be provided externally. - dependencies: - microchip,rmii-clk-internal: [ethernet] + "^(ethernet-)?ports$": + patternProperties: + "^(ethernet-)?port@[0-2]$": + $ref: dsa-port.yaml# + unevaluatedProperties: false + properties: + microchip,rmii-clk-internal: + $ref: /schemas/types.yaml#/definitions/flag + description: + When ksz88x3 is acting as clock provier (via REFCLKO) it + can select between internal and external RMII reference + clock. Internal reference clock means that the clock for + the RMII of ksz88x3 is provided by the ksz88x3 internally + and the REFCLKI pin is unconnected. For the external + reference clock, the clock needs to be fed back to ksz88x3 + via REFCLKI. + If microchip,rmii-clk-internal is set, ksz88x3 will provide + rmii reference clock internally, otherwise reference clock + should be provided externally. + dependencies: + microchip,rmii-clk-internal: [ethernet] + - if: + properties: + compatible: + contains: + const: microchip,ksz8463 + then: + properties: + straps-rxd-gpios: + description: + RXD0 and RXD1 pins, used to select SPI as bus interface. + minItems: 2 + maxItems: 2 unevaluatedProperties: false diff --git a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml index 9432565f4f5d..e9dd914b0734 100644 --- a/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml +++ b/Documentation/devicetree/bindings/net/dsa/nxp,sja1105.yaml @@ -32,6 +32,15 @@ properties: reg: maxItems: 1 + reset-gpios: + description: + A GPIO connected to the active-low RST_N pin of the SJA1105. Note that + reset of this chip is performed via SPI and the RST_N pin must be wired + to satisfy the power-up sequence documented in "SJA1105PQRS Application + Hints" (AH1704) sec. 2.4.4. Connecting the SJA1105 RST_N pin to a GPIO is + therefore discouraged. + maxItems: 1 + spi-cpha: true spi-cpol: true diff --git a/Documentation/devicetree/bindings/net/ethernet-controller.yaml b/Documentation/devicetree/bindings/net/ethernet-controller.yaml index 66b1cfbbfe22..1bafd687dcb1 100644 --- a/Documentation/devicetree/bindings/net/ethernet-controller.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-controller.yaml @@ -108,6 +108,11 @@ properties: $ref: "#/properties/phy-handle" deprecated: true + ptp-timer: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Specifies a reference to a node representing an IEEE 1588 PTP device. + rx-fifo-depth: $ref: /schemas/types.yaml#/definitions/uint32 description: @@ -222,7 +227,7 @@ properties: reg: maxItems: 1 description: - This define the LED index in the PHY or the MAC. It's really + This defines the LED index in the PHY or the MAC. It's really driver dependent and required for ports that define multiple LED for the same port. @@ -274,7 +279,7 @@ additionalProperties: true # specified. # # One option is to make the clock traces on the PCB longer than the -# data traces. A sufficiently difference in length can provide the 2ns +# data traces. A sufficient difference in length can provide the 2ns # delay. If both the RX and TX delays are implemented in this manner, # 'rgmii' should be used, so indicating the PCB adds the delays. # diff --git a/Documentation/devicetree/bindings/net/ethernet-phy.yaml b/Documentation/devicetree/bindings/net/ethernet-phy.yaml index 71e2cd32580f..2ec2d9fda7e3 100644 --- a/Documentation/devicetree/bindings/net/ethernet-phy.yaml +++ b/Documentation/devicetree/bindings/net/ethernet-phy.yaml @@ -266,7 +266,7 @@ properties: reg: maxItems: 1 description: - This define the LED index in the PHY or the MAC. It's really + This defines the LED index in the PHY or the MAC. It's really driver dependent and required for ports that define multiple LED for the same port. diff --git a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml index 60aaf30d68ed..ef1e30a48c91 100644 --- a/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml +++ b/Documentation/devicetree/bindings/net/fsl,fman-dtsec.yaml @@ -81,10 +81,6 @@ properties: An array of two references: the first is the FMan RX port and the second is the TX port used by this MAC. - ptp-timer: - $ref: /schemas/types.yaml#/definitions/phandle - description: A reference to the IEEE1588 timer - phys: description: A reference to the SerDes lane(s) maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/litex,liteeth.yaml b/Documentation/devicetree/bindings/net/litex,liteeth.yaml index ebf4e360f8dd..200b198b0d9b 100644 --- a/Documentation/devicetree/bindings/net/litex,liteeth.yaml +++ b/Documentation/devicetree/bindings/net/litex,liteeth.yaml @@ -86,14 +86,12 @@ examples: phy-handle = <ð_phy>; mdio { - #address-cells = <1>; - #size-cells = <0>; + #address-cells = <1>; + #size-cells = <0>; - eth_phy: ethernet-phy@0 { - reg = <0>; - }; + eth_phy: ethernet-phy@0 { + reg = <0>; + }; }; }; ... - -# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml : diff --git a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt index 2681168777a1..6f7b907d5a04 100644 --- a/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt +++ b/Documentation/devicetree/bindings/net/micrel-ksz90x1.txt @@ -13,7 +13,7 @@ KSZ9021: All skew control options are specified in picoseconds. The minimum value is 0, the maximum value is 3000, and it can be specified in 200ps - steps, *but* these values are in not fact what you get because this chip's + steps, *but* these values are in no way what you get because this chip's skew values actually increase in 120ps steps, starting from -840ps. The incorrect values came from an error in the original KSZ9021 datasheet before it was corrected in revision 1.2 (Feb 2014), but it is too late to @@ -153,7 +153,7 @@ KSZ9031: - micrel,force-master: Boolean, force phy to master mode. Only set this option if the phy reference clock provided at CLK125_NDO pin is used as MAC reference - clock because the clock jitter in slave mode is to high (errata#2). + clock because the clock jitter in slave mode is too high (errata#2). Attention: The link partner must be configurable as slave otherwise no link will be established. diff --git a/Documentation/devicetree/bindings/net/micrel.txt b/Documentation/devicetree/bindings/net/micrel.txt index a407dd1b4614..01622ce58112 100644 --- a/Documentation/devicetree/bindings/net/micrel.txt +++ b/Documentation/devicetree/bindings/net/micrel.txt @@ -26,7 +26,7 @@ Optional properties: Setting the RMII Reference Clock Select bit enables 25 MHz rather than 50 MHz clock mode. - Note that this option in only needed for certain PHY revisions with a + Note that this option is only needed for certain PHY revisions with a non-standard, inverted function of this configuration bit. Specifically, a clock reference ("rmii-ref" below) is always needed to actually select a mode. diff --git a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml index a73fc5036905..5caa3779660d 100644 --- a/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml +++ b/Documentation/devicetree/bindings/net/microchip,sparx5-switch.yaml @@ -55,12 +55,14 @@ properties: - const: microchip,lan9691-switch reg: + minItems: 2 items: - description: cpu target - description: devices target - description: general control block target reg-names: + minItems: 2 items: - const: cpu - const: devices @@ -168,6 +170,26 @@ required: - interrupt-names - ethernet-ports +allOf: + - if: + properties: + compatible: + contains: + enum: + - microchip,lan9691-switch + then: + properties: + reg: + minItems: 2 + reg-names: + minItems: 2 + else: + properties: + reg: + minItems: 3 + reg-names: + minItems: 3 + additionalProperties: false examples: @@ -245,4 +267,3 @@ examples: }; ... -# vim: set ts=2 sw=2 sts=2 tw=80 et cc=80 ft=yaml : diff --git a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml index 5f49bd9ac5e6..7e96a625f0cf 100644 --- a/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml +++ b/Documentation/devicetree/bindings/net/nfc/ti,trf7970a.yaml @@ -56,10 +56,10 @@ properties: Regulator for supply voltage to VIN pin ti,rx-gain-reduction-db: - $ref: /schemas/types.yaml#/definitions/uint32 description: | Specify an RX gain reduction to reduce antenna sensitivity with 5dB per - increment, with a maximum of 15dB. Supported values: [0, 5, 10, 15]. + increment, with a maximum of 15dB. + enum: [ 0, 5, 10, 15] required: - compatible diff --git a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml index 2d33bbab7163..3adbcf56d2be 100644 --- a/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml +++ b/Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml @@ -4,14 +4,15 @@ $id: http://devicetree.org/schemas/net/pcs/renesas,rzn1-miic.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Renesas RZ/N1 MII converter +title: Renesas RZ/N1, RZ/N2H and RZ/T2H MII converter maintainers: - Clément Léger <clement.leger@bootlin.com> + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> description: | - This MII converter is present on the Renesas RZ/N1 SoC family. It is - responsible to do MII passthrough or convert it to RMII/RGMII. + This MII converter is present on the Renesas RZ/N1, RZ/N2H and RZ/T2H SoC + families. It is responsible to do MII passthrough or convert it to RMII/RGMII. properties: '#address-cells': @@ -21,10 +22,16 @@ properties: const: 0 compatible: - items: - - enum: - - renesas,r9a06g032-miic - - const: renesas,rzn1-miic + oneOf: + - items: + - enum: + - renesas,r9a06g032-miic + - const: renesas,rzn1-miic + - items: + - const: renesas,r9a09g077-miic # RZ/T2H + - items: + - const: renesas,r9a09g087-miic # RZ/N2H + - const: renesas,r9a09g077-miic reg: maxItems: 1 @@ -43,11 +50,22 @@ properties: - const: rmii_ref - const: hclk + resets: + items: + - description: Converter register reset + - description: Converter reset + + reset-names: + items: + - const: rst + - const: crst + renesas,miic-switch-portin: description: MII Switch PORTIN configuration. This value should use one of - the values defined in dt-bindings/net/pcs-rzn1-miic.h. + the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC and + include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 - enum: [1, 2] + enum: [0, 1, 2] power-domains: maxItems: 1 @@ -60,11 +78,12 @@ patternProperties: properties: reg: description: MII Converter port number. - enum: [1, 2, 3, 4, 5] + enum: [0, 1, 2, 3, 4, 5] renesas,miic-input: description: Converter input port configuration. This value should use - one of the values defined in dt-bindings/net/pcs-rzn1-miic.h. + one of the values defined in dt-bindings/net/pcs-rzn1-miic.h for RZ/N1 SoC + and include/dt-bindings/net/renesas,r9a09g077-pcs-miic.h for RZ/N2H, RZ/T2H SoCs. $ref: /schemas/types.yaml#/definitions/uint32 required: @@ -73,47 +92,109 @@ patternProperties: additionalProperties: false - allOf: - - if: - properties: - reg: - const: 1 - then: - properties: - renesas,miic-input: - const: 0 - - if: +allOf: + - if: + properties: + compatible: + contains: + const: renesas,rzn1-miic + then: + properties: + renesas,miic-switch-portin: + enum: [1, 2] + resets: false + reset-names: false + patternProperties: + "^mii-conv@[0-5]$": properties: reg: - const: 2 - then: - properties: - renesas,miic-input: - enum: [1, 11] - - if: - properties: - reg: - const: 3 - then: - properties: - renesas,miic-input: - enum: [7, 10] - - if: + enum: [1, 2, 3, 4, 5] + allOf: + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + const: 0 + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [1, 11] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + enum: [7, 10] + - if: + properties: + reg: + const: 4 + then: + properties: + renesas,miic-input: + enum: [4, 6, 9, 13] + - if: + properties: + reg: + const: 5 + then: + properties: + renesas,miic-input: + enum: [3, 5, 8, 12] + else: + properties: + renesas,miic-switch-portin: + const: 0 + required: + - resets + - reset-names + patternProperties: + "^mii-conv@[0-5]$": properties: reg: - const: 4 - then: - properties: - renesas,miic-input: - enum: [4, 6, 9, 13] - - if: - properties: - reg: - const: 5 - then: - properties: - renesas,miic-input: - enum: [3, 5, 8, 12] + enum: [0, 1, 2, 3] + allOf: + - if: + properties: + reg: + const: 0 + then: + properties: + renesas,miic-input: + enum: [0, 3, 6] + - if: + properties: + reg: + const: 1 + then: + properties: + renesas,miic-input: + enum: [1, 4, 7] + - if: + properties: + reg: + const: 2 + then: + properties: + renesas,miic-input: + enum: [2, 5, 8] + - if: + properties: + reg: + const: 3 + then: + properties: + renesas,miic-input: + const: 1 required: - '#address-cells' diff --git a/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml b/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml new file mode 100644 index 000000000000..edd36a43a387 --- /dev/null +++ b/Documentation/devicetree/bindings/net/pse-pd/skyworks,si3474.yaml @@ -0,0 +1,144 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/pse-pd/skyworks,si3474.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Skyworks Si3474 Power Sourcing Equipment controller + +maintainers: + - Piotr Kubik <piotr.kubik@adtran.com> + +allOf: + - $ref: pse-controller.yaml# + +properties: + compatible: + enum: + - skyworks,si3474 + + reg: + maxItems: 2 + + reg-names: + items: + - const: main + - const: secondary + + channels: + description: The Si3474 is a single-chip PoE PSE controller managing + 8 physical power delivery channels. Internally, it's structured + into two logical "Quads". + Quad 0 Manages physical channels ('ports' in datasheet) 0, 1, 2, 3 + Quad 1 Manages physical channels ('ports' in datasheet) 4, 5, 6, 7. + + type: object + additionalProperties: false + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + patternProperties: + '^channel@[0-7]$': + type: object + additionalProperties: false + + properties: + reg: + maxItems: 1 + + required: + - reg + + required: + - "#address-cells" + - "#size-cells" + +required: + - compatible + - reg + - pse-pis + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-pse@26 { + compatible = "skyworks,si3474"; + reg-names = "main", "secondary"; + reg = <0x26>, <0x27>; + + channels { + #address-cells = <1>; + #size-cells = <0>; + phys0_0: channel@0 { + reg = <0>; + }; + phys0_1: channel@1 { + reg = <1>; + }; + phys0_2: channel@2 { + reg = <2>; + }; + phys0_3: channel@3 { + reg = <3>; + }; + phys0_4: channel@4 { + reg = <4>; + }; + phys0_5: channel@5 { + reg = <5>; + }; + phys0_6: channel@6 { + reg = <6>; + }; + phys0_7: channel@7 { + reg = <7>; + }; + }; + pse-pis { + #address-cells = <1>; + #size-cells = <0>; + pse_pi0: pse-pi@0 { + reg = <0>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_0>, <&phys0_1>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + pse_pi1: pse-pi@1 { + reg = <1>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_2>, <&phys0_3>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + pse_pi2: pse-pi@2 { + reg = <2>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_4>, <&phys0_5>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + pse_pi3: pse-pi@3 { + reg = <3>; + #pse-cells = <0>; + pairset-names = "alternative-a", "alternative-b"; + pairsets = <&phys0_6>, <&phys0_7>; + polarity-supported = "MDI-X", "S"; + vpwr-supply = <®_pse>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml new file mode 100644 index 000000000000..753f370b7605 --- /dev/null +++ b/Documentation/devicetree/bindings/net/qcom,ipq9574-ppe.yaml @@ -0,0 +1,533 @@ +# SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/qcom,ipq9574-ppe.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm IPQ packet process engine (PPE) + +maintainers: + - Luo Jie <quic_luoj@quicinc.com> + - Lei Wei <quic_leiwei@quicinc.com> + - Suruchi Agarwal <quic_suruchia@quicinc.com> + - Pavithra R <quic_pavir@quicinc.com> + +description: | + The Ethernet functionality in the PPE (Packet Process Engine) is comprised + of three components, the switch core, port wrapper and Ethernet DMA. + + The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and + two FIFO interfaces. One of the two FIFO interfaces is used for Ethernet + port to host CPU communication using Ethernet DMA. The other is used + communicating to the EIP engine which is used for IPsec offload. On the + IPQ9574, the PPE includes 6 GMAC/XGMACs that can be connected with external + Ethernet PHY. Switch core also includes BM (Buffer Management), QM (Queue + Management) and SCH (Scheduler) modules for supporting the packet processing. + + The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) + supporting various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There + are 3 UNIPHY (PCS) instances supported on the IPQ9574. + + Ethernet DMA is used to transmit and receive packets between the six Ethernet + ports and ARM host CPU. + + The follow diagram shows the PPE hardware block along with its connectivity + to the external hardware blocks such clock hardware blocks (CMNPLL, GCC, + NSS clock controller) and Ethernet PCS/PHY blocks. For depicting the PHY + connectivity, one 4x1 Gbps PHY (QCA8075) and two 10 GBps PHYs are used as an + example. + + +---------+ + | 48 MHZ | + +----+----+ + |(clock) + v + +----+----+ + +------| CMN PLL | + | +----+----+ + | |(clock) + | v + | +----+----+ +----+----+ (clock) +----+----+ + | +---| NSSCC | | GCC |--------->| MDIO | + | | +----+----+ +----+----+ +----+----+ + | | |(clock & reset) |(clock) + | | v v + | | +----+---------------------+--+----------+----------+---------+ + | | | +-----+ |EDMA FIFO | | EIP FIFO| + | | | | SCH | +----------+ +---------+ + | | | +-----+ | | | + | | | +------+ +------+ +-------------------+ | + | | | | BM | | QM | IPQ9574-PPE | L2/L3 Process | | + | | | +------+ +------+ +-------------------+ | + | | | | | + | | | +-------+ +-------+ +-------+ +-------+ +-------+ +-------+ | + | | | | MAC0 | | MAC1 | | MAC2 | | MAC3 | | XGMAC4| |XGMAC5 | | + | | | +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ +---+---+ | + | | | | | | | | | | + | | +-----+---------+---------+---------+---------+---------+-----+ + | | | | | | | | + | | +---+---------+---------+---------+---+ +---+---+ +---+---+ + +--+---->| PCS0 | | PCS1 | | PCS2 | + |(clock) +---+---------+---------+---------+---+ +---+---+ +---+---+ + | | | | | | | + | +---+---------+---------+---------+---+ +---+---+ +---+---+ + +------->| QCA8075 PHY | | PHY4 | | PHY5 | + (clock) +-------------------------------------+ +-------+ +-------+ + +properties: + compatible: + enum: + - qcom,ipq9574-ppe + + reg: + maxItems: 1 + + clocks: + items: + - description: PPE core clock + - description: PPE APB (Advanced Peripheral Bus) clock + - description: PPE IPE (Ingress Process Engine) clock + - description: PPE BM, QM and scheduler clock + + clock-names: + items: + - const: ppe + - const: apb + - const: ipe + - const: btq + + resets: + maxItems: 1 + description: PPE reset, which is necessary before configuring PPE hardware + + interrupts: + maxItems: 1 + description: PPE switch miscellaneous interrupt + + interconnects: + items: + - description: Bus interconnect path leading to PPE switch core function + - description: Bus interconnect path leading to PPE register access + - description: Bus interconnect path leading to QoS generation + - description: Bus interconnect path leading to timeout reference + - description: Bus interconnect path leading to NSS NOC from memory NOC + - description: Bus interconnect path leading to memory NOC from NSS NOC + - description: Bus interconnect path leading to enhanced memory NOC from NSS NOC + + interconnect-names: + items: + - const: ppe + - const: ppe_cfg + - const: qos_gen + - const: timeout_ref + - const: nssnoc_memnoc + - const: memnoc_nssnoc + - const: memnoc_nssnoc_1 + + ethernet-dma: + type: object + additionalProperties: false + description: + EDMA (Ethernet DMA) is used to transmit packets between PPE and ARM + host CPU. There are 32 TX descriptor rings, 32 TX completion rings, + 24 RX descriptor rings and 8 RX fill rings supported. + + properties: + clocks: + items: + - description: EDMA system clock + - description: EDMA APB (Advanced Peripheral Bus) clock + + clock-names: + items: + - const: sys + - const: apb + + resets: + maxItems: 1 + description: EDMA reset + + interrupts: + minItems: 65 + maxItems: 65 + + interrupt-names: + minItems: 65 + maxItems: 65 + items: + oneOf: + - pattern: '^txcmpl_([1-2]?[0-9]|3[01])$' + - pattern: '^rxfill_[0-7]$' + - pattern: '^rxdesc_(1?[0-9]|2[0-3])$' + - const: misc + description: + Interrupts "txcmpl_[0-31]" are the Ethernet DMA TX completion ring interrupts. + Interrupts "rxfill_[0-7]" are the Ethernet DMA RX fill ring interrupts. + Interrupts "rxdesc_[0-23]" are the Ethernet DMA RX Descriptor ring interrupts. + Interrupt "misc" is the Ethernet DMA miscellaneous error interrupt. + + required: + - clocks + - clock-names + - resets + - interrupts + - interrupt-names + + ethernet-ports: + patternProperties: + "^ethernet-port@[1-6]+$": + type: object + unevaluatedProperties: false + $ref: ethernet-switch-port.yaml# + + properties: + reg: + minimum: 1 + maximum: 6 + description: PPE Ethernet port ID + + clocks: + items: + - description: Port MAC clock + - description: Port RX clock + - description: Port TX clock + + clock-names: + items: + - const: mac + - const: rx + - const: tx + + resets: + items: + - description: Port MAC reset + - description: Port RX reset + - description: Port TX reset + + reset-names: + items: + - const: mac + - const: rx + - const: tx + + required: + - reg + - clocks + - clock-names + - resets + - reset-names + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - interconnects + - interconnect-names + - ethernet-dma + +allOf: + - $ref: ethernet-switch.yaml + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/qcom,ipq9574-gcc.h> + #include <dt-bindings/clock/qcom,ipq9574-nsscc.h> + #include <dt-bindings/interconnect/qcom,ipq9574.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/reset/qcom,ipq9574-nsscc.h> + + ethernet-switch@3a000000 { + compatible = "qcom,ipq9574-ppe"; + reg = <0x3a000000 0xbef800>; + clocks = <&nsscc NSS_CC_PPE_SWITCH_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_CFG_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_IPE_CLK>, + <&nsscc NSS_CC_PPE_SWITCH_BTQ_CLK>; + clock-names = "ppe", + "apb", + "ipe", + "btq"; + resets = <&nsscc PPE_FULL_RESET>; + interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>; + interconnects = <&nsscc MASTER_NSSNOC_PPE &nsscc SLAVE_NSSNOC_PPE>, + <&nsscc MASTER_NSSNOC_PPE_CFG &nsscc SLAVE_NSSNOC_PPE_CFG>, + <&gcc MASTER_NSSNOC_QOSGEN_REF &gcc SLAVE_NSSNOC_QOSGEN_REF>, + <&gcc MASTER_NSSNOC_TIMEOUT_REF &gcc SLAVE_NSSNOC_TIMEOUT_REF>, + <&gcc MASTER_MEM_NOC_NSSNOC &gcc SLAVE_MEM_NOC_NSSNOC>, + <&gcc MASTER_NSSNOC_MEMNOC &gcc SLAVE_NSSNOC_MEMNOC>, + <&gcc MASTER_NSSNOC_MEM_NOC_1 &gcc SLAVE_NSSNOC_MEM_NOC_1>; + interconnect-names = "ppe", + "ppe_cfg", + "qos_gen", + "timeout_ref", + "nssnoc_memnoc", + "memnoc_nssnoc", + "memnoc_nssnoc_1"; + + ethernet-dma { + clocks = <&nsscc NSS_CC_PPE_EDMA_CLK>, + <&nsscc NSS_CC_PPE_EDMA_CFG_CLK>; + clock-names = "sys", + "apb"; + resets = <&nsscc EDMA_HW_RESET>; + interrupts = <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 370 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 371 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 372 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 377 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 378 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 379 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 380 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 381 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 382 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 383 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 346 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 347 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 348 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 349 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 350 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 351 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "txcmpl_0", + "txcmpl_1", + "txcmpl_2", + "txcmpl_3", + "txcmpl_4", + "txcmpl_5", + "txcmpl_6", + "txcmpl_7", + "txcmpl_8", + "txcmpl_9", + "txcmpl_10", + "txcmpl_11", + "txcmpl_12", + "txcmpl_13", + "txcmpl_14", + "txcmpl_15", + "txcmpl_16", + "txcmpl_17", + "txcmpl_18", + "txcmpl_19", + "txcmpl_20", + "txcmpl_21", + "txcmpl_22", + "txcmpl_23", + "txcmpl_24", + "txcmpl_25", + "txcmpl_26", + "txcmpl_27", + "txcmpl_28", + "txcmpl_29", + "txcmpl_30", + "txcmpl_31", + "rxfill_0", + "rxfill_1", + "rxfill_2", + "rxfill_3", + "rxfill_4", + "rxfill_5", + "rxfill_6", + "rxfill_7", + "rxdesc_0", + "rxdesc_1", + "rxdesc_2", + "rxdesc_3", + "rxdesc_4", + "rxdesc_5", + "rxdesc_6", + "rxdesc_7", + "rxdesc_8", + "rxdesc_9", + "rxdesc_10", + "rxdesc_11", + "rxdesc_12", + "rxdesc_13", + "rxdesc_14", + "rxdesc_15", + "rxdesc_16", + "rxdesc_17", + "rxdesc_18", + "rxdesc_19", + "rxdesc_20", + "rxdesc_21", + "rxdesc_22", + "rxdesc_23", + "misc"; + }; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + + ethernet-port@1 { + reg = <1>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy0>; + pcs-handle = <&pcs0_ch0>; + clocks = <&nsscc NSS_CC_PORT1_MAC_CLK>, + <&nsscc NSS_CC_PORT1_RX_CLK>, + <&nsscc NSS_CC_PORT1_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT1_MAC_ARES>, + <&nsscc PORT1_RX_ARES>, + <&nsscc PORT1_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@2 { + reg = <2>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy1>; + pcs-handle = <&pcs0_ch1>; + clocks = <&nsscc NSS_CC_PORT2_MAC_CLK>, + <&nsscc NSS_CC_PORT2_RX_CLK>, + <&nsscc NSS_CC_PORT2_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT2_MAC_ARES>, + <&nsscc PORT2_RX_ARES>, + <&nsscc PORT2_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@3 { + reg = <3>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy2>; + pcs-handle = <&pcs0_ch2>; + clocks = <&nsscc NSS_CC_PORT3_MAC_CLK>, + <&nsscc NSS_CC_PORT3_RX_CLK>, + <&nsscc NSS_CC_PORT3_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT3_MAC_ARES>, + <&nsscc PORT3_RX_ARES>, + <&nsscc PORT3_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@4 { + reg = <4>; + phy-mode = "qsgmii"; + managed = "in-band-status"; + phy-handle = <&phy3>; + pcs-handle = <&pcs0_ch3>; + clocks = <&nsscc NSS_CC_PORT4_MAC_CLK>, + <&nsscc NSS_CC_PORT4_RX_CLK>, + <&nsscc NSS_CC_PORT4_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT4_MAC_ARES>, + <&nsscc PORT4_RX_ARES>, + <&nsscc PORT4_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@5 { + reg = <5>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + phy-handle = <&phy4>; + pcs-handle = <&pcs1_ch0>; + clocks = <&nsscc NSS_CC_PORT5_MAC_CLK>, + <&nsscc NSS_CC_PORT5_RX_CLK>, + <&nsscc NSS_CC_PORT5_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT5_MAC_ARES>, + <&nsscc PORT5_RX_ARES>, + <&nsscc PORT5_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + + ethernet-port@6 { + reg = <6>; + phy-mode = "usxgmii"; + managed = "in-band-status"; + phy-handle = <&phy5>; + pcs-handle = <&pcs2_ch0>; + clocks = <&nsscc NSS_CC_PORT6_MAC_CLK>, + <&nsscc NSS_CC_PORT6_RX_CLK>, + <&nsscc NSS_CC_PORT6_TX_CLK>; + clock-names = "mac", + "rx", + "tx"; + resets = <&nsscc PORT6_MAC_ARES>, + <&nsscc PORT6_RX_ARES>, + <&nsscc PORT6_TX_ARES>; + reset-names = "mac", + "rx", + "tx"; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml b/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml index d248a08a2136..2b5697bd7c5d 100644 --- a/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml +++ b/Documentation/devicetree/bindings/net/realtek,rtl82xx.yaml @@ -45,12 +45,16 @@ properties: description: Disable CLKOUT clock, CLKOUT clock default is enabled after hardware reset. - realtek,aldps-enable: type: boolean description: Enable ALDPS mode, ALDPS mode default is disabled after hardware reset. + wakeup-source: + type: boolean + description: + Enable Wake-on-LAN support for the RTL8211F PHY. + unevaluatedProperties: false allOf: diff --git a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml index d9a8d586e260..16dd7a2631ab 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzn1-gmac.yaml @@ -30,6 +30,15 @@ properties: - const: renesas,rzn1-gmac - const: snps,dwmac + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + pcs-handle: description: phandle pointing to a PCS sub-node compatible with diff --git a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml index 23e39bcea96b..bd53ab300f50 100644 --- a/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml +++ b/Documentation/devicetree/bindings/net/renesas,rzv2h-gbeth.yaml @@ -17,63 +17,111 @@ select: - renesas,r9a09g047-gbeth - renesas,r9a09g056-gbeth - renesas,r9a09g057-gbeth + - renesas,r9a09g077-gbeth + - renesas,r9a09g087-gbeth - renesas,rzv2h-gbeth required: - compatible properties: compatible: - items: - - enum: - - renesas,r9a09g047-gbeth # RZ/G3E - - renesas,r9a09g056-gbeth # RZ/V2N - - renesas,r9a09g057-gbeth # RZ/V2H(P) - - const: renesas,rzv2h-gbeth - - const: snps,dwmac-5.20 + oneOf: + - items: + - enum: + - renesas,r9a09g047-gbeth # RZ/G3E + - renesas,r9a09g056-gbeth # RZ/V2N + - renesas,r9a09g057-gbeth # RZ/V2H(P) + - const: renesas,rzv2h-gbeth + - const: snps,dwmac-5.20 + - items: + - const: renesas,r9a09g077-gbeth # RZ/T2H + - const: snps,dwmac-5.20 + - items: + - const: renesas,r9a09g087-gbeth # RZ/N2H + - const: renesas,r9a09g077-gbeth + - const: snps,dwmac-5.20 reg: maxItems: 1 clocks: - items: - - description: CSR clock - - description: AXI system clock - - description: PTP clock - - description: TX clock - - description: RX clock - - description: TX clock phase-shifted by 180 degrees - - description: RX clock phase-shifted by 180 degrees + oneOf: + - items: + - description: CSR clock + - description: AXI system clock + - description: PTP clock + - description: TX clock + - description: RX clock + - description: TX clock phase-shifted by 180 degrees + - description: RX clock phase-shifted by 180 degrees + - items: + - description: CSR clock + - description: AXI system clock + - description: TX clock clock-names: - items: - - const: stmmaceth - - const: pclk - - const: ptp_ref - - const: tx - - const: rx - - const: tx-180 - - const: rx-180 - - interrupts: - minItems: 11 + oneOf: + - items: + - const: stmmaceth + - const: pclk + - const: ptp_ref + - const: tx + - const: rx + - const: tx-180 + - const: rx-180 + - items: + - const: stmmaceth + - const: pclk + - const: tx interrupt-names: - items: - - const: macirq - - const: eth_wake_irq - - const: eth_lpi - - const: rx-queue-0 - - const: rx-queue-1 - - const: rx-queue-2 - - const: rx-queue-3 - - const: tx-queue-0 - - const: tx-queue-1 - - const: tx-queue-2 - - const: tx-queue-3 + oneOf: + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - items: + - const: macirq + - const: eth_wake_irq + - const: eth_lpi + - const: rx-queue-0 + - const: rx-queue-1 + - const: rx-queue-2 + - const: rx-queue-3 + - const: rx-queue-4 + - const: rx-queue-5 + - const: rx-queue-6 + - const: rx-queue-7 + - const: tx-queue-0 + - const: tx-queue-1 + - const: tx-queue-2 + - const: tx-queue-3 + - const: tx-queue-4 + - const: tx-queue-5 + - const: tx-queue-6 + - const: tx-queue-7 resets: - items: - - description: AXI power-on system reset + oneOf: + - items: + - description: AXI power-on system reset + - items: + - description: AXI power-on system reset + - description: AHB reset + + pcs-handle: + description: + phandle pointing to a PCS sub-node compatible with + Documentation/devicetree/bindings/net/pcs/renesas,rzn1-miic.yaml# + (Refer RZ/T2H portion in the DT-binding file) required: - compatible @@ -87,6 +135,56 @@ required: allOf: - $ref: snps,dwmac.yaml# + - if: + properties: + compatible: + contains: + const: renesas,r9a09g077-gbeth + then: + properties: + clocks: + maxItems: 3 + + clock-names: + maxItems: 3 + + interrupts: + minItems: 19 + + interrupt-names: + minItems: 19 + + resets: + minItems: 2 + + reset-names: + minItems: 2 + + required: + - reset-names + else: + properties: + clocks: + minItems: 7 + + clock-names: + minItems: 7 + + interrupts: + minItems: 11 + maxItems: 11 + + interrupt-names: + minItems: 11 + maxItems: 11 + + resets: + maxItems: 1 + + pcs-handle: false + + reset-names: false + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/net/snps,dwmac.yaml b/Documentation/devicetree/bindings/net/snps,dwmac.yaml index 4e3cbaa06229..658c004e6a5c 100644 --- a/Documentation/devicetree/bindings/net/snps,dwmac.yaml +++ b/Documentation/devicetree/bindings/net/snps,dwmac.yaml @@ -75,6 +75,7 @@ properties: - qcom,sc8280xp-ethqos - qcom,sm8150-ethqos - renesas,r9a06g032-gmac + - renesas,r9a09g077-gbeth - renesas,rzn1-gmac - renesas,rzv2h-gbeth - rockchip,px30-gmac @@ -118,11 +119,11 @@ properties: interrupts: minItems: 1 - maxItems: 11 + maxItems: 19 interrupt-names: minItems: 1 - maxItems: 11 + maxItems: 19 items: oneOf: - description: Combined signal for various interrupt events @@ -134,9 +135,9 @@ properties: - description: The interrupt that occurs when HW safety error triggered const: sfty - description: Per channel receive completion interrupt - pattern: '^rx-queue-[0-3]$' + pattern: '^rx-queue-[0-7]$' - description: Per channel transmit completion interrupt - pattern: '^tx-queue-[0-3]$' + pattern: '^tx-queue-[0-7]$' clocks: minItems: 1 diff --git a/Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml b/Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml new file mode 100644 index 000000000000..500a3e1daa23 --- /dev/null +++ b/Documentation/devicetree/bindings/net/spacemit,k1-emac.yaml @@ -0,0 +1,81 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/spacemit,k1-emac.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SpacemiT K1 Ethernet MAC + +allOf: + - $ref: ethernet-controller.yaml# + +maintainers: + - Vivian Wang <wangruikang@iscas.ac.cn> + +properties: + compatible: + const: spacemit,k1-emac + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + + mdio-bus: + $ref: mdio.yaml# + unevaluatedProperties: false + + resets: + maxItems: 1 + + spacemit,apmu: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to syscon that controls this MAC + - description: offset of control registers + description: + A phandle to syscon with byte offset to control registers for this MAC + +required: + - compatible + - reg + - clocks + - interrupts + - resets + - spacemit,apmu + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/spacemit,k1-syscon.h> + + ethernet@cac80000 { + compatible = "spacemit,k1-emac"; + reg = <0xcac80000 0x00000420>; + clocks = <&syscon_apmu CLK_EMAC0_BUS>; + interrupts = <131>; + mac-address = [ 00 00 00 00 00 00 ]; + phy-handle = <&rgmii0>; + phy-mode = "rgmii-id"; + pinctrl-names = "default"; + pinctrl-0 = <&gmac0_cfg>; + resets = <&syscon_apmu RESET_EMAC0>; + rx-internal-delay-ps = <0>; + tx-internal-delay-ps = <0>; + spacemit,apmu = <&syscon_apmu 0x3e4>; + + mdio-bus { + #address-cells = <0x1>; + #size-cells = <0x0>; + + rgmii0: phy@1 { + reg = <0x1>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ti,icss-iep.yaml b/Documentation/devicetree/bindings/net/ti,icss-iep.yaml index e36e3a622904..ea2659d90a52 100644 --- a/Documentation/devicetree/bindings/net/ti,icss-iep.yaml +++ b/Documentation/devicetree/bindings/net/ti,icss-iep.yaml @@ -8,6 +8,8 @@ title: Texas Instruments ICSS Industrial Ethernet Peripheral (IEP) module maintainers: - Md Danish Anwar <danishanwar@ti.com> + - Parvathi Pudi <parvathi@couthit.com> + - Basharath Hussain Khaja <basharath@couthit.com> properties: compatible: @@ -17,9 +19,11 @@ properties: - ti,am642-icss-iep - ti,j721e-icss-iep - const: ti,am654-icss-iep - - - const: ti,am654-icss-iep - + - enum: + - ti,am654-icss-iep + - ti,am5728-icss-iep + - ti,am4376-icss-iep + - ti,am3356-icss-iep reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml new file mode 100644 index 000000000000..a98ad45ca66f --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,icssm-prueth.yaml @@ -0,0 +1,233 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,icssm-prueth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments ICSSM PRUSS Ethernet + +maintainers: + - Roger Quadros <rogerq@ti.com> + - Andrew F. Davis <afd@ti.com> + - Parvathi Pudi <parvathi@couthit.com> + - Basharath Hussain Khaja <basharath@couthit.com> + +description: + Ethernet based on the Programmable Real-Time Unit and Industrial + Communication Subsystem. + +properties: + compatible: + enum: + - ti,am57-prueth # for AM57x SoC family + - ti,am4376-prueth # for AM43x SoC family + - ti,am3359-prueth # for AM33x SoC family + + sram: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to OCMC SRAM node + + ti,mii-rt: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to the MII_RT peripheral for ICSS + + ti,iep: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to IEP (Industrial Ethernet Peripheral) for ICSS + + ti,ecap: + $ref: /schemas/types.yaml#/definitions/phandle + description: + phandle to Enhanced Capture (eCAP) event for ICSS + + interrupts: + items: + - description: High priority Rx Interrupt specifier. + - description: Low priority Rx Interrupt specifier. + + interrupt-names: + items: + - const: rx_hp + - const: rx_lp + + ethernet-ports: + type: object + additionalProperties: false + + properties: + '#address-cells': + const: 1 + '#size-cells': + const: 0 + + patternProperties: + ^ethernet-port@[0-1]$: + type: object + description: ICSSM PRUETH external ports + $ref: ethernet-controller.yaml# + unevaluatedProperties: false + + properties: + reg: + items: + - enum: [0, 1] + description: ICSSM PRUETH port number + + interrupts: + maxItems: 3 + + interrupt-names: + items: + - const: rx + - const: emac_ptp_tx + - const: hsr_ptp_tx + + required: + - reg + + anyOf: + - required: + - ethernet-port@0 + - required: + - ethernet-port@1 + +required: + - compatible + - sram + - ti,mii-rt + - ti,iep + - ti,ecap + - ethernet-ports + - interrupts + - interrupt-names + +allOf: + - $ref: /schemas/remoteproc/ti,pru-consumer.yaml# + +unevaluatedProperties: false + +examples: + - | + /* Dual-MAC Ethernet application node on PRU-ICSS2 */ + pruss2_eth: pruss2-eth { + compatible = "ti,am57-prueth"; + ti,prus = <&pru2_0>, <&pru2_1>; + sram = <&ocmcram1>; + ti,mii-rt = <&pruss2_mii_rt>; + ti,iep = <&pruss2_iep>; + ti,ecap = <&pruss2_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss2_intc>; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss2_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss2_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss2_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss2_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + - | + /* Dual-MAC Ethernet application node on PRU-ICSS1 */ + pruss1_eth: pruss1-eth { + compatible = "ti,am4376-prueth"; + ti,prus = <&pru1_0>, <&pru1_1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss1_mii_rt>; + ti,iep = <&pruss1_iep>; + ti,ecap = <&pruss1_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss1_intc>; + + pinctrl-0 = <&pruss1_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss1_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss1_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss1_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss1_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; + - | + /* Dual-MAC Ethernet application node on PRU-ICSS */ + pruss_eth: pruss-eth { + compatible = "ti,am3359-prueth"; + ti,prus = <&pru0>, <&pru1>; + sram = <&ocmcram>; + ti,mii-rt = <&pruss_mii_rt>; + ti,iep = <&pruss_iep>; + ti,ecap = <&pruss_ecap>; + interrupts = <20 2 2>, <21 3 3>; + interrupt-names = "rx_hp", "rx_lp"; + interrupt-parent = <&pruss_intc>; + + pinctrl-0 = <&pruss_eth_default>; + pinctrl-names = "default"; + + ethernet-ports { + #address-cells = <1>; + #size-cells = <0>; + pruss_emac0: ethernet-port@0 { + reg = <0>; + phy-handle = <&pruss_eth0_phy>; + phy-mode = "mii"; + interrupts = <20 2 2>, <26 6 6>, <23 6 6>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + + pruss_emac1: ethernet-port@1 { + reg = <1>; + phy-handle = <&pruss_eth1_phy>; + phy-mode = "mii"; + interrupts = <21 3 3>, <27 9 7>, <24 9 7>; + interrupt-names = "rx", "emac_ptp_tx", + "hsr_ptp_tx"; + /* Filled in by bootloader */ + local-mac-address = [00 00 00 00 00 00]; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml b/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml new file mode 100644 index 000000000000..42f217099b2e --- /dev/null +++ b/Documentation/devicetree/bindings/net/ti,pruss-ecap.yaml @@ -0,0 +1,32 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/ti,pruss-ecap.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PRU-ICSS Enhanced Capture (eCAP) event module + +maintainers: + - Murali Karicheri <m-karicheri2@ti.com> + - Parvathi Pudi <parvathi@couthit.com> + - Basharath Hussain Khaja <basharath@couthit.com> + +properties: + compatible: + const: ti,pruss-ecap + + reg: + maxItems: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + pruss2_ecap: ecap@30000 { + compatible = "ti,pruss-ecap"; + reg = <0x30000 0x60>; + }; diff --git a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml index 7c8100e59a6c..3be757678764 100644 --- a/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml +++ b/Documentation/devicetree/bindings/net/wireless/brcm,bcm4329-fmac.yaml @@ -53,6 +53,7 @@ properties: - pci14e4,4488 # BCM4377 - pci14e4,4425 # BCM4378 - pci14e4,4433 # BCM4387 + - pci14e4,4434 # BCM4388 - pci14e4,449d # BCM43752 reg: diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml new file mode 100644 index 000000000000..caca2a4903cd --- /dev/null +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -0,0 +1,112 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Neural Processing Unit IP from Rockchip + +maintainers: + - Tomeu Vizoso <tomeu@tomeuvizoso.net> + +description: + Rockchip IP for accelerating inference of neural networks. + + There is to be a node per each NPU core in the SoC, and each core should reference all the + resources that it needs to function, such as clocks, power domains, and resets. + +properties: + $nodename: + pattern: '^npu@[a-f0-9]+$' + + compatible: + enum: + - rockchip,rk3588-rknn-core + + reg: + maxItems: 3 + + reg-names: + items: + - const: pc # Program Control-related registers + - const: cna # Convolution Neural Network Accelerator registers + - const: core # Main NPU core processing unit registers + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aclk + - const: hclk + - const: npu + - const: pclk + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + npu-supply: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: srst_a + - const: srst_h + + sram-supply: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - iommus + - power-domains + - resets + - reset-names + - npu-supply + - sram-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/rockchip,rk3588-cru.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/power/rk3588-power.h> + #include <dt-bindings/reset/rockchip,rk3588-cru.h> + + bus { + #address-cells = <2>; + #size-cells = <2>; + + npu@fdab0000 { + compatible = "rockchip,rk3588-rknn-core"; + reg = <0x0 0xfdab0000 0x0 0x1000>, + <0x0 0xfdab1000 0x0 0x1000>, + <0x0 0xfdab3000 0x0 0x1000>; + reg-names = "pc", "cna", "core"; + clocks = <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names = "aclk", "hclk", "npu", "pclk"; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH 0>; + iommus = <&rknn_mmu_0>; + npu-supply = <&vdd_npu_s0>; + power-domains = <&power RK3588_PD_NPUTOP>; + resets = <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; + reset-names = "srst_a", "srst_h"; + sram-supply = <&vdd_npu_mem_s0>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml index fc6555724e18..4c0b1f90aff8 100644 --- a/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml +++ b/Documentation/devicetree/bindings/nvme/apple,nvme-ans.yaml @@ -11,12 +11,18 @@ maintainers: properties: compatible: - items: - - enum: - - apple,t8103-nvme-ans2 - - apple,t8112-nvme-ans2 - - apple,t6000-nvme-ans2 - - const: apple,nvme-ans2 + oneOf: + - const: apple,t8015-nvme-ans2 + - items: + - const: apple,t6020-nvme-ans2 + - const: apple,t8103-nvme-ans2 + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t8103-nvme-ans2 + - apple,t8112-nvme-ans2 + - apple,t6000-nvme-ans2 + - const: apple,nvme-ans2 reg: items: @@ -67,20 +73,20 @@ if: compatible: contains: enum: - - apple,t8103-nvme-ans2 - - apple,t8112-nvme-ans2 + - apple,t6000-nvme-ans2 + - apple,t6020-nvme-ans2 then: properties: power-domains: - maxItems: 2 + minItems: 3 power-domain-names: - maxItems: 2 + minItems: 3 else: properties: power-domains: - minItems: 3 + maxItems: 2 power-domain-names: - minItems: 3 + maxItems: 2 required: - compatible diff --git a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml index 5434c144d2ec..18e7981241b5 100644 --- a/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/brcm,iproc-pcie.yaml @@ -108,6 +108,7 @@ examples: #include <dt-bindings/interrupt-controller/arm-gic.h> gic: interrupt-controller { + #address-cells = <0>; interrupt-controller; #interrupt-cells = <3>; }; diff --git a/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml b/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml index 68090b3ca419..8403c79634ed 100644 --- a/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/marvell,armada-3700-pcie.yaml @@ -42,6 +42,9 @@ properties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': @@ -92,6 +95,7 @@ examples: reset-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>; pcie_intc: interrupt-controller { + #address-cells = <0>; interrupt-controller; #interrupt-cells = <1>; }; diff --git a/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml b/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml index 7be695320ddf..3d68bfbe6feb 100644 --- a/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/marvell,kirkwood-pcie.yaml @@ -101,6 +101,9 @@ patternProperties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': diff --git a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml index 638b99db0433..c07b0ed51613 100644 --- a/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml +++ b/Documentation/devicetree/bindings/pci/socionext,uniphier-pcie.yaml @@ -56,6 +56,9 @@ properties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': @@ -109,6 +112,7 @@ examples: <0 0 0 4 &pcie_intc 3>; pcie_intc: interrupt-controller { + #address-cells = <0>; interrupt-controller; #interrupt-cells = <1>; interrupt-parent = <&gic>; diff --git a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml index 69b499c96c71..c704099f134b 100644 --- a/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml +++ b/Documentation/devicetree/bindings/pci/ti,j721e-pci-host.yaml @@ -99,6 +99,9 @@ properties: additionalProperties: false properties: + '#address-cells': + const: 0 + interrupt-controller: true '#interrupt-cells': diff --git a/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml b/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml new file mode 100644 index 000000000000..314048a2a134 --- /dev/null +++ b/Documentation/devicetree/bindings/perf/apm,xgene-pmu.yaml @@ -0,0 +1,142 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/perf/apm,xgene-pmu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: APM X-Gene SoC PMU + +maintainers: + - Khuong Dinh <khuong@os.amperecomputing.com> + +description: | + This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. + The following PMU devices are supported: + + L3C - L3 cache controller + IOB - IO bridge + MCB - Memory controller bridge + MC - Memory controller + +properties: + compatible: + enum: + - apm,xgene-pmu + - apm,xgene-pmu-v2 + + "#address-cells": + const: 2 + + "#size-cells": + const: 2 + + ranges: true + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regmap-csw: + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcba: + $ref: /schemas/types.yaml#/definitions/phandle + + regmap-mcbb: + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - regmap-csw + - regmap-mcba + - regmap-mcbb + - reg + - interrupts + +additionalProperties: + type: object + additionalProperties: false + + properties: + compatible: + enum: + - apm,xgene-pmu-l3c + - apm,xgene-pmu-iob + - apm,xgene-pmu-mcb + - apm,xgene-pmu-mc + + reg: + maxItems: 1 + + enable-bit-index: + description: + Specifies which bit enables the associated resource in MCB or MC subnodes. + $ref: /schemas/types.yaml#/definitions/uint32 + maximum: 31 + +examples: + - | + bus { + #address-cells = <2>; + #size-cells = <2>; + + pmu@78810000 { + compatible = "apm,xgene-pmu-v2"; + reg = <0x0 0x78810000 0x0 0x1000>; + #address-cells = <2>; + #size-cells = <2>; + ranges; + regmap-csw = <&csw>; + regmap-mcba = <&mcba>; + regmap-mcbb = <&mcbb>; + interrupts = <0x0 0x22 0x4>; + + pmul3c@7e610000 { + compatible = "apm,xgene-pmu-l3c"; + reg = <0x0 0x7e610000 0x0 0x1000>; + }; + + pmuiob@7e940000 { + compatible = "apm,xgene-pmu-iob"; + reg = <0x0 0x7e940000 0x0 0x1000>; + }; + + pmucmcb@7e710000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e710000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmcb@7e730000 { + compatible = "apm,xgene-pmu-mcb"; + reg = <0x0 0x7e730000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e810000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e810000 0x0 0x1000>; + enable-bit-index = <0>; + }; + + pmucmc@7e850000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e850000 0x0 0x1000>; + enable-bit-index = <1>; + }; + + pmucmc@7e890000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e890000 0x0 0x1000>; + enable-bit-index = <2>; + }; + + pmucmc@7e8d0000 { + compatible = "apm,xgene-pmu-mc"; + reg = <0x0 0x7e8d0000 0x0 0x1000>; + enable-bit-index = <3>; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt b/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt deleted file mode 100644 index afb11cf693c0..000000000000 --- a/Documentation/devicetree/bindings/perf/apm-xgene-pmu.txt +++ /dev/null @@ -1,112 +0,0 @@ -* APM X-Gene SoC PMU bindings - -This is APM X-Gene SoC PMU (Performance Monitoring Unit) module. -The following PMU devices are supported: - - L3C - L3 cache controller - IOB - IO bridge - MCB - Memory controller bridge - MC - Memory controller - -The following section describes the SoC PMU DT node binding. - -Required properties: -- compatible : Shall be "apm,xgene-pmu" for revision 1 or - "apm,xgene-pmu-v2" for revision 2. -- regmap-csw : Regmap of the CPU switch fabric (CSW) resource. -- regmap-mcba : Regmap of the MCB-A (memory bridge) resource. -- regmap-mcbb : Regmap of the MCB-B (memory bridge) resource. -- reg : First resource shall be the CPU bus PMU resource. -- interrupts : Interrupt-specifier for PMU IRQ. - -Required properties for L3C subnode: -- compatible : Shall be "apm,xgene-pmu-l3c". -- reg : First resource shall be the L3C PMU resource. - -Required properties for IOB subnode: -- compatible : Shall be "apm,xgene-pmu-iob". -- reg : First resource shall be the IOB PMU resource. - -Required properties for MCB subnode: -- compatible : Shall be "apm,xgene-pmu-mcb". -- reg : First resource shall be the MCB PMU resource. -- enable-bit-index : The bit indicates if the according MCB is enabled. - -Required properties for MC subnode: -- compatible : Shall be "apm,xgene-pmu-mc". -- reg : First resource shall be the MC PMU resource. -- enable-bit-index : The bit indicates if the according MC is enabled. - -Example: - csw: csw@7e200000 { - compatible = "apm,xgene-csw", "syscon"; - reg = <0x0 0x7e200000 0x0 0x1000>; - }; - - mcba: mcba@7e700000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e700000 0x0 0x1000>; - }; - - mcbb: mcbb@7e720000 { - compatible = "apm,xgene-mcb", "syscon"; - reg = <0x0 0x7e720000 0x0 0x1000>; - }; - - pmu: pmu@78810000 { - compatible = "apm,xgene-pmu-v2"; - #address-cells = <2>; - #size-cells = <2>; - ranges; - regmap-csw = <&csw>; - regmap-mcba = <&mcba>; - regmap-mcbb = <&mcbb>; - reg = <0x0 0x78810000 0x0 0x1000>; - interrupts = <0x0 0x22 0x4>; - - pmul3c@7e610000 { - compatible = "apm,xgene-pmu-l3c"; - reg = <0x0 0x7e610000 0x0 0x1000>; - }; - - pmuiob@7e940000 { - compatible = "apm,xgene-pmu-iob"; - reg = <0x0 0x7e940000 0x0 0x1000>; - }; - - pmucmcb@7e710000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e710000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmcb@7e730000 { - compatible = "apm,xgene-pmu-mcb"; - reg = <0x0 0x7e730000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e810000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e810000 0x0 0x1000>; - enable-bit-index = <0>; - }; - - pmucmc@7e850000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e850000 0x0 0x1000>; - enable-bit-index = <1>; - }; - - pmucmc@7e890000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e890000 0x0 0x1000>; - enable-bit-index = <2>; - }; - - pmucmc@7e8d0000 { - compatible = "apm,xgene-pmu-mc"; - reg = <0x0 0x7e8d0000 0x0 0x1000>; - enable-bit-index = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml index 8597ea625edb..d2e578d6b83b 100644 --- a/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml +++ b/Documentation/devicetree/bindings/perf/fsl-imx-ddr.yaml @@ -33,6 +33,7 @@ properties: - items: - enum: - fsl,imx91-ddr-pmu + - fsl,imx94-ddr-pmu - fsl,imx95-ddr-pmu - const: fsl,imx93-ddr-pmu diff --git a/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml b/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml index d9501df42886..c35d31642805 100644 --- a/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml +++ b/Documentation/devicetree/bindings/phy/marvell,comphy-cp110.yaml @@ -47,21 +47,19 @@ properties: const: 0 clocks: + minItems: 1 maxItems: 3 - description: Reference clocks for CP110; MG clock, MG Core clock, AXI clock clock-names: - items: - - const: mg_clk - - const: mg_core_clk - - const: axi_clk + minItems: 1 + maxItems: 3 marvell,system-controller: description: Phandle to the Marvell system controller (CP110 only) $ref: /schemas/types.yaml#/definitions/phandle patternProperties: - '^phy@[0-2]$': + '^phy@[0-5]$': description: A COMPHY lane child node type: object additionalProperties: false @@ -69,10 +67,14 @@ patternProperties: properties: reg: description: COMPHY lane number + maximum: 5 '#phy-cells': const: 1 + connector: + type: object + required: - reg - '#phy-cells' @@ -91,13 +93,24 @@ allOf: then: properties: - clocks: false - clock-names: false + clocks: + maxItems: 1 + clock-names: + const: xtal required: - reg-names else: + properties: + clocks: + minItems: 3 + clock-names: + items: + - const: mg_clk + - const: mg_core_clk + - const: axi_clk + required: - marvell,system-controller diff --git a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml index a1ae8c7988c8..b6f140bf5b3b 100644 --- a/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/qcom,sc8280xp-qmp-pcie-phy.yaml @@ -176,6 +176,8 @@ allOf: compatible: contains: enum: + - qcom,sa8775p-qmp-gen4x2-pcie-phy + - qcom,sa8775p-qmp-gen4x4-pcie-phy - qcom,sc8280xp-qmp-gen3x1-pcie-phy - qcom,sc8280xp-qmp-gen3x2-pcie-phy - qcom,sc8280xp-qmp-gen3x4-pcie-phy @@ -197,8 +199,6 @@ allOf: contains: enum: - qcom,qcs8300-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x2-pcie-phy - - qcom,sa8775p-qmp-gen4x4-pcie-phy then: properties: clocks: diff --git a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml index 63737d858944..665ec79a69f1 100644 --- a/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml @@ -16,17 +16,22 @@ description: | properties: compatible: - items: - - enum: - - apple,s5l8960x-pinctrl - - apple,t7000-pinctrl - - apple,s8000-pinctrl - - apple,t8010-pinctrl - - apple,t8015-pinctrl - - apple,t8103-pinctrl - - apple,t8112-pinctrl - - apple,t6000-pinctrl - - const: apple,pinctrl + oneOf: + - items: + - const: apple,t6020-pinctrl + - const: apple,t8103-pinctrl + - items: + # Do not add additional SoC to this list. + - enum: + - apple,s5l8960x-pinctrl + - apple,t7000-pinctrl + - apple,s8000-pinctrl + - apple,t8010-pinctrl + - apple,t8015-pinctrl + - apple,t8103-pinctrl + - apple,t8112-pinctrl + - apple,t6000-pinctrl + - const: apple,pinctrl reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml new file mode 100644 index 000000000000..ae6c13a746b9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2712c0-pinctrl.yaml @@ -0,0 +1,137 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2712c0-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom STB family pin controller + +maintainers: + - Ivan T. Ivanov <iivanov@suse.de> + - A. della Porta <andrea.porta@suse.com> + +description: > + Broadcom's STB family of memory-mapped pin controllers. + + This includes the pin controllers inside the BCM2712 SoC which + are instances of the STB family and has two silicon variants, + C0 and D0, which differs slightly in terms of registers layout. + + The -aon- (Always On) variant is the same IP block but differs + in the number of pins that are associated and the pinmux functions + for each of those pins. + +allOf: + - $ref: pinctrl.yaml# + +properties: + compatible: + enum: + - brcm,bcm2712c0-pinctrl + - brcm,bcm2712c0-aon-pinctrl + - brcm,bcm2712d0-pinctrl + - brcm,bcm2712d0-aon-pinctrl + + reg: + maxItems: 1 + +patternProperties: + '-state$': + oneOf: + - $ref: '#/$defs/brcmstb-pinctrl-state' + - patternProperties: + '-pins$': + $ref: '#/$defs/brcmstb-pinctrl-state' + additionalProperties: false + +$defs: + brcmstb-pinctrl-state: + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + + description: > + Pin controller client devices use pin configuration subnodes (children + and grandchildren) for desired pin configuration. + + Client device subnodes use below standard properties. + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode (either this or "groups" must be specified). + items: + pattern: '^((aon_)?s?gpio[0-6]?[0-9])|(emmc_(clk|cmd|dat[0-7]|ds))$' + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, alt1, alt2, alt3, alt4, alt5, alt6, alt7, alt8, + aon_cpu_standbyb, aon_fp_4sec_resetb, aon_gpclk, aon_pwm, + arm_jtag, aud_fs_clk0, avs_pmu_bsc, bsc_m0, bsc_m1, bsc_m2, + bsc_m3, clk_observe, ctl_hdmi_5v, enet0, enet0_mii, enet0_rgmii, + ext_sc_clk, fl0, fl1, gpclk0, gpclk1, gpclk2, hdmi_tx0_auto_i2c, + hdmi_tx0_bsc, hdmi_tx1_auto_i2c, hdmi_tx1_bsc, i2s_in, i2s_out, + ir_in, mtsif, mtsif_alt, mtsif_alt1, pdm, pkt, pm_led_out, sc0, + sd0, sd2, sd_card_a, sd_card_b, sd_card_c, sd_card_d, sd_card_e, + sd_card_f, sd_card_g, spdif_out, spi_m, spi_s, sr_edm_sense, te0, + te1, tsio, uart0, uart1, uart2, usb_pwr, usb_vbus, uui, vc_i2c0, + vc_i2c3, vc_i2c4, vc_i2c5, vc_i2csl, vc_pcm, vc_pwm0, vc_pwm1, + vc_spi0, vc_spi3, vc_spi4, vc_spi5, vc_uart0, vc_uart2, vc_uart3, + vc_uart4 ] + + bias-disable: true + bias-pull-down: true + bias-pull-up: true + + required: + - pins + + if: + properties: + pins: + not: + contains: + pattern: "^emmc_(clk|cmd|dat[0-7]|ds)$" + then: + required: + - function + else: + properties: + function: false + + additionalProperties: false + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + pinctrl@7d504100 { + compatible = "brcm,bcm2712c0-pinctrl"; + reg = <0x7d504100 0x30>; + + bt-shutdown-default-state { + function = "gpio"; + pins = "gpio29"; + }; + + uarta-default-state { + rts-tx-pins { + function = "uart0"; + pins = "gpio24", "gpio26"; + bias-disable; + }; + + cts-rx-pins { + function = "uart0"; + pins = "gpio25", "gpio27"; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt deleted file mode 100644 index 5682b2010e50..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.txt +++ /dev/null @@ -1,99 +0,0 @@ -Broadcom BCM2835 GPIO (and pinmux) controller - -The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt -controller, and pinmux/control device. - -Required properties: -- compatible: "brcm,bcm2835-gpio" -- compatible: should be one of: - "brcm,bcm2835-gpio" - BCM2835 compatible pinctrl - "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl - "brcm,bcm2711-gpio" - BCM2711 compatible pinctrl - "brcm,bcm7211-gpio" - BCM7211 compatible pinctrl -- reg: Should contain the physical address of the GPIO module's registers. -- gpio-controller: Marks the device node as a GPIO controller. -- #gpio-cells : Should be two. The first cell is the pin number and the - second cell is used to specify optional parameters: - - bit 0 specifies polarity (0 for normal, 1 for inverted) -- interrupts : The interrupt outputs from the controller. One interrupt per - individual bank followed by the "all banks" interrupt. For BCM7211, an - additional set of per-bank interrupt line and an "all banks" wake-up - interrupt may be specified. -- interrupt-controller: Marks the device node as an interrupt controller. -- #interrupt-cells : Should be 2. - The first cell is the GPIO number. - The second cell is used to specify flags: - bits[3:0] trigger type and level flags: - 1 = low-to-high edge triggered. - 2 = high-to-low edge triggered. - 4 = active high level-sensitive. - 8 = active low level-sensitive. - Valid combinations are 1, 2, 3, 4, 8. - -Please refer to ../gpio/gpio.txt for a general description of GPIO bindings. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices, including the meaning of the -phrase "pin configuration node". - -Each pin configuration node lists the pin(s) to which it applies, and one or -more of the mux function to select on those pin(s), and pull-up/down -configuration. Each subnode only affects those parameters that are explicitly -listed. In other words, a subnode that lists only a mux function implies no -information about any pull configuration. Similarly, a subnode that lists only -a pul parameter implies no information about the mux function. - -The BCM2835 pin configuration and multiplexing supports the generic bindings. -For details on each properties, you can refer to ./pinctrl-bindings.txt. - -Required sub-node properties: - - pins - - function - -Optional sub-node properties: - - bias-disable - - bias-pull-up - - bias-pull-down - - output-high - - output-low - -Legacy pin configuration and multiplexing binding: -*** (Its use is deprecated, use generic multiplexing and configuration -bindings instead) - -Required subnode-properties: -- brcm,pins: An array of cells. Each cell contains the ID of a pin. Valid IDs - are the integer GPIO IDs; 0==GPIO0, 1==GPIO1, ... 53==GPIO53. - -Optional subnode-properties: -- brcm,function: Integer, containing the function to mux to the pin(s): - 0: GPIO in - 1: GPIO out - 2: alt5 - 3: alt4 - 4: alt0 - 5: alt1 - 6: alt2 - 7: alt3 -- brcm,pull: Integer, representing the pull-down/up to apply to the pin(s): - 0: none - 1: down - 2: up - -Each of brcm,function and brcm,pull may contain either a single value which -will be applied to all pins in brcm,pins, or 1 value for each entry in -brcm,pins. - -Example: - - gpio: gpio { - compatible = "brcm,bcm2835-gpio"; - reg = <0x2200000 0xb4>; - interrupts = <2 17>, <2 19>, <2 18>, <2 20>; - - gpio-controller; - #gpio-cells = <2>; - - interrupt-controller; - #interrupt-cells = <2>; - }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml new file mode 100644 index 000000000000..6514f347f6bc --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,bcm2835-gpio.yaml @@ -0,0 +1,120 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,bcm2835-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 GPIO (and pinmux) controller + +maintainers: + - Florian Fainelli <f.fainelli@gmail.com> + +description: > + The BCM2835 GPIO module is a combined GPIO controller, (GPIO) interrupt + controller, and pinmux/control device. + +properties: + compatible: + enum: + - brcm,bcm2835-gpio + - brcm,bcm2711-gpio + - brcm,bcm7211-gpio + + reg: + maxItems: 1 + + '#gpio-cells': + const: 2 + + gpio-controller: true + gpio-ranges: true + gpio-line-names: true + + interrupts: + description: > + Interrupt outputs: one per bank, then the combined “all banks” line. + BCM7211 may specify up to four per-bank wake-up lines and one combined + wake-up interrupt. + minItems: 4 + maxItems: 10 + + '#interrupt-cells': + const: 2 + + interrupt-controller: true + +additionalProperties: + oneOf: + - type: object + additionalProperties: false + + patternProperties: + '^pins?-': + type: object + allOf: + - $ref: /schemas/pinctrl/pincfg-node.yaml# + - $ref: /schemas/pinctrl/pinmux-node.yaml# + additionalProperties: false + + properties: + pins: true + function: true + bias-disable: true + bias-pull-up: true + bias-pull-down: true + output-high: true + output-low: true + + required: + - pins + - function + + - type: object + additionalProperties: false + deprecated: true + + properties: + brcm,pins: + description: + GPIO pin numbers for legacy configuration. + $ref: /schemas/types.yaml#/definitions/uint32-array + + brcm,function: + description: + Legacy mux function for the pins (0=input, 1=output, 2–7=alt functions). + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 7 + + brcm,pull: + description: > + Legacy pull setting for the pins (0=none, 1=pull-down, 2=pull-up). + $ref: /schemas/types.yaml#/definitions/uint32-array + maximum: 2 + + required: + - brcm,pins + +allOf: + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm2835-gpio + - brcm,bcm2711-gpio + then: + properties: + interrupts: + maxItems: 5 + +examples: + - | + gpio@2200000 { + compatible = "brcm,bcm2835-gpio"; + reg = <0x2200000 0xb4>; + interrupts = <2 17>, <2 19>, <2 18>, <2 20>, <2 21>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupt-controller; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt deleted file mode 100644 index a73cbeb0f309..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.txt +++ /dev/null @@ -1,123 +0,0 @@ -Broadcom iProc GPIO/PINCONF Controller - -Required properties: - -- compatible: - "brcm,iproc-gpio" for the generic iProc based GPIO controller IP that - supports full-featured pinctrl and GPIO functions used in various iProc - based SoCs - - May contain an SoC-specific compatibility string to accommodate any - SoC-specific features - - "brcm,cygnus-ccm-gpio", "brcm,cygnus-asiu-gpio", or - "brcm,cygnus-crmu-gpio" for Cygnus SoCs - - "brcm,iproc-nsp-gpio" for the iProc NSP SoC that has drive strength support - disabled - - "brcm,iproc-stingray-gpio" for the iProc Stingray SoC that has the general - pinctrl support completely disabled in this IP block. In Stingray, a - different IP block is used to handle pinctrl related functions - -- reg: - Define the base and range of the I/O address space that contains SoC -GPIO/PINCONF controller registers - -- ngpios: - Total number of in-use slots in GPIO controller - -- #gpio-cells: - Must be two. The first cell is the GPIO pin number (within the -controller's pin space) and the second cell is used for the following: - bit[0]: polarity (0 for active high and 1 for active low) - -- gpio-controller: - Specifies that the node is a GPIO controller - -Optional properties: - -- interrupts: - Interrupt ID - -- interrupt-controller: - Specifies that the node is an interrupt controller - -- gpio-ranges: - Specifies the mapping between gpio controller and pin-controllers pins. - This requires 4 fields in cells defined as - - 1. Phandle of pin-controller. - 2. GPIO base pin offset. - 3 Pin-control base pin offset. - 4. number of gpio pins which are linearly mapped from pin base. - -Supported generic PINCONF properties in child nodes: - -- pins: - The list of pins (within the controller's own pin space) that properties -in the node apply to. Pin names are "gpio-<pin>" - -- bias-disable: - Disable pin bias - -- bias-pull-up: - Enable internal pull up resistor - -- bias-pull-down: - Enable internal pull down resistor - -- drive-strength: - Valid drive strength values include 2, 4, 6, 8, 10, 12, 14, 16 (mA) - -Example: - gpio_ccm: gpio@1800a000 { - compatible = "brcm,cygnus-ccm-gpio"; - reg = <0x1800a000 0x50>, - <0x0301d164 0x20>; - ngpios = <24>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - - touch_pins: touch_pins { - pwr: pwr { - pins = "gpio-0"; - drive-strength = <16>; - }; - - event: event { - pins = "gpio-1"; - bias-pull-up; - }; - }; - }; - - gpio_asiu: gpio@180a5000 { - compatible = "brcm,cygnus-asiu-gpio"; - reg = <0x180a5000 0x668>; - ngpios = <146>; - #gpio-cells = <2>; - gpio-controller; - interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; - interrupt-controller; - gpio-ranges = <&pinctrl 0 42 1>, - <&pinctrl 1 44 3>; - }; - - /* - * Touchscreen that uses the CCM GPIO 0 and 1 - */ - tsc { - ... - ... - gpio-pwr = <&gpio_ccm 0 0>; - gpio-event = <&gpio_ccm 1 0>; - }; - - /* Bluetooth that uses the ASIU GPIO 5, with polarity inverted */ - bluetooth { - ... - ... - bcm,rfkill-bank-sel = <&gpio_asiu 5 1> - } diff --git a/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml new file mode 100644 index 000000000000..a0ed308b7fc8 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/brcm,iproc-gpio.yaml @@ -0,0 +1,111 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/brcm,iproc-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom iProc GPIO/PINCONF Controller + +maintainers: + - Ray Jui <rjui@broadcom.com> + - Scott Branden <sbranden@broadcom.com> + +properties: + compatible: + oneOf: + - enum: + - brcm,cygnus-asiu-gpio + - brcm,cygnus-ccm-gpio + - brcm,cygnus-crmu-gpio + - brcm,iproc-gpio + - brcm,iproc-stingray-gpio + - items: + - enum: + - brcm,iproc-hr2-gpio + - brcm,iproc-nsp-gpio + - const: brcm,iproc-gpio + + reg: + minItems: 1 + items: + - description: GPIO Bank registers + - description: IO Ctrl registers + + "#gpio-cells": + const: 2 + + gpio-controller: true + + gpio-ranges: true + + ngpios: true + + "#interrupt-cells": + const: 2 + + interrupts: + maxItems: 1 + + interrupt-controller: true + +required: + - compatible + - reg + - "#gpio-cells" + - gpio-controller + - ngpios + +patternProperties: + '-pins$': + type: object + additionalProperties: + description: Pin configuration child nodes. + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + additionalProperties: false + + properties: + pins: + items: + pattern: '^gpio-' + + bias-disable: true + bias-pull-up: true + bias-pull-down: true + + drive-strength: + enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] + + required: + - pins + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + + gpio@1800a000 { + compatible = "brcm,cygnus-ccm-gpio"; + reg = <0x1800a000 0x50>, + <0x0301d164 0x20>; + ngpios = <24>; + #gpio-cells = <2>; + gpio-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + interrupt-controller; + + touch-pins { + pwr { + pins = "gpio-0"; + drive-strength = <16>; + }; + + event { + pins = "gpio-1"; + bias-pull-up; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt b/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt deleted file mode 100644 index 1e70a8aff260..000000000000 --- a/Documentation/devicetree/bindings/pinctrl/fsl,mxs-pinctrl.txt +++ /dev/null @@ -1,127 +0,0 @@ -* Freescale MXS Pin Controller - -The pins controlled by mxs pin controller are organized in banks, each bank -has 32 pins. Each pin has 4 multiplexing functions, and generally, the 4th -function is GPIO. The configuration on the pins includes drive strength, -voltage and pull-up. - -Required properties: -- compatible: "fsl,imx23-pinctrl" or "fsl,imx28-pinctrl" -- reg: Should contain the register physical address and length for the - pin controller. - -Please refer to pinctrl-bindings.txt in this directory for details of the -common pinctrl bindings used by client devices. - -The node of mxs pin controller acts as a container for an arbitrary number of -subnodes. Each of these subnodes represents some desired configuration for -a group of pins, and only affects those parameters that are explicitly listed. -In other words, a subnode that describes a drive strength parameter implies no -information about pull-up. For this reason, even seemingly boolean values are -actually tristates in this binding: unspecified, off, or on. Unspecified is -represented as an absent property, and off/on are represented as integer -values 0 and 1. - -Those subnodes under mxs pin controller node will fall into two categories. -One is to set up a group of pins for a function, both mux selection and pin -configurations, and it's called group node in the binding document. The other -one is to adjust the pin configuration for some particular pins that need a -different configuration than what is defined in group node. The binding -document calls this type of node config node. - -On mxs, there is no hardware pin group. The pin group in this binding only -means a group of pins put together for particular peripheral to work in -particular function, like SSP0 functioning as mmc0-8bit. That said, the -group node should include all the pins needed for one function rather than -having these pins defined in several group nodes. It also means each of -"pinctrl-*" phandle in client device node should only have one group node -pointed in there, while the phandle can have multiple config node referenced -there to adjust configurations for some pins in the group. - -Required subnode-properties: -- fsl,pinmux-ids: An integer array. Each integer in the array specify a pin - with given mux function, with bank, pin and mux packed as below. - - [15..12] : bank number - [11..4] : pin number - [3..0] : mux selection - - This integer with mux selection packed is used as an entity by both group - and config nodes to identify a pin. The mux selection in the integer takes - effects only on group node, and will get ignored by driver with config node, - since config node is only meant to set up pin configurations. - - Valid values for these integers are listed below. - -- reg: Should be the index of the group nodes for same function. This property - is required only for group nodes, and should not be present in any config - nodes. - -Optional subnode-properties: -- fsl,drive-strength: Integer. - 0: MXS_DRIVE_4mA - 1: MXS_DRIVE_8mA - 2: MXS_DRIVE_12mA - 3: MXS_DRIVE_16mA -- fsl,voltage: Integer. - 0: MXS_VOLTAGE_LOW - 1.8 V - 1: MXS_VOLTAGE_HIGH - 3.3 V -- fsl,pull-up: Integer. - 0: MXS_PULL_DISABLE - Disable the internal pull-up - 1: MXS_PULL_ENABLE - Enable the internal pull-up - -Note that when enabling the pull-up, the internal pad keeper gets disabled. -Also, some pins doesn't have a pull up, in that case, setting the fsl,pull-up -will only disable the internal pad keeper. - -Examples: - -pinctrl@80018000 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx28-pinctrl"; - reg = <0x80018000 2000>; - - mmc0_8bit_pins_a: mmc0-8bit@0 { - reg = <0>; - fsl,pinmux-ids = < - MX28_PAD_SSP0_DATA0__SSP0_D0 - MX28_PAD_SSP0_DATA1__SSP0_D1 - MX28_PAD_SSP0_DATA2__SSP0_D2 - MX28_PAD_SSP0_DATA3__SSP0_D3 - MX28_PAD_SSP0_DATA4__SSP0_D4 - MX28_PAD_SSP0_DATA5__SSP0_D5 - MX28_PAD_SSP0_DATA6__SSP0_D6 - MX28_PAD_SSP0_DATA7__SSP0_D7 - MX28_PAD_SSP0_CMD__SSP0_CMD - MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT - MX28_PAD_SSP0_SCK__SSP0_SCK - >; - fsl,drive-strength = <MXS_DRIVE_4mA>; - fsl,voltage = <MXS_VOLTAGE_HIGH>; - fsl,pull-up = <MXS_PULL_ENABLE>; - }; - - mmc_cd_cfg: mmc-cd-cfg { - fsl,pinmux-ids = <MX28_PAD_SSP0_DETECT__SSP0_CARD_DETECT>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; - - mmc_sck_cfg: mmc-sck-cfg { - fsl,pinmux-ids = <MX28_PAD_SSP0_SCK__SSP0_SCK>; - fsl,drive-strength = <MXS_DRIVE_12mA>; - fsl,pull-up = <MXS_PULL_DISABLE>; - }; -}; - -In this example, group node mmc0-8bit defines a group of pins for mxs SSP0 -to function as a 8-bit mmc device, with 8mA, 3.3V and pull-up configurations -applied on all these pins. And config nodes mmc-cd-cfg and mmc-sck-cfg are -adjusting the configuration for pins card-detection and clock from what group -node mmc0-8bit defines. Only the configuration properties to be adjusted need -to be listed in the config nodes. - -Valid values for i.MX28/i.MX23 pinmux-id are defined in -arch/arm/boot/dts/imx28-pinfunc.h and arch/arm/boot/dts/imx23-pinfunc.h. -The definitions for the padconfig properties can be found in -arch/arm/boot/dts/mxs-pinfunc.h. diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml index b9680b896f12..aa71398cf522 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml @@ -43,6 +43,8 @@ properties: the amount of cells must be specified as 2. See the below mentioned gpio binding representation for description of particular cells. + gpio-line-names: true + mediatek,pctl-regmap: $ref: /schemas/types.yaml#/definitions/phandle-array items: diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml index 9acca85184fa..6b925c5099cc 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml @@ -19,10 +19,11 @@ properties: - mediatek,mt7629-pinctrl reg: - maxItems: 1 + maxItems: 2 reg-names: items: + - const: base - const: eint gpio-controller: true @@ -204,7 +205,7 @@ patternProperties: pwm_ch2_2, pwm_ch3_0, pwm_ch3_1, pwm_ch3_2, pwm_ch4_0, pwm_ch4_1, pwm_ch4_2, pwm_ch4_3, pwm_ch5_0, pwm_ch5_1, pwm_ch5_2, pwm_ch6_0, pwm_ch6_1, pwm_ch6_2, pwm_ch6_3, - pwm_ch7_0, pwm_0, pwm_1] + pwm_ch7_0, pwm_ch7_2, pwm_0, pwm_1] - if: properties: function: @@ -367,7 +368,8 @@ examples: pio: pinctrl@10211000 { compatible = "mediatek,mt7622-pinctrl"; - reg = <0 0x10211000 0 0x1000>; + reg = <0 0x10211000 0 0x1000>, + <0 0x10005000 0 0x1000>; gpio-controller; #gpio-cells = <2>; diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml index 464879274cae..3db2438fadc7 100644 --- a/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml @@ -48,6 +48,8 @@ properties: description: GPIO valid number range. + gpio-line-names: true + interrupt-controller: true interrupts: diff --git a/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml new file mode 100644 index 000000000000..ac764d0ac4b6 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/nvidia,tegra186-pinmux.yaml @@ -0,0 +1,285 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/nvidia,tegra186-pinmux.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra186 Pinmux Controller + +maintainers: + - Thierry Reding <thierry.reding@gmail.com> + - Jon Hunter <jonathanh@nvidia.com> + +properties: + compatible: + enum: + - nvidia,tegra186-pinmux + - nvidia,tegra186-pinmux-aon + + reg: + items: + - description: pinmux registers + +patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + + # pin groups + additionalProperties: + $ref: nvidia,tegra-pinmux-common.yaml + unevaluatedProperties: false + properties: + nvidia,function: + enum: [ aud, can0, can1, ccla, dca, dcb, dcc, directdc, directdc1, + displaya, displayb, dmic1, dmic2, dmic3, dmic4, dmic5, dp, + dspk0, dspk1, dtv, eqos, extperiph1, extperiph2, extperiph3, + extperiph4, gp, gpio, hdmi, i2c1, i2c2, i2c3, i2c5, i2c7, + i2c8, i2c9, i2s1, i2s2, i2s3, i2s4, i2s5, i2s6, iqc0, iqc1, + nv, pe, pe0, pe1, pe2, qspi, rsvd0, rsvd1, rsvd2, rsvd3, + sata, sce, sdmmc1, sdmmc2, sdmmc3, sdmmc4, soc, spdif, spi1, + spi2, spi3, spi4, touch, uarta, uartb, uartc, uartd, uarte, + uartf, uartg, ufs0, usb, vgp1, vgp2, vgp3, vgp4, vgp5, vgp6, + wdt ] + + nvidia,pull: true + nvidia,tristate: true + nvidia,schmitt: true + nvidia,enable-input: true + nvidia,open-drain: true + nvidia,lock: true + nvidia,drive-type: true + nvidia,io-hv: true + + required: + - nvidia,pins + +additionalProperties: false + +allOf: + - if: + properties: + compatible: + const: nvidia,tegra186-pinmux + then: + patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + description: An array of strings. Each string contains the name + of a pin or group. Valid values for these names are listed + below. + items: + enum: [ pex_l0_rst_n_pa0, pex_l0_clkreq_n_pa1, + pex_wake_n_pa2, pex_l1_rst_n_pa3, + pex_l1_clkreq_n_pa4, pex_l2_rst_n_pa5, + pex_l2_clkreq_n_pa6, uart4_tx_pb0, uart4_rx_pb1, + uart4_rts_pb2, uart4_cts_pb3, gpio_wan1_pb4, + gpio_wan2_pb5, gpio_wan3_pb6, gpio_wan4_pc0, + dap2_sclk_pc1, dap2_dout_pc2, dap2_din_pc3, + dap2_fs_pc4, gen1_i2c_scl_pc5, gen1_i2c_sda_pc6, + sdmmc1_clk_pd0, sdmmc1_cmd_pd1, sdmmc1_dat0_pd2, + sdmmc1_dat1_pd3, sdmmc1_dat2_pd4, sdmmc1_dat3_pd5, + eqos_txc_pe0, eqos_td0_pe1, eqos_td1_pe2, + eqos_td2_pe3, eqos_td3_pe4, eqos_tx_ctl_pe5, + eqos_rd0_pe6, eqos_rd1_pe7, eqos_rd2_pf0, + eqos_rd3_pf1, eqos_rx_ctl_pf2, eqos_rxc_pf3, + eqos_mdio_pf4, eqos_mdc_pf5, sdmmc3_clk_pg0, + sdmmc3_cmd_pg1, sdmmc3_dat0_pg2, sdmmc3_dat1_pg3, + sdmmc3_dat2_pg4, sdmmc3_dat3_pg5, gpio_wan5_ph0, + gpio_wan6_ph1, gpio_wan7_ph2, gpio_wan8_ph3, + bcpu_pwr_req_ph4, mcpu_pwr_req_ph5, gpu_pwr_req_ph6, + gpio_pq0_pi0, gpio_pq1_pi1, gpio_pq2_pi2, + gpio_pq3_pi3, gpio_pq4_pi4, gpio_pq5_pi5, + gpio_pq6_pi6, gpio_pq7_pi7, dap1_sclk_pj0, + dap1_dout_pj1, dap1_din_pj2, dap1_fs_pj3, + aud_mclk_pj4, gpio_aud0_pj5, gpio_aud1_pj6, + gpio_aud2_pj7, gpio_aud3_pk0, gen7_i2c_scl_pl0, + gen7_i2c_sda_pl1, gen9_i2c_scl_pl2, gen9_i2c_sda_pl3, + usb_vbus_en0_pl4, usb_vbus_en1_pl5, gp_pwm6_pl6, + gp_pwm7_pl7, dmic1_dat_pm0, dmic1_clk_pm1, + dmic2_dat_pm2, dmic2_clk_pm3, dmic4_dat_pm4, + dmic4_clk_pm5, gpio_cam1_pn0, gpio_cam2_pn1, + gpio_cam3_pn2, gpio_cam4_pn3, gpio_cam6_pn5, + gpio_cam7_pn6, extperiph1_clk_po0, + extperiph2_clk_po1, cam_i2c_scl_po2, cam_i2c_sda_po3, + dp_aux_ch0_hpd_pp0, dp_aux_ch1_hpd_pp1, hdmi_cec_pp2, + gpio_edp0_pp3, gpio_edp1_pp4, gpio_edp2_pp5, + gpio_edp3_pp6, directdc1_clk_pq0, directdc1_in_pq1, + directdc1_out0_pq2, directdc1_out1_pq3, + directdc1_out2_pq4, directdc1_out3_pq5, + qspi_sck_pr0, qspi_io0_pr1, qspi_io1_pr2, + qspi_io2_pr3, qspi_io3_pr4, qspi_cs_n_pr5, + uart1_tx_pt0, uart1_rx_pt1, uart1_rts_pt2, + uart1_cts_pt3, uart2_tx_px0, uart2_rx_px1, + uart2_rts_px2, uart2_cts_px3, uart5_tx_px4, + uart5_rx_px5, uart5_rts_px6, uart5_cts_px7, + gpio_mdm1_py0, gpio_mdm2_py1, gpio_mdm3_py2, + gpio_mdm4_py3, gpio_mdm5_py4, gpio_mdm6_py5, + gpio_mdm7_py6, ufs0_ref_clk_pbb0, ufs0_rst_pbb1, + dap4_sclk_pcc0, dap4_dout_pcc1, dap4_din_pcc2, + dap4_fs_pcc3, directdc_comp, sdmmc1_comp, eqos_comp, + sdmmc3_comp, qspi_comp, + # drive groups + drive_gpio_aud3_pk0, drive_gpio_aud2_pj7, + drive_gpio_aud1_pj6, drive_gpio_aud0_pj5, + drive_aud_mclk_pj4, drive_dap1_fs_pj3, + drive_dap1_din_pj2, drive_dap1_dout_pj1, + drive_dap1_sclk_pj0, drive_dmic1_clk_pm1, + drive_dmic1_dat_pm0, drive_dmic2_dat_pm2, + drive_dmic2_clk_pm3, drive_dmic4_dat_pm4, + drive_dmic4_clk_pm5, drive_dap4_fs_pcc3, + drive_dap4_din_pcc2, drive_dap4_dout_pcc1, + drive_dap4_sclk_pcc0, drive_extperiph2_clk_po1, + drive_extperiph1_clk_po0, drive_cam_i2c_sda_po3, + drive_cam_i2c_scl_po2, drive_gpio_cam1_pn0, + drive_gpio_cam2_pn1, drive_gpio_cam3_pn2, + drive_gpio_cam4_pn3, drive_gpio_cam5_pn4, + drive_gpio_cam6_pn5, drive_gpio_cam7_pn6, + drive_dap2_din_pc3, drive_dap2_dout_pc2, + drive_dap2_fs_pc4, drive_dap2_sclk_pc1, + drive_uart4_cts_pb3, drive_uart4_rts_pb2, + drive_uart4_rx_pb1, drive_uart4_tx_pb0, + drive_gpio_wan4_pc0, drive_gpio_wan3_pb6, + drive_gpio_wan2_pb5, drive_gpio_wan1_pb4, + drive_gen1_i2c_scl_pc5, drive_gen1_i2c_sda_pc6, + drive_uart1_cts_pt3, drive_uart1_rts_pt2, + drive_uart1_rx_pt1, drive_uart1_tx_pt0, + drive_directdc1_out3_pq5, drive_directdc1_out2_pq4, + drive_directdc1_out1_pq3, drive_directdc1_out0_pq2, + drive_directdc1_in_pq1, drive_directdc1_clk_pq0, + drive_gpio_pq0_pi0, drive_gpio_pq1_pi1, + drive_gpio_pq2_pi2, drive_gpio_pq3_pi3, + drive_gpio_pq4_pi4, drive_gpio_pq5_pi5, + drive_gpio_pq6_pi6, drive_gpio_pq7_pi7, + drive_gpio_edp2_pp5, drive_gpio_edp3_pp6, + drive_gpio_edp0_pp3, drive_gpio_edp1_pp4, + drive_dp_aux_ch0_hpd_pp0, drive_dp_aux_ch1_hpd_pp1, + drive_hdmi_cec_pp2, drive_pex_l2_clkreq_n_pa6, + drive_pex_wake_n_pa2, drive_pex_l1_clkreq_n_pa4, + drive_pex_l1_rst_n_pa3, drive_pex_l0_clkreq_n_pa1, + drive_pex_l0_rst_n_pa0, drive_pex_l2_rst_n_pa5, + drive_sdmmc1_clk_pd0, drive_sdmmc1_cmd_pd1, + drive_sdmmc1_dat3_pd5, drive_sdmmc1_dat2_pd4, + drive_sdmmc1_dat1_pd3, drive_sdmmc1_dat0_pd2, + drive_eqos_td3_pe4, drive_eqos_td2_pe3, + drive_eqos_td1_pe2, drive_eqos_td0_pe1, + drive_eqos_rd3_pf1, drive_eqos_rd2_pf0, + drive_eqos_rd1_pe7, drive_eqos_mdio_pf4, + drive_eqos_rd0_pe6, drive_eqos_mdc_pf5, + drive_eqos_txc_pe0, drive_eqos_rxc_pf3, + drive_eqos_tx_ctl_pe5, drive_eqos_rx_ctl_pf2, + drive_sdmmc3_dat3_pg5, drive_sdmmc3_dat2_pg4, + drive_sdmmc3_dat1_pg3, drive_sdmmc3_dat0_pg2, + drive_sdmmc3_cmd_pg1, drive_sdmmc3_clk_pg0, + drive_qspi_io3_pr4, drive_qspi_io2_pr3, + drive_qspi_io1_pr2, drive_qspi_io0_pr1, + drive_qspi_sck_pr0, drive_qspi_cs_n_pr5, + drive_gpio_wan8_ph3, drive_gpio_wan7_ph2, + drive_gpio_wan6_ph1, drive_gpio_wan5_ph0, + drive_uart2_tx_px0, drive_uart2_rx_px1, + drive_uart2_rts_px2, drive_uart2_cts_px3, + drive_uart5_rx_px5, drive_uart5_tx_px4, + drive_uart5_rts_px6, drive_uart5_cts_px7, + drive_gpio_mdm1_py0, drive_gpio_mdm2_py1, + drive_gpio_mdm3_py2, drive_gpio_mdm4_py3, + drive_gpio_mdm5_py4, drive_gpio_mdm6_py5, + drive_gpio_mdm7_py6, drive_bcpu_pwr_req_ph4, + drive_mcpu_pwr_req_ph5, drive_gpu_pwr_req_ph6, + drive_gen7_i2c_scl_pl0, drive_gen7_i2c_sda_pl1, + drive_gen9_i2c_sda_pl3, drive_gen9_i2c_scl_pl2, + drive_usb_vbus_en0_pl4, drive_usb_vbus_en1_pl5, + drive_gp_pwm7_pl7, drive_gp_pwm6_pl6, + drive_ufs0_rst_pbb1, drive_ufs0_ref_clk_pbb0, + drive_directdc_comp, drive_sdmmc1_comp, + drive_eqos_comp, drive_sdmmc3_comp, drive_sdmmc4_clk, + drive_sdmmc4_cmd, drive_sdmmc4_dqs, + drive_sdmmc4_dat7, drive_sdmmc4_dat6, + drive_sdmmc4_dat5, drive_sdmmc4_dat4, + drive_sdmmc4_dat3, drive_sdmmc4_dat2, + drive_sdmmc4_dat1, drive_sdmmc4_dat0, + drive_qspi_comp ] + + - if: + properties: + compatible: + const: nvidia,tegra186-pinmux-aon + then: + patternProperties: + "^pinmux(-[a-z0-9-]+)?$": + type: object + additionalProperties: + properties: + nvidia,pins: + items: + enum: [ pwr_i2c_scl_ps0, pwr_i2c_sda_ps1, batt_oc_ps2, + safe_state_ps3, vcomp_alert_ps4, gpio_dis0_pu0, + gpio_dis1_pu1, gpio_dis2_pu2, gpio_dis3_pu3, + gpio_dis4_pu4, gpio_dis5_pu5, gpio_sen0_pv0, + gpio_sen1_pv1, gpio_sen2_pv2, gpio_sen3_pv3, + gpio_sen4_pv4, gpio_sen5_pv5, gpio_sen6_pv6, + gpio_sen7_pv7, gen8_i2c_scl_pw0, gen8_i2c_sda_pw1, + uart3_tx_pw2, uart3_rx_pw3, uart3_rts_pw4, + uart3_cts_pw5, uart7_tx_pw6, uart7_rx_pw7, + can1_dout_pz0, can1_din_pz1, can0_dout_pz2, + can0_din_pz3, can_gpio0_paa0, can_gpio1_paa1, + can_gpio2_paa2, can_gpio3_paa3, can_gpio4_paa4, + can_gpio5_paa5, can_gpio6_paa6, can_gpio7_paa7, + gpio_sen8_pee0, gpio_sen9_pee1, touch_clk_pee2, + power_on_pff0, gpio_sw1_pff1, gpio_sw2_pff2, + gpio_sw3_pff3, gpio_sw4_pff4, shutdown, pmu_int, + soc_pwr_req, clk_32k_in, + # drive groups + drive_touch_clk_pee2, drive_uart3_cts_pw5, + drive_uart3_rts_pw4, drive_uart3_rx_pw3, + drive_uart3_tx_pw2, drive_gen8_i2c_sda_pw1, + drive_gen8_i2c_scl_pw0, drive_uart7_rx_pw7, + drive_uart7_tx_pw6, drive_gpio_sen0_pv0, + drive_gpio_sen1_pv1, drive_gpio_sen2_pv2, + drive_gpio_sen3_pv3, drive_gpio_sen4_pv4, + drive_gpio_sen5_pv5, drive_gpio_sen6_pv6, + drive_gpio_sen7_pv7, drive_gpio_sen8_pee0, + drive_gpio_sen9_pee1, drive_can_gpio7_paa7, + drive_can1_dout_pz0, drive_can1_din_pz1, + drive_can0_dout_pz2, drive_can0_din_pz3, + drive_can_gpio0_paa0, drive_can_gpio1_paa1, + drive_can_gpio2_paa2, drive_can_gpio3_paa3, + drive_can_gpio4_paa4, drive_can_gpio5_paa5, + drive_can_gpio6_paa6, drive_gpio_sw1_pff1, + drive_gpio_sw2_pff2, drive_gpio_sw3_pff3, + drive_gpio_sw4_pff4, drive_shutdown, drive_pmu_int, + drive_safe_state_ps3, drive_vcomp_alert_ps4, + drive_soc_pwr_req, drive_batt_oc_ps2, + drive_clk_32k_in, drive_power_on_pff0, + drive_pwr_i2c_scl_ps0, drive_pwr_i2c_sda_ps1, + drive_gpio_dis0_pu0, drive_gpio_dis1_pu1, + drive_gpio_dis2_pu2, drive_gpio_dis3_pu3, + drive_gpio_dis4_pu4, drive_gpio_dis5_pu5 ] + +required: + - compatible + - reg + +examples: + - | + #include <dt-bindings/pinctrl/pinctrl-tegra.h> + + pinmux@2430000 { + compatible = "nvidia,tegra186-pinmux"; + reg = <0x2430000 0x15000>; + + pinctrl-names = "jetson_io"; + pinctrl-0 = <&jetson_io_pinmux>; + + jetson_io_pinmux: pinmux { + hdr40-pin7 { + nvidia,pins = "aud_mclk_pj4"; + nvidia,function = "aud"; + nvidia,pull = <TEGRA_PIN_PULL_DOWN>; + nvidia,tristate = <TEGRA_PIN_DISABLE>; + nvidia,enable-input = <TEGRA_PIN_DISABLE>; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml new file mode 100644 index 000000000000..d2b0cfeffb50 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,glymur-tlmm.yaml @@ -0,0 +1,133 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,glymur-tlmm.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. Glymur TLMM block + +maintainers: + - Bjorn Andersson <bjorn.andersson@oss.qualcomm.com> + +description: + Top Level Mode Multiplexer pin controller in Qualcomm Glymur SoC. + +allOf: + - $ref: /schemas/pinctrl/qcom,tlmm-common.yaml# + +properties: + compatible: + const: qcom,glymur-tlmm + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + gpio-reserved-ranges: + minItems: 1 + maxItems: 125 + + gpio-line-names: + maxItems: 250 + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-glymur-tlmm-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-glymur-tlmm-state" + additionalProperties: false + +$defs: + qcom-glymur-tlmm-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + oneOf: + - pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|2[0-4][0-9])$" + - enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ] + minItems: 1 + maxItems: 36 + + function: + description: + Specify the alternative function to be configured for the specified + pins. + enum: [ gpio, resout_gpio_n, aoss_cti, asc_cci, atest_char, atest_usb, + audio_ext_mclk0, audio_ext_mclk1, audio_ref_clk, cam_asc_mclk4, + cam_mclk, cci_async_in, cci_i2c_scl, cci_i2c_sda, cci_timer, + cmu_rng, cri_trng, dbg_out_clk, ddr_bist_complete, + ddr_bist_fail, ddr_bist_start, ddr_bist_stop, ddr_pxi, + edp0_hot, edp0_lcd, edp1_lcd, egpio, eusb0_ac_en, eusb1_ac_en, + eusb2_ac_en, eusb3_ac_en, eusb5_ac_en, eusb6_ac_en, gcc_gp1, + gcc_gp2, gcc_gp3, host2wlan_sol, i2c0_s_scl, i2c0_s_sda, + i2s0_data, i2s0_sck, i2s0_ws, i2s1_data, i2s1_sck, i2s1_ws, + ibi_i3c, jitter_bist, mdp_vsync_out, mdp_vsync_e, mdp_vsync_p, + mdp_vsync_s, pcie3a_clk, pcie3a_rst_n, pcie3b_clk, + pcie4_clk_req_n, pcie5_clk_req_n, pcie6_clk_req_n, phase_flag, + pll_bist_sync, pll_clk_aux, pmc_oca_n, pmc_uva_n, prng_rosc, + qdss_cti, qdss_gpio, qspi, qup0_se0, qup0_se1, qup0_se2, + qup0_se3_l0, qup0_se3, qup0_se4, qup0_se5, qup0_se6, qup0_se7, + qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4, qup1_se5, + qup1_se6, qup1_se7, qup2_se0, qup2_se1, qup2_se2, qup2_se3, + qup2_se4, qup2_se5, qup2_se6, qup2_se7, qup3_se0, qup3_se1, + sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data, smb_acok_n, + sys_throttle, tb_trig_sdc2, tb_trig_sdc4, tmess_prng, + tsense_pwm, tsense_therm, usb0_dp, usb0_phy_ps, usb0_sbrx, + usb0_sbtx, usb0_tmu, usb1_dbg, usb1_dp, usb1_phy_ps, usb1_sbrx, + usb1_sbtx, usb1_tmu, usb2_dp, usb2_phy_ps, usb2_sbrx, usb2_sbtx, + usb2_tmu, vsense_trigger_mirnat, wcn_sw, wcn_sw_ctrl ] + + required: + - pins + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + tlmm: pinctrl@f100000 { + compatible = "qcom,glymur-tlmm"; + reg = <0x0f100000 0xf00000>; + interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + gpio-ranges = <&tlmm 0 0 249>; + wakeup-parent = <&pdc>; + gpio-reserved-ranges = <4 4>, <10 2>, <33 3>, <44 4>; + qup_uart21_default: qup-uart21-default-state { + tx-pins { + pins = "gpio86"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + + rx-pins { + pins = "gpio87"; + function = "qup2_se5"; + drive-strength = <2>; + bias-disable; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml index 08801cc4e476..bc7b8dda8837 100644 --- a/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sc7280-lpass-lpi-pinctrl.yaml @@ -20,6 +20,16 @@ properties: reg: maxItems: 2 + clocks: + items: + - description: LPASS Core voting clock + - description: LPASS Audio voting clock + + clock-names: + items: + - const: core + - const: audio + patternProperties: "-state$": oneOf: @@ -70,10 +80,16 @@ unevaluatedProperties: false examples: - | + #include <dt-bindings/sound/qcom,q6afe.h> lpass_tlmm: pinctrl@33c0000 { compatible = "qcom,sc7280-lpass-lpi-pinctrl"; reg = <0x33c0000 0x20000>, <0x3550000 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + gpio-controller; #gpio-cells = <2>; gpio-ranges = <&lpass_tlmm 0 0 15>; diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml new file mode 100644 index 000000000000..409e5a4d4da9 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml @@ -0,0 +1,109 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/qcom,sdm660-lpass-lpi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SDM660 SoC LPASS LPI TLMM + +maintainers: + - Nickolay Goppen <setotau@mainlining.org> + +description: + Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem + (LPASS) Low Power Island (LPI) of Qualcomm SDM660 SoC. + +properties: + compatible: + const: qcom,sdm660-lpass-lpi-pinctrl + + reg: + items: + - description: LPASS LPI TLMM Control and Status registers + +patternProperties: + "-state$": + oneOf: + - $ref: "#/$defs/qcom-sdm660-lpass-state" + - patternProperties: + "-pins$": + $ref: "#/$defs/qcom-sdm660-lpass-state" + additionalProperties: false + +$defs: + qcom-sdm660-lpass-state: + type: object + description: + Pinctrl node's client devices use subnodes for desired pin configuration. + Client device subnodes use below standard properties. + $ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state + unevaluatedProperties: false + + properties: + pins: + description: + List of gpio pins affected by the properties specified in this + subnode. + items: + pattern: "^gpio([0-9]|[1-2][0-9]|3[0-1])$" + + function: + enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, + mclk0, pdm_tx, pdm_clk, pdm_rx, pdm_sync ] + description: + Specify the alternative function to be configured for the specified + pins. + +allOf: + - $ref: qcom,lpass-lpi-common.yaml# + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + lpi_tlmm: pinctrl@15070000 { + compatible = "qcom,sdm660-lpass-lpi-pinctrl"; + reg = <0x15070000 0x20000>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpi_tlmm 0 0 32>; + + cdc_pdm_default: cdc-pdm-default-state { + clk-pins { + pins = "gpio18"; + function = "pdm_clk"; + drive-strength = <8>; + output-high; + }; + + sync-pins{ + pins = "gpio19"; + function = "pdm_sync"; + drive-strength = <4>; + output-high; + }; + + tx-pins { + pins = "gpio20"; + function = "pdm_tx"; + drive-strength = <8>; + }; + + rx-pins { + pins = "gpio21", "gpio23", "gpio25"; + function = "pdm_rx"; + drive-strength = <4>; + output-high; + }; + }; + + cdc_comp_default: cdc-comp-default-state { + pins = "gpio22", "gpio24"; + function = "comp_rx"; + drive-strength = <8>; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml b/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml index eec9a9b58542..af6fbbd4feea 100644 --- a/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml +++ b/Documentation/devicetree/bindings/pinctrl/raspberrypi,rp1-gpio.yaml @@ -72,10 +72,36 @@ $defs: pins: description: List of gpio pins affected by the properties specified in this - subnode. + subnode (either this or "groups" must be specified). items: pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + groups: + description: + List of groups affected by the properties specified in this + subnode (either this or "pins" must be specified). + items: + anyOf: + - pattern: '^gpio([0-9]|[1-4][0-9]|5[0-3])$' + - enum: [ uart0, uart0_ctrl, uart1, uart1_ctrl, uart2, uart2_ctrl, + uart3, uart3_ctrl, uart4, uart4_ctrl, uart5_0, + uart5_0_ctrl, uart5_1, uart5_1_ctrl, uart5_2, + uart5_2_ctrl, uart5_3, + sd0, sd1, + i2s0, i2s0_dual, i2s0_quad, i2s1, i2s1_dual, i2s1_quad, + i2s2_0, i2s2_0_dual, i2s2_1, i2s2_1_dual, + i2c4_0, i2c4_1, i2c4_2, i2c4_3, i2c6_0, i2c6_1, i2c5_0, + i2c5_1, i2c5_2, i2c5_3, i2c0_0, i2c0_1, i2c1_0, i2c1_1, + i2c2_0, i2c2_1, i2c3_0, i2c3_1, i2c3_2, + dpi_16bit, dpi_16bit_cpadhi, dpi_16bit_pad666, + dpi_18bit, dpi_18bit_cpadhi, dpi_24bit, + spi0, spi0_quad, spi1, spi2, spi3, spi4, spi5, spi6_0, + spi6_1, spi7_0, spi7_1, spi8_0, spi8_1, + aaud_0, aaud_1, aaud_2, aaud_3, aaud_4, + vbus0_0, vbus0_1, vbus1, vbus2, vbus3, + mic_0, mic_1, mic_2, mic_3, + ir ] + function: enum: [ alt0, alt1, alt2, alt3, alt4, gpio, alt6, alt7, alt8, none, aaud, dcd0, dpi, dsi0_te_ext, dsi1_te_ext, dsr0, dtr0, gpclk0, @@ -103,6 +129,13 @@ $defs: drive-strength: enum: [ 2, 4, 8, 12 ] + required: + - function + + oneOf: + - required: [ groups ] + - required: [ pins ] + additionalProperties: false allOf: diff --git a/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml new file mode 100644 index 000000000000..36d665971484 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/renesas,r9a09g077-pinctrl.yaml @@ -0,0 +1,172 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/renesas,r9a09g077-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/T2H and RZ/N2H Pin and GPIO controller + +maintainers: + - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> + +description: + The Renesas RZ/T2H and RZ/N2H SoCs feature a combined Pin and GPIO controller. + Pin multiplexing and GPIO configuration are performed on a per-pin basis. + Each port supports up to 8 pins, each configurable for either GPIO (port mode) + or alternate function mode. Each pin supports function mode values ranging from + 0x0 to 0x2A, allowing selection from up to 43 different functions. + +properties: + compatible: + enum: + - renesas,r9a09g077-pinctrl # RZ/T2H + - renesas,r9a09g087-pinctrl # RZ/N2H + + reg: + minItems: 1 + items: + - description: Non-safety I/O Port base + - description: Safety I/O Port safety region base + - description: Safety I/O Port Non-safety region base + + reg-names: + minItems: 1 + items: + - const: nsr + - const: srs + - const: srn + + gpio-controller: true + + '#gpio-cells': + const: 2 + description: + The first cell contains the global GPIO port index, constructed using the + RZT2H_GPIO() helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> + (e.g. "RZT2H_GPIO(3, 0)" for P03_0). The second cell represents the consumer + flag. Use the macros defined in include/dt-bindings/gpio/gpio.h. + + gpio-ranges: + maxItems: 1 + + clocks: + maxItems: 1 + + power-domains: + maxItems: 1 + +definitions: + renesas-rzt2h-n2h-pins-node: + type: object + allOf: + - $ref: pincfg-node.yaml# + - $ref: pinmux-node.yaml# + properties: + pinmux: + description: + Values are constructed from I/O port number, pin number, and + alternate function configuration number using the RZT2H_PORT_PINMUX() + helper macro from <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h>. + pins: true + phandle: true + input: true + input-enable: true + output-enable: true + oneOf: + - required: [pinmux] + - required: [pins] + additionalProperties: false + +patternProperties: + # Grouping nodes: allow multiple "-pins" subnodes within a "-group" + '.*-group$': + type: object + description: + Pin controller client devices can organize pin configuration entries into + grouping nodes ending in "-group". These group nodes may contain multiple + child nodes each ending in "-pins" to configure distinct sets of pins. + additionalProperties: false + patternProperties: + '-pins$': + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' + + # Standalone "-pins" nodes under client devices or groups + '-pins$': + $ref: '#/definitions/renesas-rzt2h-n2h-pins-node' + + '-hog$': + type: object + description: GPIO hog node + properties: + gpio-hog: true + gpios: true + input: true + output-high: true + output-low: true + line-name: true + required: + - gpio-hog + - gpios + additionalProperties: false + +allOf: + - $ref: pinctrl.yaml# + +required: + - compatible + - reg + - reg-names + - gpio-controller + - '#gpio-cells' + - gpio-ranges + - clocks + - power-domains + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> + #include <dt-bindings/pinctrl/renesas,r9a09g077-pinctrl.h> + + pinctrl@802c0000 { + compatible = "renesas,r9a09g077-pinctrl"; + reg = <0x802c0000 0x2000>, + <0x812c0000 0x2000>, + <0x802b0000 0x2000>; + reg-names = "nsr", "srs", "srn"; + clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pinctrl 0 0 288>; + power-domains = <&cpg>; + + serial0-pins { + pinmux = <RZT2H_PORT_PINMUX(38, 0, 1)>, /* Tx */ + <RZT2H_PORT_PINMUX(38, 1, 1)>; /* Rx */ + }; + + sd1-pwr-en-hog { + gpio-hog; + gpios = <RZT2H_GPIO(39, 2) 0>; + output-high; + line-name = "sd1_pwr_en"; + }; + + i2c0-pins { + pins = "RIIC0_SDA", "RIIC0_SCL"; + input-enable; + }; + + sd0-sd-group { + ctrl-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ + }; + + data-pins { + pinmux = <RZT2H_PORT_PINMUX(12, 0, 0x29)>, /* SD0_CLK */ + <RZT2H_PORT_PINMUX(12, 1, 0x29)>; /* SD0_CMD */ + }; + }; + }; diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml index 0da6d69f5991..dd11c73a55da 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl-wakeup-interrupt.yaml @@ -30,8 +30,6 @@ properties: compatible: oneOf: - enum: - - samsung,s3c2410-wakeup-eint - - samsung,s3c2412-wakeup-eint - samsung,s3c64xx-wakeup-eint - samsung,s5pv210-wakeup-eint - samsung,exynos4210-wakeup-eint @@ -59,7 +57,7 @@ properties: description: Interrupt used by multiplexed external wake-up interrupts. minItems: 1 - maxItems: 6 + maxItems: 4 required: - compatible @@ -69,21 +67,6 @@ allOf: properties: compatible: contains: - enum: - - samsung,s3c2410-wakeup-eint - - samsung,s3c2412-wakeup-eint - then: - properties: - interrupts: - minItems: 6 - maxItems: 6 - required: - - interrupts - - - if: - properties: - compatible: - contains: const: samsung,s3c64xx-wakeup-eint then: properties: diff --git a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml index de8460856141..f1094d65e846 100644 --- a/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml +++ b/Documentation/devicetree/bindings/pinctrl/samsung,pinctrl.yaml @@ -35,11 +35,8 @@ properties: compatible: enum: + - axis,artpec8-pinctrl - google,gs101-pinctrl - - samsung,s3c2412-pinctrl - - samsung,s3c2416-pinctrl - - samsung,s3c2440-pinctrl - - samsung,s3c2450-pinctrl - samsung,s3c64xx-pinctrl - samsung,s5pv210-pinctrl - samsung,exynos2200-pinctrl diff --git a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml index 15d74138baa3..12b71688dd34 100644 --- a/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml +++ b/Documentation/devicetree/bindings/power/amlogic,meson-sec-pwrc.yaml @@ -24,6 +24,9 @@ properties: - amlogic,a5-pwrc - amlogic,c3-pwrc - amlogic,t7-pwrc + - amlogic,s6-pwrc + - amlogic,s7-pwrc + - amlogic,s7d-pwrc "#power-domain-cells": const: 1 diff --git a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml index 6e9a670eaf56..caf151880999 100644 --- a/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml +++ b/Documentation/devicetree/bindings/power/apple,pmgr-pwrstate.yaml @@ -29,17 +29,22 @@ description: | properties: compatible: - items: - - enum: - - apple,s5l8960x-pmgr-pwrstate - - apple,t7000-pmgr-pwrstate - - apple,s8000-pmgr-pwrstate - - apple,t8010-pmgr-pwrstate - - apple,t8015-pmgr-pwrstate - - apple,t8103-pmgr-pwrstate - - apple,t8112-pmgr-pwrstate - - apple,t6000-pmgr-pwrstate - - const: apple,pmgr-pwrstate + oneOf: + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-pmgr-pwrstate + - apple,t7000-pmgr-pwrstate + - apple,s8000-pmgr-pwrstate + - apple,t8010-pmgr-pwrstate + - apple,t8015-pmgr-pwrstate + - apple,t8103-pmgr-pwrstate + - apple,t8112-pmgr-pwrstate + - apple,t6000-pmgr-pwrstate + - const: apple,pmgr-pwrstate + - items: + - const: apple,t6020-pmgr-pwrstate + - const: apple,t8103-pmgr-pwrstate reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml index 9c7cc632abee..500d98921581 100644 --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml @@ -44,6 +44,15 @@ properties: '#size-cells': const: 0 + access-controllers: + description: + A number of phandles to external blocks to set and clear the required + bits to enable or disable bus protection, necessary to avoid any bus + faults while enabling or disabling a power domain. + For example, this may hold phandles to INFRACFG and SMI. + minItems: 1 + maxItems: 3 + patternProperties: "^power-domain@[0-9a-f]+$": $ref: "#/$defs/power-domain-node" @@ -123,14 +132,17 @@ $defs: mediatek,infracfg: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG register range. + deprecated: true mediatek,infracfg-nao: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the INFRACFG-NAO register range. + deprecated: true mediatek,smi: $ref: /schemas/types.yaml#/definitions/phandle description: phandle to the device containing the SMI register range. + deprecated: true required: - reg @@ -138,6 +150,31 @@ $defs: required: - compatible +allOf: + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8183-power-controller + then: + properties: + access-controllers: + minItems: 2 + maxItems: 2 + + - if: + properties: + compatible: + contains: + enum: + - mediatek,mt8365-power-controller + then: + properties: + access-controllers: + minItems: 3 + maxItems: 3 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml b/Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml deleted file mode 100644 index 5220d9cb16d8..000000000000 --- a/Documentation/devicetree/bindings/power/supply/active-semi,act8945a-charger.yaml +++ /dev/null @@ -1,76 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0 -%YAML 1.2 ---- -$id: http://devicetree.org/schemas/power/supply/active-semi,act8945a-charger.yaml# -$schema: http://devicetree.org/meta-schemas/core.yaml# - -title: Active-semi ACT8945A Charger Function - -maintainers: - - Sebastian Reichel <sre@kernel.org> - -allOf: - - $ref: power-supply.yaml# - -properties: - compatible: - const: active-semi,act8945a-charger - - interrupts: - maxItems: 1 - - active-semi,chglev-gpios: - maxItems: 1 - description: charge current level GPIO - - active-semi,lbo-gpios: - maxItems: 1 - description: low battery voltage detect GPIO - - active-semi,input-voltage-threshold-microvolt: - description: | - Specifies the charger's input over-voltage threshold value. - Despite the name, specified values are in millivolt (mV). - Defaults to 6.6 V - enum: [ 6600, 7000, 7500, 8000 ] - - active-semi,precondition-timeout: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Specifies the charger's PRECONDITION safety timer setting value in minutes. - If 0, it means to disable this timer. - Defaults to 40 minutes. - enum: [ 0, 40, 60, 80 ] - - active-semi,total-timeout: - $ref: /schemas/types.yaml#/definitions/uint32 - description: | - Specifies the charger's total safety timer setting value in hours; - If 0, it means to disable this timer; - Defaults to 3 hours. - enum: [ 0, 3, 4, 5 ] - -required: - - compatible - - interrupts - - active-semi,chglev-gpios - - active-semi,lbo-gpios - -additionalProperties: false - -examples: - - | - #include <dt-bindings/gpio/gpio.h> - #include <dt-bindings/interrupt-controller/irq.h> - pmic { - charger { - compatible = "active-semi,act8945a-charger"; - interrupt-parent = <&pioA>; - interrupts = <45 IRQ_TYPE_LEVEL_LOW>; - active-semi,chglev-gpios = <&pioA 12 GPIO_ACTIVE_HIGH>; - active-semi,lbo-gpios = <&pioA 72 GPIO_ACTIVE_LOW>; - active-semi,input-voltage-threshold-microvolt = <6600>; - active-semi,precondition-timeout = <40>; - active-semi,total-timeout = <3>; - }; - }; diff --git a/Documentation/devicetree/bindings/power/supply/bq24190.yaml b/Documentation/devicetree/bindings/power/supply/bq24190.yaml index ac9a76fc5876..938554a9fb02 100644 --- a/Documentation/devicetree/bindings/power/supply/bq24190.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq24190.yaml @@ -30,6 +30,12 @@ properties: interrupts: maxItems: 1 + ce-gpios: + description: + Active low Charge Enable pin. Battery charging is enabled when + REG01[5:4] = 01 and CE pin is Low. CE pin must be pulled high or low. + maxItems: 1 + usb-otg-vbus: $ref: /schemas/regulator/regulator.yaml# description: | diff --git a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml index 309ea33b5b25..bc05400186cf 100644 --- a/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml +++ b/Documentation/devicetree/bindings/power/supply/bq27xxx.yaml @@ -16,9 +16,6 @@ description: | Support various Texas Instruments fuel gauge devices that share similar register maps and power supply properties -allOf: - - $ref: power-supply.yaml# - properties: compatible: enum: @@ -58,6 +55,10 @@ properties: maxItems: 1 description: integer, I2C address of the fuel gauge. + interrupts: + maxItems: 1 + description: the SOC_INT or GPOUT pin + monitored-battery: description: | The fuel gauge uses the following battery properties: @@ -68,6 +69,36 @@ properties: power-supplies: true +allOf: + - $ref: power-supply.yaml# + - if: + properties: + compatible: + contains: + enum: + - ti,bq27200 + - ti,bq27210 + - ti,bq27500 # deprecated, use revision specific property below + - ti,bq27510 # deprecated, use revision specific property below + - ti,bq27520 # deprecated, use revision specific property below + - ti,bq27500-1 + - ti,bq27510g1 + - ti,bq27510g2 + - ti,bq27521 + - ti,bq27541 + - ti,bq27542 + - ti,bq27546 + - ti,bq27742 + - ti,bq27545 + - ti,bq27411 + - ti,bq27z561 + - ti,bq28z610 + - ti,bq34z100 + - ti,bq78z100 + then: + properties: + interrupts: false + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt b/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt deleted file mode 100644 index dc5744636a57..000000000000 --- a/Documentation/devicetree/bindings/powerpc/fsl/mpic.txt +++ /dev/null @@ -1,231 +0,0 @@ -===================================================================== -Freescale MPIC Interrupt Controller Node -Copyright (C) 2010,2011 Freescale Semiconductor Inc. -===================================================================== - -The Freescale MPIC interrupt controller is found on all PowerQUICC -and QorIQ processors and is compatible with the Open PIC. The -notable difference from Open PIC binding is the addition of 2 -additional cells in the interrupt specifier defining interrupt type -information. - -PROPERTIES - - - compatible - Usage: required - Value type: <string> - Definition: Shall include "fsl,mpic". Freescale MPIC - controllers compatible with this binding have Block - Revision Registers BRR1 and BRR2 at offset 0x0 and - 0x10 in the MPIC. - - - reg - Usage: required - Value type: <prop-encoded-array> - Definition: A standard property. Specifies the physical - offset and length of the device's registers within the - CCSR address space. - - - interrupt-controller - Usage: required - Value type: <empty> - Definition: Specifies that this node is an interrupt - controller - - - #interrupt-cells - Usage: required - Value type: <u32> - Definition: Shall be 2 or 4. A value of 2 means that interrupt - specifiers do not contain the interrupt-type or type-specific - information cells. - - - #address-cells - Usage: required - Value type: <u32> - Definition: Shall be 0. - - - pic-no-reset - Usage: optional - Value type: <empty> - Definition: The presence of this property specifies that the - MPIC must not be reset by the client program, and that - the boot program has initialized all interrupt source - configuration registers to a sane state-- masked or - directed at other cores. This ensures that the client - program will not receive interrupts for sources not belonging - to the client. The presence of this property also mandates - that any initialization related to interrupt sources shall - be limited to sources explicitly referenced in the device tree. - - - big-endian - Usage: optional - Value type: <empty> - If present the MPIC will be assumed to be big-endian. Some - device-trees omit this property on MPIC nodes even when the MPIC is - in fact big-endian, so certain boards override this property. - - - single-cpu-affinity - Usage: optional - Value type: <empty> - If present the MPIC will be assumed to only be able to route - non-IPI interrupts to a single CPU at a time (EG: Freescale MPIC). - - - last-interrupt-source - Usage: optional - Value type: <u32> - Some MPICs do not correctly report the number of hardware sources - in the global feature registers. If specified, this field will - override the value read from MPIC_GREG_FEATURE_LAST_SRC. - -INTERRUPT SPECIFIER DEFINITION - - Interrupt specifiers consists of 4 cells encoded as - follows: - - <1st-cell> interrupt-number - - Identifies the interrupt source. The meaning - depends on the type of interrupt. - - Note: If the interrupt-type cell is undefined - (i.e. #interrupt-cells = 2), this cell - should be interpreted the same as for - interrupt-type 0-- i.e. an external or - normal SoC device interrupt. - - <2nd-cell> level-sense information, encoded as follows: - 0 = low-to-high edge triggered - 1 = active low level-sensitive - 2 = active high level-sensitive - 3 = high-to-low edge triggered - - <3rd-cell> interrupt-type - - The following types are supported: - - 0 = external or normal SoC device interrupt - - The interrupt-number cell contains - the SoC device interrupt number. The - type-specific cell is undefined. The - interrupt-number is derived from the - MPIC a block of registers referred to as - the "Interrupt Source Configuration Registers". - Each source has 32-bytes of registers - (vector/priority and destination) in this - region. So interrupt 0 is at offset 0x0, - interrupt 1 is at offset 0x20, and so on. - - 1 = error interrupt - - The interrupt-number cell contains - the SoC device interrupt number for - the error interrupt. The type-specific - cell identifies the specific error - interrupt number. - - 2 = MPIC inter-processor interrupt (IPI) - - The interrupt-number cell identifies - the MPIC IPI number. The type-specific - cell is undefined. - - 3 = MPIC timer interrupt - - The interrupt-number cell identifies - the MPIC timer number. The type-specific - cell is undefined. - - <4th-cell> type-specific information - - The type-specific cell is encoded as follows: - - - For interrupt-type 1 (error interrupt), - the type-specific cell contains the - bit number of the error interrupt in the - Error Interrupt Summary Register. - -EXAMPLE 1 - /* - * mpic interrupt controller with 4 cells per specifier - */ - mpic: pic@40000 { - compatible = "fsl,mpic"; - interrupt-controller; - #interrupt-cells = <4>; - #address-cells = <0>; - reg = <0x40000 0x40000>; - }; - -EXAMPLE 2 - /* - * The MPC8544 I2C controller node has an internal - * interrupt number of 27. As per the reference manual - * this corresponds to interrupt source configuration - * registers at 0x5_0560. - * - * The interrupt source configuration registers begin - * at 0x5_0000. - * - * To compute the interrupt specifier interrupt number - * - * 0x560 >> 5 = 43 - * - * The interrupt source configuration registers begin - * at 0x5_0000, and so the i2c vector/priority registers - * are at 0x5_0560. - */ - i2c@3000 { - #address-cells = <1>; - #size-cells = <0>; - cell-index = <0>; - compatible = "fsl-i2c"; - reg = <0x3000 0x100>; - interrupts = <43 2>; - interrupt-parent = <&mpic>; - dfsrr; - }; - - -EXAMPLE 3 - /* - * Definition of a node defining the 4 - * MPIC IPI interrupts. Note the interrupt - * type of 2. - */ - ipi@410a0 { - compatible = "fsl,mpic-ipi"; - reg = <0x40040 0x10>; - interrupts = <0 0 2 0 - 1 0 2 0 - 2 0 2 0 - 3 0 2 0>; - }; - -EXAMPLE 4 - /* - * Definition of a node defining the MPIC - * global timers. Note the interrupt - * type of 3. - */ - timer0: timer@41100 { - compatible = "fsl,mpic-global-timer"; - reg = <0x41100 0x100 0x41300 4>; - interrupts = <0 0 3 0 - 1 0 3 0 - 2 0 3 0 - 3 0 3 0>; - }; - -EXAMPLE 5 - /* - * Definition of an error interrupt (interrupt type 1). - * SoC interrupt number is 16 and the specific error - * interrupt bit in the error interrupt summary register - * is 23. - */ - memory-controller@8000 { - compatible = "fsl,p4080-memory-controller"; - reg = <0x8000 0x1000>; - interrupts = <16 2 1 23>; - }; diff --git a/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml b/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml new file mode 100644 index 000000000000..042de9d5a92b --- /dev/null +++ b/Documentation/devicetree/bindings/ptp/nxp,ptp-netc.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/ptp/nxp,ptp-netc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP NETC V4 Timer PTP clock + +description: + NETC V4 Timer provides current time with nanosecond resolution, precise + periodic pulse, pulse on timeout (alarm), and time capture on external + pulse support. And it supports time synchronization as required for + IEEE 1588 and IEEE 802.1AS-2020. + +maintainers: + - Wei Fang <wei.fang@nxp.com> + - Clark Wang <xiaoning.wang@nxp.com> + +properties: + compatible: + enum: + - pci1131,ee02 + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + description: + The reference clock of NETC Timer, can be selected between 3 different + clock sources using an integrated hardware mux TMR_CTRL[CK_SEL]. + The "ccm" means the reference clock comes from CCM of SoC. + The "ext" means the reference clock comes from external IO pins. + If not present, indicates that the system clock of NETC IP is selected + as the reference clock. + + clock-names: + enum: + - ccm + - ext + +required: + - compatible + - reg + +allOf: + - $ref: /schemas/pci/pci-device.yaml + +unevaluatedProperties: false + +examples: + - | + pcie { + #address-cells = <3>; + #size-cells = <2>; + + ptp-timer@18,0 { + compatible = "pci1131,ee02"; + reg = <0x00c000 0 0 0 0>; + clocks = <&scmi_clk 18>; + clock-names = "ccm"; + }; + }; diff --git a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml index 142157bff0cd..04519b0c581d 100644 --- a/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml +++ b/Documentation/devicetree/bindings/pwm/apple,s5l-fpwm.yaml @@ -17,8 +17,9 @@ properties: items: - enum: - apple,t8103-fpwm - - apple,t6000-fpwm - apple,t8112-fpwm + - apple,t6000-fpwm + - apple,t6020-fpwm - const: apple,s5l-fpwm reg: diff --git a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml index 7f9f72d95e7a..c7a10180208e 100644 --- a/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/fsl,vf610-ftm-pwm.yaml @@ -26,9 +26,14 @@ maintainers: properties: compatible: - enum: - - fsl,vf610-ftm-pwm - - fsl,imx8qm-ftm-pwm + oneOf: + - enum: + - fsl,vf610-ftm-pwm + - fsl,imx8qm-ftm-pwm + - nxp,s32g2-ftm-pwm + - items: + - const: nxp,s32g3-ftm-pwm + - const: nxp,s32g2-ftm-pwm reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml index f7bc84b05a87..8f5a468cfb91 100644 --- a/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/google,cros-ec-pwm.yaml @@ -14,7 +14,7 @@ description: | Google's ChromeOS EC PWM is a simple PWM attached to the Embedded Controller (EC) and controlled via a host-command interface. An EC PWM node should be only found as a sub-node of the EC node (see - Documentation/devicetree/bindings/mfd/google,cros-ec.yaml). + Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml). allOf: - $ref: pwm.yaml# diff --git a/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml b/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml index 981cfec53f37..19a9d2e15a96 100644 --- a/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/kontron,sl28cpld-pwm.yaml @@ -11,7 +11,7 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. The controller supports one PWM channel and supports only four distinct frequencies (250Hz, 500Hz, 1kHz, 2kHz). diff --git a/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml b/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml index ffda0123878e..920e0413d431 100644 --- a/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml +++ b/Documentation/devicetree/bindings/pwm/nxp,lpc1850-sct-pwm.yaml @@ -48,7 +48,7 @@ examples: pwm@40000000 { compatible = "nxp,lpc1850-sct-pwm"; reg = <0x40000000 0x1000>; - clocks =<&ccu1 CLK_CPU_SCT>; + clocks = <&ccu1 CLK_CPU_SCT>; clock-names = "pwm"; #pwm-cells = <3>; }; diff --git a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml index 17a2b927af33..97acbdec39f1 100644 --- a/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml +++ b/Documentation/devicetree/bindings/pwm/pwm-samsung.yaml @@ -31,6 +31,7 @@ properties: - enum: - samsung,exynos5433-pwm - samsung,exynos7-pwm + - samsung,exynos8890-pwm - samsung,exynosautov9-pwm - samsung,exynosautov920-pwm - tesla,fsd-pwm diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt deleted file mode 100644 index d97ca1964e94..000000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwm.txt +++ /dev/null @@ -1,17 +0,0 @@ -Texas Instruments TWL series PWM drivers - -Supported PWMs: -On TWL4030 series: PWM1 and PWM2 -On TWL6030 series: PWM0 and PWM1 - -Required properties: -- compatible: "ti,twl4030-pwm" or "ti,twl6030-pwm" -- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of - the cells format. - -Example: - -twl_pwm: pwm { - compatible = "ti,twl6030-pwm"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt b/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt deleted file mode 100644 index 31ca1b032ef0..000000000000 --- a/Documentation/devicetree/bindings/pwm/ti,twl-pwmled.txt +++ /dev/null @@ -1,17 +0,0 @@ -Texas Instruments TWL series PWM drivers connected to LED terminals - -Supported PWMs: -On TWL4030 series: PWMA and PWMB (connected to LEDA and LEDB terminals) -On TWL6030 series: LED PWM (mainly used as charging indicator LED) - -Required properties: -- compatible: "ti,twl4030-pwmled" or "ti,twl6030-pwmled" -- #pwm-cells: should be 2. See pwm.yaml in this directory for a description of - the cells format. - -Example: - -twl_pwmled: pwmled { - compatible = "ti,twl6030-pwmled"; - #pwm-cells = <2>; -}; diff --git a/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml b/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml index bdf3f7d34ef5..a8d579844dc7 100644 --- a/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml +++ b/Documentation/devicetree/bindings/regulator/active-semi,act8945a.yaml @@ -91,28 +91,41 @@ properties: maxItems: 1 active-semi,chglev-gpios: - description: CGHLEV GPIO + description: charge current level GPIO maxItems: 1 active-semi,lbo-gpios: - description: LBO GPIO + description: low battery voltage detect GPIO maxItems: 1 active-semi,input-voltage-threshold-microvolt: - description: Input voltage threshold - maxItems: 1 + description: + Specifies the charger's input over-voltage threshold value. Despite + the name, specified values are in millivolt (mV). + enum: [ 6600, 7000, 7500, 8000 ] + default: 6600 active-semi,precondition-timeout: - description: Precondition timeout + description: + Specifies the charger's PRECONDITION safety timer setting value in + minutes. If 0, it means to disable this timer. + enum: [ 0, 40, 60, 80 ] + default: 40 $ref: /schemas/types.yaml#/definitions/uint32 active-semi,total-timeout: - description: Total timeout + description: + Specifies the charger's total safety timer setting value in hours; If + 0, it means to disable this timer; + enum: [ 0, 3, 4, 5 ] + default: 3 $ref: /schemas/types.yaml#/definitions/uint32 required: - compatible - interrupts + - active-semi,chglev-gpios + - active-semi,lbo-gpios additionalProperties: false diff --git a/Documentation/devicetree/bindings/regulator/maxim,max77838.yaml b/Documentation/devicetree/bindings/regulator/maxim,max77838.yaml new file mode 100644 index 000000000000..bed36af5493d --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/maxim,max77838.yaml @@ -0,0 +1,68 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/maxim,max77838.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Maxim Integrated MAX77838 PMIC + +maintainers: + - Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> + +properties: + $nodename: + pattern: "pmic@[0-9a-f]{1,2}" + compatible: + enum: + - maxim,max77838 + + reg: + maxItems: 1 + + regulators: + type: object + $ref: regulator.yaml# + description: | + list of regulators provided by this controller, must be named + after their hardware counterparts ldo[1-4] and buck + + properties: + buck: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + patternProperties: + "^ldo([1-4])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + additionalProperties: false + +required: + - compatible + - reg + - regulators + +additionalProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@60 { + compatible = "maxim,max77838"; + reg = <0x60>; + + regulators { + ldo2 { + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + }; +... diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml index 79e5198e1c73..c654acf13768 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6331-regulator.yaml @@ -15,6 +15,10 @@ description: | buck-<name> and ldo-<name>. MT6331 regulators node should be sub node of the MT6397 MFD node. +properties: + compatible: + const: mediatek,mt6331-regulator + patternProperties: "^buck-v(core2|io18|dvfs11|dvfs12|dvfs13|dvfs14)$": type: object @@ -26,23 +30,23 @@ patternProperties: unevaluatedProperties: false - "^ldo-v(avdd32aud|auxa32)$": + "^ldo-(avdd32aud|vauxa32)$": type: object $ref: regulator.yaml# properties: regulator-name: - pattern: "^v(avdd32aud|auxa32)$" + pattern: "^(avdd32_aud|vauxa32)$" unevaluatedProperties: false - "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$": + "^ldo-v(dig18|emc33|ibr|mc|mch|mipi|rtc|sim1|sim2|sram|usb10)$": type: object $ref: regulator.yaml# properties: regulator-name: - pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sram|usb10)$" + pattern: "^v(dig18|emc33|ibr|mc|mch|mipi|rtc|sim1|sim2|sram|usb)$" unevaluatedProperties: false @@ -52,7 +56,7 @@ patternProperties: properties: regulator-name: - pattern: "^vcam(a|af|d|io)$" + pattern: "^vcam(a|_af|d|io)$" unevaluatedProperties: false @@ -75,13 +79,16 @@ patternProperties: properties: regulator-name: - pattern: "^vgp[12]$" + pattern: "^vgp[1234]$" required: - regulator-name unevaluatedProperties: false +required: + - compatible + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml b/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml index 2eb512c29a0d..475f18d4f261 100644 --- a/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/mediatek,mt6332-regulator.yaml @@ -15,6 +15,10 @@ description: | buck-<name> and ldo-<name>. MT6332 regulators node should be sub node of the MT6397 MFD node. +properties: + compatible: + const: mediatek,mt6332-regulator + patternProperties: "^buck-v(dram|dvfs2|pa|rf18a|rf18b|sbst)$": type: object @@ -36,6 +40,9 @@ patternProperties: unevaluatedProperties: false +required: + - compatible + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml b/Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml new file mode 100644 index 000000000000..8c8fc2cd4ced --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/nxp,pf0900.yaml @@ -0,0 +1,163 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/nxp,pf0900.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PF0900 Power Management Integrated Circuit regulators + +maintainers: + - Joy Zou <joy.zou@nxp.com> + +description: + The PF0900 is a power management integrated circuit (PMIC) optimized + for high performance i.MX9x based applications. It features five high + efficiency buck converters, three linear and one vaon regulators. It + provides low quiescent current in Standby and low power off Modes. + +properties: + compatible: + enum: + - nxp,pf0900 + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + regulators: + type: object + additionalProperties: false + + properties: + vaon: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + patternProperties: + "^ldo[1-3]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + "^sw[1-5]$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + + nxp,i2c-crc-enable: + type: boolean + description: + The CRC enabled during register read/write. Controlled by customer + unviewable fuse bits OTP_I2C_CRC_EN. Check chip part number. + +required: + - compatible + - reg + - interrupts + - regulators + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@8 { + compatible = "nxp,pf0900"; + reg = <0x08>; + interrupt-parent = <&pcal6524>; + interrupts = <89 IRQ_TYPE_LEVEL_LOW>; + nxp,i2c-crc-enable; + + regulators { + vaon { + regulator-name = "VAON"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + sw1 { + regulator-name = "SW1"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + regulator-state-mem { + regulator-on-in-suspend; + regulator-suspend-max-microvolt = <650000>; + regulator-suspend-min-microvolt = <650000>; + }; + }; + + sw2 { + regulator-name = "SW2"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + sw3 { + regulator-name = "SW3"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + sw4 { + regulator-name = "SW4"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + sw5 { + regulator-name = "SW5"; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + regulator-ramp-delay = <1950>; + }; + + ldo1 { + regulator-name = "LDO1"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo2 { + regulator-name = "LDO2"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + + ldo3 { + regulator-name = "LDO3"; + regulator-min-microvolt = <650000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml b/Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml new file mode 100644 index 000000000000..5b9d5d4e48d0 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/nxp,pf5300.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/nxp,pf5300.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP PF5300/PF5301/PF5302 PMIC regulators + +maintainers: + - Woodrow Douglass <wdouglass@carnegierobotics.com> + +description: | + The PF5300, PF5301, and PF5302 integrate high-performance buck converters, + 12 A, 8 A, and 15 A, respectively, to power high-end automotive and industrial + processors. With adaptive voltage positioning and a high-bandwidth loop, they + offer transient regulation to minimize capacitor requirements. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + oneOf: + - const: nxp,pf5300 + - items: + - enum: + - nxp,pf5301 + - nxp,pf5302 + - const: nxp,pf5300 + reg: + maxItems: 1 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + regulator@28 { + compatible = "nxp,pf5302", "nxp,pf5300"; + reg = <0x28>; + + regulator-always-on; + regulator-boot-on; + regulator-max-microvolt = <1200000>; + regulator-min-microvolt = <500000>; + }; + }; diff --git a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml index f02f97d4fdd2..40f9223d4c27 100644 --- a/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/qcom,sdm845-refgen-regulator.yaml @@ -23,11 +23,14 @@ properties: - enum: - qcom,sc7180-refgen-regulator - qcom,sc8180x-refgen-regulator + - qcom,sdm670-refgen-regulator - qcom,sm8150-refgen-regulator - const: qcom,sdm845-refgen-regulator - items: - enum: + - qcom,qcs8300-refgen-regulator + - qcom,sa8775p-refgen-regulator - qcom,sc7280-refgen-regulator - qcom,sc8280xp-refgen-regulator - qcom,sm6350-refgen-regulator diff --git a/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml new file mode 100644 index 000000000000..37b9ed371b67 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml @@ -0,0 +1,61 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/raspberrypi,7inch-touchscreen-panel-regulator-v2.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: RaspberryPi 5" and 7" display V2 MCU-based regulator/backlight controller + +maintainers: + - Marek Vasut <marek.vasut+renesas@mailbox.org> + +description: | + The RaspberryPi 5" and 7" display 2 has an MCU-based regulator, PWM + backlight and GPIO controller on the PCB, which is used to turn the + display unit on/off and control the backlight. + +allOf: + - $ref: regulator.yaml# + +properties: + compatible: + const: raspberrypi,touchscreen-panel-regulator-v2 + + reg: + maxItems: 1 + + gpio-controller: true + "#gpio-cells": + const: 2 + description: + The first cell is the pin number, and the second cell is used to + specify the gpio polarity (GPIO_ACTIVE_HIGH or GPIO_ACTIVE_LOW). + + "#pwm-cells": + const: 3 + description: See ../../pwm/pwm.yaml for description of the cell formats. + +additionalProperties: false + +required: + - compatible + - reg + - gpio-controller + - "#gpio-cells" + - "#pwm-cells" + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + regulator@45 { + compatible = "raspberrypi,touchscreen-panel-regulator-v2"; + reg = <0x45>; + gpio-controller; + #gpio-cells = <2>; + #pwm-cells = <3>; + }; + }; + +... diff --git a/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml index 18944d39d08f..41678400e63f 100644 --- a/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml +++ b/Documentation/devicetree/bindings/regulator/raspberrypi,7inch-touchscreen-panel-regulator.yaml @@ -12,17 +12,14 @@ maintainers: description: | The RaspberryPi 7" display has an ATTINY88-based regulator/backlight controller on the PCB, which is used to turn the display unit on/off - and control the backlight. The V2 supports 5" and 7" panels and also - offers PWM backlight control. + and control the backlight. allOf: - $ref: regulator.yaml# properties: compatible: - enum: - - raspberrypi,7inch-touchscreen-panel-regulator - - raspberrypi,touchscreen-panel-regulator-v2 + const: raspberrypi,7inch-touchscreen-panel-regulator reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml b/Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml new file mode 100644 index 000000000000..d2e007fee6ba --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/richtek,rt5133.yaml @@ -0,0 +1,178 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/richtek,rt5133.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Richtek RT5133 PMIC Regulator + +maintainers: + - ShihChia Chang <jeff_chang@richtek.com> + +description: + The RT5133 is an integrated Power Management IC for portable devices, + featuring 8 LDOs and 3 GPOs. It allows programmable output voltages, + soft-start times, and protections via I2C. GPO operation depends on LDO1 + voltage. + +properties: + compatible: + enum: + - richtek,rt5133 + + reg: + maxItems: 1 + + enable-gpios: + maxItems: 1 + + wakeup-source: true + + interrupts: + maxItems: 1 + + gpio-controller: true + + "#gpio-cells": + const: 2 + + richtek,oc-shutdown-all: + type: boolean + description: + Controls the behavior when any LDO (Low Dropout Regulator) enters an + Over Current state. + If set to true, all LDO channels will be shut down. + If set to false, only the affected LDO channel will shut down itself. + + richtek,pgb-shutdown-all: + type: boolean + description: + Controls the behavior when any LDO enters a Power Good Bad state. + If set to true, all LDO channels will be shut down. + If set to false, only the affected LDO channel will shut down itself. + + regulators: + type: object + additionalProperties: false + + properties: + base: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for the base regulator, which is the top-level supply for + LDO1 to LDO6. It functions merely as an on/off switch rather than + regulating voltages. If none of LDO1 to LDO6 are in use, switching + off the base will reduce the quiescent current. + + required: + - regulator-name + + patternProperties: + "^ldo([1-6])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator + + required: + - regulator-name + + "^ldo([7-8])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator + + properties: + vin-supply: true + + required: + - regulator-name + - vin-supply + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + + pmic@18 { + compatible = "richtek,rt5133"; + reg = <0x18>; + wakeup-source; + interrupts-extended = <&gpio 0 IRQ_TYPE_EDGE_FALLING>; + enable-gpios = <&gpio 2 GPIO_ACTIVE_HIGH>; + gpio-controller; + #gpio-cells = <2>; + richtek,oc-shutdown-all; + richtek,pgb-shutdown-all; + regulators { + base { + regulator-name = "base"; + }; + pvin78: ldo1 { + regulator-name = "ldo1"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3199998>; + regulator-active-discharge = <1>; + }; + ldo2 { + regulator-name = "ldo2"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <3200000>; + regulator-active-discharge = <1>; + }; + ldo3 { + regulator-name = "ldo3"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo4 { + regulator-name = "ldo4"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo5 { + regulator-name = "ldo5"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo6 { + regulator-name = "ldo6"; + regulator-min-microvolt = <1700000>; + regulator-max-microvolt = <3000000>; + regulator-active-discharge = <1>; + }; + ldo7 { + regulator-name = "ldo7"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <1200000>; + regulator-active-discharge = <1>; + vin-supply = <&pvin78>; + }; + ldo8 { + regulator-name = "ldo8"; + regulator-min-microvolt = <855000>; + regulator-max-microvolt = <1200000>; + regulator-active-discharge = <1>; + vin-supply = <&pvin78>; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml index adc6b3f36fde..179c98b33b4d 100644 --- a/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml +++ b/Documentation/devicetree/bindings/remoteproc/mtk,scp.yaml @@ -58,7 +58,7 @@ properties: maxItems: 1 cros-ec-rpmsg: - $ref: /schemas/mfd/google,cros-ec.yaml + $ref: /schemas/embedded-controller/google,cros-ec.yaml description: This subnode represents the rpmsg device. The properties of this node are defined by the individual bindings for @@ -126,7 +126,7 @@ patternProperties: maxItems: 1 cros-ec-rpmsg: - $ref: /schemas/mfd/google,cros-ec.yaml + $ref: /schemas/embedded-controller/google,cros-ec.yaml description: This subnode represents the rpmsg device. The properties of this node are defined by the individual bindings for diff --git a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml index 00150b93fca0..b8a320bb1776 100644 --- a/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml +++ b/Documentation/devicetree/bindings/reset/brcm,bcm6345-reset.yaml @@ -13,7 +13,9 @@ maintainers: properties: compatible: - const: brcm,bcm6345-reset + enum: + - brcm,bcm6345-reset + - brcm,bcm63xx-ephy-ctrl reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index 1a0cf0702a45..153d0dac57fb 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -52,6 +52,7 @@ properties: - sifive,e5 - sifive,e7 - sifive,e71 + - sifive,p550 - sifive,rocket0 - sifive,s7 - sifive,u5 diff --git a/Documentation/devicetree/bindings/riscv/eswin.yaml b/Documentation/devicetree/bindings/riscv/eswin.yaml new file mode 100644 index 000000000000..c603c45eef22 --- /dev/null +++ b/Documentation/devicetree/bindings/riscv/eswin.yaml @@ -0,0 +1,29 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/riscv/eswin.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN SoC-based boards + +maintainers: + - Min Lin <linmin@eswincomputing.com> + - Pinkesh Vaghela <pinkesh.vaghela@einfochips.com> + - Pritesh Patel <pritesh.patel@einfochips.com> + +description: + ESWIN SoC-based boards + +properties: + $nodename: + const: '/' + compatible: + oneOf: + - items: + - enum: + - sifive,hifive-premier-p550 + - const: eswin,eic7700 + +additionalProperties: true + +... diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index ede6a58ccf53..543ac94718e8 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -662,7 +662,31 @@ properties: Registers in the AX45MP datasheet. https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf + # MIPS + - const: xmipsexectl + description: + The MIPS extension for execution control as documented in + https://mips.com/wp-content/uploads/2025/06/P8700_Programmers_Reference_Manual_Rev1.84_5-31-2025.pdf + # SiFive + - const: xsfcease + description: + SiFive CEASE Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfcflushdlone + description: + SiFive L1D Cache Flush Instruction Extensions Specification. + See more details in + https://www.sifive.com/document-file/freedom-u740-c000-manual + + - const: xsfpgflushdlone + description: + SiFive PGFLUSH Instruction Extensions for the power management. The + CPU will flush the L1D and enter the cease state after executing + the instruction. + - const: xsfvqmaccdod description: SiFive Int8 Matrix Multiplication Extensions Specification. diff --git a/Documentation/devicetree/bindings/riscv/microchip.yaml b/Documentation/devicetree/bindings/riscv/microchip.yaml index 78ce76ae1b6d..381d6eb6672e 100644 --- a/Documentation/devicetree/bindings/riscv/microchip.yaml +++ b/Documentation/devicetree/bindings/riscv/microchip.yaml @@ -19,13 +19,26 @@ properties: compatible: oneOf: - items: + - const: microchip,mpfs-icicle-prod-reference-rtl-v2507 + - const: microchip,mpfs-icicle-kit-prod + - const: microchip,mpfs-icicle-kit + - const: microchip,mpfs-prod + - const: microchip,mpfs + + - items: - enum: - microchip,mpfs-icicle-reference-rtlv2203 - microchip,mpfs-icicle-reference-rtlv2210 + - microchip,mpfs-icicle-es-reference-rtl-v2507 - const: microchip,mpfs-icicle-kit - const: microchip,mpfs - items: + - const: microchip,mpfs-disco-kit-reference-rtl-v2507 + - const: microchip,mpfs-disco-kit + - const: microchip,mpfs + + - items: - enum: - aldec,tysom-m-mpfs250t-rev2 - aries,m100pfsevp diff --git a/Documentation/devicetree/bindings/riscv/spacemit.yaml b/Documentation/devicetree/bindings/riscv/spacemit.yaml index 077b94f10dca..c56b62a6299a 100644 --- a/Documentation/devicetree/bindings/riscv/spacemit.yaml +++ b/Documentation/devicetree/bindings/riscv/spacemit.yaml @@ -22,6 +22,7 @@ properties: - enum: - bananapi,bpi-f3 - milkv,jupiter + - xunlong,orangepi-rv2 - const: spacemit,k1 additionalProperties: true diff --git a/Documentation/devicetree/bindings/riscv/starfive.yaml b/Documentation/devicetree/bindings/riscv/starfive.yaml index 7ef85174353d..04510341a71e 100644 --- a/Documentation/devicetree/bindings/riscv/starfive.yaml +++ b/Documentation/devicetree/bindings/riscv/starfive.yaml @@ -28,6 +28,8 @@ properties: - enum: - deepcomputing,fml13v01 - milkv,mars + - milkv,marscm-emmc + - milkv,marscm-lite - pine64,star64 - starfive,visionfive-2-v1.2a - starfive,visionfive-2-v1.3b diff --git a/Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml b/Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml new file mode 100644 index 000000000000..6eafc532dc76 --- /dev/null +++ b/Documentation/devicetree/bindings/rng/SUNW,n2-rng.yaml @@ -0,0 +1,50 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/rng/SUNW,n2-rng.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SUN UltraSPARC HWRNG + +maintainers: + - David S. Miller <davem@davemloft.net> + +properties: + compatible: + enum: + - SUNW,n2-rng # for Niagara 2 Platform (SUN UltraSPARC T2 CPU) + - SUNW,vf-rng # for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU) + # for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), + # (UltraSPARC KT/Niagara 3 - development names) + # more recent systems (after Oracle acquisition of SUN) + - SUNW,kt-rng + - ORCL,m4-rng # for SPARC T5/M5 + - ORCL,m7-rng # for SPARC T7/M7 + + reg: + maxItems: 1 + + "rng-#units": + description: Number of RNG units + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 1 + +required: + - compatible + - reg + +additionalProperties: false + +# PS: see as well prtconfs.git by DaveM +examples: + - | + bus { + #address-cells = <1>; + #size-cells = <0>; + + rng@e { + compatible = "ORCL,m4-rng"; + reg = <0xe>; + rng-#units = <2>; + }; + }; diff --git a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt b/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt deleted file mode 100644 index b0b211194c71..000000000000 --- a/Documentation/devicetree/bindings/rng/sparc_sun_oracle_rng.txt +++ /dev/null @@ -1,30 +0,0 @@ -HWRNG support for the n2_rng driver - -Required properties: -- reg : base address to sample from -- compatible : should contain one of the following - RNG versions: - - 'SUNW,n2-rng' for Niagara 2 Platform (SUN UltraSPARC T2 CPU) - - 'SUNW,vf-rng' for Victoria Falls Platform (SUN UltraSPARC T2 Plus CPU) - - 'SUNW,kt-rng' for Rainbow/Yosemite Falls Platform (SUN SPARC T3/T4), (UltraSPARC KT/Niagara 3 - development names) - more recent systems (after Oracle acquisition of SUN) - - 'ORCL,m4-rng' for SPARC T5/M5 - - 'ORCL,m7-rng' for SPARC T7/M7 - -Examples: -/* linux LDOM on SPARC T5-2 */ -Node 0xf029a4f4 - .node: f029a4f4 - rng-#units: 00000002 - compatible: 'ORCL,m4-rng' - reg: 0000000e - name: 'random-number-generator' - -/* solaris on SPARC M7-8 */ -Node 0xf028c08c - rng-#units: 00000003 - compatible: 'ORCL,m7-rng' - reg: 0000000e - name: 'random-number-generator' - -PS: see as well prtconfs.git by DaveM diff --git a/Documentation/devicetree/bindings/serial/8250.yaml b/Documentation/devicetree/bindings/serial/8250.yaml index e46bee8d25bf..b243afa69a1a 100644 --- a/Documentation/devicetree/bindings/serial/8250.yaml +++ b/Documentation/devicetree/bindings/serial/8250.yaml @@ -48,7 +48,6 @@ allOf: oneOf: - required: [ clock-frequency ] - required: [ clocks ] - - if: properties: compatible: @@ -60,12 +59,39 @@ allOf: items: - const: uartclk - const: reg - else: + - if: + properties: + compatible: + contains: + const: spacemit,k1-uart + then: properties: clock-names: items: - const: core - const: bus + - if: + properties: + compatible: + contains: + enum: + - spacemit,k1-uart + - nxp,lpc1850-uart + then: + required: + - clocks + - clock-names + properties: + clocks: + minItems: 2 + clock-names: + minItems: 2 + else: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 properties: compatible: @@ -162,6 +188,9 @@ properties: minItems: 1 maxItems: 2 oneOf: + - enum: + - main + - uart - items: - const: core - const: bus @@ -264,29 +293,6 @@ required: - reg - interrupts -if: - properties: - compatible: - contains: - enum: - - spacemit,k1-uart - - nxp,lpc1850-uart -then: - required: - - clocks - - clock-names - properties: - clocks: - minItems: 2 - clock-names: - minItems: 2 -else: - properties: - clocks: - maxItems: 1 - clock-names: - maxItems: 1 - unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml index 89c462653e2d..8cc848ae11cb 100644 --- a/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml +++ b/Documentation/devicetree/bindings/serial/brcm,bcm7271-uart.yaml @@ -41,7 +41,7 @@ properties: - const: dma_intr2 clocks: - minItems: 1 + maxItems: 1 clock-names: const: sw_baud diff --git a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml index dd33794b3534..ed7b3909d87d 100644 --- a/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/serial/qcom,serial-geni-qcom.yaml @@ -12,6 +12,7 @@ maintainers: allOf: - $ref: /schemas/serial/serial.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt deleted file mode 100644 index 55259cf39c25..000000000000 --- a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.txt +++ /dev/null @@ -1,19 +0,0 @@ -Eckelmann SIOX GPIO bus - -Required properties: -- compatible : "eckelmann,siox-gpio" -- din-gpios, dout-gpios, dclk-gpios, dld-gpios: references gpios for the - corresponding bus signals. - -Examples: - - siox { - compatible = "eckelmann,siox-gpio"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_siox>; - - din-gpios = <&gpio6 11 0>; - dout-gpios = <&gpio6 8 0>; - dclk-gpios = <&gpio6 9 0>; - dld-gpios = <&gpio6 10 0>; - }; diff --git a/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml new file mode 100644 index 000000000000..2ff204109b93 --- /dev/null +++ b/Documentation/devicetree/bindings/siox/eckelmann,siox-gpio.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/siox/eckelmann,siox-gpio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eckelmann SIOX GPIO bus + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + const: eckelmann,siox-gpio + + din-gpios: + maxItems: 1 + + dout-gpios: + maxItems: 1 + + dclk-gpios: + maxItems: 1 + + dld-gpios: + maxItems: 1 + +required: + - compatible + - din-gpios + - dout-gpios + - dclk-gpios + - dld-gpios + +additionalProperties: false + +examples: + - | + siox { + compatible = "eckelmann,siox-gpio"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_siox>; + + din-gpios = <&gpio6 11 0>; + dout-gpios = <&gpio6 8 0>; + dclk-gpios = <&gpio6 9 0>; + dld-gpios = <&gpio6 10 0>; + }; diff --git a/Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml b/Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml new file mode 100644 index 000000000000..6fb93e8be929 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/fsl/fsl,vf610-src.yaml @@ -0,0 +1,47 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/fsl/fsl,vf610-src.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale vf610 System Reset Controller (SRC) + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +description: + IC reference manual calls it as SRC, but it is not module as reset + controller, which used to reset individual device. SRC works as reboot + controller, which reboots whole system. It provides a syscon interface to + syscon-reboot. + +properties: + compatible: + items: + - enum: + - fsl,vf610-src + - const: syscon + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + syscon@4006e000 { + compatible = "fsl,vf610-src", "syscon"; + reg = <0x4006e000 0x1000>; + interrupts = <96 IRQ_TYPE_LEVEL_HIGH>; + }; + diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml index 8451cb4dd87c..b77ce8c6a935 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx-iomuxc-gpr.yaml @@ -38,6 +38,7 @@ properties: - const: simple-mfd - items: - enum: + - fsl,imx53-iomuxc-gpr - fsl,imx8mm-iomuxc-gpr - fsl,imx8mn-iomuxc-gpr - fsl,imx8mp-iomuxc-gpr diff --git a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml index b3554e7f9e76..34aea58094e5 100644 --- a/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml +++ b/Documentation/devicetree/bindings/soc/imx/fsl,imx93-media-blk-ctrl.yaml @@ -18,7 +18,9 @@ description: properties: compatible: items: - - const: fsl,imx93-media-blk-ctrl + - enum: + - fsl,imx91-media-blk-ctrl + - fsl,imx93-media-blk-ctrl - const: syscon reg: @@ -31,21 +33,54 @@ properties: maxItems: 1 clocks: + minItems: 8 maxItems: 10 clock-names: - items: - - const: apb - - const: axi - - const: nic - - const: disp - - const: cam - - const: pxp - - const: lcdif - - const: isi - - const: csi - - const: dsi + minItems: 8 + maxItems: 10 +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx91-media-blk-ctrl + then: + properties: + clocks: + maxItems: 8 + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: lcdif + - const: isi + - const: csi + - if: + properties: + compatible: + contains: + const: fsl,imx93-media-blk-ctrl + then: + properties: + clocks: + minItems: 10 + clock-names: + items: + - const: apb + - const: axi + - const: nic + - const: disp + - const: cam + - const: pxp + - const: lcdif + - const: isi + - const: csi + - const: dsi required: - compatible - reg diff --git a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml index 4737e5f45d54..54c0cd64d309 100644 --- a/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml +++ b/Documentation/devicetree/bindings/soc/mediatek/mediatek,pwrap.yaml @@ -98,6 +98,9 @@ properties: - const: pwrap - const: pwrap-bridge + power-domains: + maxItems: 1 + pmic: type: object @@ -126,6 +129,18 @@ allOf: clock-names: minItems: 4 + - if: + properties: + compatible: + contains: + const: mediatek,mt8173-pwrap + then: + properties: + power-domains: true + else: + properties: + power-domains: false + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml index 48114bb0c927..7085bf88afab 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,pmic-glink.yaml @@ -56,6 +56,20 @@ properties: The array should contain a gpio entry for each PMIC Glink connector, in reg order. It is defined that GPIO active level means "CC2" or Reversed/Flipped orientation. + nvmem-cells: + minItems: 3 + maxItems: 3 + description: + The nvmem cells contain the charge control settings, including the charge control + enable status, the battery state of charge (SoC) threshold for stopping charging, + and the battery SoC delta required to restart charging. + + nvmem-cell-names: + items: + - const: charge_limit_en + - const: charge_limit_end + - const: charge_limit_delta + patternProperties: '^connector@\d$': $ref: /schemas/connector/usb-connector.yaml# diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml index 036562eb5140..26d9bc773ec5 100644 --- a/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,rpmh-rsc.yaml @@ -28,7 +28,7 @@ description: | SLEEP - Triggered by F/W WAKE - Triggered by F/W CONTROL - Triggered by F/W - See also:: <dt-bindings/soc/qcom,rpmh-rsc.h> + See also: <dt-bindings/soc/qcom,rpmh-rsc.h> The order in which they are described in the DT, should match the hardware configuration. diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml new file mode 100644 index 000000000000..6a34f05a07e8 --- /dev/null +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,se-common-props.yaml @@ -0,0 +1,26 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/soc/qcom/qcom,se-common-props.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: QUP Peripheral-specific properties for I2C, SPI and SERIAL bus + +description: + The Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) is + a programmable module that supports a wide range of serial interfaces + such as UART, SPI, I2C, I3C, etc. This defines the common properties used + across QUP-supported peripherals. + +maintainers: + - Mukesh Kumar Savaliya <mukesh.savaliya@oss.qualcomm.com> + - Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> + +properties: + qcom,enable-gsi-dma: + $ref: /schemas/types.yaml#/definitions/flag + description: + Configure the Serial Engine (SE) to transfer data in QCOM GPI DMA mode. + By default, FIFO mode (PIO/CPU DMA) will be selected. + +additionalProperties: true diff --git a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml index 5f9d541d177a..f4947ac65460 100644 --- a/Documentation/devicetree/bindings/soc/renesas/renesas.yaml +++ b/Documentation/devicetree/bindings/soc/renesas/renesas.yaml @@ -473,6 +473,12 @@ properties: - const: renesas,r8a779mb - const: renesas,r8a7795 + - description: R-Car X5H (R8A78000) + items: + - enum: + - renesas,ironhide # Ironhide (RTP8A78000ASKB0F10S) + - const: renesas,r8a78000 + - description: RZ/N1D (R9A06G032) items: - enum: diff --git a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml index 1ab0b092e2a5..01641692418b 100644 --- a/Documentation/devicetree/bindings/soc/rockchip/grf.yaml +++ b/Documentation/devicetree/bindings/soc/rockchip/grf.yaml @@ -31,6 +31,7 @@ properties: - rockchip,rk3568-usb2phy-grf - rockchip,rk3576-bigcore-grf - rockchip,rk3576-cci-grf + - rockchip,rk3576-dcphy-grf - rockchip,rk3576-gpu-grf - rockchip,rk3576-hdptxphy-grf - rockchip,rk3576-litcore-grf @@ -47,6 +48,7 @@ properties: - rockchip,rk3576-vop-grf - rockchip,rk3588-bigcore0-grf - rockchip,rk3588-bigcore1-grf + - rockchip,rk3588-csidphy-grf - rockchip,rk3588-dcphy-grf - rockchip,rk3588-hdptxphy-grf - rockchip,rk3588-ioc @@ -300,6 +302,7 @@ allOf: compatible: contains: enum: + - rockchip,rk3576-dcphy-grf - rockchip,rk3576-vo1-grf - rockchip,rk3588-vo-grf - rockchip,rk3588-vo0-grf diff --git a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml index cb22637091e8..c694926e56ef 100644 --- a/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml +++ b/Documentation/devicetree/bindings/soc/samsung/exynos-usi.yaml @@ -36,6 +36,7 @@ properties: - items: - enum: - google,gs101-usi + - samsung,exynos2200-usi - samsung,exynosautov9-usi - samsung,exynosautov920-usi - const: samsung,exynos850-usi diff --git a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml index 927b3200e29e..b5336bcbfb01 100644 --- a/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml +++ b/Documentation/devicetree/bindings/soc/ti/ti,pruss.yaml @@ -251,6 +251,15 @@ patternProperties: type: object + ecap@[a-f0-9]+$: + description: + PRU-ICSS has a Enhanced Capture (eCAP) event module which can generate + and capture periodic timer based events which will be used for features + like RX Pacing to rise interrupt when the timer event has occurred. + Each PRU-ICSS instance has one eCAP module irrespective of SOCs. + $ref: /schemas/net/ti,pruss-ecap.yaml# + type: object + mii-rt@[a-f0-9]+$: description: | Real-Time Ethernet to support multiple industrial communication protocols. diff --git a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml index fb5c39c79d28..c9f99e0df2b3 100644 --- a/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml +++ b/Documentation/devicetree/bindings/soc/xilinx/xilinx.yaml @@ -116,6 +116,36 @@ properties: - const: xlnx,zynqmp-zcu111 - const: xlnx,zynqmp + - description: Xilinx Kria SOMs K24 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sm-k24-rev1 + - xlnx,zynqmp-sm-k24-revB + - xlnx,zynqmp-sm-k24-revA + - xlnx,zynqmp-sm-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-sm-k24 + + - description: Xilinx Kria SOMs K24 (starter) + minItems: 3 + items: + enum: + - xlnx,zynqmp-smk-k24-rev1 + - xlnx,zynqmp-smk-k24-revB + - xlnx,zynqmp-smk-k24-revA + - xlnx,zynqmp-smk-k24 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp + - contains: + const: xlnx,zynqmp-smk-k24 + - description: Xilinx Kria SOMs minItems: 3 items: @@ -148,6 +178,57 @@ properties: - contains: const: xlnx,zynqmp-smk-k26 + - description: Xilinx Kria SOM KD240 revA/B/1 + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kd240-rev1 + - xlnx,zynqmp-sk-kd240-revB + - xlnx,zynqmp-sk-kd240-revA + - xlnx,zynqmp-sk-kd240 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kd240-revA + - contains: + const: xlnx,zynqmp-sk-kd240 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 revA/Y/Z + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-revA + - xlnx,zynqmp-sk-kr260-revY + - xlnx,zynqmp-sk-kr260-revZ + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revA + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + + - description: Xilinx Kria SOM KR260 rev2/1/B + minItems: 3 + items: + enum: + - xlnx,zynqmp-sk-kr260-rev2 + - xlnx,zynqmp-sk-kr260-rev1 + - xlnx,zynqmp-sk-kr260-revB + - xlnx,zynqmp-sk-kr260 + - xlnx,zynqmp + allOf: + - contains: + const: xlnx,zynqmp-sk-kr260-revB + - contains: + const: xlnx,zynqmp-sk-kr260 + - contains: + const: xlnx,zynqmp + - description: Xilinx Kria SOM KV260 revA/Y/Z minItems: 3 items: diff --git a/Documentation/devicetree/bindings/sound/alc5623.txt b/Documentation/devicetree/bindings/sound/alc5623.txt deleted file mode 100644 index 26c86c98d671..000000000000 --- a/Documentation/devicetree/bindings/sound/alc5623.txt +++ /dev/null @@ -1,25 +0,0 @@ -ALC5621/ALC5622/ALC5623 audio Codec - -Required properties: - - - compatible: "realtek,alc5623" - - reg: the I2C address of the device. - -Optional properties: - - - add-ctrl: Default register value for Reg-40h, Additional Control - Register. If absent or has the value of 0, the - register is untouched. - - - jack-det-ctrl: Default register value for Reg-5Ah, Jack Detect - Control Register. If absent or has value 0, the - register is untouched. - -Example: - - alc5621: alc5621@1a { - compatible = "alc5621"; - reg = <0x1a>; - add-ctrl = <0x3700>; - jack-det-ctrl = <0x4810>; - }; diff --git a/Documentation/devicetree/bindings/sound/apple,mca.yaml b/Documentation/devicetree/bindings/sound/apple,mca.yaml index 5c6ec08c7d24..2beb725118ad 100644 --- a/Documentation/devicetree/bindings/sound/apple,mca.yaml +++ b/Documentation/devicetree/bindings/sound/apple,mca.yaml @@ -19,12 +19,17 @@ allOf: properties: compatible: - items: - - enum: - - apple,t6000-mca - - apple,t8103-mca - - apple,t8112-mca - - const: apple,mca + oneOf: + - items: + - const: apple,t6020-mca + - const: apple,t8103-mca + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t6000-mca + - apple,t8103-mca + - apple,t8112-mca + - const: apple,mca reg: items: diff --git a/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml b/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml index 4477f84b7acc..1fdbeecc5eff 100644 --- a/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml +++ b/Documentation/devicetree/bindings/sound/asahi-kasei,ak4458.yaml @@ -15,6 +15,9 @@ properties: - asahi-kasei,ak4458 - asahi-kasei,ak4497 + "#sound-dai-cells": + const: 0 + reg: maxItems: 1 @@ -46,6 +49,7 @@ required: - reg allOf: + - $ref: dai-common.yaml# - if: properties: compatible: diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt deleted file mode 100644 index 7bb0362828ec..000000000000 --- a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.txt +++ /dev/null @@ -1,24 +0,0 @@ -* Broadcom BCM2835 SoC I2S/PCM module - -Required properties: -- compatible: "brcm,bcm2835-i2s" -- reg: Should contain PCM registers location and length. -- clocks: the (PCM) clock to use -- dmas: List of DMA controller phandle and DMA request line ordered pairs. -- dma-names: Identifier string for each DMA request line in the dmas property. - These strings correspond 1:1 with the ordered pairs in dmas. - - One of the DMA channels will be responsible for transmission (should be - named "tx") and one for reception (should be named "rx"). - -Example: - -bcm2835_i2s: i2s@7e203000 { - compatible = "brcm,bcm2835-i2s"; - reg = <0x7e203000 0x24>; - clocks = <&clocks BCM2835_CLOCK_PCM>; - - dmas = <&dma 2>, - <&dma 3>; - dma-names = "tx", "rx"; -}; diff --git a/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml new file mode 100644 index 000000000000..f3cfe92684d0 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/brcm,bcm2835-i2s.yaml @@ -0,0 +1,51 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/brcm,bcm2835-i2s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Broadcom BCM2835 SoC I2S/PCM module + +maintainers: + - Florian Fainelli <florian.fainelli@broadcom.com> + +properties: + compatible: + const: brcm,bcm2835-i2s + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + dmas: + items: + - description: Transmission DMA controller phandle and request line. + - description: Reception DMA controller phandle and request line. + + dma-names: + items: + - const: tx + - const: rx + +required: + - compatible + - reg + - clocks + - dmas + - dma-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/bcm2835.h> + + i2s@7e203000 { + compatible = "brcm,bcm2835-i2s"; + reg = <0x7e203000 0x24>; + clocks = <&clocks BCM2835_CLOCK_PCM>; + dmas = <&dma 2>, <&dma 3>; + dma-names = "tx", "rx"; + }; diff --git a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml index 14dea1feefc5..e6cf2ebcd777 100644 --- a/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml +++ b/Documentation/devicetree/bindings/sound/cirrus,cs35l41.yaml @@ -151,6 +151,12 @@ properties: minimum: 0 maximum: 5 + cirrus,subsystem-id: + $ref: /schemas/types.yaml#/definitions/string + description: + Subsystem ID. If this property is present, it sets the system name, + used to identify the firmware and tuning to load. + required: - compatible - reg diff --git a/Documentation/devicetree/bindings/sound/everest,es8316.yaml b/Documentation/devicetree/bindings/sound/everest,es8316.yaml index e4b2eb5fae2f..81a0215050e0 100644 --- a/Documentation/devicetree/bindings/sound/everest,es8316.yaml +++ b/Documentation/devicetree/bindings/sound/everest,es8316.yaml @@ -12,6 +12,22 @@ maintainers: - Matteo Martelli <matteomartelli3@gmail.com> - Binbin Zhou <zhoubinbin@loongson.cn> +description: | + Everest ES8311, ES8316 and ES8323 audio CODECs + + Pins on the device (for linking into audio routes): + + Outputs: + * LOUT: Left Analog Output + * ROUT: Right Analog Output + * MICBIAS: Microphone Bias + + Inputs: + * MIC1P: Microphone 1 Positive Analog Input + * MIC1N: Microphone 1 Negative Analog Input + * MIC2P: Microphone 2 Positive Analog Input + * MIC2N: Microphone 2 Negative Analog Input + allOf: - $ref: dai-common.yaml# diff --git a/Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml b/Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml new file mode 100644 index 000000000000..4da735317e0f --- /dev/null +++ b/Documentation/devicetree/bindings/sound/foursemi,fs2105s.yaml @@ -0,0 +1,101 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/foursemi,fs2105s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: FourSemi FS2104/5S Digital Audio Amplifier + +maintainers: + - Nick Li <nick.li@foursemi.com> + +description: + The FS2104 is a 15W Inductor-Less, Stereo, Closed-Loop, + Digital Input Class-D Power Amplifier with Enhanced Signal Processing. + The FS2105S is a 30W Inductor-Less, Stereo, Closed-Loop, + Digital Input Class-D Power Amplifier with Enhanced Signal Processing. + +properties: + compatible: + oneOf: + - items: + - enum: + - foursemi,fs2104 + - const: foursemi,fs2105s + - enum: + - foursemi,fs2105s + + reg: + maxItems: 1 + + clocks: + items: + - description: The clock of I2S BCLK + + clock-names: + items: + - const: bclk + + interrupts: + maxItems: 1 + + '#sound-dai-cells': + const: 0 + + pvdd-supply: + description: + Regulator for power supply(PVDD in datasheet). + + dvdd-supply: + description: + Regulator for digital supply(DVDD in datasheet). + + reset-gpios: + maxItems: 1 + description: + It's the SDZ pin in datasheet, the pin is active low, + it will power down and reset the chip to shut down state. + + firmware-name: + maxItems: 1 + description: | + The firmware(*.bin) contains: + a. Register initialization settings + b. DSP effect parameters + c. Multi-scene sound effect configurations(optional) + It's gernerated by FourSemi's tuning tool. + +required: + - compatible + - reg + - '#sound-dai-cells' + - pvdd-supply + - dvdd-supply + - reset-gpios + - firmware-name + +allOf: + - $ref: dai-common.yaml# + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + i2c { + #address-cells = <1>; + #size-cells = <0>; + audio-codec@68 { + compatible = "foursemi,fs2105s"; + reg = <0x68>; + clocks = <&clocks 18>; + clock-names = "bclk"; + #sound-dai-cells = <0>; + pvdd-supply = <&pvdd_supply>; + dvdd-supply = <&dvdd_supply>; + reset-gpios = <&gpio 18 GPIO_ACTIVE_LOW>; + firmware-name = "fs2105s-btl-2p0-0s.bin"; + pinctrl-names = "default"; + pinctrl-0 = <&fs210x_pins_default>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml index 8f1108e7e14e..d5727f8bfb0b 100644 --- a/Documentation/devicetree/bindings/sound/fsl,easrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,easrc.yaml @@ -104,6 +104,6 @@ examples: "ctx2_rx", "ctx2_tx", "ctx3_rx", "ctx3_tx"; firmware-name = "imx/easrc/easrc-imx8mn.bin"; - fsl,asrc-rate = <8000>; + fsl,asrc-rate = <8000>; fsl,asrc-format = <2>; }; diff --git a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml index 85799f83e65f..c9152bac7421 100644 --- a/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml +++ b/Documentation/devicetree/bindings/sound/fsl,imx-asrc.yaml @@ -176,7 +176,7 @@ examples: <&sdma 20 23 1>, <&sdma 21 23 1>, <&sdma 22 23 1>; dma-names = "rxa", "rxb", "rxc", "txa", "txb", "txc"; - fsl,asrc-rate = <48000>; + fsl,asrc-rate = <48000>; fsl,asrc-width = <16>; port { diff --git a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml index 1434f4433738..dd51e8c5b8c2 100644 --- a/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml +++ b/Documentation/devicetree/bindings/sound/google,cros-ec-codec.yaml @@ -15,7 +15,7 @@ description: | Embedded Controller (EC) and is controlled via a host-command interface. An EC codec node should only be found inside the "codecs" subnode of a cros-ec node. - (see Documentation/devicetree/bindings/mfd/google,cros-ec.yaml). + (see Documentation/devicetree/bindings/embedded-controller/google,cros-ec.yaml). allOf: - $ref: dai-common.yaml# diff --git a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt b/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt deleted file mode 100644 index 2f89db88fd57..000000000000 --- a/Documentation/devicetree/bindings/sound/imx-audio-sgtl5000.txt +++ /dev/null @@ -1,56 +0,0 @@ -Freescale i.MX audio complex with SGTL5000 codec - -Required properties: - - - compatible : "fsl,imx-audio-sgtl5000" - - - model : The user-visible name of this sound complex - - - ssi-controller : The phandle of the i.MX SSI controller - - - audio-codec : The phandle of the SGTL5000 audio codec - - - audio-routing : A list of the connections between audio components. - Each entry is a pair of strings, the first being the - connection's sink, the second being the connection's - source. Valid names could be power supplies, SGTL5000 - pins, and the jacks on the board: - - Power supplies: - * Mic Bias - - SGTL5000 pins: - * MIC_IN - * LINE_IN - * HP_OUT - * LINE_OUT - - Board connectors: - * Mic Jack - * Line In Jack - * Headphone Jack - * Line Out Jack - * Ext Spk - - - mux-int-port : The internal port of the i.MX audio muxer (AUDMUX) - - - mux-ext-port : The external port of the i.MX audio muxer - -Note: The AUDMUX port numbering should start at 1, which is consistent with -hardware manual. - -Example: - -sound { - compatible = "fsl,imx51-babbage-sgtl5000", - "fsl,imx-audio-sgtl5000"; - model = "imx51-babbage-sgtl5000"; - ssi-controller = <&ssi1>; - audio-codec = <&sgtl5000>; - audio-routing = - "MIC_IN", "Mic Jack", - "Mic Jack", "Mic Bias", - "Headphone Jack", "HP_OUT"; - mux-int-port = <1>; - mux-ext-port = <3>; -}; diff --git a/Documentation/devicetree/bindings/sound/linux,spdif.yaml b/Documentation/devicetree/bindings/sound/linux,spdif.yaml index 0f4893e11ec4..aea6230db54c 100644 --- a/Documentation/devicetree/bindings/sound/linux,spdif.yaml +++ b/Documentation/devicetree/bindings/sound/linux,spdif.yaml @@ -23,6 +23,9 @@ properties: sound-name-prefix: true + port: + $ref: /schemas/graph.yaml#/properties/port + required: - "#sound-dai-cells" - compatible diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml new file mode 100644 index 000000000000..031b0fa7b4dc --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183-audio.yaml @@ -0,0 +1,228 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8183-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek AFE PCM controller for mt8183 + +maintainers: + - Julien Massot <jmassot@collabora.com> + +properties: + compatible: + const: mediatek,mt8183-audio + + interrupts: + maxItems: 1 + + resets: + maxItems: 1 + + reset-names: + const: audiosys + + power-domains: + maxItems: 1 + + memory-region: + maxItems: 1 + + clocks: + items: + - description: AFE clock + - description: ADDA DAC clock + - description: ADDA DAC pre-distortion clock + - description: ADDA ADC clock + - description: ADDA6 ADC clock + - description: Audio low-jitter 22.5792m clock + - description: Audio low-jitter 24.576m clock + - description: Audio PLL1 tuner clock + - description: Audio PLL2 tuner clock + - description: I2S1 bit clock + - description: I2S2 bit clock + - description: I2S3 bit clock + - description: I2S4 bit clock + - description: Audio Time-Division Multiplexing interface clock + - description: Powerdown Audio test model clock + - description: Audio infra sys clock + - description: Audio infra 26M clock + - description: Mux for audio clock + - description: Mux for audio internal bus clock + - description: Mux main divider by 4 + - description: Primary audio mux + - description: Primary audio PLL + - description: Secondary audio mux + - description: Secondary audio PLL + - description: Primary audio en-generator clock + - description: Primary PLL divider by 4 for IEC + - description: Secondary audio en-generator clock + - description: Secondary PLL divider by 8 for IEC + - description: Mux selector for I2S port 0 + - description: Mux selector for I2S port 1 + - description: Mux selector for I2S port 2 + - description: Mux selector for I2S port 3 + - description: Mux selector for I2S port 4 + - description: Mux selector for I2S port 5 + - description: APLL1 and APLL2 divider for I2S port 0 + - description: APLL1 and APLL2 divider for I2S port 1 + - description: APLL1 and APLL2 divider for I2S port 2 + - description: APLL1 and APLL2 divider for I2S port 3 + - description: APLL1 and APLL2 divider for I2S port 4 + - description: APLL1 and APLL2 divider for IEC + - description: 26MHz clock for audio subsystem + + clock-names: + items: + - const: aud_afe_clk + - const: aud_dac_clk + - const: aud_dac_predis_clk + - const: aud_adc_clk + - const: aud_adc_adda6_clk + - const: aud_apll22m_clk + - const: aud_apll24m_clk + - const: aud_apll1_tuner_clk + - const: aud_apll2_tuner_clk + - const: aud_i2s1_bclk_sw + - const: aud_i2s2_bclk_sw + - const: aud_i2s3_bclk_sw + - const: aud_i2s4_bclk_sw + - const: aud_tdm_clk + - const: aud_tml_clk + - const: aud_infra_clk + - const: mtkaif_26m_clk + - const: top_mux_audio + - const: top_mux_aud_intbus + - const: top_syspll_d2_d4 + - const: top_mux_aud_1 + - const: top_apll1_ck + - const: top_mux_aud_2 + - const: top_apll2_ck + - const: top_mux_aud_eng1 + - const: top_apll1_d8 + - const: top_mux_aud_eng2 + - const: top_apll2_d8 + - const: top_i2s0_m_sel + - const: top_i2s1_m_sel + - const: top_i2s2_m_sel + - const: top_i2s3_m_sel + - const: top_i2s4_m_sel + - const: top_i2s5_m_sel + - const: top_apll12_div0 + - const: top_apll12_div1 + - const: top_apll12_div2 + - const: top_apll12_div3 + - const: top_apll12_div4 + - const: top_apll12_divb + - const: top_clk26m_clk + +required: + - compatible + - interrupts + - resets + - reset-names + - power-domains + - clocks + - clock-names + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/mt8183-clk.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/power/mt8183-power.h> + #include <dt-bindings/reset/mt8183-resets.h> + + audio-controller { + compatible = "mediatek,mt8183-audio"; + interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; + resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; + reset-names = "audiosys"; + power-domains = <&spm MT8183_POWER_DOMAIN_AUDIO>; + clocks = <&audiosys CLK_AUDIO_AFE>, + <&audiosys CLK_AUDIO_DAC>, + <&audiosys CLK_AUDIO_DAC_PREDIS>, + <&audiosys CLK_AUDIO_ADC>, + <&audiosys CLK_AUDIO_PDN_ADDA6_ADC>, + <&audiosys CLK_AUDIO_22M>, + <&audiosys CLK_AUDIO_24M>, + <&audiosys CLK_AUDIO_APLL_TUNER>, + <&audiosys CLK_AUDIO_APLL2_TUNER>, + <&audiosys CLK_AUDIO_I2S1>, + <&audiosys CLK_AUDIO_I2S2>, + <&audiosys CLK_AUDIO_I2S3>, + <&audiosys CLK_AUDIO_I2S4>, + <&audiosys CLK_AUDIO_TDM>, + <&audiosys CLK_AUDIO_TML>, + <&infracfg CLK_INFRA_AUDIO>, + <&infracfg CLK_INFRA_AUDIO_26M_BCLK>, + <&topckgen CLK_TOP_MUX_AUDIO>, + <&topckgen CLK_TOP_MUX_AUD_INTBUS>, + <&topckgen CLK_TOP_SYSPLL_D2_D4>, + <&topckgen CLK_TOP_MUX_AUD_1>, + <&topckgen CLK_TOP_APLL1_CK>, + <&topckgen CLK_TOP_MUX_AUD_2>, + <&topckgen CLK_TOP_APLL2_CK>, + <&topckgen CLK_TOP_MUX_AUD_ENG1>, + <&topckgen CLK_TOP_APLL1_D8>, + <&topckgen CLK_TOP_MUX_AUD_ENG2>, + <&topckgen CLK_TOP_APLL2_D8>, + <&topckgen CLK_TOP_MUX_APLL_I2S0>, + <&topckgen CLK_TOP_MUX_APLL_I2S1>, + <&topckgen CLK_TOP_MUX_APLL_I2S2>, + <&topckgen CLK_TOP_MUX_APLL_I2S3>, + <&topckgen CLK_TOP_MUX_APLL_I2S4>, + <&topckgen CLK_TOP_MUX_APLL_I2S5>, + <&topckgen CLK_TOP_APLL12_DIV0>, + <&topckgen CLK_TOP_APLL12_DIV1>, + <&topckgen CLK_TOP_APLL12_DIV2>, + <&topckgen CLK_TOP_APLL12_DIV3>, + <&topckgen CLK_TOP_APLL12_DIV4>, + <&topckgen CLK_TOP_APLL12_DIVB>, + <&clk26m>; + clock-names = "aud_afe_clk", + "aud_dac_clk", + "aud_dac_predis_clk", + "aud_adc_clk", + "aud_adc_adda6_clk", + "aud_apll22m_clk", + "aud_apll24m_clk", + "aud_apll1_tuner_clk", + "aud_apll2_tuner_clk", + "aud_i2s1_bclk_sw", + "aud_i2s2_bclk_sw", + "aud_i2s3_bclk_sw", + "aud_i2s4_bclk_sw", + "aud_tdm_clk", + "aud_tml_clk", + "aud_infra_clk", + "mtkaif_26m_clk", + "top_mux_audio", + "top_mux_aud_intbus", + "top_syspll_d2_d4", + "top_mux_aud_1", + "top_apll1_ck", + "top_mux_aud_2", + "top_apll2_ck", + "top_mux_aud_eng1", + "top_apll1_d8", + "top_mux_aud_eng2", + "top_apll2_d8", + "top_i2s0_m_sel", + "top_i2s1_m_sel", + "top_i2s2_m_sel", + "top_i2s3_m_sel", + "top_i2s4_m_sel", + "top_i2s5_m_sel", + "top_apll12_div0", + "top_apll12_div1", + "top_apll12_div2", + "top_apll12_div3", + "top_apll12_div4", + "top_apll12_divb", + "top_clk26m_clk"; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml new file mode 100644 index 000000000000..b526e8123182 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183_da7219.yaml @@ -0,0 +1,49 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8183_da7219.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8183 sound card with external codecs + +maintainers: + - Julien Massot <jmassot@collabora.com> + +description: + MediaTek MT8183 SoC-based sound cards with DA7219 as headset codec, + and MAX98357A, RT1015 or RT1015P as speaker amplifiers. Optionally includes HDMI codec. + +properties: + compatible: + enum: + - mediatek,mt8183_da7219_max98357 + - mediatek,mt8183_da7219_rt1015 + - mediatek,mt8183_da7219_rt1015p + + mediatek,headset-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the DA7219 headset codec. + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the MT8183 ASoC platform (e.g., AFE node). + + mediatek,hdmi-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Optional phandle to the HDMI codec (e.g., IT6505). + +required: + - compatible + - mediatek,headset-codec + - mediatek,platform + +additionalProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt8183_da7219_max98357"; + mediatek,headset-codec = <&da7219>; + mediatek,hdmi-codec = <&it6505dptx>; + mediatek,platform = <&afe>; + }; diff --git a/Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml b/Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml new file mode 100644 index 000000000000..43a6f9d40644 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/mediatek,mt8183_mt6358_ts3a227.yaml @@ -0,0 +1,59 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/mediatek,mt8183_mt6358_ts3a227.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: MediaTek MT8183 sound card with MT6358, TS3A227, and MAX98357/RT1015 codecs + +maintainers: + - Julien Massot <julien.massot@collabora.com> + +description: + MediaTek MT8183 SoC-based sound cards using the MT6358 codec, + with optional TS3A227 headset codec, EC codec (via Chrome EC), and HDMI audio. + Speaker amplifier can be one of MAX98357A/B, RT1015, or RT1015P. + +properties: + compatible: + enum: + - mediatek,mt8183_mt6358_ts3a227_max98357 + - mediatek,mt8183_mt6358_ts3a227_max98357b + - mediatek,mt8183_mt6358_ts3a227_rt1015 + - mediatek,mt8183_mt6358_ts3a227_rt1015p + + mediatek,platform: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the MT8183 ASoC platform node (e.g., AFE). + + mediatek,headset-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Phandle to the TS3A227 headset codec. + + mediatek,ec-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + Optional phandle to a ChromeOS EC codec node. + See bindings in google,cros-ec-codec.yaml. + + mediatek,hdmi-codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: Optional phandle to an HDMI audio codec node. + +required: + - compatible + - mediatek,platform + +additionalProperties: false + +examples: + - | + sound { + compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; + mediatek,headset-codec = <&ts3a227>; + mediatek,ec-codec = <&ec_codec>; + mediatek,hdmi-codec = <&it6505dptx>; + mediatek,platform = <&afe>; + }; + +... diff --git a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt b/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt deleted file mode 100644 index 1f1cba4152ce..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8183-afe-pcm.txt +++ /dev/null @@ -1,42 +0,0 @@ -Mediatek AFE PCM controller for mt8183 - -Required properties: -- compatible = "mediatek,mt68183-audio"; -- reg: register location and size -- interrupts: should contain AFE interrupt -- resets: Must contain an entry for each entry in reset-names - See ../reset/reset.txt for details. -- reset-names: should have these reset names: - "audiosys"; -- power-domains: should define the power domain -- clocks: Must contain an entry for each entry in clock-names -- clock-names: should have these clock names: - "infra_sys_audio_clk", - "mtkaif_26m_clk", - "top_mux_audio", - "top_mux_aud_intbus", - "top_sys_pll3_d4", - "top_clk26m_clk"; - -Example: - - afe: mt8183-afe-pcm@11220000 { - compatible = "mediatek,mt8183-audio"; - reg = <0 0x11220000 0 0x1000>; - interrupts = <GIC_SPI 161 IRQ_TYPE_LEVEL_LOW>; - resets = <&watchdog MT8183_TOPRGU_AUDIO_SW_RST>; - reset-names = "audiosys"; - power-domains = <&scpsys MT8183_POWER_DOMAIN_AUDIO>; - clocks = <&infrasys CLK_INFRA_AUDIO>, - <&infrasys CLK_INFRA_AUDIO_26M_BCLK>, - <&topckgen CLK_TOP_MUX_AUDIO>, - <&topckgen CLK_TOP_MUX_AUD_INTBUS>, - <&topckgen CLK_TOP_SYSPLL_D2_D4>, - <&clk26m>; - clock-names = "infra_sys_audio_clk", - "mtkaif_26m_clk", - "top_mux_audio", - "top_mux_aud_intbus", - "top_sys_pll_d2_d4", - "top_clk26m_clk"; - }; diff --git a/Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt b/Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt deleted file mode 100644 index f276dfc74b46..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8183-da7219-max98357.txt +++ /dev/null @@ -1,21 +0,0 @@ -MT8183 with MT6358, DA7219, MAX98357, and RT1015 CODECS - -Required properties: -- compatible : "mediatek,mt8183_da7219_max98357" for MAX98357A codec - "mediatek,mt8183_da7219_rt1015" for RT1015 codec - "mediatek,mt8183_da7219_rt1015p" for RT1015P codec -- mediatek,headset-codec: the phandles of da7219 codecs -- mediatek,platform: the phandle of MT8183 ASoC platform - -Optional properties: -- mediatek,hdmi-codec: the phandles of HDMI codec - -Example: - - sound { - compatible = "mediatek,mt8183_da7219_max98357"; - mediatek,headset-codec = <&da7219>; - mediatek,hdmi-codec = <&it6505dptx>; - mediatek,platform = <&afe>; - }; - diff --git a/Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt b/Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt deleted file mode 100644 index ecd46ed8eb98..000000000000 --- a/Documentation/devicetree/bindings/sound/mt8183-mt6358-ts3a227-max98357.txt +++ /dev/null @@ -1,25 +0,0 @@ -MT8183 with MT6358, TS3A227, MAX98357, and RT1015 CODECS - -Required properties: -- compatible : "mediatek,mt8183_mt6358_ts3a227_max98357" for MAX98357A codec - "mediatek,mt8183_mt6358_ts3a227_max98357b" for MAX98357B codec - "mediatek,mt8183_mt6358_ts3a227_rt1015" for RT1015 codec - "mediatek,mt8183_mt6358_ts3a227_rt1015p" for RT1015P codec -- mediatek,platform: the phandle of MT8183 ASoC platform - -Optional properties: -- mediatek,headset-codec: the phandles of ts3a227 codecs -- mediatek,ec-codec: the phandle of EC codecs. - See google,cros-ec-codec.txt for more details. -- mediatek,hdmi-codec: the phandles of HDMI codec - -Example: - - sound { - compatible = "mediatek,mt8183_mt6358_ts3a227_max98357"; - mediatek,headset-codec = <&ts3a227>; - mediatek,ec-codec = <&ec_codec>; - mediatek,hdmi-codec = <&it6505dptx>; - mediatek,platform = <&afe>; - }; - diff --git a/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml b/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml index a54f194a0b49..4ebbcb4e6056 100644 --- a/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml +++ b/Documentation/devicetree/bindings/sound/nuvoton,nau8825.yaml @@ -9,6 +9,20 @@ title: NAU8825 audio CODEC maintainers: - John Hsu <KCHSU0@nuvoton.com> +description: | + NAU8825 audio CODEC + + Pins on the device (for linking into audio routes): + + Outputs: + * HPOL : Headphone Left Output + * HPOR : Headphone Right Output + * MICBIAS : Microphone Bias Output + + Inputs: + * MICP : Analog Microphone Positive Input + * MICN : Analog Microphone Negative Input + allOf: - $ref: dai-common.yaml# diff --git a/Documentation/devicetree/bindings/sound/omap-twl4030.txt b/Documentation/devicetree/bindings/sound/omap-twl4030.txt deleted file mode 100644 index f6a715e4ef43..000000000000 --- a/Documentation/devicetree/bindings/sound/omap-twl4030.txt +++ /dev/null @@ -1,62 +0,0 @@ -* Texas Instruments SoC with twl4030 based audio setups - -Required properties: -- compatible: "ti,omap-twl4030" -- ti,model: Name of the sound card (for example "omap3beagle") -- ti,mcbsp: phandle for the McBSP node - -Optional properties: -- ti,codec: phandle for the twl4030 audio node -- ti,mcbsp-voice: phandle for the McBSP node connected to the voice port of twl -- ti, jack-det-gpio: Jack detect GPIO -- ti,audio-routing: List of connections between audio components. - Each entry is a pair of strings, the first being the connection's sink, - the second being the connection's source. - If the routing is not provided all possible connection will be available - -Available audio endpoints for the audio-routing table: - -Board connectors: - * Headset Stereophone - * Earpiece Spk - * Handsfree Spk - * Ext Spk - * Main Mic - * Sub Mic - * Headset Mic - * Carkit Mic - * Digital0 Mic - * Digital1 Mic - * Line In - -twl4030 pins: - * HSOL - * HSOR - * EARPIECE - * HFL - * HFR - * PREDRIVEL - * PREDRIVER - * CARKITL - * CARKITR - * MAINMIC - * SUBMIC - * HSMIC - * DIGIMIC0 - * DIGIMIC1 - * CARKITMIC - * AUXL - * AUXR - - * Headset Mic Bias - * Mic Bias 1 /* Used for Main Mic or Digimic0 */ - * Mic Bias 2 /* Used for Sub Mic or Digimic1 */ - -Example: - -sound { - compatible = "ti,omap-twl4030"; - ti,model = "omap3beagle"; - - ti,mcbsp = <&mcbsp2>; -}; diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml index dd549db6c841..1c0d78af3c05 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-va-macro.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc8280xp-lpass-va-macro - items: - enum: + - qcom,glymur-lpass-va-macro - qcom,sm8650-lpass-va-macro - qcom,sm8750-lpass-va-macro - qcom,x1e80100-lpass-va-macro @@ -79,12 +80,25 @@ allOf: compatible: contains: const: qcom,sc7280-lpass-va-macro + then: - properties: - clocks: - maxItems: 1 - clock-names: - maxItems: 1 + if: + required: + - power-domains + then: + properties: + clocks: + maxItems: 1 + clock-names: + maxItems: 1 + else: + properties: + clocks: + minItems: 3 + maxItems: 3 + clock-names: + minItems: 3 + maxItems: 3 - if: properties: diff --git a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml index 9082e363c709..b6f5ba5d1320 100644 --- a/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,lpass-wsa-macro.yaml @@ -20,6 +20,7 @@ properties: - qcom,sc8280xp-lpass-wsa-macro - items: - enum: + - qcom,glymur-lpass-wsa-macro - qcom,sm8650-lpass-wsa-macro - qcom,sm8750-lpass-wsa-macro - qcom,x1e80100-lpass-wsa-macro diff --git a/Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml b/Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml new file mode 100644 index 000000000000..6e2f103be1d3 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,pm4125-codec.yaml @@ -0,0 +1,134 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,pm4125-codec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm PM4125 Audio Codec + +maintainers: + - Alexey Klimov <alexey.klimov@linaro.org> + +description: + The audio codec IC found on Qualcomm PM4125/PM2250 PMIC. + It has RX and TX Soundwire slave devices. + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + const: qcom,pm4125-codec + + reg: + description: + Specifies the SPMI base address for the audio codec peripherals. The + address space contains reset register needed to power-on the codec. + maxItems: 1 + + reg-names: + maxItems: 1 + + vdd-io-supply: + description: A reference to the 1.8V I/O supply + + vdd-cp-supply: + description: A reference to the charge pump I/O supply + + vdd-mic-bias-supply: + description: A reference to the 3.3V mic bias supply + + vdd-pa-vpos-supply: + description: A reference to the PA VPOS supply + + qcom,tx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire tx device phandle + + qcom,rx-device: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: A reference to Soundwire rx device phandle + + qcom,micbias1-microvolt: + description: micbias1 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias2-microvolt: + description: micbias2 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,micbias3-microvolt: + description: micbias3 voltage + minimum: 1800000 + maximum: 2850000 + + qcom,mbhc-buttons-vthreshold-microvolt: + description: + Array of 8 Voltage threshold values corresponding to headset + button0 - button7 + minItems: 8 + maxItems: 8 + + '#sound-dai-cells': + const: 1 + +required: + - compatible + - reg + - vdd-io-supply + - vdd-cp-supply + - vdd-mic-bias-supply + - vdd-pa-vpos-supply + - qcom,tx-device + - qcom,rx-device + - qcom,micbias1-microvolt + - qcom,micbias2-microvolt + - qcom,micbias3-microvolt + - '#sound-dai-cells' + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/spmi/spmi.h> + + spmi { + #address-cells = <2>; + #size-cells = <0>; + + pmic { + #address-cells = <1>; + #size-cells = <0>; + + audio-codec@f000 { + compatible = "qcom,pm4125-codec"; + reg = <0xf000>; + vdd-io-supply = <&pm4125_l15>; + vdd-cp-supply = <&pm4125_s4>; + vdd-pa-vpos-supply = <&pm4125_s4>; + vdd-mic-bias-supply = <&pm4125_l22>; + qcom,micbias1-microvolt = <1800000>; + qcom,micbias2-microvolt = <1800000>; + qcom,micbias3-microvolt = <1800000>; + qcom,rx-device = <&pm4125_rx>; + qcom,tx-device = <&pm4125_tx>; + #sound-dai-cells = <1>; + }; + }; + }; + + /* ... */ + + soundwire@a610000 { + reg = <0x0a610000 0x2000>; + #address-cells = <2>; + #size-cells = <0>; + pm4125_rx: audio-codec@0,4 { + compatible = "sdw20217010c00"; + reg = <0 4>; + qcom,rx-port-mapping = <1 3>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml b/Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml new file mode 100644 index 000000000000..23624f32ac30 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/qcom,pm4125-sdw.yaml @@ -0,0 +1,79 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/qcom,pm4125-sdw.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SoundWire Slave devices on PM4125/PM2250 PMIC audio codec. + +maintainers: + - Alexey Klimov <alexey.klimov@linaro.org> + +description: + The audio codec IC found on Qualcomm PM4125/PM2250 PMICs. + It has RX and TX Soundwire slave devices. + +properties: + compatible: + const: sdw20217010c00 + + reg: + maxItems: 1 + + qcom,tx-port-mapping: + description: | + Specifies static port mapping between device and host tx ports. + In the order of the device port index which are adc1_port, adc23_port, + dmic03_mbhc_port, dmic46_port. + Supports maximum 2 tx soundwire ports. + + PM4125 TX Port 1 (ADC1,2 & DMIC0 & MBHC) <=> SWR0 Port 1 + PM4125 TX Port 2 (ADC1 & DMIC0,1,2 & MBHC) <=> SWR0 Port 2 + + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + enum: [1, 2, 3, 4] + + qcom,rx-port-mapping: + description: | + Specifies static port mapping between device and host rx ports. + In the order of device port index which are hph_port, clsh_port, + comp_port, lo_port, dsd port. + Supports maximum 2 rx soundwire ports. + + PM4125 RX Port 1 (HPH_L/R) <==> SWR1 Port 1 (HPH_L/R) + PM4125 RX Port 2 (COMP_L/R) <==> SWR1 Port 3 (COMP_L/R) + + $ref: /schemas/types.yaml#/definitions/uint32-array + minItems: 2 + maxItems: 2 + items: + enum: [1, 2, 3, 4, 5] + +required: + - compatible + - reg + +oneOf: + - required: + - qcom,tx-port-mapping + - required: + - qcom,rx-port-mapping + +additionalProperties: false + +examples: + - | + soundwire@a610000 { + reg = <0x0a610000 0x2000>; + #address-cells = <2>; + #size-cells = <0>; + pm4125_rx: codec@0,1 { + compatible = "sdw20217010c00"; + reg = <0 1>; + qcom,rx-port-mapping = <1 3>; + }; + }; +... diff --git a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml index 5d3dbb6cb1ae..8ac91625dce5 100644 --- a/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,sm8250.yaml @@ -31,6 +31,7 @@ properties: - fairphone,fp4-sndcard - fairphone,fp5-sndcard - qcom,apq8096-sndcard + - qcom,glymur-sndcard - qcom,qcm6490-idp-sndcard - qcom,qcs6490-rb3gen2-sndcard - qcom,qcs8275-sndcard diff --git a/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml b/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml index 14d312f9c345..098f1df62c8c 100644 --- a/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml +++ b/Documentation/devicetree/bindings/sound/qcom,wsa883x.yaml @@ -29,6 +29,10 @@ properties: description: GPIO spec for Powerdown/Shutdown line to use (pin SD_N) maxItems: 1 + reset-gpios: + description: Powerdown/Shutdown line to use (pin SD_N) + maxItems: 1 + vdd-supply: description: VDD Supply for the Codec @@ -50,10 +54,15 @@ required: - compatible - reg - vdd-supply - - powerdown-gpios - "#thermal-sensor-cells" - "#sound-dai-cells" +oneOf: + - required: + - powerdown-gpios + - required: + - reset-gpios + unevaluatedProperties: false examples: diff --git a/Documentation/devicetree/bindings/sound/realtek,alc5623.yaml b/Documentation/devicetree/bindings/sound/realtek,alc5623.yaml new file mode 100644 index 000000000000..683c58c3ef50 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/realtek,alc5623.yaml @@ -0,0 +1,54 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/realtek,alc5623.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ALC5621/ALC5623 Audio Codec + +maintainers: + - Mahdi Khosravi <mmk1776@gmail.com> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - realtek,alc5621 + - realtek,alc5623 + + reg: + maxItems: 1 + + add-ctrl: + description: + Default register value for Reg-40h, Additional Control Register. + If absent or zero, the register is left untouched. + $ref: /schemas/types.yaml#/definitions/uint32 + + jack-det-ctrl: + description: + Default register value for Reg-5Ah, Jack Detect Control Register. + If absent or zero, the register is left untouched. + $ref: /schemas/types.yaml#/definitions/uint32 + +required: + - compatible + - reg + +unevaluatedProperties: false + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + codec@1a { + compatible = "realtek,alc5623"; + reg = <0x1a>; + add-ctrl = <0x3700>; + jack-det-ctrl = <0x4810>; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml b/Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml new file mode 100644 index 000000000000..27c7019bdc85 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,omap-twl4030.yaml @@ -0,0 +1,98 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,omap-twl4030.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments SoC with twl4030 based audio setups + +maintainers: + - Peter Ujfalusi <peter.ujfalusi@gmail.com> + +description: + Audio setups on TI OMAP SoCs using TWL4030-family + audio codec connected via a McBSP port. + +properties: + compatible: + const: ti,omap-twl4030 + + ti,model: + $ref: /schemas/types.yaml#/definitions/string + description: Name of the sound card (for example "omap3beagle"). + + ti,mcbsp: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle for the McBSP node. + + ti,codec: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle for the twl4030 audio node. + + ti,mcbsp-voice: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the McBSP node connected to the voice port. + + ti,jack-det-gpio: + description: GPIO specifier for jack detection. + maxItems: 1 + + ti,audio-routing: + description: | + A list of audio routing connections. Each entry is a pair of strings, + with the first being the connection's sink and the second being the + source. If not provided, all possible connections are available. + + $ref: /schemas/types.yaml#/definitions/non-unique-string-array + items: + enum: + # Board Connectors + - Headset Stereophone + - Earpiece Spk + - Handsfree Spk + - Ext Spk + - Main Mic + - Sub Mic + - Headset Mic + - Carkit Mic + - Digital0 Mic + - Digital1 Mic + - Line In + + # CODEC Pins + - HSOL + - HSOR + - EARPIECE + - HFL + - HFR + - PREDRIVEL + - PREDRIVER + - CARKITL + - CARKITR + - MAINMIC + - SUBMIC + - HSMIC + - DIGIMIC0 + - DIGIMIC1 + - CARKITMIC + - AUXL + - AUXR + + # Headset Mic Bias + - Mic Bias 1 # Used for Main Mic or Digimic0 + - Mic Bias 2 # Used for Sub Mic or Digimic1 + +required: + - compatible + - ti,model + - ti,mcbsp + +additionalProperties: false + +examples: + - | + sound { + compatible = "ti,omap-twl4030"; + ti,model = "omap3beagle"; + ti,mcbsp = <&mcbsp2>; + }; diff --git a/Documentation/devicetree/bindings/sound/ti,pcm1754.yaml b/Documentation/devicetree/bindings/sound/ti,pcm1754.yaml new file mode 100644 index 000000000000..a757f737690c --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,pcm1754.yaml @@ -0,0 +1,55 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,pcm1754.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments PCM1754 Stereo DAC + +description: + The PCM1754 is a simple stereo DAC that is controlled via hardware gpios. + +maintainers: + - Stefan Kerkmann <s.kerkmann@pengutronix.de> + +allOf: + - $ref: dai-common.yaml# + +properties: + compatible: + enum: + - ti,pcm1754 + + vcc-supply: true + + '#sound-dai-cells': + const: 0 + + format-gpios: + maxItems: 1 + description: + GPIO used to select the PCM format + + mute-gpios: + maxItems: 1 + description: + GPIO used to mute all outputs + +required: + - compatible + - '#sound-dai-cells' + - vcc-supply + +additionalProperties: false + +examples: + - | + #include <dt-bindings/gpio/gpio.h> + codec { + compatible = "ti,pcm1754"; + #sound-dai-cells = <0>; + + vcc-supply = <&vcc_reg>; + mute-gpios = <&gpio 0 GPIO_ACTIVE_HIGH>; + format-gpios = <&gpio 1 GPIO_ACTIVE_HIGH>; + }; diff --git a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml index 5ea1cdc593b5..bd00afa47d62 100644 --- a/Documentation/devicetree/bindings/sound/ti,tas2781.yaml +++ b/Documentation/devicetree/bindings/sound/ti,tas2781.yaml @@ -1,5 +1,5 @@ # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) -# Copyright (C) 2022 - 2023 Texas Instruments Incorporated +# Copyright (C) 2022 - 2025 Texas Instruments Incorporated %YAML 1.2 --- $id: http://devicetree.org/schemas/sound/ti,tas2781.yaml# @@ -11,30 +11,77 @@ maintainers: - Shenghao Ding <shenghao-ding@ti.com> description: | + The TAS2118/TAS2X20 is mono, digital input Class-D audio + amplifier optimized for efficiently driving high peak power into + small loudspeakers. + The TAS257x is mono, digital input Class-D audio amplifier optimized + for efficiently driving high peak power into small loudspeakers. + Integrated speaker voltage and current sense provides for real time + monitoring of loudspeaker behavior. The TAS2563/TAS2781 is a mono, digital input Class-D audio amplifier optimized for efficiently driving high peak power into small loudspeakers. An integrated on-chip DSP supports Texas Instruments Smart Amp speaker protection algorithm. The integrated speaker voltage and current sense provides for real time monitoring of loudspeaker behavior. + The TAS5825/TAS5827 is a stereo, digital input Class-D audio + amplifier optimized for efficiently driving high peak power into + small loudspeakers. An integrated on-chip DSP supports Texas + Instruments Smart Amp speaker protection algorithm. Specifications about the audio amplifier can be found at: + https://www.ti.com/lit/gpn/tas2120 + https://www.ti.com/lit/gpn/tas2320 https://www.ti.com/lit/gpn/tas2563 + https://www.ti.com/lit/gpn/tas2572 https://www.ti.com/lit/gpn/tas2781 + https://www.ti.com/lit/gpn/tas5825m + https://www.ti.com/lit/gpn/tas5827 properties: compatible: description: | + ti,tas2020: 3.2-W Mono Digital Input Class-D Speaker Amp with 5.5V PVDD + Support. + + ti,tas2118: 5-W Mono Digital Input Class-D Speaker Amp with Integrated + 8.4-V Class-H Boost. + + ti,tas2120: 8.2-W Mono Digital Input Class-D Speaker Amp with + Integrated 14.75V Class-H Boost. + + ti,tas2320: 15-W Mono Digital Input Class-D Speaker Amp with 15V Support. + ti,tas2563: 6.1-W Boosted Class-D Audio Amplifier With Integrated DSP and IV Sense, 16/20/24/32bit stereo I2S or multichannel TDM. + ti,tas2570: 5.8-W Digital Input smart amp with I/V sense and integrated + 11-V Class-H Boost + + ti,tas2572: 6.6-W Digital Input smart amp with I/V sense and integrated + 13-V Class-H Boost + ti,tas2781: 24-V Class-D Amplifier with Real Time Integrated Speaker Protection and Audio Processing, 16/20/24/32bit stereo I2S or multichannel TDM. + + ti,tas5825: 38-W Stereo, Inductor-Less, Digital Input, Closed-Loop 4.5V + to 26.4V Class-D Audio Amplifier with 192-kHz Extended Audio Processing. + + ti,tas5827: 47-W Stereo, Digital Input, High Efficiency Closed-Loop Class-D + Amplifier with Class-H Algorithm oneOf: - items: - enum: + - ti,tas2020 + - ti,tas2118 + - ti,tas2120 + - ti,tas2320 - ti,tas2563 + - ti,tas2570 + - ti,tas2572 + - ti,tas5825 + - ti,tas5827 - const: ti,tas2781 - enum: - ti,tas2781 @@ -66,7 +113,25 @@ allOf: compatible: contains: enum: + - ti,tas2020 + - ti,tas2118 + - ti,tas2120 + - ti,tas2320 + then: + properties: + reg: + maxItems: 4 + items: + minimum: 0x48 + maximum: 0x4b + + - if: + properties: + compatible: + contains: + enum: - ti,tas2563 + - ti,tas5825 then: properties: reg: @@ -84,6 +149,21 @@ allOf: compatible: contains: enum: + - ti,tas2570 + - ti,tas2572 + then: + properties: + reg: + maxItems: 4 + items: + minimum: 0x48 + maximum: 0x4b + + - if: + properties: + compatible: + contains: + enum: - ti,tas2781 then: properties: @@ -97,6 +177,20 @@ allOf: minimum: 0x38 maximum: 0x3f + - if: + properties: + compatible: + contains: + enum: + - ti,tas5827 + then: + properties: + reg: + maxItems: 6 + items: + minimum: 0x60 + maximum: 0x65 + additionalProperties: false examples: diff --git a/Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml b/Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml new file mode 100644 index 000000000000..c9c3f7513ad4 --- /dev/null +++ b/Documentation/devicetree/bindings/sound/ti,twl4030-audio.yaml @@ -0,0 +1,90 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/sound/ti,twl4030-audio.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Texas Instruments TWL4030-family Audio Module + +maintainers: + - Peter Ujfalusi <peter.ujfalusi@gmail.com> + +description: + The audio module within the TWL4030-family of companion chips consists + of an audio codec and a vibra driver. This binding describes the parent + node for these functions. + +properties: + compatible: + const: ti,twl4030-audio + + codec: + type: object + description: Node containing properties for the audio codec functionality. + + properties: + ti,digimic_delay: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Delay in milliseconds after enabling digital microphones to reduce + artifacts. + + ti,ramp_delay_value: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Headset ramp delay configuration to reduce pop noise. + + ti,hs_extmute: + type: boolean + description: + Enable the use of an external mute for headset pop reduction. + + ti,hs_extmute_gpio: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + The GPIO specifier for the external mute control. + maxItems: 1 + + ti,offset_cncl_path: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Offset cancellation path selection. Refer to the Technical + Reference Manual for valid values. + + # The 'codec' node itself is optional, but if it exists, it can be empty. + # We don't require any of its sub-properties. + + ti,enable-vibra: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1] + description: + Enable or disable the vibra functionality. + +additionalProperties: false + +required: + - compatible + +examples: + - | + i2c { + #address-cells = <1>; + #size-cells = <0>; + + twl: twl@48 { + reg = <0x48>; + interrupts = <7>; /* SYS_NIRQ cascaded to intc */ + interrupt-parent = <&intc>; + + twl_audio: audio { + compatible = "ti,twl4030-audio"; + + ti,enable-vibra = <1>; + + codec { + ti,ramp_delay_value = <3>; + }; + + }; + }; + }; diff --git a/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml b/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml index 3c2b9790ffcf..c8c786cb6c4b 100644 --- a/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml +++ b/Documentation/devicetree/bindings/sound/wlf,wm8960.yaml @@ -9,6 +9,28 @@ title: Wolfson WM8960 audio codec maintainers: - patches@opensource.cirrus.com +description: | + Wolfson WM8960 audio codec + + Pins on the device (for linking into audio routes): + + Outputs: + * HP_L : Left Headphone/Line Output + * HP_R : Right Headphone/Line Output + * SPK_LP : Left Speaker Output (Positive) + * SPK_LN : Left Speaker Output (Negative) + * SPK_RP : Right Speaker Output (Positive) + * SPK_RN : Right Speaker Output (Negative) + * OUT3 : Mono, Left, Right or buffered midrail output for capless mode + + Inputs: + * LINPUT1 : Left single-ended or negative differential microphone input + * RINPUT1 : Right single-ended or negative differential microphone input + * LINPUT2 : Left line input or positive differential microphone input + * RINPUT2 : Right line input or positive differential microphone input + * LINPUT3 : Left line input, positive differential microphone, or Jack Detect 2 + * RINPUT3 : Right line input, positive differential microphone, or Jack Detect 3 + properties: compatible: const: wlf,wm8960 diff --git a/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml new file mode 100644 index 000000000000..b4cef838bcd4 --- /dev/null +++ b/Documentation/devicetree/bindings/spi/amlogic,a4-spifc.yaml @@ -0,0 +1,82 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2025 Amlogic, Inc. All rights reserved +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/spi/amlogic,a4-spifc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: SPI flash controller for Amlogic ARM SoCs + +maintainers: + - Liang Yang <liang.yang@amlogic.com> + - Feng Chen <feng.chen@amlogic.com> + - Xianwei Zhao <xianwei.zhao@amlogic.com> + +description: + The Amlogic SPI flash controller is an extended version of the Amlogic NAND + flash controller. It supports SPI Nor Flash and SPI NAND Flash(where the Host + ECC HW engine could be enabled). + +allOf: + - $ref: /schemas/spi/spi-controller.yaml# + +properties: + compatible: + const: amlogic,a4-spifc + + reg: + maxItems: 1 + + clocks: + items: + - description: clock apb gate + - description: clock used for the controller + + clock-names: + items: + - const: gate + - const: core + + interrupts: + maxItems: 1 + + amlogic,rx-adj: + description: + Number of clock cycles by which sampling is delayed. + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2, 3] + default: 0 + +required: + - compatible + - reg + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + sfc0: spi@fe08d000 { + compatible = "amlogic,a4-spifc"; + reg = <0xfe08d000 0x800>; + clocks = <&clkc_periphs 31>, + <&clkc_periphs 102>; + clock-names = "gate", "core"; + + pinctrl-0 = <&spiflash_default>; + pinctrl-names = "default"; + + #address-cells = <1>; + #size-cells = <0>; + + flash@0 { + compatible = "spi-nand"; + reg = <0>; + #address-cells = <1>; + #size-cells = <1>; + nand-ecc-engine = <&sfc0>; + nand-ecc-strength = <8>; + nand-ecc-step-size = <512>; + }; + }; diff --git a/Documentation/devicetree/bindings/spi/apple,spi.yaml b/Documentation/devicetree/bindings/spi/apple,spi.yaml index 7bef605a2963..9356b9c337c8 100644 --- a/Documentation/devicetree/bindings/spi/apple,spi.yaml +++ b/Documentation/devicetree/bindings/spi/apple,spi.yaml @@ -14,12 +14,16 @@ maintainers: properties: compatible: - items: - - enum: - - apple,t8103-spi - - apple,t8112-spi - - apple,t6000-spi - - const: apple,spi + oneOf: + - items: + - const: apple,t6020-spi + - const: apple,t8103-spi + - items: + - enum: + - apple,t8103-spi + - apple,t8112-spi + - apple,t6000-spi + - const: apple,spi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml index d29772994cf5..11885d0cc209 100644 --- a/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,at91rm9200-spi.yaml @@ -31,11 +31,16 @@ properties: maxItems: 1 clock-names: - contains: - const: spi_clk + items: + - const: spi_clk + - const: spi_gclk + minItems: 1 clocks: - maxItems: 1 + items: + - description: Peripheral Bus clock + - description: Programmable Generic clock + minItems: 1 dmas: items: diff --git a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml index b0d99bc10535..30ab42c95c08 100644 --- a/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml +++ b/Documentation/devicetree/bindings/spi/atmel,quadspi.yaml @@ -17,6 +17,9 @@ properties: enum: - atmel,sama5d2-qspi - microchip,sam9x60-qspi + - microchip,sam9x7-ospi + - microchip,sama7d65-qspi + - microchip,sama7d65-ospi - microchip,sama7g5-qspi - microchip,sama7g5-ospi diff --git a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml index 2e20ca313ec1..d12c5a060ed0 100644 --- a/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml +++ b/Documentation/devicetree/bindings/spi/qcom,spi-geni-qcom.yaml @@ -25,6 +25,7 @@ description: allOf: - $ref: /schemas/spi/spi-controller.yaml# + - $ref: /schemas/soc/qcom/qcom,se-common-props.yaml# properties: compatible: diff --git a/Documentation/devicetree/bindings/spi/samsung,spi.yaml b/Documentation/devicetree/bindings/spi/samsung,spi.yaml index fe298d47b1a9..1ce8b2770a4a 100644 --- a/Documentation/devicetree/bindings/spi/samsung,spi.yaml +++ b/Documentation/devicetree/bindings/spi/samsung,spi.yaml @@ -18,7 +18,6 @@ properties: oneOf: - enum: - google,gs101-spi - - samsung,s3c2443-spi # for S3C2443, S3C2416 and S3C2450 - samsung,s3c6410-spi - samsung,s5pv210-spi # for S5PV210 and S5PC110 - samsung,exynos4210-spi diff --git a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml index a65a42ccaafe..a82360bed188 100644 --- a/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml +++ b/Documentation/devicetree/bindings/spi/spi-fsl-lpspi.yaml @@ -20,6 +20,7 @@ properties: - enum: - fsl,imx7ulp-spi - fsl,imx8qxp-spi + - nxp,s32g2-lpspi - items: - enum: - fsl,imx8ulp-spi @@ -27,6 +28,10 @@ properties: - fsl,imx94-spi - fsl,imx95-spi - const: fsl,imx7ulp-spi + - items: + - const: nxp,s32g3-lpspi + - const: nxp,s32g2-lpspi + reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml index 16bd7eb2b7af..ba524f1eb704 100644 --- a/Documentation/devicetree/bindings/spmi/apple,spmi.yaml +++ b/Documentation/devicetree/bindings/spmi/apple,spmi.yaml @@ -16,12 +16,20 @@ allOf: properties: compatible: - items: - - enum: - - apple,t8103-spmi - - apple,t6000-spmi - - apple,t8112-spmi - - const: apple,spmi + oneOf: + - items: + - enum: + - apple,t6020-spmi + - apple,t8012-spmi + - apple,t8015-spmi + - const: apple,t8103-spmi + - items: + - enum: + # Do not add additional SoC to this list. + - apple,t8103-spmi + - apple,t6000-spmi + - apple,t8112-spmi + - const: apple,spmi reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/sram/qcom,imem.yaml b/Documentation/devicetree/bindings/sram/qcom,imem.yaml index 72d35e30c439..6a627c57ae2f 100644 --- a/Documentation/devicetree/bindings/sram/qcom,imem.yaml +++ b/Documentation/devicetree/bindings/sram/qcom,imem.yaml @@ -18,6 +18,7 @@ properties: items: - enum: - qcom,apq8064-imem + - qcom,ipq5424-imem - qcom,msm8226-imem - qcom,msm8974-imem - qcom,msm8976-imem diff --git a/Documentation/devicetree/bindings/submitting-patches.rst b/Documentation/devicetree/bindings/submitting-patches.rst index 46d0b036c97e..5f24570f72e9 100644 --- a/Documentation/devicetree/bindings/submitting-patches.rst +++ b/Documentation/devicetree/bindings/submitting-patches.rst @@ -95,7 +95,7 @@ II. For kernel maintainers For subsystem bindings (anything affecting more than a single device), getting a devicetree maintainer to review it is required. - 3) For a series going though multiple trees, the binding patch should be + 3) For a series going through multiple trees, the binding patch should be kept with the driver using the binding. 4) The DTS files should however never be applied via driver subsystem tree, diff --git a/Documentation/devicetree/bindings/thermal/armada-thermal.txt b/Documentation/devicetree/bindings/thermal/armada-thermal.txt deleted file mode 100644 index ab8b8fccc7af..000000000000 --- a/Documentation/devicetree/bindings/thermal/armada-thermal.txt +++ /dev/null @@ -1,42 +0,0 @@ -* Marvell Armada 370/375/380/XP thermal management - -Required properties: - -- compatible: Should be set to one of the following: - * marvell,armada370-thermal - * marvell,armada375-thermal - * marvell,armada380-thermal - * marvell,armadaxp-thermal - * marvell,armada-ap806-thermal - * marvell,armada-ap807-thermal - * marvell,armada-cp110-thermal - -Note: these bindings are deprecated for AP806/CP110 and should instead -follow the rules described in: -Documentation/devicetree/bindings/arm/marvell/ap80x-system-controller.txt -Documentation/devicetree/bindings/arm/marvell/cp110-system-controller.txt - -- reg: Device's register space. - Two entries are expected, see the examples below. The first one points - to the status register (4B). The second one points to the control - registers (8B). - Note: The compatibles marvell,armada370-thermal, - marvell,armada380-thermal, and marvell,armadaxp-thermal must point to - "control MSB/control 1", with size of 4 (deprecated binding), or point - to "control LSB/control 0" with size of 8 (current binding). All other - compatibles must point to "control LSB/control 0" with size of 8. - -Examples: - - /* Legacy bindings */ - thermal@d0018300 { - compatible = "marvell,armada370-thermal"; - reg = <0xd0018300 0x4 - 0xd0018304 0x4>; - }; - - ap_thermal: thermal@6f8084 { - compatible = "marvell,armada-ap806-thermal"; - reg = <0x6f808C 0x4>, - <0x6f8084 0x8>; - }; diff --git a/Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml b/Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml new file mode 100644 index 000000000000..2c370317a40e --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/marvell,armada-ap806-thermal.yaml @@ -0,0 +1,46 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/marvell,armada-ap806-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada AP80x/CP110 thermal management + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + +properties: + compatible: + enum: + - marvell,armada-ap806-thermal + - marvell,armada-ap807-thermal + - marvell,armada-cp110-thermal + + reg: + maxItems: 1 + + interrupts: + description: + Overheat interrupt. The interrupt is connected thru a System Error + Interrupt (SEI) controller. + maxItems: 1 + + '#thermal-sensor-cells': + description: Cell represents the channel ID. There is one sensor per + channel. O refers to the thermal IP internal channel. + const: 1 + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + thermal-sensor@80 { + compatible = "marvell,armada-ap806-thermal"; + reg = <0x80 0x10>; + interrupts = <18>; + #thermal-sensor-cells = <1>; + }; diff --git a/Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml b/Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml new file mode 100644 index 000000000000..337792859448 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/marvell,armada370-thermal.yaml @@ -0,0 +1,37 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/marvell,armada370-thermal.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada 3xx/XP thermal management + +maintainers: + - Miquel Raynal <miquel.raynal@bootlin.com> + +properties: + compatible: + enum: + - marvell,armada370-thermal + - marvell,armada375-thermal + - marvell,armada380-thermal + - marvell,armadaxp-thermal + + reg: + items: + - description: status register (4B) + - description: control register (8B) + +required: + - compatible + - reg + +additionalProperties: false + +examples: + - | + thermal@d0018300 { + compatible = "marvell,armada370-thermal"; + reg = <0xd0018300 0x4>, + <0xd0018304 0x8>; + }; diff --git a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml index cf47a1f3b384..25efedced584 100644 --- a/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml +++ b/Documentation/devicetree/bindings/thermal/nvidia,tegra124-soctherm.yaml @@ -18,6 +18,7 @@ description: The SOCTHERM IP block contains thermal sensors, support for properties: compatible: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra132-soctherm - nvidia,tegra210-soctherm @@ -206,6 +207,7 @@ allOf: compatible: contains: enum: + - nvidia,tegra114-soctherm - nvidia,tegra124-soctherm - nvidia,tegra210-soctherm - nvidia,tegra210b01-soctherm diff --git a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml index 94311ebd7652..78e2f6573b96 100644 --- a/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml +++ b/Documentation/devicetree/bindings/thermal/qcom-tsens.yaml @@ -49,11 +49,13 @@ properties: - description: v2 of TSENS items: - enum: + - qcom,glymur-tsens - qcom,milos-tsens - qcom,msm8953-tsens - qcom,msm8996-tsens - qcom,msm8998-tsens - qcom,qcm2290-tsens + - qcom,qcs615-tsens - qcom,sa8255p-tsens - qcom,sa8775p-tsens - qcom,sar2130p-tsens diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml new file mode 100644 index 000000000000..573e2b9d3752 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a08g045-tsu.yaml @@ -0,0 +1,93 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a08g045-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S Thermal Sensor Unit + +description: + The thermal sensor unit (TSU) measures the temperature(Tj) inside + the LSI. + +maintainers: + - Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> + +$ref: thermal-sensor.yaml# + +properties: + compatible: + const: renesas,r9a08g045-tsu + + reg: + maxItems: 1 + + clocks: + items: + - description: TSU module clock + + power-domains: + maxItems: 1 + + resets: + items: + - description: TSU module reset + + io-channels: + items: + - description: ADC channel which reports the TSU temperature + + io-channel-names: + items: + - const: tsu + + "#thermal-sensor-cells": + const: 0 + +required: + - compatible + - reg + - clocks + - power-domains + - resets + - io-channels + - io-channel-names + - '#thermal-sensor-cells' + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/r9a08g045-cpg.h> + + tsu: thermal@10059000 { + compatible = "renesas,r9a08g045-tsu"; + reg = <0x10059000 0x1000>; + clocks = <&cpg CPG_MOD R9A08G045_TSU_PCLK>; + resets = <&cpg R9A08G045_TSU_PRESETN>; + power-domains = <&cpg>; + #thermal-sensor-cells = <0>; + io-channels = <&adc 8>; + io-channel-names = "tsu"; + }; + + thermal-zones { + cpu-thermal { + polling-delay-passive = <250>; + polling-delay = <1000>; + thermal-sensors = <&tsu>; + + trips { + sensor_crit: sensor-crit { + temperature = <125000>; + hysteresis = <1000>; + type = "critical"; + }; + target: trip-point { + temperature = <100000>; + hysteresis = <1000>; + type = "passive"; + }; + }; + }; + }; diff --git a/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml new file mode 100644 index 000000000000..8d3f3c24f0f2 --- /dev/null +++ b/Documentation/devicetree/bindings/thermal/renesas,r9a09g047-tsu.yaml @@ -0,0 +1,87 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/thermal/renesas,r9a09g047-tsu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3E Temperature Sensor Unit (TSU) + +maintainers: + - John Madieu <john.madieu.xa@bp.renesas.com> + +description: + The Temperature Sensor Unit (TSU) is an integrated thermal sensor that + monitors the chip temperature on the Renesas RZ/G3E SoC. The TSU provides + real-time temperature measurements for thermal management. + +properties: + compatible: + const: renesas,r9a09g047-tsu + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + resets: + maxItems: 1 + + power-domains: + maxItems: 1 + + interrupts: + items: + - description: Conversion complete interrupt signal (pulse) + - description: Comparison result interrupt signal (level) + + interrupt-names: + items: + - const: adi + - const: adcmpi + + "#thermal-sensor-cells": + const: 0 + + renesas,tsu-trim: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: phandle to system controller + - description: offset of trim registers + description: + Phandle and offset to the system controller containing the TSU + calibration trim values. The offset points to the first trim register + (OTPTSU1TRMVAL0), with the second trim register (OTPTSU1TRMVAL1) located + at offset + 4. + +required: + - compatible + - reg + - clocks + - resets + - power-domains + - interrupts + - interrupt-names + - "#thermal-sensor-cells" + - renesas,tsu-trim + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/renesas,r9a09g047-cpg.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + thermal-sensor@14002000 { + compatible = "renesas,r9a09g047-tsu"; + reg = <0x14002000 0x1000>; + clocks = <&cpg CPG_MOD 0x10a>; + resets = <&cpg 0xf8>; + power-domains = <&cpg>; + interrupts = <GIC_SPI 250 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "adi", "adcmpi"; + #thermal-sensor-cells = <0>; + renesas,tsu-trim = <&sys 0x330>; + }; diff --git a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml index 573f447cc26e..9fa5c4c49d76 100644 --- a/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml +++ b/Documentation/devicetree/bindings/thermal/rockchip-thermal.yaml @@ -120,6 +120,21 @@ required: allOf: - if: + properties: + compatible: + contains: + enum: + - rockchip,px30-tsadc + - rockchip,rk3366-tsadc + - rockchip,rk3399-tsadc + - rockchip,rk3568-tsadc + then: + required: + - rockchip,grf + else: + properties: + rockchip,grf: false + - if: not: properties: compatible: diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt b/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt deleted file mode 100644 index 3cb2f4c98d64..000000000000 --- a/Documentation/devicetree/bindings/timer/faraday,fttmr010.txt +++ /dev/null @@ -1,38 +0,0 @@ -Faraday Technology timer - -This timer is a generic IP block from Faraday Technology, embedded in the -Cortina Systems Gemini SoCs and other designs. - -Required properties: - -- compatible : Must be one of - "faraday,fttmr010" - "cortina,gemini-timer", "faraday,fttmr010" - "moxa,moxart-timer", "faraday,fttmr010" - "aspeed,ast2400-timer" - "aspeed,ast2500-timer" - "aspeed,ast2600-timer" - -- reg : Should contain registers location and length -- interrupts : Should contain the three timer interrupts usually with - flags for falling edge - -Optionally required properties: - -- clocks : a clock to provide the tick rate for "faraday,fttmr010" -- clock-names : should be "EXTCLK" and "PCLK" for the external tick timer - and peripheral clock respectively, for "faraday,fttmr010" -- syscon : a phandle to the global Gemini system controller if the compatible - type is "cortina,gemini-timer" - -Example: - -timer@43000000 { - compatible = "faraday,fttmr010"; - reg = <0x43000000 0x1000>; - interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ - <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ - <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ - clocks = <&extclk>, <&pclk>; - clock-names = "EXTCLK", "PCLK"; -}; diff --git a/Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml b/Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml new file mode 100644 index 000000000000..39506323556c --- /dev/null +++ b/Documentation/devicetree/bindings/timer/faraday,fttmr010.yaml @@ -0,0 +1,89 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/faraday,fttmr010.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Faraday FTTMR010 timer + +maintainers: + - Joel Stanley <joel@jms.id.au> + - Linus Walleij <linus.walleij@linaro.org> + +description: + This timer is a generic IP block from Faraday Technology, embedded in the + Cortina Systems Gemini SoCs and other designs. + +properties: + compatible: + oneOf: + - items: + - const: moxa,moxart-timer + - const: faraday,fttmr010 + - enum: + - aspeed,ast2400-timer + - aspeed,ast2500-timer + - aspeed,ast2600-timer + - cortina,gemini-timer + - faraday,fttmr010 + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 8 + description: One interrupt per timer + + clocks: + minItems: 1 + items: + - description: Peripheral clock + - description: External tick clock + + clock-names: + minItems: 1 + items: + - const: PCLK + - const: EXTCLK + + resets: + maxItems: 1 + + syscon: + description: System controller phandle for Gemini systems + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - interrupts + +allOf: + - if: + properties: + compatible: + contains: + const: cortina,gemini-timer + then: + required: + - syscon + else: + properties: + syscon: false + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + + timer@43000000 { + compatible = "faraday,fttmr010"; + reg = <0x43000000 0x1000>; + interrupts = <14 IRQ_TYPE_EDGE_FALLING>, /* Timer 1 */ + <15 IRQ_TYPE_EDGE_FALLING>, /* Timer 2 */ + <16 IRQ_TYPE_EDGE_FALLING>; /* Timer 3 */ + clocks = <&pclk>, <&extclk>; + clock-names = "PCLK", "EXTCLK"; + }; diff --git a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml index 0e4a8ddc3de3..e3b61b62521e 100644 --- a/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,ftm-timer.yaml @@ -14,7 +14,9 @@ properties: const: fsl,ftm-timer reg: - maxItems: 1 + items: + - description: clock event device + - description: clock source device interrupts: maxItems: 1 @@ -50,7 +52,8 @@ examples: ftm@400b8000 { compatible = "fsl,ftm-timer"; - reg = <0x400b8000 0x1000>; + reg = <0x400b8000 0x1000>, + <0x400b9000 0x1000>; interrupts = <0 44 IRQ_TYPE_LEVEL_HIGH>; clock-names = "ftm-evt", "ftm-src", "ftm-evt-counter-en", "ftm-src-counter-en"; clocks = <&clks VF610_CLK_FTM2>, <&clks VF610_CLK_FTM3>, diff --git a/Documentation/devicetree/bindings/timer/fsl,timrot.yaml b/Documentation/devicetree/bindings/timer/fsl,timrot.yaml new file mode 100644 index 000000000000..d181f274ef9f --- /dev/null +++ b/Documentation/devicetree/bindings/timer/fsl,timrot.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/fsl,timrot.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale MXS Timer + +maintainers: + - Frank Li <Frank.Li@nxp.com> + +properties: + compatible: + items: + - enum: + - fsl,imx23-timrot + - fsl,imx28-timrot + - const: fsl,timrot + + reg: + maxItems: 1 + + interrupts: + items: + - description: irq for timer0 + - description: irq for timer1 + - description: irq for timer2 + - description: irq for timer3 + + clocks: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + timer: timer@80068000 { + compatible = "fsl,imx28-timrot", "fsl,timrot"; + reg = <0x80068000 0x2000>; + interrupts = <48>, <49>, <50>, <51>; + clocks = <&clks 26>; + }; diff --git a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml index bee2c35bd0e2..42e130654d58 100644 --- a/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml +++ b/Documentation/devicetree/bindings/timer/fsl,vf610-pit.yaml @@ -15,8 +15,13 @@ description: properties: compatible: - enum: - - fsl,vf610-pit + oneOf: + - enum: + - fsl,vf610-pit + - nxp,s32g2-pit + - items: + - const: nxp,s32g3-pit + - const: nxp,s32g2-pit reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml index f68fc7050c56..337580dc77d8 100644 --- a/Documentation/devicetree/bindings/timer/mediatek,timer.yaml +++ b/Documentation/devicetree/bindings/timer/mediatek,timer.yaml @@ -26,9 +26,11 @@ properties: - items: - enum: - mediatek,mt2701-timer + - mediatek,mt6572-timer - mediatek,mt6580-timer - mediatek,mt6582-timer - mediatek,mt6589-timer + - mediatek,mt6795-timer - mediatek,mt7623-timer - mediatek,mt8127-timer - mediatek,mt8135-timer @@ -44,6 +46,7 @@ properties: - mediatek,mt8188-timer - mediatek,mt8192-timer - mediatek,mt8195-timer + - mediatek,mt8196-timer - mediatek,mt8365-systimer - const: mediatek,mt6765-timer diff --git a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml index 3931054b42fb..3ad10c5b66ba 100644 --- a/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml +++ b/Documentation/devicetree/bindings/timer/renesas,rz-mtu3.yaml @@ -221,7 +221,10 @@ properties: maxItems: 1 "#pwm-cells": - const: 2 + oneOf: + - const: 2 + deprecated: true + - const: 3 required: - compatible @@ -299,5 +302,5 @@ examples: clocks = <&cpg CPG_MOD R9A07G044_MTU_X_MCK_MTU3>; power-domains = <&cpg>; resets = <&cpg R9A07G044_MTU_X_PRESET_MTU3>; - #pwm-cells = <2>; + #pwm-cells = <3>; }; diff --git a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml index 10578f544581..a4b229e0e78a 100644 --- a/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml +++ b/Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml @@ -26,6 +26,7 @@ properties: - items: - enum: - axis,artpec8-mct + - axis,artpec9-mct - google,gs101-mct - samsung,exynos2200-mct-peris - samsung,exynos3250-mct @@ -131,6 +132,7 @@ allOf: contains: enum: - axis,artpec8-mct + - axis,artpec9-mct - google,gs101-mct - samsung,exynos2200-mct-peris - samsung,exynos5260-mct diff --git a/Documentation/devicetree/bindings/trivial-devices.yaml b/Documentation/devicetree/bindings/trivial-devices.yaml index f3dd18681aa6..174a67707b08 100644 --- a/Documentation/devicetree/bindings/trivial-devices.yaml +++ b/Documentation/devicetree/bindings/trivial-devices.yaml @@ -293,10 +293,20 @@ properties: - mps,mp2856 # Monolithic Power Systems Inc. multi-phase controller mp2857 - mps,mp2857 + # Monolithic Power Systems Inc. multi-phase controller mp2869 + - mps,mp2869 # Monolithic Power Systems Inc. multi-phase controller mp2888 - mps,mp2888 # Monolithic Power Systems Inc. multi-phase controller mp2891 - mps,mp2891 + # Monolithic Power Systems Inc. multi-phase controller mp29502 + - mps,mp29502 + # Monolithic Power Systems Inc. multi-phase controller mp29608 + - mps,mp29608 + # Monolithic Power Systems Inc. multi-phase controller mp29612 + - mps,mp29612 + # Monolithic Power Systems Inc. multi-phase controller mp29816 + - mps,mp29816 # Monolithic Power Systems Inc. multi-phase controller mp2993 - mps,mp2993 # Monolithic Power Systems Inc. hot-swap protection device @@ -305,6 +315,8 @@ properties: - mps,mp5920 # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5990 - mps,mp5990 + # Monolithic Power Systems Inc. multi-phase hot-swap controller mp5998 + - mps,mp5998 # Monolithic Power Systems Inc. digital step-down converter mp9941 - mps,mp9941 # Temperature sensor with integrated fan control @@ -362,6 +374,9 @@ properties: # Sensirion low power multi-pixel gas sensor with I2C interface - sensirion,sgpc3 # Sensirion temperature & humidity sensor with I2C interface + - sensirion,sht20 + - sensirion,sht21 + - sensirion,sht25 - sensirion,sht4x # Sensortek 3 axis accelerometer - sensortek,stk8312 @@ -395,6 +410,8 @@ properties: - sparkfun,qwiic-joystick # Sierra Wireless mangOH Green SPI IoT interface - swir,mangoh-iotport-spi + # Synaptics I2C touchpad + - synaptics,synaptics_i2c # Ambient Light Sensor with SMBUS/Two Wire Serial Interface - taos,tsl2550 # Digital PWM System Controller PMBus diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 77160cd47f54..f1d1882009ba 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -48,6 +48,8 @@ patternProperties: description: Acme Systems srl "^actions,.*": description: Actions Semiconductor Co., Ltd. + "^actiontec,.*": + description: Actiontec Electronics, Inc "^active-semi,.*": description: Active-Semi International Inc "^ad,.*": @@ -86,6 +88,8 @@ patternProperties: description: Allegro DVT "^allegromicro,.*": description: Allegro MicroSystems, Inc. + "^alliedtelesis,.*": + description: Allied Telesis, Inc. "^alliedvision,.*": description: Allied Vision Technologies GmbH "^allo,.*": @@ -221,6 +225,8 @@ patternProperties: description: BeagleBoard.org Foundation "^belling,.*": description: Shanghai Belling Co., Ltd. + "^bestar,.*": + description: Shenzhen Bestar Electronic Technology Co., Ltd. "^bhf,.*": description: Beckhoff Automation GmbH & Co. KG "^bigtreetech,.*": @@ -229,6 +235,8 @@ patternProperties: description: Bitmain Technologies "^blaize,.*": description: Blaize, Inc. + "^bluegiga,.*": + description: Bluegiga Technologies Ltd. "^blutek,.*": description: BluTek Power "^boe,.*": @@ -247,6 +255,8 @@ patternProperties: description: Bticino International "^buffalo,.*": description: Buffalo, Inc. + "^buglabs,.*": + description: Bug Labs, Inc. "^bur,.*": description: B&R Industrial Automation GmbH "^bytedance,.*": @@ -325,6 +335,8 @@ patternProperties: description: Conexant Systems, Inc. "^colorfly,.*": description: Colorful GRP, Shenzhen Xueyushi Technology Ltd. + "^compal,.*": + description: Compal Electronics, Inc. "^compulab,.*": description: CompuLab Ltd. "^comvetia,.*": @@ -353,6 +365,8 @@ patternProperties: description: Guangzhou China Star Optoelectronics Technology Co., Ltd "^csq,.*": description: Shenzen Chuangsiqi Technology Co.,Ltd. + "^csr,.*": + description: Cambridge Silicon Radio "^ctera,.*": description: CTERA Networks Intl. "^ctu,.*": @@ -455,6 +469,8 @@ patternProperties: description: Emtop Embedded Solutions "^eeti,.*": description: eGalax_eMPIA Technology Inc + "^egnite,.*": + description: egnite GmbH "^einfochips,.*": description: Einfochips "^eink,.*": @@ -485,8 +501,12 @@ patternProperties: description: Empire Electronix "^emtrion,.*": description: emtrion GmbH + "^enbw,.*": + description: Energie Baden-Württemberg AG "^enclustra,.*": description: Enclustra GmbH + "^endian,.*": + description: Endian SRL "^endless,.*": description: Endless Mobile, Inc. "^ene,.*": @@ -507,6 +527,8 @@ patternProperties: description: Espressif Systems Co. Ltd. "^est,.*": description: ESTeem Wireless Modems + "^eswin,.*": + description: Beijing ESWIN Technology Group Co. Ltd. "^ettus,.*": description: NI Ettus Research "^eukrea,.*": @@ -548,10 +570,16 @@ patternProperties: description: Foxconn Industrial Internet "^firefly,.*": description: Firefly + "^flipkart,.*": + description: Flipkart Inc. "^focaltech,.*": description: FocalTech Systems Co.,Ltd "^forlinx,.*": description: Baoding Forlinx Embedded Technology Co., Ltd. + "^foursemi,.*": + description: Shanghai FourSemi Semiconductor Co.,Ltd. + "^foxlink,.*": + description: Foxlink Group "^freebox,.*": description: Freebox SAS "^freecom,.*": @@ -640,12 +668,18 @@ patternProperties: description: Haoyu Microelectronic Co. Ltd. "^hardkernel,.*": description: Hardkernel Co., Ltd + "^hce,.*": + description: HCE Engineering SRL + "^headacoustics,.*": + description: HEAD acoustics "^hechuang,.*": description: Shenzhen Hechuang Intelligent Co. "^hideep,.*": description: HiDeep Inc. "^himax,.*": description: Himax Technologies, Inc. + "^hinlink,.*": + description: Shenzhen HINLINK Technology Co., Ltd. "^hirschmann,.*": description: Hirschmann Automation and Control GmbH "^hisi,.*": @@ -723,6 +757,8 @@ patternProperties: description: Shenzhen INANBO Electronic Technology Co., Ltd. "^incircuit,.*": description: In-Circuit GmbH + "^incostartec,.*": + description: INCOstartec GmbH "^indiedroid,.*": description: Indiedroid "^inet-tek,.*": @@ -931,6 +967,10 @@ patternProperties: description: Maxim Integrated Products "^maxlinear,.*": description: MaxLinear Inc. + "^maxtor,.*": + description: Maxtor Corporation + "^mayqueen,.*": + description: Mayqueen Technologies Ltd. "^mbvl,.*": description: Mobiveil Inc. "^mcube,.*": @@ -1094,6 +1134,8 @@ patternProperties: description: Nordic Semiconductor "^nothing,.*": description: Nothing Technology Limited + "^novatech,.*": + description: NovaTech Automation "^novatek,.*": description: Novatek "^novtech,.*": @@ -1179,6 +1221,8 @@ patternProperties: description: Parade Technologies Inc. "^parallax,.*": description: Parallax Inc. + "^particle,.*": + description: Particle Industries, Inc. "^pda,.*": description: Precision Design Associates, Inc. "^pegatron,.*": @@ -1189,6 +1233,8 @@ patternProperties: description: Pervasive Displays, Inc. "^phicomm,.*": description: PHICOMM Co., Ltd. + "^phontech,.*": + description: Phontech "^phytec,.*": description: PHYTEC Messtechnik GmbH "^picochip,.*": @@ -1273,6 +1319,8 @@ patternProperties: description: Ramtron International "^raspberrypi,.*": description: Raspberry Pi Foundation + "^raumfeld,.*": + description: Raumfeld GmbH "^raydium,.*": description: Raydium Semiconductor Corp. "^rda,.*": @@ -1311,6 +1359,8 @@ patternProperties: description: ROHM Semiconductor Co., Ltd "^ronbo,.*": description: Ronbo Electronics + "^ronetix,.*": + description: Ronetix GmbH "^roofull,.*": description: Shenzhen Roofull Technology Co, Ltd "^roseapplepi,.*": @@ -1337,8 +1387,12 @@ patternProperties: description: Schindler "^schneider,.*": description: Schneider Electric + "^schulercontrol,.*": + description: Schuler Group "^sciosense,.*": description: ScioSense B.V. + "^sdmc,.*": + description: SDMC Technology Co., Ltd "^seagate,.*": description: Seagate Technology PLC "^seeed,.*": @@ -1377,6 +1431,8 @@ patternProperties: description: Si-En Technology Ltd. "^si-linux,.*": description: Silicon Linux Corporation + "^sielaff,.*": + description: Sielaff GmbH & Co. "^siemens,.*": description: Siemens AG "^sifive,.*": @@ -1445,6 +1501,8 @@ patternProperties: description: SolidRun "^solomon,.*": description: Solomon Systech Limited + "^somfy,.*": + description: Somfy Systems Inc. "^sony,.*": description: Sony Corporation "^sophgo,.*": @@ -1510,11 +1568,16 @@ patternProperties: description: Sierra Wireless "^syna,.*": description: Synaptics Inc. + "^synaptics,.*": + description: Synaptics Inc. + deprecated: true "^synology,.*": description: Synology, Inc. "^synopsys,.*": description: Synopsys, Inc. (deprecated, use snps) deprecated: true + "^taos,.*": + description: Texas Advanced Optoelectronic Solutions Inc. "^tbs,.*": description: TBS Technologies "^tbs-biometrics,.*": @@ -1545,6 +1608,8 @@ patternProperties: description: Teltonika Networks "^tempo,.*": description: Tempo Semiconductor + "^tenda,.*": + description: Shenzhen Tenda Technology Co., Ltd. "^terasic,.*": description: Terasic Inc. "^tesla,.*": @@ -1648,6 +1713,8 @@ patternProperties: description: V3 Semiconductor "^vaisala,.*": description: Vaisala + "^valve,.*": + description: Valve Corporation "^vamrs,.*": description: Vamrs Ltd. "^variscite,.*": @@ -1748,6 +1815,8 @@ patternProperties: description: Extreme Engineering Solutions (X-ES) "^xiaomi,.*": description: Xiaomi Technology Co., Ltd. + "^xicor,.*": + description: Xicor Inc. "^xillybus,.*": description: Xillybus Ltd. "^xingbangda,.*": @@ -1809,7 +1878,7 @@ patternProperties: # Normal property name match without a comma # These should catch all node/property names without a prefix - "^[a-zA-Z0-9#_][a-zA-Z0-9+\\-._@]{0,63}$": true + "^[a-zA-Z0-9#_][a-zA-Z0-9#+\\-._@]{0,63}$": true "^[a-zA-Z0-9+\\-._]*@[0-9a-zA-Z,]*$": true "^#.*": true diff --git a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml index 310832fa8c28..05602678c070 100644 --- a/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/apple,wdt.yaml @@ -14,17 +14,22 @@ allOf: properties: compatible: - items: - - enum: - - apple,s5l8960x-wdt - - apple,t7000-wdt - - apple,s8000-wdt - - apple,t8010-wdt - - apple,t8015-wdt - - apple,t8103-wdt - - apple,t8112-wdt - - apple,t6000-wdt - - const: apple,wdt + oneOf: + - items: + - const: apple,t6020-wdt + - const: apple,t8103-wdt + - items: + - enum: + # Do not add additional SoC to this list. + - apple,s5l8960x-wdt + - apple,t7000-wdt + - apple,s8000-wdt + - apple,t8010-wdt + - apple,t8015-wdt + - apple,t8103-wdt + - apple,t8112-wdt + - apple,t6000-wdt + - const: apple,wdt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt b/Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt deleted file mode 100644 index a8d00c31a1d8..000000000000 --- a/Documentation/devicetree/bindings/watchdog/armada-37xx-wdt.txt +++ /dev/null @@ -1,23 +0,0 @@ -* Armada 37xx CPU Watchdog Timer Controller - -Required properties: -- compatible : must be "marvell,armada-3700-wdt" -- reg : base physical address of the controller and length of memory mapped - region. -- clocks : the clock feeding the watchdog timer. See clock-bindings.txt -- marvell,system-controller : reference to syscon node for the CPU Miscellaneous - Registers - -Example: - - cpu_misc: system-controller@d000 { - compatible = "marvell,armada-3700-cpu-misc", "syscon"; - reg = <0xd000 0x1000>; - }; - - wdt: watchdog@8300 { - compatible = "marvell,armada-3700-wdt"; - reg = <0x8300 0x40>; - marvell,system-controller = <&cpu_misc>; - clocks = <&xtalclk>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml index 179272f74de5..0821ba0e84a3 100644 --- a/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml +++ b/Documentation/devicetree/bindings/watchdog/kontron,sl28cpld-wdt.yaml @@ -11,14 +11,19 @@ maintainers: description: | This module is part of the sl28cpld multi-function device. For more - details see ../mfd/kontron,sl28cpld.yaml. + details see ../embedded-controller/kontron,sl28cpld.yaml. allOf: - $ref: watchdog.yaml# properties: compatible: - const: kontron,sl28cpld-wdt + oneOf: + - items: + - enum: + - kontron,sa67mcu-wdt + - const: kontron,sl28cpld-wdt + - const: kontron,sl28cpld-wdt reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml b/Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml new file mode 100644 index 000000000000..60d44d642fb5 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/marvell,armada-3700-wdt.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/marvell,armada-3700-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Armada 37xx CPU Watchdog Timer Controller + +maintainers: + - Marek Behún <kabel@kernel.org> + +properties: + compatible: + const: marvell,armada-3700-wdt + + reg: + maxItems: 1 + + clocks: + maxItems: 1 + + marvell,system-controller: + description: Reference to syscon node for the CPU Miscellaneous Registers + $ref: /schemas/types.yaml#/definitions/phandle + +required: + - compatible + - reg + - clocks + - marvell,system-controller + +additionalProperties: false + +examples: + - | + watchdog@8300 { + compatible = "marvell,armada-3700-wdt"; + reg = <0x8300 0x40>; + marvell,system-controller = <&cpu_misc>; + clocks = <&xtalclk>; + }; diff --git a/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt b/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt deleted file mode 100644 index 1169857d1d12..000000000000 --- a/Documentation/devicetree/bindings/watchdog/moxa,moxart-watchdog.txt +++ /dev/null @@ -1,15 +0,0 @@ -MOXA ART Watchdog timer - -Required properties: - -- compatible : Must be "moxa,moxart-watchdog" -- reg : Should contain registers location and length -- clocks : Should contain phandle for the clock that drives the counter - -Example: - - watchdog: watchdog@98500000 { - compatible = "moxa,moxart-watchdog"; - reg = <0x98500000 0x10>; - clocks = <&coreclk>; - }; diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt deleted file mode 100644 index 866a958b8a2b..000000000000 --- a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm-wdt.txt +++ /dev/null @@ -1,30 +0,0 @@ -Nuvoton NPCM Watchdog - -Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. -The watchdog supports a pre-timeout interrupt that fires 10ms before the -expiry. - -Required properties: -- compatible : "nuvoton,npcm750-wdt" for NPCM750 (Poleg), or - "nuvoton,wpcm450-wdt" for WPCM450 (Hermon), or - "nuvoton,npcm845-wdt" for NPCM845 (Arbel). -- reg : Offset and length of the register set for the device. -- interrupts : Contain the timer interrupt with flags for - falling edge. - -Required clocking property, have to be one of: -- clocks : phandle of timer reference clock. -- clock-frequency : The frequency in Hz of the clock that drives the NPCM7xx - timer (usually 25000000). - -Optional properties: -- timeout-sec : Contains the watchdog timeout in seconds - -Example: - -timer@f000801c { - compatible = "nuvoton,npcm750-wdt"; - interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; - reg = <0xf000801c 0x4>; - clocks = <&clk NPCM7XX_CLK_TIMER>; -}; diff --git a/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml new file mode 100644 index 000000000000..7aa30f5b5c49 --- /dev/null +++ b/Documentation/devicetree/bindings/watchdog/nuvoton,npcm750-wdt.yaml @@ -0,0 +1,60 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/watchdog/nuvoton,npcm750-wdt.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Nuvoton NPCM Watchdog + +maintainers: + - Joel Stanley <joel@jms.id.au> + +description: + Nuvoton NPCM timer module provides five 24-bit timer counters, and a watchdog. + The watchdog supports a pre-timeout interrupt that fires 10ms before the + expiry. + +allOf: + - $ref: watchdog.yaml# + +properties: + compatible: + oneOf: + - enum: + - nuvoton,npcm750-wdt + - nuvoton,wpcm450-wdt + - items: + - enum: + - nuvoton,npcm845-wdt + - const: nuvoton,npcm750-wdt + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + maxItems: 1 + + clock-frequency: + description: Frequency in Hz of the clock that drives the NPCM timer. + +required: + - compatible + - reg + - interrupts + +unevaluatedProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> + + watchdog@f000801c { + compatible = "nuvoton,npcm750-wdt"; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + reg = <0xf000801c 0x4>; + clocks = <&clk NPCM7XX_CLK_TIMER>; + }; diff --git a/Documentation/devicetree/bindings/writing-bindings.rst b/Documentation/devicetree/bindings/writing-bindings.rst index f8e0293a7c06..667816dd7d50 100644 --- a/Documentation/devicetree/bindings/writing-bindings.rst +++ b/Documentation/devicetree/bindings/writing-bindings.rst @@ -31,10 +31,19 @@ Overall design devices only need child nodes when the child nodes have their own DT resources. A single node can be multiple providers (e.g. clocks and resets). +- DON'T treat device node names as a stable ABI, but instead use phandles or + compatibles to find sibling devices. Exception: sub-nodes of given device + could be treated as ABI, if explicitly documented in the bindings. + - DON'T use 'syscon' alone without a specific compatible string. A 'syscon' hardware block should have a compatible string unique enough to infer the register layout of the entire block (at a minimum). +- DON'T use 'simple-mfd' compatible for non-trivial devices, where children + depend on some resources from the parent. Similarly, 'simple-bus' should not + be used for complex buses and even 'regs' property means device is not + a simple bus. + Properties ========== diff --git a/Documentation/devicetree/bindings/writing-schema.rst b/Documentation/devicetree/bindings/writing-schema.rst index 470d1521fa17..05c34248e544 100644 --- a/Documentation/devicetree/bindings/writing-schema.rst +++ b/Documentation/devicetree/bindings/writing-schema.rst @@ -53,7 +53,7 @@ description The default without any indicators is flowed, plain scalar style where single line breaks and leading whitespace are stripped. Paragraphs are delimited by blank lines (i.e. double line break). This style cannot contain ": " in it as - it will be interpretted as a key. Any " #" sequence will be interpretted as + it will be interpreted as a key. Any " #" sequence will be interpreted as a comment. There's other restrictions on characters as well. Most restrictions are on what the first character can be. @@ -165,6 +165,14 @@ The YAML Devicetree format also makes all string values an array and scalar values a matrix (in order to define groupings) even when only a single value is present. Single entries in schemas are fixed up to match this encoding. +When bindings cover multiple similar devices that differ in some properties, +those properties should be constrained for each device. This usually means: + + * In top level 'properties' define the property with the broadest constraints. + * In 'if:then:' blocks, further narrow the constraints for those properties. + * Do not define the properties within an 'if:then:' block (note that + 'additionalItems' also won't allow that). + Coding style ------------ diff --git a/Documentation/devicetree/of_unittest.rst b/Documentation/devicetree/of_unittest.rst index a6c05962add3..8b557acd29d1 100644 --- a/Documentation/devicetree/of_unittest.rst +++ b/Documentation/devicetree/of_unittest.rst @@ -56,7 +56,7 @@ drivers/of/unittest.c. See the content of the folder:: for the Device Tree Source Include files (.dtsi) included in testcases.dts. -When the kernel is build with CONFIG_OF_UNITTEST enabled, then the following make +When the kernel is built with CONFIG_OF_UNITTEST enabled, then the following make rule:: $(obj)/%.dtb: $(src)/%.dts FORCE @@ -133,7 +133,7 @@ via the following kernel symbols:: __dtb_testcases_end - address marking the end of test data blob Secondly, it calls of_fdt_unflatten_tree() to unflatten the flattened -blob. And finally, if the machine's device tree (i.e live tree) is present, +blob. And finally, if the machine's device tree (i.e. live tree) is present, then it attaches the unflattened test data tree to the live tree, else it attaches itself as a live device tree. diff --git a/Documentation/devicetree/overlay-notes.rst b/Documentation/devicetree/overlay-notes.rst index 35e79242af9a..ba401ef850e7 100644 --- a/Documentation/devicetree/overlay-notes.rst +++ b/Documentation/devicetree/overlay-notes.rst @@ -14,11 +14,11 @@ How overlays work A Devicetree's overlay purpose is to modify the kernel's live tree, and have the modification affecting the state of the kernel in a way that is reflecting the changes. -Since the kernel mainly deals with devices, any new device node that result +Since the kernel mainly deals with devices, any new device node that results in an active device should have it created while if the device node is either disabled or removed all together, the affected device should be deregistered. -Lets take an example where we have a foo board with the following base tree:: +Let's take an example where we have a foo board with the following base tree:: ---- foo.dts --------------------------------------------------------------- /* FOO platform */ @@ -111,7 +111,7 @@ The API is quite easy to use. 1) Call of_overlay_fdt_apply() to create and apply an overlay changeset. The return value is an error or a cookie identifying this overlay. -2) Call of_overlay_remove() to remove and cleanup the overlay changeset +2) Call of_overlay_remove() to remove and clean up the overlay changeset previously created via the call to of_overlay_fdt_apply(). Removal of an overlay changeset that is stacked by another will not be permitted. diff --git a/Documentation/devicetree/usage-model.rst b/Documentation/devicetree/usage-model.rst index 0717426856b2..c6146c96ac56 100644 --- a/Documentation/devicetree/usage-model.rst +++ b/Documentation/devicetree/usage-model.rst @@ -46,7 +46,7 @@ The DT was originally created by Open Firmware as part of the communication method for passing data from Open Firmware to a client program (like to an operating system). An operating system used the Device Tree to discover the topology of the hardware at runtime, and -thereby support a majority of available hardware without hard coded +thereby supported a majority of available hardware without hard coded information (assuming drivers were available for all devices). Since Open Firmware is commonly used on PowerPC and SPARC platforms, @@ -128,7 +128,7 @@ successor, the BeagleBoard xM board might look like, respectively:: compatible = "ti,omap3-beagleboard-xm", "ti,omap3450", "ti,omap3"; Where "ti,omap3-beagleboard-xm" specifies the exact model, it also -claims that it compatible with the OMAP 3450 SoC, and the omap3 family +claims that it is compatible with the OMAP 3450 SoC, and the omap3 family of SoCs in general. You'll notice that the list is sorted from most specific (exact board) to least specific (SoC family). @@ -205,7 +205,7 @@ platform-specific configuration data. During early boot, the architecture setup code calls of_scan_flat_dt() several times with different helper callbacks to parse device tree -data before paging is setup. The of_scan_flat_dt() code scans through +data before paging is set up. The of_scan_flat_dt() code scans through the device tree and uses the helpers to extract information required during early boot. Typically the early_init_dt_scan_chosen() helper is used to parse the chosen node including kernel parameters, diff --git a/Documentation/driver-api/crypto/iaa/iaa-crypto.rst b/Documentation/driver-api/crypto/iaa/iaa-crypto.rst index 8e50b900d51c..f815d4fd8372 100644 --- a/Documentation/driver-api/crypto/iaa/iaa-crypto.rst +++ b/Documentation/driver-api/crypto/iaa/iaa-crypto.rst @@ -476,7 +476,6 @@ Use the following commands to enable zswap:: # echo 0 > /sys/module/zswap/parameters/enabled # echo 50 > /sys/module/zswap/parameters/max_pool_percent # echo deflate-iaa > /sys/module/zswap/parameters/compressor - # echo zsmalloc > /sys/module/zswap/parameters/zpool # echo 1 > /sys/module/zswap/parameters/enabled # echo 100 > /proc/sys/vm/swappiness # echo never > /sys/kernel/mm/transparent_hugepage/enabled @@ -625,7 +624,6 @@ the 'fixed' compression mode:: echo 0 > /sys/module/zswap/parameters/enabled echo 50 > /sys/module/zswap/parameters/max_pool_percent echo deflate-iaa > /sys/module/zswap/parameters/compressor - echo zsmalloc > /sys/module/zswap/parameters/zpool echo 1 > /sys/module/zswap/parameters/enabled echo 100 > /proc/sys/vm/swappiness diff --git a/Documentation/driver-api/dpll.rst b/Documentation/driver-api/dpll.rst index eca72d9b9ed8..be1fc643b645 100644 --- a/Documentation/driver-api/dpll.rst +++ b/Documentation/driver-api/dpll.rst @@ -179,7 +179,23 @@ Phase offset measurement and adjustment Device may provide ability to measure a phase difference between signals on a pin and its parent dpll device. If pin-dpll phase offset measurement is supported, it shall be provided with ``DPLL_A_PIN_PHASE_OFFSET`` -attribute for each parent dpll device. +attribute for each parent dpll device. The reported phase offset may be +computed as the average of prior values and the current measurement, using +the following formula: + +.. math:: + curr\_avg = prev\_avg * \frac{2^N-1}{2^N} + new\_val * \frac{1}{2^N} + +where `curr_avg` is the current reported phase offset, `prev_avg` is the +previously reported value, `new_val` is the current measurement, and `N` is +the averaging factor. Configured averaging factor value is provided with +``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attribute of a device and value change can +be requested with the same attribute with ``DPLL_CMD_DEVICE_SET`` command. + + ================================== ====================================== + ``DPLL_A_PHASE_OFFSET_AVG_FACTOR`` attr configured value of phase offset + averaging factor + ================================== ====================================== Device may also provide ability to adjust a signal phase on a pin. If pin phase adjustment is supported, minimal and maximal values that pin diff --git a/Documentation/driver-api/early-userspace/buffer-format.rst b/Documentation/driver-api/early-userspace/buffer-format.rst index 726bfa2fe70d..4597a91100b7 100644 --- a/Documentation/driver-api/early-userspace/buffer-format.rst +++ b/Documentation/driver-api/early-userspace/buffer-format.rst @@ -86,6 +86,11 @@ c_mtime is ignored unless CONFIG_INITRAMFS_PRESERVE_MTIME=y is set. The c_filesize should be zero for any file which is not a regular file or symlink. +c_namesize may account for more than one trailing '\0', as long as the +value doesn't exceed PATH_MAX. This can be useful for ensuring that a +subsequent file data segment is aligned, e.g. to a filesystem block +boundary. + The c_chksum field contains a simple 32-bit unsigned sum of all the bytes in the data field. cpio(1) refers to this as "crc", which is clearly incorrect (a cyclic redundancy check is a different and diff --git a/Documentation/driver-api/gpio/board.rst b/Documentation/driver-api/gpio/board.rst index 4fd1cbd8296e..069b54d8591b 100644 --- a/Documentation/driver-api/gpio/board.rst +++ b/Documentation/driver-api/gpio/board.rst @@ -94,6 +94,71 @@ with the help of _DSD (Device Specific Data), introduced in ACPI 5.1:: For more information about the ACPI GPIO bindings see Documentation/firmware-guide/acpi/gpio-properties.rst. +Software Nodes +-------------- + +Software nodes allow board-specific code to construct an in-memory, +device-tree-like structure using struct software_node and struct +property_entry. This structure can then be associated with a platform device, +allowing drivers to use the standard device properties API to query +configuration, just as they would on an ACPI or device tree system. + +Software-node-backed GPIOs are described using the ``PROPERTY_ENTRY_GPIO()`` +macro, which ties a software node representing the GPIO controller with +consumer device. It allows consumers to use regular gpiolib APIs, such as +gpiod_get(), gpiod_get_optional(). + +The software node representing a GPIO controller need not be attached to the +GPIO controller device. The only requirement is that the node must be +registered and its name must match the GPIO controller's label. + +For example, here is how to describe a single GPIO-connected LED. This is an +alternative to using platform_data on legacy systems. + +.. code-block:: c + + #include <linux/property.h> + #include <linux/gpio/machine.h> + #include <linux/gpio/property.h> + + /* + * 1. Define a node for the GPIO controller. Its .name must match the + * controller's label. + */ + static const struct software_node gpio_controller_node = { + .name = "gpio-foo", + }; + + /* 2. Define the properties for the LED device. */ + static const struct property_entry led_device_props[] = { + PROPERTY_ENTRY_STRING("label", "myboard:green:status"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), + PROPERTY_ENTRY_GPIO("gpios", &gpio_controller_node, 42, GPIO_ACTIVE_HIGH), + { } + }; + + /* 3. Define the software node for the LED device. */ + static const struct software_node led_device_swnode = { + .name = "status-led", + .properties = led_device_props, + }; + + /* + * 4. Register the software nodes and the platform device. + */ + const struct software_node *swnodes[] = { + &gpio_controller_node, + &led_device_swnode, + NULL + }; + software_node_register_node_group(swnodes); + + // Then register a platform_device for "leds-gpio" and associate + // it with &led_device_swnode via .fwnode. + +For a complete guide on converting board files to use software nodes, see +Documentation/driver-api/gpio/legacy-boards.rst. + Platform Data ------------- Finally, GPIOs can be bound to devices and functions using platform data. Board diff --git a/Documentation/driver-api/gpio/index.rst b/Documentation/driver-api/gpio/index.rst index 43f6a3afe10b..87929840e85a 100644 --- a/Documentation/driver-api/gpio/index.rst +++ b/Documentation/driver-api/gpio/index.rst @@ -12,6 +12,7 @@ Contents: driver consumer board + legacy-boards drivers-on-gpio bt8xxgpio diff --git a/Documentation/driver-api/gpio/legacy-boards.rst b/Documentation/driver-api/gpio/legacy-boards.rst new file mode 100644 index 000000000000..46e3a26dba77 --- /dev/null +++ b/Documentation/driver-api/gpio/legacy-boards.rst @@ -0,0 +1,298 @@ +Supporting Legacy Boards +======================== + +Many drivers in the kernel, such as ``leds-gpio`` and ``gpio-keys``, are +migrating away from using board-specific ``platform_data`` to a unified device +properties interface. This interface allows drivers to be simpler and more +generic, as they can query properties in a standardized way. + +On modern systems, these properties are provided via device tree. However, some +older platforms have not been converted to device tree and instead rely on +board files to describe their hardware configuration. To bridge this gap and +allow these legacy boards to work with modern, generic drivers, the kernel +provides a mechanism called **software nodes**. + +This document provides a guide on how to convert a legacy board file from using +``platform_data`` and ``gpiod_lookup_table`` to the modern software node +approach for describing GPIO-connected devices. + +The Core Idea: Software Nodes +----------------------------- + +Software nodes allow board-specific code to construct an in-memory, +device-tree-like structure using struct software_node and struct +property_entry. This structure can then be associated with a platform device, +allowing drivers to use the standard device properties API (e.g., +device_property_read_u32(), device_property_read_string()) to query +configuration, just as they would on an ACPI or device tree system. + +The gpiolib code has support for handling software nodes, so that if GPIO is +described properly, as detailed in the section below, then regular gpiolib APIs, +such as gpiod_get(), gpiod_get_optional(), and others will work. + +Requirements for GPIO Properties +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +When using software nodes to describe GPIO connections, the following +requirements must be met for the GPIO core to correctly resolve the reference: + +1. **The GPIO controller's software node "name" must match the controller's + "label".** The gpiolib core uses this name to find the corresponding + struct gpio_chip at runtime. + This software node has to be registered, but need not be attached to the + device representing the GPIO controller that is providing the GPIO in + question. It may be left as a "free floating" node. + +2. **The GPIO property must be a reference.** The ``PROPERTY_ENTRY_GPIO()`` + macro handles this as it is an alias for ``PROPERTY_ENTRY_REF()``. + +3. **The reference must have exactly two arguments:** + + - The first argument is the GPIO offset within the controller. + - The second argument is the flags for the GPIO line (e.g., + GPIO_ACTIVE_HIGH, GPIO_ACTIVE_LOW). + +The ``PROPERTY_ENTRY_GPIO()`` macro is the preferred way of defining GPIO +properties in software nodes. + +Conversion Example +------------------ + +Let's walk through an example of converting a board file that defines a GPIO- +connected LED and a button. + +Before: Using Platform Data +~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +A typical legacy board file might look like this: + +.. code-block:: c + + #include <linux/platform_device.h> + #include <linux/leds.h> + #include <linux/gpio_keys.h> + #include <linux/gpio/machine.h> + + #define MYBOARD_GPIO_CONTROLLER "gpio-foo" + + /* LED setup */ + static const struct gpio_led myboard_leds[] = { + { + .name = "myboard:green:status", + .default_trigger = "heartbeat", + }, + }; + + static const struct gpio_led_platform_data myboard_leds_pdata = { + .num_leds = ARRAY_SIZE(myboard_leds), + .leds = myboard_leds, + }; + + static struct gpiod_lookup_table myboard_leds_gpios = { + .dev_id = "leds-gpio", + .table = { + GPIO_LOOKUP_IDX(MYBOARD_GPIO_CONTROLLER, 42, NULL, 0, GPIO_ACTIVE_HIGH), + { }, + }, + }; + + /* Button setup */ + static struct gpio_keys_button myboard_buttons[] = { + { + .code = KEY_WPS_BUTTON, + .desc = "WPS Button", + .active_low = 1, + }, + }; + + static const struct gpio_keys_platform_data myboard_buttons_pdata = { + .buttons = myboard_buttons, + .nbuttons = ARRAY_SIZE(myboard_buttons), + }; + + static struct gpiod_lookup_table myboard_buttons_gpios = { + .dev_id = "gpio-keys", + .table = { + GPIO_LOOKUP_IDX(MYBOARD_GPIO_CONTROLLER, 15, NULL, 0, GPIO_ACTIVE_LOW), + { }, + }, + }; + + /* Device registration */ + static int __init myboard_init(void) + { + gpiod_add_lookup_table(&myboard_leds_gpios); + gpiod_add_lookup_table(&myboard_buttons_gpios); + + platform_device_register_data(NULL, "leds-gpio", -1, + &myboard_leds_pdata, sizeof(myboard_leds_pdata)); + platform_device_register_data(NULL, "gpio-keys", -1, + &myboard_buttons_pdata, sizeof(myboard_buttons_pdata)); + + return 0; + } + +After: Using Software Nodes +~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Here is how the same configuration can be expressed using software nodes. + +Step 1: Define the GPIO Controller Node +*************************************** + +First, define a software node that represents the GPIO controller that the +LEDs and buttons are connected to. The ``name`` of this node must match the +name of the driver for the GPIO controller (e.g., "gpio-foo"). + +.. code-block:: c + + #include <linux/property.h> + #include <linux/gpio/property.h> + + #define MYBOARD_GPIO_CONTROLLER "gpio-foo" + + static const struct software_node myboard_gpio_controller_node = { + .name = MYBOARD_GPIO_CONTROLLER, + }; + +Step 2: Define Consumer Device Nodes and Properties +*************************************************** + +Next, define the software nodes for the consumer devices (the LEDs and buttons). +This involves creating a parent node for each device type and child nodes for +each individual LED or button. + +.. code-block:: c + + /* LED setup */ + static const struct software_node myboard_leds_node = { + .name = "myboard-leds", + }; + + static const struct property_entry myboard_status_led_props[] = { + PROPERTY_ENTRY_STRING("label", "myboard:green:status"), + PROPERTY_ENTRY_STRING("linux,default-trigger", "heartbeat"), + PROPERTY_ENTRY_GPIO("gpios", &myboard_gpio_controller_node, 42, GPIO_ACTIVE_HIGH), + { } + }; + + static const struct software_node myboard_status_led_swnode = { + .name = "status-led", + .parent = &myboard_leds_node, + .properties = myboard_status_led_props, + }; + + /* Button setup */ + static const struct software_node myboard_keys_node = { + .name = "myboard-keys", + }; + + static const struct property_entry myboard_wps_button_props[] = { + PROPERTY_ENTRY_STRING("label", "WPS Button"), + PROPERTY_ENTRY_U32("linux,code", KEY_WPS_BUTTON), + PROPERTY_ENTRY_GPIO("gpios", &myboard_gpio_controller_node, 15, GPIO_ACTIVE_LOW), + { } + }; + + static const struct software_node myboard_wps_button_swnode = { + .name = "wps-button", + .parent = &myboard_keys_node, + .properties = myboard_wps_button_props, + }; + + + +Step 3: Group and Register the Nodes +************************************ + +For maintainability, it is often beneficial to group all software nodes into a +single array and register them with one call. + +.. code-block:: c + + static const struct software_node * const myboard_swnodes[] = { + &myboard_gpio_controller_node, + &myboard_leds_node, + &myboard_status_led_swnode, + &myboard_keys_node, + &myboard_wps_button_swnode, + NULL + }; + + static int __init myboard_init(void) + { + int error; + + error = software_node_register_node_group(myboard_swnodes); + if (error) { + pr_err("Failed to register software nodes: %d\n", error); + return error; + } + + // ... platform device registration follows + } + +.. note:: + When splitting registration of nodes by devices that they represent, it is + essential that the software node representing the GPIO controller itself + is registered first, before any of the nodes that reference it. + +Step 4: Register Platform Devices with Software Nodes +***************************************************** + +Finally, register the platform devices and associate them with their respective +software nodes using the ``fwnode`` field in struct platform_device_info. + +.. code-block:: c + + static struct platform_device *leds_pdev; + static struct platform_device *keys_pdev; + + static int __init myboard_init(void) + { + struct platform_device_info pdev_info; + int error; + + error = software_node_register_node_group(myboard_swnodes); + if (error) + return error; + + memset(&pdev_info, 0, sizeof(pdev_info)); + pdev_info.name = "leds-gpio"; + pdev_info.id = PLATFORM_DEVID_NONE; + pdev_info.fwnode = software_node_fwnode(&myboard_leds_node); + leds_pdev = platform_device_register_full(&pdev_info); + if (IS_ERR(leds_pdev)) { + error = PTR_ERR(leds_pdev); + goto err_unregister_nodes; + } + + memset(&pdev_info, 0, sizeof(pdev_info)); + pdev_info.name = "gpio-keys"; + pdev_info.id = PLATFORM_DEVID_NONE; + pdev_info.fwnode = software_node_fwnode(&myboard_keys_node); + keys_pdev = platform_device_register_full(&pdev_info); + if (IS_ERR(keys_pdev)) { + error = PTR_ERR(keys_pdev); + platform_device_unregister(leds_pdev); + goto err_unregister_nodes; + } + + return 0; + + err_unregister_nodes: + software_node_unregister_node_group(myboard_swnodes); + return error; + } + + static void __exit myboard_exit(void) + { + platform_device_unregister(keys_pdev); + platform_device_unregister(leds_pdev); + software_node_unregister_node_group(myboard_swnodes); + } + +With these changes, the generic ``leds-gpio`` and ``gpio-keys`` drivers will +be able to probe successfully and get their configuration from the properties +defined in the software nodes, removing the need for board-specific platform +data. diff --git a/Documentation/driver-api/media/camera-sensor.rst b/Documentation/driver-api/media/camera-sensor.rst index c290833165e6..94bd1dae82d5 100644 --- a/Documentation/driver-api/media/camera-sensor.rst +++ b/Documentation/driver-api/media/camera-sensor.rst @@ -29,21 +29,31 @@ used in the system. Using another frequency may cause harmful effects elsewhere. Therefore only the pre-determined frequencies are configurable by the user. +The external clock frequency shall be retrieved by obtaining the external clock +using the ``devm_v4l2_sensor_clk_get()`` helper function, and then getting its +frequency with ``clk_get_rate()``. Usage of the helper function guarantees +correct behaviour regardless of whether the sensor is integrated in a DT-based +or ACPI-based system. + ACPI ~~~~ -Read the ``clock-frequency`` _DSD property to denote the frequency. The driver -can rely on this frequency being used. +ACPI-based systems typically don't register the sensor external clock with the +kernel, but specify the external clock frequency in the ``clock-frequency`` +_DSD property. The ``devm_v4l2_sensor_clk_get()`` helper creates and returns a +fixed clock set at that rate. Devicetree ~~~~~~~~~~ -The preferred way to achieve this is using ``assigned-clocks``, -``assigned-clock-parents`` and ``assigned-clock-rates`` properties. See the -`clock device tree bindings +Devicetree-based systems declare the sensor external clock in the device tree +and reference it from the sensor node. The preferred way to select the external +clock frequency is to use the ``assigned-clocks``, ``assigned-clock-parents`` +and ``assigned-clock-rates`` properties in the sensor node to set the clock +rate. See the `clock device tree bindings <https://github.com/devicetree-org/dt-schema/blob/main/dtschema/schemas/clock/clock.yaml>`_ -for more information. The driver then gets the frequency using -``clk_get_rate()``. +for more information. The ``devm_v4l2_sensor_clk_get()`` helper retrieves and +returns that clock. This approach has the drawback that there's no guarantee that the frequency hasn't been modified directly or indirectly by another driver, or supported by diff --git a/Documentation/driver-api/media/maintainer-entry-profile.rst b/Documentation/driver-api/media/maintainer-entry-profile.rst index ad96a89ee916..2127e5b15e8f 100644 --- a/Documentation/driver-api/media/maintainer-entry-profile.rst +++ b/Documentation/driver-api/media/maintainer-entry-profile.rst @@ -75,7 +75,7 @@ The media maintainers that work on specific areas of the subsystem are: Sean Young <sean@mess.org> - HDMI CEC: - Hans Verkuil <hverkuil@xs4all.nl> + Hans Verkuil <hverkuil@kernel.org> - Media controller drivers: Laurent Pinchart <laurent.pinchart@ideasonboard.com> @@ -84,7 +84,7 @@ The media maintainers that work on specific areas of the subsystem are: Sakari Ailus <sakari.ailus@linux.intel.com> - V4L2 drivers and core V4L2 frameworks: - Hans Verkuil <hverkuil@xs4all.nl> + Hans Verkuil <hverkuil@kernel.org> The subsystem maintainer is: Mauro Carvalho Chehab <mchehab@kernel.org> diff --git a/Documentation/driver-api/media/v4l2-fh.rst b/Documentation/driver-api/media/v4l2-fh.rst index 3eeaa8da0c9e..a934caa483a4 100644 --- a/Documentation/driver-api/media/v4l2-fh.rst +++ b/Documentation/driver-api/media/v4l2-fh.rst @@ -1,33 +1,27 @@ .. SPDX-License-Identifier: GPL-2.0 -V4L2 File handlers ------------------- +V4L2 File handles +----------------- -struct v4l2_fh provides a way to easily keep file handle specific -data that is used by the V4L2 framework. +struct v4l2_fh provides a way to easily keep file handle specific data that is +used by the V4L2 framework. Its usage is mandatory in all drivers. -.. attention:: - New drivers must use struct v4l2_fh - since it is also used to implement priority handling - (:ref:`VIDIOC_G_PRIORITY`). +struct v4l2_fh is allocated in the driver's ``open()`` file operation handler. +It is typically embedded in a larger driver-specific structure. The +:c:type:`v4l2_fh` must be initialized with a call to :c:func:`v4l2_fh_init`, +and added to the video device with :c:func:`v4l2_fh_add`. This associates the +:c:type:`v4l2_fh` with the :c:type:`file` by setting ``file->private_data`` to +point to the :c:type:`v4l2_fh`. -The users of :c:type:`v4l2_fh` (in the V4L2 framework, not the driver) know -whether a driver uses :c:type:`v4l2_fh` as its ``file->private_data`` pointer -by testing the ``V4L2_FL_USES_V4L2_FH`` bit in :c:type:`video_device`->flags. -This bit is set whenever :c:func:`v4l2_fh_init` is called. +Similarly, the struct v4l2_fh is freed in the driver's ``release()`` file +operation handler. It must be removed from the video device with +:c:func:`v4l2_fh_del` and cleaned up with :c:func:`v4l2_fh_exit` before being +freed. -struct v4l2_fh is allocated as a part of the driver's own file handle -structure and ``file->private_data`` is set to it in the driver's ``open()`` -function by the driver. - -In many cases the struct v4l2_fh will be embedded in a larger -structure. In that case you should call: - -#) :c:func:`v4l2_fh_init` and :c:func:`v4l2_fh_add` in ``open()`` -#) :c:func:`v4l2_fh_del` and :c:func:`v4l2_fh_exit` in ``release()`` - -Drivers can extract their own file handle structure by using the container_of -macro. +Drivers must not access ``file->private_data`` directly. They can retrieve the +:c:type:`v4l2_fh` associated with a :c:type:`file` by calling +:c:func:`file_to_v4l2_fh`. Drivers can extract their own file handle structure +by using the container_of macro. Example: @@ -56,18 +50,17 @@ Example: ... - file->private_data = &my_fh->fh; - v4l2_fh_add(&my_fh->fh); + v4l2_fh_add(&my_fh->fh, file); return 0; } int my_release(struct file *file) { - struct v4l2_fh *fh = file->private_data; + struct v4l2_fh *fh = file_to_v4l2_fh(file); struct my_fh *my_fh = container_of(fh, struct my_fh, fh); ... - v4l2_fh_del(&my_fh->fh); + v4l2_fh_del(&my_fh->fh, file); v4l2_fh_exit(&my_fh->fh); kfree(my_fh); return 0; @@ -78,19 +71,17 @@ Below is a short description of the :c:type:`v4l2_fh` functions used: :c:func:`v4l2_fh_init <v4l2_fh_init>` (:c:type:`fh <v4l2_fh>`, :c:type:`vdev <video_device>`) - - Initialise the file handle. This **MUST** be performed in the driver's :c:type:`v4l2_file_operations`->open() handler. - :c:func:`v4l2_fh_add <v4l2_fh_add>` -(:c:type:`fh <v4l2_fh>`) +(:c:type:`fh <v4l2_fh>`, struct file \*filp) - Add a :c:type:`v4l2_fh` to :c:type:`video_device` file handle list. Must be called once the file handle is completely initialized. :c:func:`v4l2_fh_del <v4l2_fh_del>` -(:c:type:`fh <v4l2_fh>`) +(:c:type:`fh <v4l2_fh>`, struct file \*filp) - Unassociate the file handle from :c:type:`video_device`. The file handle exit function may now be called. @@ -101,6 +92,10 @@ Below is a short description of the :c:type:`v4l2_fh` functions used: - Uninitialise the file handle. After uninitialisation the :c:type:`v4l2_fh` memory can be freed. +:c:func:`file_to_v4l2_fh <file_to_v4l2_fh>` +(struct file \*filp) + +- Retrieve the :c:type:`v4l2_fh` instance associated with a :c:type:`file`. If struct v4l2_fh is not embedded, then you can use these helper functions: diff --git a/Documentation/driver-api/pin-control.rst b/Documentation/driver-api/pin-control.rst index 27ea1236307e..8208924e513e 100644 --- a/Documentation/driver-api/pin-control.rst +++ b/Documentation/driver-api/pin-control.rst @@ -863,7 +863,7 @@ has to be handled by the ``<linux/gpio/consumer.h>`` interface. Instead view thi a certain pin config setting. Look in e.g. ``<linux/pinctrl/pinconf-generic.h>`` and you find this in the documentation: - PIN_CONFIG_OUTPUT: + PIN_CONFIG_LEVEL: this will configure the pin in output, use argument 1 to indicate high level, argument 0 to indicate low level. @@ -897,7 +897,7 @@ And your machine configuration may look like this: }; static unsigned long uart_sleep_mode[] = { - PIN_CONF_PACKED(PIN_CONFIG_OUTPUT, 0), + PIN_CONF_PACKED(PIN_CONFIG_LEVEL, 0), }; static struct pinctrl_map pinmap[] __initdata = { diff --git a/Documentation/filesystems/bcachefs/CodingStyle.rst b/Documentation/filesystems/bcachefs/CodingStyle.rst deleted file mode 100644 index b29562a6bf55..000000000000 --- a/Documentation/filesystems/bcachefs/CodingStyle.rst +++ /dev/null @@ -1,186 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -bcachefs coding style -===================== - -Good development is like gardening, and codebases are our gardens. Tend to them -every day; look for little things that are out of place or in need of tidying. -A little weeding here and there goes a long way; don't wait until things have -spiraled out of control. - -Things don't always have to be perfect - nitpicking often does more harm than -good. But appreciate beauty when you see it - and let people know. - -The code that you are afraid to touch is the code most in need of refactoring. - -A little organizing here and there goes a long way. - -Put real thought into how you organize things. - -Good code is readable code, where the structure is simple and leaves nowhere -for bugs to hide. - -Assertions are one of our most important tools for writing reliable code. If in -the course of writing a patchset you encounter a condition that shouldn't -happen (and will have unpredictable or undefined behaviour if it does), or -you're not sure if it can happen and not sure how to handle it yet - make it a -BUG_ON(). Don't leave undefined or unspecified behavior lurking in the codebase. - -By the time you finish the patchset, you should understand better which -assertions need to be handled and turned into checks with error paths, and -which should be logically impossible. Leave the BUG_ON()s in for the ones which -are logically impossible. (Or, make them debug mode assertions if they're -expensive - but don't turn everything into a debug mode assertion, so that -we're not stuck debugging undefined behaviour should it turn out that you were -wrong). - -Assertions are documentation that can't go out of date. Good assertions are -wonderful. - -Good assertions drastically and dramatically reduce the amount of testing -required to shake out bugs. - -Good assertions are based on state, not logic. To write good assertions, you -have to think about what the invariants on your state are. - -Good invariants and assertions will hold everywhere in your codebase. This -means that you can run them in only a few places in the checked in version, but -should you need to debug something that caused the assertion to fail, you can -quickly shotgun them everywhere to find the codepath that broke the invariant. - -A good assertion checks something that the compiler could check for us, and -elide - if we were working in a language with embedded correctness proofs that -the compiler could check. This is something that exists today, but it'll likely -still be a few decades before it comes to systems programming languages. But we -can still incorporate that kind of thinking into our code and document the -invariants with runtime checks - much like the way people working in -dynamically typed languages may add type annotations, gradually making their -code statically typed. - -Looking for ways to make your assertions simpler - and higher level - will -often nudge you towards making the entire system simpler and more robust. - -Good code is code where you can poke around and see what it's doing - -introspection. We can't debug anything if we can't see what's going on. - -Whenever we're debugging, and the solution isn't immediately obvious, if the -issue is that we don't know where the issue is because we can't see what's -going on - fix that first. - -We have the tools to make anything visible at runtime, efficiently - RCU and -percpu data structures among them. Don't let things stay hidden. - -The most important tool for introspection is the humble pretty printer - in -bcachefs, this means `*_to_text()` functions, which output to printbufs. - -Pretty printers are wonderful, because they compose and you can use them -everywhere. Having functions to print whatever object you're working with will -make your error messages much easier to write (therefore they will actually -exist) and much more informative. And they can be used from sysfs/debugfs, as -well as tracepoints. - -Runtime info and debugging tools should come with clear descriptions and -labels, and good structure - we don't want files with a list of bare integers, -like in procfs. Part of the job of the debugging tools is to educate users and -new developers as to how the system works. - -Error messages should, whenever possible, tell you everything you need to debug -the issue. It's worth putting effort into them. - -Tracepoints shouldn't be the first thing you reach for. They're an important -tool, but always look for more immediate ways to make things visible. When we -have to rely on tracing, we have to know which tracepoints we're looking for, -and then we have to run the troublesome workload, and then we have to sift -through logs. This is a lot of steps to go through when a user is hitting -something, and if it's intermittent it may not even be possible. - -The humble counter is an incredibly useful tool. They're cheap and simple to -use, and many complicated internal operations with lots of things that can -behave weirdly (anything involving memory reclaim, for example) become -shockingly easy to debug once you have counters on every distinct codepath. - -Persistent counters are even better. - -When debugging, try to get the most out of every bug you come across; don't -rush to fix the initial issue. Look for things that will make related bugs -easier the next time around - introspection, new assertions, better error -messages, new debug tools, and do those first. Look for ways to make the system -better behaved; often one bug will uncover several other bugs through -downstream effects. - -Fix all that first, and then the original bug last - even if that means keeping -a user waiting. They'll thank you in the long run, and when they understand -what you're doing you'll be amazed at how patient they're happy to be. Users -like to help - otherwise they wouldn't be reporting the bug in the first place. - -Talk to your users. Don't isolate yourself. - -Users notice all sorts of interesting things, and by just talking to them and -interacting with them you can benefit from their experience. - -Spend time doing support and helpdesk stuff. Don't just write code - code isn't -finished until it's being used trouble free. - -This will also motivate you to make your debugging tools as good as possible, -and perhaps even your documentation, too. Like anything else in life, the more -time you spend at it the better you'll get, and you the developer are the -person most able to improve the tools to make debugging quick and easy. - -Be wary of how you take on and commit to big projects. Don't let development -become product-manager focused. Often time an idea is a good one but needs to -wait for its proper time - but you won't know if it's the proper time for an -idea until you start writing code. - -Expect to throw a lot of things away, or leave them half finished for later. -Nobody writes all perfect code that all gets shipped, and you'll be much more -productive in the long run if you notice this early and shift to something -else. The experience gained and lessons learned will be valuable for all the -other work you do. - -But don't be afraid to tackle projects that require significant rework of -existing code. Sometimes these can be the best projects, because they can lead -us to make existing code more general, more flexible, more multipurpose and -perhaps more robust. Just don't hesitate to abandon the idea if it looks like -it's going to make a mess of things. - -Complicated features can often be done as a series of refactorings, with the -final change that actually implements the feature as a quite small patch at the -end. It's wonderful when this happens, especially when those refactorings are -things that improve the codebase in their own right. When that happens there's -much less risk of wasted effort if the feature you were going for doesn't work -out. - -Always strive to work incrementally. Always strive to turn the big projects -into little bite sized projects that can prove their own merits. - -Instead of always tackling those big projects, look for little things that -will be useful, and make the big projects easier. - -The question of what's likely to be useful is where junior developers most -often go astray - doing something because it seems like it'll be useful often -leads to overengineering. Knowing what's useful comes from many years of -experience, or talking with people who have that experience - or from simply -reading lots of code and looking for common patterns and issues. Don't be -afraid to throw things away and do something simpler. - -Talk about your ideas with your fellow developers; often times the best things -come from relaxed conversations where people aren't afraid to say "what if?". - -Don't neglect your tools. - -The most important tools (besides the compiler and our text editor) are the -tools we use for testing. The shortest possible edit/test/debug cycle is -essential for working productively. We learn, gain experience, and discover the -errors in our thinking by running our code and seeing what happens. If your -time is being wasted because your tools are bad or too slow - don't accept it, -fix it. - -Put effort into your documentation, commit messages, and code comments - but -don't go overboard. A good commit message is wonderful - but if the information -was important enough to go in a commit message, ask yourself if it would be -even better as a code comment. - -A good code comment is wonderful, but even better is the comment that didn't -need to exist because the code was so straightforward as to be obvious; -organized into small clean and tidy modules, with clear and descriptive names -for functions and variables, where every line of code has a clear purpose. diff --git a/Documentation/filesystems/bcachefs/SubmittingPatches.rst b/Documentation/filesystems/bcachefs/SubmittingPatches.rst deleted file mode 100644 index 18c79d548391..000000000000 --- a/Documentation/filesystems/bcachefs/SubmittingPatches.rst +++ /dev/null @@ -1,105 +0,0 @@ -Submitting patches to bcachefs -============================== - -Here are suggestions for submitting patches to bcachefs subsystem. - -Submission checklist --------------------- - -Patches must be tested before being submitted, either with the xfstests suite -[0]_, or the full bcachefs test suite in ktest [1]_, depending on what's being -touched. Note that ktest wraps xfstests and will be an easier method to running -it for most users; it includes single-command wrappers for all the mainstream -in-kernel local filesystems. - -Patches will undergo more testing after being merged (including -lockdep/kasan/preempt/etc. variants), these are not generally required to be -run by the submitter - but do put some thought into what you're changing and -which tests might be relevant, e.g. are you dealing with tricky memory layout -work? kasan, are you doing locking work? then lockdep; and ktest includes -single-command variants for the debug build types you'll most likely need. - -The exception to this rule is incomplete WIP/RFC patches: if you're working on -something nontrivial, it's encouraged to send out a WIP patch to let people -know what you're doing and make sure you're on the right track. Just make sure -it includes a brief note as to what's done and what's incomplete, to avoid -confusion. - -Rigorous checkpatch.pl adherence is not required (many of its warnings are -considered out of date), but try not to deviate too much without reason. - -Focus on writing code that reads well and is organized well; code should be -aesthetically pleasing. - -CI --- - -Instead of running your tests locally, when running the full test suite it's -preferable to let a server farm do it in parallel, and then have the results -in a nice test dashboard (which can tell you which failures are new, and -presents results in a git log view, avoiding the need for most bisecting). - -That exists [2]_, and community members may request an account. If you work for -a big tech company, you'll need to help out with server costs to get access - -but the CI is not restricted to running bcachefs tests: it runs any ktest test -(which generally makes it easy to wrap other tests that can run in qemu). - -Other things to think about ---------------------------- - -- How will we debug this code? Is there sufficient introspection to diagnose - when something starts acting wonky on a user machine? - - We don't necessarily need every single field of every data structure visible - with introspection, but having the important fields of all the core data - types wired up makes debugging drastically easier - a bit of thoughtful - foresight greatly reduces the need to have people build custom kernels with - debug patches. - - More broadly, think about all the debug tooling that might be needed. - -- Does it make the codebase more or less of a mess? Can we also try to do some - organizing, too? - -- Do new tests need to be written? New assertions? How do we know and verify - that the code is correct, and what happens if something goes wrong? - - We don't yet have automated code coverage analysis or easy fault injection - - but for now, pretend we did and ask what they might tell us. - - Assertions are hugely important, given that we don't yet have a systems - language that can do ergonomic embedded correctness proofs. Hitting an assert - in testing is much better than wandering off into undefined behaviour la-la - land - use them. Use them judiciously, and not as a replacement for proper - error handling, but use them. - -- Does it need to be performance tested? Should we add new performance counters? - - bcachefs has a set of persistent runtime counters which can be viewed with - the 'bcachefs fs top' command; this should give users a basic idea of what - their filesystem is currently doing. If you're doing a new feature or looking - at old code, think if anything should be added. - -- If it's a new on disk format feature - have upgrades and downgrades been - tested? (Automated tests exists but aren't in the CI, due to the hassle of - disk image management; coordinate to have them run.) - -Mailing list, IRC ------------------ - -Patches should hit the list [3]_, but much discussion and code review happens -on IRC as well [4]_; many people appreciate the more conversational approach -and quicker feedback. - -Additionally, we have a lively user community doing excellent QA work, which -exists primarily on IRC. Please make use of that resource; user feedback is -important for any nontrivial feature, and documenting it in commit messages -would be a good idea. - -.. rubric:: References - -.. [0] git://git.kernel.org/pub/scm/fs/xfs/xfstests-dev.git -.. [1] https://evilpiepirate.org/git/ktest.git/ -.. [2] https://evilpiepirate.org/~testdashboard/ci/ -.. [3] linux-bcachefs@vger.kernel.org -.. [4] irc.oftc.net#bcache, #bcachefs-dev diff --git a/Documentation/filesystems/bcachefs/casefolding.rst b/Documentation/filesystems/bcachefs/casefolding.rst deleted file mode 100644 index 871a38f557e8..000000000000 --- a/Documentation/filesystems/bcachefs/casefolding.rst +++ /dev/null @@ -1,108 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -Casefolding -=========== - -bcachefs has support for case-insensitive file and directory -lookups using the regular `chattr +F` (`S_CASEFOLD`, `FS_CASEFOLD_FL`) -casefolding attributes. - -The main usecase for casefolding is compatibility with software written -against other filesystems that rely on casefolded lookups -(eg. NTFS and Wine/Proton). -Taking advantage of file-system level casefolding can lead to great -loading time gains in many applications and games. - -Casefolding support requires a kernel with the `CONFIG_UNICODE` enabled. -Once a directory has been flagged for casefolding, a feature bit -is enabled on the superblock which marks the filesystem as using -casefolding. -When the feature bit for casefolding is enabled, it is no longer possible -to mount that filesystem on kernels without `CONFIG_UNICODE` enabled. - -On the lookup/query side: casefolding is implemented by allocating a new -string of `BCH_NAME_MAX` length using the `utf8_casefold` function to -casefold the query string. - -On the dirent side: casefolding is implemented by ensuring the `bkey`'s -hash is made from the casefolded string and storing the cached casefolded -name with the regular name in the dirent. - -The structure looks like this: - -* Regular: [dirent data][regular name][nul][nul]... -* Casefolded: [dirent data][reg len][cf len][regular name][casefolded name][nul][nul]... - -(Do note, the number of NULs here is merely for illustration; their count can -vary per-key, and they may not even be present if the key is aligned to -`sizeof(u64)`.) - -This is efficient as it means that for all file lookups that require casefolding, -it has identical performance to a regular lookup: -a hash comparison and a `memcmp` of the name. - -Rationale ---------- - -Several designs were considered for this system: -One was to introduce a dirent_v2, however that would be painful especially as -the hash system only has support for a single key type. This would also need -`BCH_NAME_MAX` to change between versions, and a new feature bit. - -Another option was to store without the two lengths, and just take the length of -the regular name and casefolded name contiguously / 2 as the length. This would -assume that the regular length == casefolded length, but that could potentially -not be true, if the uppercase unicode glyph had a different UTF-8 encoding than -the lowercase unicode glyph. -It would be possible to disregard the casefold cache for those cases, but it was -decided to simply encode the two string lengths in the key to avoid random -performance issues if this edgecase was ever hit. - -The option settled on was to use a free-bit in d_type to mark a dirent as having -a casefold cache, and then treat the first 4 bytes the name block as lengths. -You can see this in the `d_cf_name_block` member of union in `bch_dirent`. - -The feature bit was used to allow casefolding support to be enabled for the majority -of users, but some allow users who have no need for the feature to still use bcachefs as -`CONFIG_UNICODE` can increase the kernel side a significant amount due to the tables used, -which may be decider between using bcachefs for eg. embedded platforms. - -Other filesystems like ext4 and f2fs have a super-block level option for casefolding -encoding, but bcachefs currently does not provide this. ext4 and f2fs do not expose -any encodings than a single UTF-8 version. When future encodings are desirable, -they will be added trivially using the opts mechanism. - -dentry/dcache considerations ----------------------------- - -Currently, in casefolded directories, bcachefs (like other filesystems) will not cache -negative dentry's. - -This is because currently doing so presents a problem in the following scenario: - - - Lookup file "blAH" in a casefolded directory - - Creation of file "BLAH" in a casefolded directory - - Lookup file "blAH" in a casefolded directory - -This would fail if negative dentry's were cached. - -This is slightly suboptimal, but could be fixed in future with some vfs work. - - -References ----------- - -(from Peter Anvin, on the list) - -It is worth noting that Microsoft has basically declared their -"recommended" case folding (upcase) table to be permanently frozen (for -new filesystem instances in the case where they use an on-disk -translation table created at format time.) As far as I know they have -never supported anything other than 1:1 conversion of BMP code points, -nor normalization. - -The exFAT specification enumerates the full recommended upcase table, -although in a somewhat annoying format (basically a hex dump of -compressed data): - -https://learn.microsoft.com/en-us/windows/win32/fileio/exfat-specification diff --git a/Documentation/filesystems/bcachefs/errorcodes.rst b/Documentation/filesystems/bcachefs/errorcodes.rst deleted file mode 100644 index 2cccaa0ba7cd..000000000000 --- a/Documentation/filesystems/bcachefs/errorcodes.rst +++ /dev/null @@ -1,30 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -bcachefs private error codes ----------------------------- - -In bcachefs, as a hard rule we do not throw or directly use standard error -codes (-EINVAL, -EBUSY, etc.). Instead, we define private error codes as needed -in fs/bcachefs/errcode.h. - -This gives us much better error messages and makes debugging much easier. Any -direct uses of standard error codes you see in the source code are simply old -code that has yet to be converted - feel free to clean it up! - -Private error codes may subtype another error code, this allows for grouping of -related errors that should be handled similarly (e.g. transaction restart -errors), as well as specifying which standard error code should be returned at -the bcachefs module boundary. - -At the module boundary, we use bch2_err_class() to convert to a standard error -code; this also emits a trace event so that the original error code be -recovered even if it wasn't logged. - -Do not reuse error codes! Generally speaking, a private error code should only -be thrown in one place. That means that when we see it in a log message we can -see, unambiguously, exactly which file and line number it was returned from. - -Try to give error codes names that are as reasonably descriptive of the error -as possible. Frequently, the error will be logged at a place far removed from -where the error was generated; good names for error codes mean much more -descriptive and useful error messages. diff --git a/Documentation/filesystems/bcachefs/future/idle_work.rst b/Documentation/filesystems/bcachefs/future/idle_work.rst deleted file mode 100644 index 59a332509dcd..000000000000 --- a/Documentation/filesystems/bcachefs/future/idle_work.rst +++ /dev/null @@ -1,78 +0,0 @@ -Idle/background work classes design doc: - -Right now, our behaviour at idle isn't ideal, it was designed for servers that -would be under sustained load, to keep pending work at a "medium" level, to -let work build up so we can process it in more efficient batches, while also -giving headroom for bursts in load. - -But for desktops or mobile - scenarios where work is less sustained and power -usage is more important - we want to operate differently, with a "rush to -idle" so the system can go to sleep. We don't want to be dribbling out -background work while the system should be idle. - -The complicating factor is that there are a number of background tasks, which -form a heirarchy (or a digraph, depending on how you divide it up) - one -background task may generate work for another. - -Thus proper idle detection needs to model this heirarchy. - -- Foreground writes -- Page cache writeback -- Copygc, rebalance -- Journal reclaim - -When we implement idle detection and rush to idle, we need to be careful not -to disturb too much the existing behaviour that works reasonably well when the -system is under sustained load (or perhaps improve it in the case of -rebalance, which currently does not actively attempt to let work batch up). - -SUSTAINED LOAD REGIME ---------------------- - -When the system is under continuous load, we want these jobs to run -continuously - this is perhaps best modelled with a P/D controller, where -they'll be trying to keep a target value (i.e. fragmented disk space, -available journal space) roughly in the middle of some range. - -The goal under sustained load is to balance our ability to handle load spikes -without running out of x resource (free disk space, free space in the -journal), while also letting some work accumululate to be batched (or become -unnecessary). - -For example, we don't want to run copygc too aggressively, because then it -will be evacuating buckets that would have become empty (been overwritten or -deleted) anyways, and we don't want to wait until we're almost out of free -space because then the system will behave unpredicably - suddenly we're doing -a lot more work to service each write and the system becomes much slower. - -IDLE REGIME ------------ - -When the system becomes idle, we should start flushing our pending work -quicker so the system can go to sleep. - -Note that the definition of "idle" depends on where in the heirarchy a task -is - a task should start flushing work more quickly when the task above it has -stopped generating new work. - -e.g. rebalance should start flushing more quickly when page cache writeback is -idle, and journal reclaim should only start flushing more quickly when both -copygc and rebalance are idle. - -It's important to let work accumulate when more work is still incoming and we -still have room, because flushing is always more efficient if we let it batch -up. New writes may overwrite data before rebalance moves it, and tasks may be -generating more updates for the btree nodes that journal reclaim needs to flush. - -On idle, how much work we do at each interval should be proportional to the -length of time we have been idle for. If we're idle only for a short duration, -we shouldn't flush everything right away; the system might wake up and start -generating new work soon, and flushing immediately might end up doing a lot of -work that would have been unnecessary if we'd allowed things to batch more. - -To summarize, we will need: - - - A list of classes for background tasks that generate work, which will - include one "foreground" class. - - Tracking for each class - "Am I doing work, or have I gone to sleep?" - - And each class should check the class above it when deciding how much work to issue. diff --git a/Documentation/filesystems/bcachefs/index.rst b/Documentation/filesystems/bcachefs/index.rst deleted file mode 100644 index e5c4c2120b93..000000000000 --- a/Documentation/filesystems/bcachefs/index.rst +++ /dev/null @@ -1,38 +0,0 @@ -.. SPDX-License-Identifier: GPL-2.0 - -====================== -bcachefs Documentation -====================== - -Subsystem-specific development process notes --------------------------------------------- - -Development notes specific to bcachefs. These are intended to supplement -:doc:`general kernel development handbook </process/index>`. - -.. toctree:: - :maxdepth: 1 - :numbered: - - CodingStyle - SubmittingPatches - -Filesystem implementation -------------------------- - -Documentation for filesystem features and their implementation details. -At this moment, only a few of these are described here. - -.. toctree:: - :maxdepth: 1 - :numbered: - - casefolding - errorcodes - -Future design -------------- -.. toctree:: - :maxdepth: 1 - - future/idle_work diff --git a/Documentation/filesystems/index.rst b/Documentation/filesystems/index.rst index 11a599387266..622187a96bdc 100644 --- a/Documentation/filesystems/index.rst +++ b/Documentation/filesystems/index.rst @@ -72,7 +72,6 @@ Documentation for filesystem implementations. afs autofs autofs-mount-control - bcachefs/index befs bfs btrfs diff --git a/Documentation/filesystems/locking.rst b/Documentation/filesystems/locking.rst index aa287ccdac2f..77704fde9845 100644 --- a/Documentation/filesystems/locking.rst +++ b/Documentation/filesystems/locking.rst @@ -443,7 +443,7 @@ prototypes:: int (*direct_access) (struct block_device *, sector_t, void **, unsigned long *); void (*unlock_native_capacity) (struct gendisk *); - int (*getgeo)(struct block_device *, struct hd_geometry *); + int (*getgeo)(struct gendisk *, struct hd_geometry *); void (*swap_slot_free_notify) (struct block_device *, unsigned long); locking rules: diff --git a/Documentation/filesystems/porting.rst b/Documentation/filesystems/porting.rst index 85f590254f07..78c3d07c0c08 100644 --- a/Documentation/filesystems/porting.rst +++ b/Documentation/filesystems/porting.rst @@ -340,8 +340,8 @@ of those. Caller makes sure async writeback cannot be running for the inode whil ->drop_inode() returns int now; it's called on final iput() with inode->i_lock held and it returns true if filesystems wants the inode to be -dropped. As before, generic_drop_inode() is still the default and it's been -updated appropriately. generic_delete_inode() is also alive and it consists +dropped. As before, inode_generic_drop() is still the default and it's been +updated appropriately. inode_just_drop() is also alive and it consists simply of return 1. Note that all actual eviction work is done by caller after ->drop_inode() returns. @@ -1285,3 +1285,15 @@ rather than a VMA, as the VMA at this stage is not yet valid. The vm_area_desc provides the minimum required information for a filesystem to initialise state upon memory mapping of a file-backed region, and output parameters for the file system to set this state. + +--- + +**mandatory** + +Several functions are renamed: + +- kern_path_locked -> start_removing_path +- kern_path_create -> start_creating_path +- user_path_create -> start_creating_user_path +- user_path_locked_at -> start_removing_user_path_at +- done_path_create -> end_creating_path diff --git a/Documentation/filesystems/proc.rst b/Documentation/filesystems/proc.rst index 2971551b7235..42f2fb9e3c8f 100644 --- a/Documentation/filesystems/proc.rst +++ b/Documentation/filesystems/proc.rst @@ -291,8 +291,9 @@ It's slow but very precise. HugetlbPages size of hugetlb memory portions CoreDumping process's memory is currently being dumped (killing the process may lead to a corrupted core) - THP_enabled process is allowed to use THP (returns 0 when - PR_SET_THP_DISABLE is set on the process + THP_enabled process is allowed to use THP (returns 0 when + PR_SET_THP_DISABLE is set on the process to disable + THP completely, not just partially) Threads number of threads SigQ number of signals queued/max. number for queue SigPnd bitmap of pending signals for the thread @@ -1008,6 +1009,19 @@ number, module (if originates from a loadable module) and the function calling the allocation. The number of bytes allocated and number of calls at each location are reported. The first line indicates the version of the file, the second line is the header listing fields in the file. +If file version is 2.0 or higher then each line may contain additional +<key>:<value> pairs representing extra information about the call site. +For example if the counters are not accurate, the line will be appended with +"accurate:no" pair. + +Supported markers in v2: +accurate:no + + Absolute values of the counters in this line are not accurate + because of the failure to allocate memory to track some of the + allocations made at this location. Deltas in these counters are + accurate, therefore counters can be used to track allocation size + and count changes. Example output. @@ -2362,6 +2376,7 @@ The following mount options are supported: hidepid= Set /proc/<pid>/ access mode. gid= Set the group authorized to learn processes information. subset= Show only the specified subset of procfs. + pidns= Specify a the namespace used by this procfs. ========= ======================================================== hidepid=off or hidepid=0 means classic mode - everybody may access all @@ -2394,6 +2409,13 @@ information about processes information, just add identd to this group. subset=pid hides all top level files and directories in the procfs that are not related to tasks. +pidns= specifies a pid namespace (either as a string path to something like +`/proc/$pid/ns/pid`, or a file descriptor when using `FSCONFIG_SET_FD`) that +will be used by the procfs instance when translating pids. By default, procfs +will use the calling process's active pid namespace. Note that the pid +namespace of an existing procfs instance cannot be modified (attempting to do +so will give an `-EBUSY` error). + Chapter 5: Filesystem behavior ============================== diff --git a/Documentation/filesystems/resctrl.rst b/Documentation/filesystems/resctrl.rst index c7949dd44f2f..006d23af66e1 100644 --- a/Documentation/filesystems/resctrl.rst +++ b/Documentation/filesystems/resctrl.rst @@ -26,6 +26,7 @@ MBM (Memory Bandwidth Monitoring) "cqm_mbm_total", "cqm_mbm_local" MBA (Memory Bandwidth Allocation) "mba" SMBA (Slow Memory Bandwidth Allocation) "" BMEC (Bandwidth Monitoring Event Configuration) "" +ABMC (Assignable Bandwidth Monitoring Counters) "" =============================================== ================================ Historically, new features were made visible by default in /proc/cpuinfo. This @@ -256,6 +257,144 @@ with the following files: # cat /sys/fs/resctrl/info/L3_MON/mbm_local_bytes_config 0=0x30;1=0x30;3=0x15;4=0x15 +"mbm_assign_mode": + The supported counter assignment modes. The enclosed brackets indicate which mode + is enabled. The MBM events associated with counters may reset when "mbm_assign_mode" + is changed. + :: + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + [mbm_event] + default + + "mbm_event": + + mbm_event mode allows users to assign a hardware counter to an RMID, event + pair and monitor the bandwidth usage as long as it is assigned. The hardware + continues to track the assigned counter until it is explicitly unassigned by + the user. Each event within a resctrl group can be assigned independently. + + In this mode, a monitoring event can only accumulate data while it is backed + by a hardware counter. Use "mbm_L3_assignments" found in each CTRL_MON and MON + group to specify which of the events should have a counter assigned. The number + of counters available is described in the "num_mbm_cntrs" file. Changing the + mode may cause all counters on the resource to reset. + + Moving to mbm_event counter assignment mode requires users to assign the counters + to the events. Otherwise, the MBM event counters will return 'Unassigned' when read. + + The mode is beneficial for AMD platforms that support more CTRL_MON + and MON groups than available hardware counters. By default, this + feature is enabled on AMD platforms with the ABMC (Assignable Bandwidth + Monitoring Counters) capability, ensuring counters remain assigned even + when the corresponding RMID is not actively used by any processor. + + "default": + + In default mode, resctrl assumes there is a hardware counter for each + event within every CTRL_MON and MON group. On AMD platforms, it is + recommended to use the mbm_event mode, if supported, to prevent reset of MBM + events between reads resulting from hardware re-allocating counters. This can + result in misleading values or display "Unavailable" if no counter is assigned + to the event. + + * To enable "mbm_event" counter assignment mode: + :: + + # echo "mbm_event" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + + * To enable "default" monitoring mode: + :: + + # echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + +"num_mbm_cntrs": + The maximum number of counters (total of available and assigned counters) in + each domain when the system supports mbm_event mode. + + For example, on a system with maximum of 32 memory bandwidth monitoring + counters in each of its L3 domains: + :: + + # cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs + 0=32;1=32 + +"available_mbm_cntrs": + The number of counters available for assignment in each domain when mbm_event + mode is enabled on the system. + + For example, on a system with 30 available [hardware] assignable counters + in each of its L3 domains: + :: + + # cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs + 0=30;1=30 + +"event_configs": + Directory that exists when "mbm_event" counter assignment mode is supported. + Contains a sub-directory for each MBM event that can be assigned to a counter. + + Two MBM events are supported by default: mbm_local_bytes and mbm_total_bytes. + Each MBM event's sub-directory contains a file named "event_filter" that is + used to view and modify which memory transactions the MBM event is configured + with. The file is accessible only when "mbm_event" counter assignment mode is + enabled. + + List of memory transaction types supported: + + ========================== ======================================================== + Name Description + ========================== ======================================================== + dirty_victim_writes_all Dirty Victims from the QOS domain to all types of memory + remote_reads_slow_memory Reads to slow memory in the non-local NUMA domain + local_reads_slow_memory Reads to slow memory in the local NUMA domain + remote_non_temporal_writes Non-temporal writes to non-local NUMA domain + local_non_temporal_writes Non-temporal writes to local NUMA domain + remote_reads Reads to memory in the non-local NUMA domain + local_reads Reads to memory in the local NUMA domain + ========================== ======================================================== + + For example:: + + # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter + local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, + local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all + + # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter + local_reads,local_non_temporal_writes,local_reads_slow_memory + + Modify the event configuration by writing to the "event_filter" file within + the "event_configs" directory. The read/write "event_filter" file contains the + configuration of the event that reflects which memory transactions are counted by it. + + For example:: + + # echo "local_reads, local_non_temporal_writes" > + /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter + + # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter + local_reads,local_non_temporal_writes + +"mbm_assign_on_mkdir": + Exists when "mbm_event" counter assignment mode is supported. Accessible + only when "mbm_event" counter assignment mode is enabled. + + Determines if a counter will automatically be assigned to an RMID, MBM event + pair when its associated monitor group is created via mkdir. Enabled by default + on boot, also when switched from "default" mode to "mbm_event" counter assignment + mode. Users can disable this capability by writing to the interface. + + "0": + Auto assignment is disabled. + "1": + Auto assignment is enabled. + + Example:: + + # echo 0 > /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_on_mkdir + 0 + "max_threshold_occupancy": Read/write file provides the largest value (in bytes) at which a previously used LLC_occupancy @@ -380,10 +519,77 @@ When monitoring is enabled all MON groups will also contain: for the L3 cache they occupy). These are named "mon_sub_L3_YY" where "YY" is the node number. + When the 'mbm_event' counter assignment mode is enabled, reading + an MBM event of a MON group returns 'Unassigned' if no hardware + counter is assigned to it. For CTRL_MON groups, 'Unassigned' is + returned if the MBM event does not have an assigned counter in the + CTRL_MON group nor in any of its associated MON groups. + "mon_hw_id": Available only with debug option. The identifier used by hardware for the monitor group. On x86 this is the RMID. +When monitoring is enabled all MON groups may also contain: + +"mbm_L3_assignments": + Exists when "mbm_event" counter assignment mode is supported and lists the + counter assignment states of the group. + + The assignment list is displayed in the following format: + + <Event>:<Domain ID>=<Assignment state>;<Domain ID>=<Assignment state> + + Event: A valid MBM event in the + /sys/fs/resctrl/info/L3_MON/event_configs directory. + + Domain ID: A valid domain ID. When writing, '*' applies the changes + to all the domains. + + Assignment states: + + _ : No counter assigned. + + e : Counter assigned exclusively. + + Example: + + To display the counter assignment states for the default group. + :: + + # cd /sys/fs/resctrl + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=e;1=e + mbm_local_bytes:0=e;1=e + + Assignments can be modified by writing to the interface. + + Examples: + + To unassign the counter associated with the mbm_total_bytes event on domain 0: + :: + + # echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=_;1=e + mbm_local_bytes:0=e;1=e + + To unassign the counter associated with the mbm_total_bytes event on all the domains: + :: + + # echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=_;1=_ + mbm_local_bytes:0=e;1=e + + To assign a counter associated with the mbm_total_bytes event on all domains in + exclusive mode: + :: + + # echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=e;1=e + mbm_local_bytes:0=e;1=e + When the "mba_MBps" mount option is used all CTRL_MON groups will also contain: "mba_MBps_event": @@ -1429,6 +1635,125 @@ View the llc occupancy snapshot:: # cat /sys/fs/resctrl/p1/mon_data/mon_L3_00/llc_occupancy 11234000 + +Examples on working with mbm_assign_mode +======================================== + +a. Check if MBM counter assignment mode is supported. +:: + + # mount -t resctrl resctrl /sys/fs/resctrl/ + + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + [mbm_event] + default + +The "mbm_event" mode is detected and enabled. + +b. Check how many assignable counters are supported. +:: + + # cat /sys/fs/resctrl/info/L3_MON/num_mbm_cntrs + 0=32;1=32 + +c. Check how many assignable counters are available for assignment in each domain. +:: + + # cat /sys/fs/resctrl/info/L3_MON/available_mbm_cntrs + 0=30;1=30 + +d. To list the default group's assign states. +:: + + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=e;1=e + mbm_local_bytes:0=e;1=e + +e. To unassign the counter associated with the mbm_total_bytes event on domain 0. +:: + + # echo "mbm_total_bytes:0=_" > /sys/fs/resctrl/mbm_L3_assignments + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=_;1=e + mbm_local_bytes:0=e;1=e + +f. To unassign the counter associated with the mbm_total_bytes event on all domains. +:: + + # echo "mbm_total_bytes:*=_" > /sys/fs/resctrl/mbm_L3_assignments + # cat /sys/fs/resctrl/mbm_L3_assignment + mbm_total_bytes:0=_;1=_ + mbm_local_bytes:0=e;1=e + +g. To assign a counter associated with the mbm_total_bytes event on all domains in +exclusive mode. +:: + + # echo "mbm_total_bytes:*=e" > /sys/fs/resctrl/mbm_L3_assignments + # cat /sys/fs/resctrl/mbm_L3_assignments + mbm_total_bytes:0=e;1=e + mbm_local_bytes:0=e;1=e + +h. Read the events mbm_total_bytes and mbm_local_bytes of the default group. There is +no change in reading the events with the assignment. +:: + + # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_total_bytes + 779247936 + # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_total_bytes + 562324232 + # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes + 212122123 + # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes + 121212144 + +i. Check the event configurations. +:: + + # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_total_bytes/event_filter + local_reads,remote_reads,local_non_temporal_writes,remote_non_temporal_writes, + local_reads_slow_memory,remote_reads_slow_memory,dirty_victim_writes_all + + # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter + local_reads,local_non_temporal_writes,local_reads_slow_memory + +j. Change the event configuration for mbm_local_bytes. +:: + + # echo "local_reads, local_non_temporal_writes, local_reads_slow_memory, remote_reads" > + /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter + + # cat /sys/fs/resctrl/info/L3_MON/event_configs/mbm_local_bytes/event_filter + local_reads,local_non_temporal_writes,local_reads_slow_memory,remote_reads + +k. Now read the local events again. The first read may come back with "Unavailable" +status. The subsequent read of mbm_local_bytes will display the current value. +:: + + # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes + Unavailable + # cat /sys/fs/resctrl/mon_data/mon_L3_00/mbm_local_bytes + 2252323 + # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes + Unavailable + # cat /sys/fs/resctrl/mon_data/mon_L3_01/mbm_local_bytes + 1566565 + +l. Users have the option to go back to 'default' mbm_assign_mode if required. This can be +done using the following command. Note that switching the mbm_assign_mode may reset all +the MBM counters (and thus all MBM events) of all the resctrl groups. +:: + + # echo "default" > /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + # cat /sys/fs/resctrl/info/L3_MON/mbm_assign_mode + mbm_event + [default] + +m. Unmount the resctrl filesystem. +:: + + # umount /sys/fs/resctrl/ + Intel RDT Errata ================ diff --git a/Documentation/filesystems/vfs.rst b/Documentation/filesystems/vfs.rst index 486a91633474..4f13b01e42eb 100644 --- a/Documentation/filesystems/vfs.rst +++ b/Documentation/filesystems/vfs.rst @@ -209,31 +209,8 @@ method fills in is the "s_op" field. This is a pointer to a "struct super_operations" which describes the next level of the filesystem implementation. -Usually, a filesystem uses one of the generic mount() implementations -and provides a fill_super() callback instead. The generic variants are: - -``mount_bdev`` - mount a filesystem residing on a block device - -``mount_nodev`` - mount a filesystem that is not backed by a device - -``mount_single`` - mount a filesystem which shares the instance between all mounts - -A fill_super() callback implementation has the following arguments: - -``struct super_block *sb`` - the superblock structure. The callback must initialize this - properly. - -``void *data`` - arbitrary mount options, usually comes as an ASCII string (see - "Mount Options" section) - -``int silent`` - whether or not to be silent on error - +For more information on mounting (and the new mount API), see +Documentation/filesystems/mount_api.rst. The Superblock Object ===================== @@ -327,11 +304,11 @@ or bottom half). inode->i_lock spinlock held. This method should be either NULL (normal UNIX filesystem - semantics) or "generic_delete_inode" (for filesystems that do + semantics) or "inode_just_drop" (for filesystems that do not want to cache inodes - causing "delete_inode" to always be called regardless of the value of i_nlink) - The "generic_delete_inode()" behavior is equivalent to the old + The "inode_just_drop()" behavior is equivalent to the old practice of using "force_delete" in the put_inode() case, but does not have the races that the "force_delete()" approach had. diff --git a/Documentation/gpu/amdgpu/amd-hardware-list-info.rst b/Documentation/gpu/amdgpu/amd-hardware-list-info.rst index 1786544fe7c1..e72f4ff770c4 100644 --- a/Documentation/gpu/amdgpu/amd-hardware-list-info.rst +++ b/Documentation/gpu/amdgpu/amd-hardware-list-info.rst @@ -10,7 +10,7 @@ Accelerated Processing Units (APU) Info .. csv-table:: :header-rows: 1 - :widths: 3, 2, 2, 1, 1, 1, 1 + :widths: 3, 2, 2, 1, 1, 1, 1, 1 :file: ./apu-asic-info-table.csv Discrete GPU Info @@ -18,6 +18,6 @@ Discrete GPU Info .. csv-table:: :header-rows: 1 - :widths: 3, 2, 2, 1, 1, 1 + :widths: 3, 2, 2, 1, 1, 1, 1, 1 :file: ./dgpu-asic-info-table.csv diff --git a/Documentation/gpu/amdgpu/apu-asic-info-table.csv b/Documentation/gpu/amdgpu/apu-asic-info-table.csv index 1d50b539677f..dee5f663a47f 100644 --- a/Documentation/gpu/amdgpu/apu-asic-info-table.csv +++ b/Documentation/gpu/amdgpu/apu-asic-info-table.csv @@ -1,17 +1,18 @@ -Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version, MP0 version -Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3, n/a -Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0, 10.0.0 -Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2, 11.0.3 -Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1, 10.0.1 -SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0 -Ryzen 5000 series / Ryzen 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1 -Ryzen 6000 series / Ryzen 7x35 series / Ryzen 7x36 series, YELLOW CARP / Rembrandt / Rembrandt-R, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3 -Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5 -Ryzen 9000 series (AM5), Granite Ridge, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5 -Ryzen 7x45 series (FL1), Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5 -Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8 -Ryzen 7x40 series, Phoenix, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11 -Ryzen 8x40 series, Hawk Point, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11 -Ryzen AI 300 series, Strix Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0 -Ryzen AI 350 series, Krackan Point, 3.5.0, 11.5.2, 4.0.5, 6.1.2, 14.0.4 -Ryzen AI Max 300 series, Strix Halo, 3.5.1, 11.5.1, 4.0.6, 6.1.1, 14.0.1 +Product Name, Code Reference, DCN/DCE version, GC version, VCE/UVD/VCN version, SDMA version, MP0 version, MP1 version +Radeon R* Graphics, CARRIZO/STONEY, DCE 11, 8, VCE 3 / UVD 6, 3, n/a, 8 +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN/PICASSO, DCN 1.0, 9.1.0, VCN 1.0, 4.1.0, 10.0.0, 10.0.0 +Ryzen 4000 series, RENOIR, DCN 2.1, 9.3, VCN 2.2, 4.1.2, 11.0.3, 12.0.1 +Ryzen 3000 series / AMD Ryzen Embedded V1*/R1* with Radeon Vega Gfx, RAVEN2, DCN 1.0, 9.2.2, VCN 1.0.1, 4.1.1, 10.0.1, 10.0.1 +SteamDeck, VANGOGH, DCN 3.0.1, 10.3.1, VCN 3.1.0, 5.2.1, 11.5.0, 11.5.0 +Ryzen 5000 series / Ryzen 7x30 series, GREEN SARDINE / Cezanne / Barcelo / Barcelo-R, DCN 2.1, 9.3, VCN 2.2, 4.1.1, 12.0.1, 12.0.1 +Ryzen 6000 series / Ryzen 7x35 series / Ryzen 7x36 series, YELLOW CARP / Rembrandt / Rembrandt-R, 3.1.2, 10.3.3, VCN 3.1.1, 5.2.3, 13.0.3, 13.0.3 +Ryzen 7000 series (AM5), Raphael, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5, 13.0.5 +Ryzen 9000 series (AM5), Granite Ridge, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5, 13.0.5 +Ryzen 7x45 series (FL1), Dragon Range, 3.1.5, 10.3.6, 3.1.2, 5.2.6, 13.0.5, 13.0.5 +Ryzen 7x20 series, Mendocino, 3.1.6, 10.3.7, 3.1.1, 5.2.7, 13.0.8, 13.0.8 +Ryzen 7x40 series, Phoenix, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11, 13.0.4 / 13.0.11 +Ryzen 8x40 series, Hawk Point, 3.1.4, 11.0.1 / 11.0.4, 4.0.2, 6.0.1, 13.0.4 / 13.0.11, 13.0.4 / 13.0.11 +Ryzen AI 300 series, Strix Point, 3.5.0, 11.5.0, 4.0.5, 6.1.0, 14.0.0, 14.0.0 +Ryzen AI 330 series, Krackan Point, 3.6.0, 11.5.3, 4.0.5, 6.1.3, 14.0.5, 14.0.5 +Ryzen AI 350 series, Krackan Point, 3.5.0, 11.5.2, 4.0.5, 6.1.2, 14.0.4, 14.0.4 +Ryzen AI Max 300 series, Strix Halo, 3.5.1, 11.5.1, 4.0.6, 6.1.1, 14.0.1, 14.0.1 diff --git a/Documentation/gpu/amdgpu/debugfs.rst b/Documentation/gpu/amdgpu/debugfs.rst index 5150d0a95658..151d8bfc79e2 100644 --- a/Documentation/gpu/amdgpu/debugfs.rst +++ b/Documentation/gpu/amdgpu/debugfs.rst @@ -94,7 +94,7 @@ amdgpu_error_<name> ------------------- Provides an interface to set an error code on the dma fences associated with -ring <name>. The error code specified is propogated to all fences associated +ring <name>. The error code specified is propagated to all fences associated with the ring. Use this to inject a fence error into a ring. amdgpu_pm_info @@ -165,7 +165,7 @@ GTT memory. amdgpu_regs_* ------------- -Provides direct access to various register aperatures on the GPU. Used +Provides direct access to various register apertures on the GPU. Used by tools like UMR to access GPU registers. amdgpu_regs2 diff --git a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv index d2f10ee69dfc..bfd44c6e052a 100644 --- a/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv +++ b/Documentation/gpu/amdgpu/dgpu-asic-info-table.csv @@ -1,28 +1,30 @@ -Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version -AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, -- -AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, -- -AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, VCE 1 / UVD 3, -- -AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, -- -AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, -- -AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1 -AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1 -AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2 -AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3 -AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3 -Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3 -Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3 -Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3 -Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0 -AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0 -MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2 -MI200 Series, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0 -MI300 Series, AQUA_VANJARAM, *, 9.4.3, VCN 4.0.3, 4.4.2 -AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0 -AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2 -AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0 -AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2 -AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4 -AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5 -AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0 -AMD Radeon RX 7800 XT, , DCN 3.2.0, 11.0.3, VCN 4.0.0, 6.0.3 -AMD Radeon RX 7600M (XT) /7700S /7600S, , DCN 3.2.1, 11.0.2, VCN 4.0.4, 6.0.2 +Product Name, Code Reference, DCN/DCE version, GC version, VCN version, SDMA version, MP0 version, MP1 version +AMD Radeon (TM) HD 8500M/ 8600M /M200 /M320 /M330 /M335 Series, HAINAN, --, 6, --, --, --, 6 +AMD Radeon HD 7800 /7900 /FireGL Series, TAHITI, DCE 6, 6, VCE 1 / UVD 3, --, --, 6 +AMD Radeon R7 (TM|HD) M265 /M370 /8500M /8600 /8700 /8700M, OLAND, DCE 6, 6, -- / UVD 3, --, --, 6 +AMD Radeon (TM) (HD|R7) 7800 /7970 /8800 /8970 /370/ Series, PITCAIRN, DCE 6, 6, VCE 1 / UVD 3, --, --, 6 +AMD Radeon (TM|R7|R9|HD) E8860 /M360 /7700 /7800 /8800 /9000(M) /W4100 Series, VERDE, DCE 6, 6, VCE 1 / UVD 3, --, --, 6 +AMD Radeon HD M280X /M380 /7700 /8950 /W5100, BONAIRE, DCE 8, 7, VCE 2 / UVD 4.2, 1, --, 7 +AMD Radeon (R9|TM) 200 /390 /W8100 /W9100 Series, HAWAII, DCE 8, 7, VCE 2 / UVD 4.2, 1, --, 7 +AMD Radeon (TM) R(5|7) M315 /M340 /M360, TOPAZ, *, 8, --, 2, n/a, 7 +AMD Radeon (TM) R9 200 /380 /W7100 /S7150 /M390 /M395 Series, TONGA, DCE 10, 8, VCE 3 / UVD 5, 3, n/a, 7 +AMD Radeon (FirePro) (TM) R9 Fury Series, FIJI, DCE 10, 8, VCE 3 / UVD 6, 3, n/a, 7 +Radeon RX 470 /480 /570 /580 /590 Series - AMD Radeon (TM) (Pro WX) 5100 /E9390 /E9560 /E9565 /V7350 /7100 /P30PH, POLARIS10, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3, n/a, 7 +Radeon (TM) (RX|Pro WX) E9260 /460 /V5300X /550 /560(X) Series, POLARIS11, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3, n/a, 7 +Radeon (RX/Pro) 500 /540(X) /550 /640 /WX2100 /WX3100 /WX200 Series, POLARIS12, DCE 11.2, 8, VCE 3.4 / UVD 6.3, 3, n/a, 7 +Radeon (RX|TM) (PRO|WX) Vega /MI25 /V320 /V340L /8200 /9100 /SSG MxGPU, VEGA10, DCE 12, 9.0.1, VCE 4.0.0 / UVD 7.0.0, 4.0.0, 9.0.0, 9.0.0 +AMD Radeon (Pro) VII /MI50 /MI60, VEGA20, DCE 12, 9.4.0, VCE 4.1.0 / UVD 7.2.0, 4.2.0, 11.0.2, 11.0.2 +MI100, ARCTURUS, *, 9.4.1, VCN 2.5.0, 4.2.2, 11.0.4, 11.0.2 +MI200 Series, ALDEBARAN, *, 9.4.2, VCN 2.6.0, 4.4.0, 13.0.2, 13.0.2 +MI300 Series, AQUA_VANJARAM, *, 9.4.3, VCN 4.0.3, 4.4.2, 13.0.6, 13.0.6 +AMD Radeon (RX|Pro) 5600(M|XT) /5700 (M|XT|XTB) /W5700, NAVI10, DCN 2.0.0, 10.1.10, VCN 2.0.0, 5.0.0, 11.0.0, 11.0.0 +AMD Radeon (Pro) 5300 /5500XTB/5500(XT|M) /W5500M /W5500, NAVI14, DCN 2.0.0, 10.1.1, VCN 2.0.2, 5.0.2, 11.0.5, 11.0.5 +AMD Radeon RX 6800(XT) /6900(XT) /W6800, SIENNA_CICHLID, DCN 3.0.0, 10.3.0, VCN 3.0.0, 5.2.0, 11.0.7, 11.0.7 +AMD Radeon RX 6700 XT / 6800M / 6700M, NAVY_FLOUNDER, DCN 3.0.0, 10.3.2, VCN 3.0.0, 5.2.2, 11.0.11, 11.0.11 +AMD Radeon RX 6600(XT) /6600M /W6600 /W6600M, DIMGREY_CAVEFISH, DCN 3.0.2, 10.3.4, VCN 3.0.16, 5.2.4, 11.0.12, 11.0.12 +AMD Radeon RX 6500M /6300M /W6500M /W6300M, BEIGE_GOBY, DCN 3.0.3, 10.3.5, VCN 3.0.33, 5.2.5, 11.0.13, 11.0.13 +AMD Radeon RX 7900 XT /XTX, , DCN 3.2.0, 11.0.0, VCN 4.0.0, 6.0.0, 13.0.0, 13.0.0 +AMD Radeon RX 7800 XT, , DCN 3.2.0, 11.0.3, VCN 4.0.0, 6.0.3, 13.0.10, 13.0.10 +AMD Radeon RX 7600M (XT) /7700S /7600S, , DCN 3.2.1, 11.0.2, VCN 4.0.4, 6.0.2, 13.0.7, 13.0.7 +AMD Radeon RX 9070 (XT), , DCN 4.0.1, 12.0.1, VCN 5.0.0, 7.0.1, 14.0.3, 14.0.3 +AMD Radeon RX 9060 XT, , DCN 4.0.1, 12.0.0, VCN 5.0.0, 7.0.0, 14.0.2, 14.0.2 diff --git a/Documentation/gpu/amdgpu/display/dc-glossary.rst b/Documentation/gpu/amdgpu/display/dc-glossary.rst index 7dc034e9e586..cbe737d1fcea 100644 --- a/Documentation/gpu/amdgpu/display/dc-glossary.rst +++ b/Documentation/gpu/amdgpu/display/dc-glossary.rst @@ -5,7 +5,7 @@ DC Glossary On this page, we try to keep track of acronyms related to the display component. If you do not find what you are looking for, look at the 'Documentation/gpu/amdgpu/amdgpu-glossary.rst'; if you cannot find it anywhere, -consider asking in the amdgfx and update this page. +consider asking on the amd-gfx mailing list and update this page. .. glossary:: diff --git a/Documentation/gpu/amdgpu/display/display-contributing.rst b/Documentation/gpu/amdgpu/display/display-contributing.rst index 36f3077eee00..2f741c52dce5 100644 --- a/Documentation/gpu/amdgpu/display/display-contributing.rst +++ b/Documentation/gpu/amdgpu/display/display-contributing.rst @@ -9,8 +9,8 @@ contribution to the display code, and for that, we say thank you :) This page summarizes some of the issues you can help with; keep in mind that this is a static page, and it is always a good idea to try to reach developers -in the amdgfx or some of the maintainers. Finally, this page follows the DRM -way of creating a TODO list; for more information, check +on the amd-gfx mailing list or some of the maintainers. Finally, this page +follows the DRM way of creating a TODO list; for more information, check 'Documentation/gpu/todo.rst'. Gitlab issues diff --git a/Documentation/gpu/amdgpu/display/programming-model-dcn.rst b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst index c1b48d49fb0b..bc7de97a746f 100644 --- a/Documentation/gpu/amdgpu/display/programming-model-dcn.rst +++ b/Documentation/gpu/amdgpu/display/programming-model-dcn.rst @@ -100,7 +100,7 @@ represents the connected display. For historical reasons, we used the name `dc_link`, which gives the wrong impression that this abstraction only deals with physical connections that the developer can easily manipulate. However, this also covers - conections like eDP or cases where the output is connected to other devices. + connections like eDP or cases where the output is connected to other devices. There are two structs that are not represented in the diagram since they were elaborated in the DCN overview page (check the DCN block diagram :ref:`Display diff --git a/Documentation/gpu/amdgpu/driver-core.rst b/Documentation/gpu/amdgpu/driver-core.rst index 81256318e93c..3ce276272171 100644 --- a/Documentation/gpu/amdgpu/driver-core.rst +++ b/Documentation/gpu/amdgpu/driver-core.rst @@ -65,7 +65,7 @@ SDMA (System DMA) GC (Graphics and Compute) This is the graphics and compute engine, i.e., the block that - encompasses the 3D pipeline and and shader blocks. This is by far the + encompasses the 3D pipeline and shader blocks. This is by far the largest block on the GPU. The 3D pipeline has tons of sub-blocks. In addition to that, it also contains the CP microcontrollers (ME, PFP, CE, MEC) and the RLC microcontroller. It's exposed to userspace for user mode @@ -210,4 +210,4 @@ IP Blocks :doc: IP Blocks .. kernel-doc:: drivers/gpu/drm/amd/include/amd_shared.h - :identifiers: amd_ip_block_type amd_ip_funcs DC_DEBUG_MASK + :identifiers: amd_ip_block_type amd_ip_funcs DC_FEATURE_MASK DC_DEBUG_MASK diff --git a/Documentation/gpu/amdgpu/index.rst b/Documentation/gpu/amdgpu/index.rst index bb2894b5edaf..45523e9860fc 100644 --- a/Documentation/gpu/amdgpu/index.rst +++ b/Documentation/gpu/amdgpu/index.rst @@ -12,6 +12,7 @@ Next (GCN), Radeon DNA (RDNA), and Compute DNA (CDNA) architectures. module-parameters gc/index display/index + userq flashing xgmi ras diff --git a/Documentation/gpu/amdgpu/process-isolation.rst b/Documentation/gpu/amdgpu/process-isolation.rst index 6b6d70e357a7..25b06ffefc33 100644 --- a/Documentation/gpu/amdgpu/process-isolation.rst +++ b/Documentation/gpu/amdgpu/process-isolation.rst @@ -26,7 +26,7 @@ Example of enabling enforce isolation on a GPU with multiple partitions: $ cat /sys/class/drm/card0/device/enforce_isolation 1 0 1 0 -The output indicates that enforce isolation is enabled on zeroth and second parition and disabled on first and fourth parition. +The output indicates that enforce isolation is enabled on zeroth and second partition and disabled on first and third partition. For devices with a single partition or those that do not support partitions, there will be only one element: diff --git a/Documentation/gpu/amdgpu/userq.rst b/Documentation/gpu/amdgpu/userq.rst new file mode 100644 index 000000000000..ca3ea71f7888 --- /dev/null +++ b/Documentation/gpu/amdgpu/userq.rst @@ -0,0 +1,203 @@ +================== + User Mode Queues +================== + +Introduction +============ + +Similar to the KFD, GPU engine queues move into userspace. The idea is to let +user processes manage their submissions to the GPU engines directly, bypassing +IOCTL calls to the driver to submit work. This reduces overhead and also allows +the GPU to submit work to itself. Applications can set up work graphs of jobs +across multiple GPU engines without needing trips through the CPU. + +UMDs directly interface with firmware via per application shared memory areas. +The main vehicle for this is queue. A queue is a ring buffer with a read +pointer (rptr) and a write pointer (wptr). The UMD writes IP specific packets +into the queue and the firmware processes those packets, kicking off work on the +GPU engines. The CPU in the application (or another queue or device) updates +the wptr to tell the firmware how far into the ring buffer to process packets +and the rtpr provides feedback to the UMD on how far the firmware has progressed +in executing those packets. When the wptr and the rptr are equal, the queue is +idle. + +Theory of Operation +=================== + +The various engines on modern AMD GPUs support multiple queues per engine with a +scheduling firmware which handles dynamically scheduling user queues on the +available hardware queue slots. When the number of user queues outnumbers the +available hardware queue slots, the scheduling firmware dynamically maps and +unmaps queues based on priority and time quanta. The state of each user queue +is managed in the kernel driver in an MQD (Memory Queue Descriptor). This is a +buffer in GPU accessible memory that stores the state of a user queue. The +scheduling firmware uses the MQD to load the queue state into an HQD (Hardware +Queue Descriptor) when a user queue is mapped. Each user queue requires a +number of additional buffers which represent the ring buffer and any metadata +needed by the engine for runtime operation. On most engines this consists of +the ring buffer itself, a rptr buffer (where the firmware will shadow the rptr +to userspace), a wptr buffer (where the application will write the wptr for the +firmware to fetch it), and a doorbell. A doorbell is a piece of one of the +device's MMIO BARs which can be mapped to specific user queues. When the +application writes to the doorbell, it will signal the firmware to take some +action. Writing to the doorbell wakes the firmware and causes it to fetch the +wptr and start processing the packets in the queue. Each 4K page of the doorbell +BAR supports specific offset ranges for specific engines. The doorbell of a +queue must be mapped into the aperture aligned to the IP used by the queue +(e.g., GFX, VCN, SDMA, etc.). These doorbell apertures are set up via NBIO +registers. Doorbells are 32 bit or 64 bit (depending on the engine) chunks of +the doorbell BAR. A 4K doorbell page provides 512 64-bit doorbells for up to +512 user queues. A subset of each page is reserved for each IP type supported +on the device. The user can query the doorbell ranges for each IP via the INFO +IOCTL. See the IOCTL Interfaces section for more information. + +When an application wants to create a user queue, it allocates the necessary +buffers for the queue (ring buffer, wptr and rptr, context save areas, etc.). +These can be separate buffers or all part of one larger buffer. The application +would map the buffer(s) into its GPUVM and use the GPU virtual addresses of for +the areas of memory they want to use for the user queue. They would also +allocate a doorbell page for the doorbells used by the user queues. The +application would then populate the MQD in the USERQ IOCTL structure with the +GPU virtual addresses and doorbell index they want to use. The user can also +specify the attributes for the user queue (priority, whether the queue is secure +for protected content, etc.). The application would then call the USERQ +CREATE IOCTL to create the queue using the specified MQD details in the IOCTL. +The kernel driver then validates the MQD provided by the application and +translates the MQD into the engine specific MQD format for the IP. The IP +specific MQD would be allocated and the queue would be added to the run list +maintained by the scheduling firmware. Once the queue has been created, the +application can write packets directly into the queue, update the wptr, and +write to the doorbell offset to kick off work in the user queue. + +When the application is done with the user queue, it would call the USERQ +FREE IOCTL to destroy it. The kernel driver would preempt the queue and +remove it from the scheduling firmware's run list. Then the IP specific MQD +would be freed and the user queue state would be cleaned up. + +Some engines may require the aggregated doorbell too if the engine does not +support doorbells from unmapped queues. The aggregated doorbell is a special +page of doorbell space which wakes the scheduler. In cases where the engine may +be oversubscribed, some queues may not be mapped. If the doorbell is rung when +the queue is not mapped, the engine firmware may miss the request. Some +scheduling firmware may work around this by polling wptr shadows when the +hardware is oversubscribed, other engines may support doorbell updates from +unmapped queues. In the event that one of these options is not available, the +kernel driver will map a page of aggregated doorbell space into each GPUVM +space. The UMD will then update the doorbell and wptr as normal and then write +to the aggregated doorbell as well. + +Special Packets +--------------- + +In order to support legacy implicit synchronization, as well as mixed user and +kernel queues, we need a synchronization mechanism that is secure. Because +kernel queues or memory management tasks depend on kernel fences, we need a way +for user queues to update memory that the kernel can use for a fence, that can't +be messed with by a bad actor. To support this, we've added a protected fence +packet. This packet works by writing a monotonically increasing value to +a memory location that only privileged clients have write access to. User +queues only have read access. When this packet is executed, the memory location +is updated and other queues (kernel or user) can see the results. The +user application would submit this packet in their command stream. The actual +packet format varies from IP to IP (GFX/Compute, SDMA, VCN, etc.), but the +behavior is the same. The packet submission is handled in userspace. The +kernel driver sets up the privileged memory used for each user queue when it +sets the queues up when the application creates them. + + +Memory Management +================= + +It is assumed that all buffers mapped into the GPUVM space for the process are +valid when engines on the GPU are running. The kernel driver will only allow +user queues to run when all buffers are mapped. If there is a memory event that +requires buffer migration, the kernel driver will preempt the user queues, +migrate buffers to where they need to be, update the GPUVM page tables and +invaldidate the TLB, and then resume the user queues. + +Interaction with Kernel Queues +============================== + +Depending on the IP and the scheduling firmware, you can enable kernel queues +and user queues at the same time, however, you are limited by the HQD slots. +Kernel queues are always mapped so any work that goes into kernel queues will +take priority. This limits the available HQD slots for user queues. + +Not all IPs will support user queues on all GPUs. As such, UMDs will need to +support both user queues and kernel queues depending on the IP. For example, a +GPU may support user queues for GFX, compute, and SDMA, but not for VCN, JPEG, +and VPE. UMDs need to support both. The kernel driver provides a way to +determine if user queues and kernel queues are supported on a per IP basis. +UMDs can query this information via the INFO IOCTL and determine whether to use +kernel queues or user queues for each IP. + +Queue Resets +============ + +For most engines, queues can be reset individually. GFX, compute, and SDMA +queues can be reset individually. When a hung queue is detected, it can be +reset either via the scheduling firmware or MMIO. Since there are no kernel +fences for most user queues, they will usually only be detected when some other +event happens; e.g., a memory event which requires migration of buffers. When +the queues are preempted, if the queue is hung, the preemption will fail. +Driver will then look up the queues that failed to preempt and reset them and +record which queues are hung. + +On the UMD side, we will add a USERQ QUERY_STATUS IOCTL to query the queue +status. UMD will provide the queue id in the IOCTL and the kernel driver +will check if it has already recorded the queue as hung (e.g., due to failed +peemption) and report back the status. + +IOCTL Interfaces +================ + +GPU virtual addresses used for queues and related data (rptrs, wptrs, context +save areas, etc.) should be validated by the kernel mode driver to prevent the +user from specifying invalid GPU virtual addresses. If the user provides +invalid GPU virtual addresses or doorbell indicies, the IOCTL should return an +error message. These buffers should also be tracked in the kernel driver so +that if the user attempts to unmap the buffer(s) from the GPUVM, the umap call +would return an error. + +INFO +---- +There are several new INFO queries related to user queues in order to query the +size of user queue meta data needed for a user queue (e.g., context save areas +or shadow buffers), whether kernel or user queues or both are supported +for each IP type, and the offsets for each IP type in each doorbell page. + +USERQ +----- +The USERQ IOCTL is used for creating, freeing, and querying the status of user +queues. It supports 3 opcodes: + +1. CREATE - Create a user queue. The application provides an MQD-like structure + that defines the type of queue and associated metadata and flags for that + queue type. Returns the queue id. +2. FREE - Free a user queue. +3. QUERY_STATUS - Query that status of a queue. Used to check if the queue is + healthy or not. E.g., if the queue has been reset. (WIP) + +USERQ_SIGNAL +------------ +The USERQ_SIGNAL IOCTL is used to provide a list of sync objects to be signaled. + +USERQ_WAIT +---------- +The USERQ_WAIT IOCTL is used to provide a list of sync object to be waited on. + +Kernel and User Queues +====================== + +In order to properly validate and test performance, we have a driver option to +select what type of queues are enabled (kernel queues, user queues or both). +The user_queue driver parameter allows you to enable kernel queues only (0), +user queues and kernel queues (1), and user queues only (2). Enabling user +queues only will free up static queue assignments that would otherwise be used +by kernel queues for use by the scheduling firmware. Some kernel queues are +required for kernel driver operation and they will always be created. When the +kernel queues are not enabled, they are not registered with the drm scheduler +and the CS IOCTL will reject any incoming command submissions which target those +queue types. Kernel queues only mirrors the behavior on all existing GPUs. +Enabling both queues allows for backwards compatibility with old userspace while +still supporting user queues. diff --git a/Documentation/gpu/drm-uapi.rst b/Documentation/gpu/drm-uapi.rst index 843facf01b2d..d98428a592f1 100644 --- a/Documentation/gpu/drm-uapi.rst +++ b/Documentation/gpu/drm-uapi.rst @@ -418,13 +418,12 @@ needed. Recovery -------- -Current implementation defines three recovery methods, out of which, drivers +Current implementation defines four recovery methods, out of which, drivers can use any one, multiple or none. Method(s) of choice will be sent in the uevent environment as ``WEDGED=<method1>[,..,<methodN>]`` in order of less to -more side-effects. If driver is unsure about recovery or method is unknown -(like soft/hard system reboot, firmware flashing, physical device replacement -or any other procedure which can't be attempted on the fly), ``WEDGED=unknown`` -will be sent instead. +more side-effects. See the section `Vendor Specific Recovery`_ +for ``WEDGED=vendor-specific``. If driver is unsure about recovery or +method is unknown, ``WEDGED=unknown`` will be sent instead. Userspace consumers can parse this event and attempt recovery as per the following expectations. @@ -435,6 +434,7 @@ following expectations. none optional telemetry collection rebind unbind + bind driver bus-reset unbind + bus reset/re-enumeration + bind + vendor-specific vendor specific recovery method unknown consumer policy =============== ======================================== @@ -446,6 +446,35 @@ telemetry information (devcoredump, syslog). This is useful because the first hang is usually the most critical one which can result in consequential hangs or complete wedging. + +Vendor Specific Recovery +------------------------ + +When ``WEDGED=vendor-specific`` is sent, it indicates that the device requires +a recovery procedure specific to the hardware vendor and is not one of the +standardized approaches. + +``WEDGED=vendor-specific`` may be used to indicate different cases within a +single vendor driver, each requiring a distinct recovery procedure. +In such scenarios, the vendor driver must provide comprehensive documentation +that describes each case, include additional hints to identify specific case and +outline the corresponding recovery procedure. The documentation includes: + +Case - A list of all cases that sends the ``WEDGED=vendor-specific`` recovery method. + +Hints - Additional Information to assist the userspace consumer in identifying and +differentiating between different cases. This can be exposed through sysfs, debugfs, +traces, dmesg etc. + +Recovery Procedure - Clear instructions and guidance for recovering each case. +This may include userspace scripts, tools needed for the recovery procedure. + +It is the responsibility of the admin/userspace consumer to identify the case and +verify additional identification hints before attempting a recovery procedure. + +Example: If the device uses the Xe driver, then userspace consumer should refer to +:ref:`Xe Device Wedging <xe-device-wedging>` for the detailed documentation. + Task information ---------------- @@ -472,8 +501,12 @@ erroring out, all device memory should be unmapped and file descriptors should be closed to prevent leaks or undefined behaviour. The idea here is to clear the device of all user context beforehand and set the stage for a clean recovery. -Example -------- +For ``WEDGED=vendor-specific`` recovery method, it is the responsibility of the +consumer to check the driver documentation and the usecase before attempting +a recovery. + +Example - rebind +---------------- Udev rule:: diff --git a/Documentation/gpu/i915.rst b/Documentation/gpu/i915.rst index 72932fa31b8d..eba09c3ddce4 100644 --- a/Documentation/gpu/i915.rst +++ b/Documentation/gpu/i915.rst @@ -358,8 +358,6 @@ Locking Guidelines #. All locking rules and interface contracts with cross-driver interfaces (dma-buf, dma_fence) need to be followed. -#. No struct_mutex anywhere in the code - #. dma_resv will be the outermost lock (when needed) and ww_acquire_ctx is to be hoisted at highest level and passed down within i915_gem_ctx in the call chain @@ -367,11 +365,6 @@ Locking Guidelines #. While holding lru/memory manager (buddy, drm_mm, whatever) locks system memory allocations are not allowed - * Enforce this by priming lockdep (with fs_reclaim). If we - allocate memory while holding these looks we get a rehash - of the shrinker vs. struct_mutex saga, and that would be - real bad. - #. Do not nest different lru/memory manager locks within each other. Take them in turn to update memory allocations, relying on the object’s dma_resv ww_mutex to serialize against other operations. diff --git a/Documentation/gpu/nova/core/todo.rst b/Documentation/gpu/nova/core/todo.rst index 894a1e9c3741..0972cb905f7a 100644 --- a/Documentation/gpu/nova/core/todo.rst +++ b/Documentation/gpu/nova/core/todo.rst @@ -131,8 +131,6 @@ crate so it can be used by other components as well. Features desired before this happens: -* Relative register with build-time base address validation, -* Arrays of registers with build-time index validation, * Make I/O optional I/O (for field values that are not registers), * Support other sizes than `u32`, * Allow visibility control for registers and individual fields, @@ -147,7 +145,6 @@ Numerical operations [NUMM] Nova uses integer operations that are not part of the standard library (or not implemented in an optimized way for the kernel). These include: -- Aligning up and down to a power of two, - The "Find Last Set Bit" (`fls` function of the C part of the kernel) operation. @@ -232,23 +229,6 @@ Rust abstraction for debugfs APIs. GPU (general) ============= -Parse firmware headers ----------------------- - -Parse ELF headers from the firmware files loaded from the filesystem. - -| Reference: ELF utils -| Complexity: Beginner -| Contact: Abdiel Janulgue - -Build radix3 page table ------------------------ - -Build the radix3 page table to map the firmware. - -| Complexity: Intermediate -| Contact: Abdiel Janulgue - Initial Devinit support ----------------------- diff --git a/Documentation/gpu/todo.rst b/Documentation/gpu/todo.rst index be8637da3fe9..b5f58b4274b1 100644 --- a/Documentation/gpu/todo.rst +++ b/Documentation/gpu/todo.rst @@ -173,31 +173,6 @@ Contact: Simona Vetter Level: Intermediate -Get rid of dev->struct_mutex from GEM drivers ---------------------------------------------- - -``dev->struct_mutex`` is the Big DRM Lock from legacy days and infested -everything. Nowadays in modern drivers the only bit where it's mandatory is -serializing GEM buffer object destruction. Which unfortunately means drivers -have to keep track of that lock and either call ``unreference`` or -``unreference_locked`` depending upon context. - -Core GEM doesn't have a need for ``struct_mutex`` any more since kernel 4.8, -and there's a GEM object ``free`` callback for any drivers which are -entirely ``struct_mutex`` free. - -For drivers that need ``struct_mutex`` it should be replaced with a driver- -private lock. The tricky part is the BO free functions, since those can't -reliably take that lock any more. Instead state needs to be protected with -suitable subordinate locks or some cleanup work pushed to a worker thread. For -performance-critical drivers it might also be better to go with a more -fine-grained per-buffer object and per-context lockings scheme. Currently only -the ``msm`` and `i915` drivers use ``struct_mutex``. - -Contact: Simona Vetter, respective driver maintainers - -Level: Advanced - Move Buffer Object Locking to dma_resv_lock() --------------------------------------------- @@ -497,19 +472,19 @@ Contact: Douglas Anderson <dianders@chromium.org> Level: Intermediate -Transition away from using mipi_dsi_*_write_seq() -------------------------------------------------- +Transition away from using deprecated MIPI DSI functions +-------------------------------------------------------- -The macros mipi_dsi_generic_write_seq() and mipi_dsi_dcs_write_seq() are -non-intuitive because, if there are errors, they return out of the *caller's* -function. We should move all callers to use mipi_dsi_generic_write_seq_multi() -and mipi_dsi_dcs_write_seq_multi() macros instead. +There are many functions defined in ``drm_mipi_dsi.c`` which have been +deprecated. Each deprecated function was deprecated in favor of its `multi` +variant (e.g. `mipi_dsi_generic_write()` and `mipi_dsi_generic_write_multi()`). +The `multi` variant of a function includes improved error handling and logic +which makes it more convenient to make several calls in a row, as most MIPI +drivers do. -Once all callers are transitioned, the macros and the functions that they call, -mipi_dsi_generic_write_chatty() and mipi_dsi_dcs_write_buffer_chatty(), can -probably be removed. Alternatively, if people feel like the _multi() variants -are overkill for some use cases, we could keep the mipi_dsi_*_write_seq() -variants but change them not to return out of the caller. +Drivers should be updated to use undeprecated functions. Once all usages of the +deprecated MIPI DSI functions have been removed, their definitions may be +removed from ``drm_mipi_dsi.c``. Contact: Douglas Anderson <dianders@chromium.org> diff --git a/Documentation/gpu/xe/index.rst b/Documentation/gpu/xe/index.rst index 42ba6c263cd0..88b22fad880e 100644 --- a/Documentation/gpu/xe/index.rst +++ b/Documentation/gpu/xe/index.rst @@ -25,5 +25,6 @@ DG2, etc is provided to prototype the driver. xe_tile xe_debugging xe_devcoredump + xe_device xe-drm-usage-stats.rst xe_configfs diff --git a/Documentation/gpu/xe/xe_device.rst b/Documentation/gpu/xe/xe_device.rst new file mode 100644 index 000000000000..39a937b97cd3 --- /dev/null +++ b/Documentation/gpu/xe/xe_device.rst @@ -0,0 +1,10 @@ +.. SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +.. _xe-device-wedging: + +================== +Xe Device Wedging +================== + +.. kernel-doc:: drivers/gpu/drm/xe/xe_device.c + :doc: Xe Device Wedging diff --git a/Documentation/gpu/xe/xe_pcode.rst b/Documentation/gpu/xe/xe_pcode.rst index 5937ef3599b0..2a43601123cb 100644 --- a/Documentation/gpu/xe/xe_pcode.rst +++ b/Documentation/gpu/xe/xe_pcode.rst @@ -13,9 +13,11 @@ Internal API .. kernel-doc:: drivers/gpu/drm/xe/xe_pcode.c :internal: +.. _xe-survivability-mode: + ================== -Boot Survivability +Survivability Mode ================== .. kernel-doc:: drivers/gpu/drm/xe/xe_survivability_mode.c - :doc: Xe Boot Survivability + :doc: Survivability Mode diff --git a/Documentation/hwmon/adm1275.rst b/Documentation/hwmon/adm1275.rst index 57bd7a850558..cf923f20fa52 100644 --- a/Documentation/hwmon/adm1275.rst +++ b/Documentation/hwmon/adm1275.rst @@ -67,6 +67,14 @@ Supported chips: Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1293_1294.pdf + * Silergy SQ24905C + + Prefix: 'mc09c' + + Addresses scanned: - + + Datasheet: https://www.silergy.com/download/downloadFile?id=5669&type=product&ftype=note + Author: Guenter Roeck <linux@roeck-us.net> @@ -74,14 +82,14 @@ Description ----------- This driver supports hardware monitoring for Analog Devices ADM1075, ADM1272, -ADM1273, ADM1275, ADM1276, ADM1278, ADM1281, ADM1293, and ADM1294 Hot-Swap -Controller and Digital Power Monitors. +ADM1273, ADM1275, ADM1276, ADM1278, ADM1281, ADM1293, ADM1294, and SQ24905C +Hot-Swap Controller and Digital Power Monitors. -ADM1075, ADM1272, ADM1273, ADM1275, ADM1276, ADM1278, ADM1281, ADM1293, and -ADM1294 are hot-swap controllers that allow a circuit board to be removed from -or inserted into a live backplane. They also feature current and voltage -readback via an integrated 12 bit analog-to-digital converter (ADC), accessed -using a PMBus interface. +ADM1075, ADM1272, ADM1273, ADM1275, ADM1276, ADM1278, ADM1281, ADM1293, +ADM1294 and SQ24905C are hot-swap controllers that allow a circuit board to be +removed from or inserted into a live backplane. They also feature current and +voltage readback via an integrated 12 bit analog-to-digital converter (ADC), +accessed using a PMBus interface. The driver is a client driver to the core PMBus driver. Please see Documentation/hwmon/pmbus.rst for details on PMBus client drivers. @@ -160,5 +168,5 @@ temp1_highest Highest observed temperature. temp1_reset_history Write any value to reset history. Temperature attributes are supported on ADM1272, - ADM1273, ADM1278, and ADM1281. + ADM1273, ADM1278, ADM1281 and SQ24905C. ======================= ======================================================= diff --git a/Documentation/hwmon/asus_ec_sensors.rst b/Documentation/hwmon/asus_ec_sensors.rst index de2f2985f06f..a5a58c00c322 100644 --- a/Documentation/hwmon/asus_ec_sensors.rst +++ b/Documentation/hwmon/asus_ec_sensors.rst @@ -8,7 +8,9 @@ Supported boards: * PRIME X470-PRO * PRIME X570-PRO * PRIME X670E-PRO WIFI + * PRIME Z270-A * Pro WS X570-ACE + * Pro WS WRX90E-SAGE SE * ProArt X570-CREATOR WIFI * ProArt X670E-CREATOR WIFI * ProArt X870E-CREATOR WIFI @@ -25,16 +27,26 @@ Supported boards: * ROG MAXIMUS Z690 FORMULA * ROG STRIX B550-E GAMING * ROG STRIX B550-I GAMING + * ROG STRIX B650E-I GAMING WIFI + * ROG STRIX B850-I GAMING WIFI * ROG STRIX X570-E GAMING * ROG STRIX X570-E GAMING WIFI II * ROG STRIX X570-F GAMING * ROG STRIX X570-I GAMING + * ROG STRIX X670E-E GAMING WIFI + * ROG STRIX X670E-I GAMING WIFI + * ROG STRIX X870-I GAMING WIFI + * ROG STRIX X870E-E GAMING WIFI * ROG STRIX Z390-F GAMING * ROG STRIX Z490-F GAMING * ROG STRIX Z690-A GAMING WIFI D4 + * ROG STRIX Z690-E GAMING WIFI + * ROG STRIX Z790-E GAMING WIFI II + * ROG STRIX Z790-I GAMING WIFI * ROG ZENITH II EXTREME * ROG ZENITH II EXTREME ALPHA * TUF GAMING X670E PLUS + * TUF GAMING X670E PLUS WIFI Authors: - Eugene Shalygin <eugene.shalygin@gmail.com> diff --git a/Documentation/hwmon/cros_ec_hwmon.rst b/Documentation/hwmon/cros_ec_hwmon.rst index 47ecae983bdb..6db812708325 100644 --- a/Documentation/hwmon/cros_ec_hwmon.rst +++ b/Documentation/hwmon/cros_ec_hwmon.rst @@ -23,4 +23,9 @@ ChromeOS embedded controller used in Chromebooks and other devices. The channel labels exposed via hwmon are retrieved from the EC itself. -Fan and temperature readings are supported. +Fan and temperature readings are supported. PWM fan control is also supported if +the EC also supports setting fan PWM values and fan mode. Note that EC will +switch fan control mode back to auto when suspended. This driver will restore +the fan state to what they were before suspended when resumed. +If a fan is controllable, this driver will register that fan as a cooling device +in the thermal framework as well. diff --git a/Documentation/hwmon/crps.rst b/Documentation/hwmon/crps.rst index 87380b496558..d42ea59d2dae 100644 --- a/Documentation/hwmon/crps.rst +++ b/Documentation/hwmon/crps.rst @@ -43,7 +43,7 @@ curr1_label "iin" curr1_input Measured input current curr1_max Maximum input current curr1_max_alarm Input maximum current high alarm -curr1_crit Critial high input current +curr1_crit Critical high input current curr1_crit_alarm Input critical current high alarm curr1_rated_max Maximum rated input current @@ -51,7 +51,7 @@ curr2_label "iout1" curr2_input Measured output current curr2_max Maximum output current curr2_max_alarm Output maximum current high alarm -curr2_crit Critial high output current +curr2_crit Critical high output current curr2_crit_alarm Output critical current high alarm curr2_rated_max Maximum rated output current diff --git a/Documentation/hwmon/dell-smm-hwmon.rst b/Documentation/hwmon/dell-smm-hwmon.rst index 5a4edb6565cf..3e4e2d916ac5 100644 --- a/Documentation/hwmon/dell-smm-hwmon.rst +++ b/Documentation/hwmon/dell-smm-hwmon.rst @@ -38,7 +38,7 @@ fan[1-4]_min RO Minimal Fan speed in RPM fan[1-4]_max RO Maximal Fan speed in RPM fan[1-4]_target RO Expected Fan speed in RPM pwm[1-4] RW Control the fan PWM duty-cycle. -pwm1_enable WO Enable or disable automatic BIOS fan +pwm[1-4]_enable RW/WO Enable or disable automatic BIOS fan control (not supported on all laptops, see below for details). temp[1-10]_input RO Temperature reading in milli-degrees @@ -49,26 +49,40 @@ temp[1-10]_label RO Temperature sensor label. Due to the nature of the SMM interface, each pwmX attribute controls fan number X. -Disabling automatic BIOS fan control ------------------------------------- - -On some laptops the BIOS automatically sets fan speed every few -seconds. Therefore the fan speed set by mean of this driver is quickly -overwritten. - -There is experimental support for disabling automatic BIOS fan -control, at least on laptops where the corresponding SMM command is -known, by writing the value ``1`` in the attribute ``pwm1_enable`` -(writing ``2`` enables automatic BIOS control again). Even if you have -more than one fan, all of them are set to either enabled or disabled -automatic fan control at the same time and, notwithstanding the name, -``pwm1_enable`` sets automatic control for all fans. - -If ``pwm1_enable`` is not available, then it means that SMM codes for -enabling and disabling automatic BIOS fan control are not whitelisted -for your hardware. It is possible that codes that work for other -laptops actually work for yours as well, or that you have to discover -new codes. +Enabling/Disabling automatic BIOS fan control +--------------------------------------------- + +There exist two methods for enabling/disabling automatic BIOS fan control: + +1. Separate SMM commands to enable/disable automatic BIOS fan control for all fans. + +2. A special fan state that enables automatic BIOS fan control for a individual fan. + +The driver cannot reliably detect what method should be used on a given +device, so instead the following heuristic is used: + +- use fan state 3 for enabling BIOS fan control if the maximum fan state + setable by the user is smaller than 3 (default setting). + +- use separate SMM commands if device is whitelisted to support them. + +When using the first method, each fan will have a standard ``pwmX_enable`` +sysfs attribute. Writing ``1`` into this attribute will disable automatic +BIOS fan control for the associated fan and set it to maximum speed. Enabling +BIOS fan control again can be achieved by writing ``2`` into this attribute. +Reading this sysfs attributes returns the current setting as reported by +the underlying hardware. + +When using the second method however, only the ``pwm1_enable`` sysfs attribute +will be available to enable/disable automatic BIOS fan control globaly for all +fans available on a given device. Additionally, this sysfs attribute is write-only +as there exists no SMM command for reading the current fan control setting. + +If no ``pwmX_enable`` attributes are available, then it means that the driver +cannot use the first method and the SMM codes for enabling and disabling automatic +BIOS fan control are not whitelisted for your device. It is possible that codes +that work for other laptops actually work for yours as well, or that you have to +discover new codes. Check the list ``i8k_whitelist_fan_control`` in file ``drivers/hwmon/dell-smm-hwmon.c`` in the kernel tree: as a first diff --git a/Documentation/hwmon/gpd-fan.rst b/Documentation/hwmon/gpd-fan.rst new file mode 100644 index 000000000000..0b56b70e6264 --- /dev/null +++ b/Documentation/hwmon/gpd-fan.rst @@ -0,0 +1,78 @@ +.. SPDX-License-Identifier: GPL-2.0-or-later + +Kernel driver gpd-fan +========================= + +Author: + - Cryolitia PukNgae <cryolitia@uniontech.com> + +Description +------------ + +Handheld devices from Shenzhen GPD Technology Co., Ltd. provide fan readings +and fan control through their embedded controllers. + +Supported devices +----------------- + +Currently the driver supports the following handhelds: + + - GPD Win Mini (7840U) + - GPD Win Mini (8840U) + - GPD Win Mini (HX370) + - GPD Pocket 4 + - GPD Duo + - GPD Win Max 2 (6800U) + - GPD Win Max 2 2023 (7840U) + - GPD Win Max 2 2024 (8840U) + - GPD Win Max 2 2025 (HX370) + - GPD Win 4 (6800U) + - GPD Win 4 (7840U) + +Module parameters +----------------- + +gpd_fan_board + Force specific which module quirk should be used. + Use it like "gpd_fan_board=wm2". + + - wm2 + - GPD Win 4 (7840U) + - GPD Win Max 2 (6800U) + - GPD Win Max 2 2023 (7840U) + - GPD Win Max 2 2024 (8840U) + - GPD Win Max 2 2025 (HX370) + - win4 + - GPD Win 4 (6800U) + - win_mini + - GPD Win Mini (7840U) + - GPD Win Mini (8840U) + - GPD Win Mini (HX370) + - GPD Pocket 4 + - GPD Duo + +Sysfs entries +------------- + +The following attributes are supported: + +fan1_input + Read Only. Reads current fan RPM. + +pwm1_enable + Read/Write. Enable manual fan control. Write "0" to disable control and run + at full speed. Write "1" to set to manual, write "2" to let the EC control + decide fan speed. Read this attribute to see current status. + + NB：In consideration of the safety of the device, when setting to manual mode, + the pwm speed will be set to the maximum value (255) by default. You can set + a different value by writing pwm1 later. + +pwm1 + Read/Write. Read this attribute to see current duty cycle in the range + [0-255]. When pwm1_enable is set to "1" (manual) write any value in the + range [0-255] to set fan speed. + + NB: Many boards (except listed under wm2 above) don't support reading the + current pwm value in auto mode. That will just return EOPNOTSUPP. In manual + mode it will always return the real value. diff --git a/Documentation/hwmon/hwmon-kernel-api.rst b/Documentation/hwmon/hwmon-kernel-api.rst index e47fc757e63e..1d7f1397a827 100644 --- a/Documentation/hwmon/hwmon-kernel-api.rst +++ b/Documentation/hwmon/hwmon-kernel-api.rst @@ -42,6 +42,9 @@ register/unregister functions:: char *devm_hwmon_sanitize_name(struct device *dev, const char *name); + void hwmon_lock(struct device *dev); + void hwmon_unlock(struct device *dev); + hwmon_device_register_with_info registers a hardware monitoring device. It creates the standard sysfs attributes in the hardware monitoring core, letting the driver focus on reading from and writing to the chip instead @@ -79,6 +82,13 @@ devm_hwmon_sanitize_name is the resource managed version of hwmon_sanitize_name; the memory will be freed automatically on device removal. +When using ``[devm_]hwmon_device_register_with_info()`` to register the +hardware monitoring device, accesses using the associated access functions +are serialised by the hardware monitoring core. If a driver needs locking +for other functions such as interrupt handlers or for attributes which are +fully implemented in the driver, hwmon_lock() and hwmon_unlock() can be used +to ensure that calls to those functions are serialized. + Using devm_hwmon_device_register_with_info() -------------------------------------------- @@ -159,6 +169,7 @@ It contains following fields: hwmon_curr Current sensor hwmon_power Power sensor hwmon_energy Energy sensor + hwmon_energy64 Energy sensor, reported as 64-bit signed value hwmon_humidity Humidity sensor hwmon_fan Fan speed sensor hwmon_pwm PWM control @@ -288,6 +299,8 @@ Parameters: The sensor channel number. val: Pointer to attribute value. + For hwmon_energy64, `'val`' is passed as `long *` but needs + a typecast to `s64 *`. Return value: 0 on success, a negative error number otherwise. diff --git a/Documentation/hwmon/ina238.rst b/Documentation/hwmon/ina238.rst index 9a24da4786a4..43950d1ec551 100644 --- a/Documentation/hwmon/ina238.rst +++ b/Documentation/hwmon/ina238.rst @@ -5,6 +5,24 @@ Kernel driver ina238 Supported chips: + * Texas Instruments INA228 + + Prefix: 'ina228' + + Addresses: I2C 0x40 - 0x4f + + Datasheet: + https://www.ti.com/lit/gpn/ina228 + + * Texas Instruments INA237 + + Prefix: 'ina237' + + Addresses: I2C 0x40 - 0x4f + + Datasheet: + https://www.ti.com/lit/gpn/ina237 + * Texas Instruments INA238 Prefix: 'ina238' @@ -14,6 +32,16 @@ Supported chips: Datasheet: https://www.ti.com/lit/gpn/ina238 + * Texas Instruments INA700 + + Datasheet: + https://www.ti.com/product/ina700 + + * Texas Instruments INA780 + + Datasheet: + https://www.ti.com/product/ina780a + * Silergy SQ52206 Prefix: 'SQ52206' @@ -29,10 +57,20 @@ The INA238 is a current shunt, power and temperature monitor with an I2C interface. It includes a number of programmable functions including alerts, conversion rate, sample averaging and selectable shunt voltage accuracy. -The shunt value in micro-ohms can be set via platform data or device tree at -compile-time or via the shunt_resistor attribute in sysfs at run-time. Please -refer to the Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml for bindings -if the device tree is used. +The shunt value in micro-ohms can be set via device properties, either from +platform code or from device tree data. Please refer to +Documentation/devicetree/bindings/hwmon/ti,ina2xx.yaml for bindings if +device tree is used. + +INA237 is a functionally equivalent variant of INA238 with slightly +different accuracy. INA228 is another variant of INA238 with higher ADC +resolution. This chip also reports the energy. + +INA700 and INA780 are variants of the chip series with built-in shunt resistor. +They also report the energy. + +SQ52206 is a mostly compatible chip from Sylergy. It reports the energy +as well as the peak power consumption. Sysfs entries ------------- @@ -53,19 +91,19 @@ in1_max_alarm Maximum shunt voltage alarm power1_input Power measurement (uW) power1_max Maximum power threshold (uW) power1_max_alarm Maximum power alarm +power1_input_highest Peak Power (uW) + (SQ52206 only) curr1_input Current measurement (mA) +curr1_min Minimum current threshold (mA) +curr1_min_alarm Minimum current alarm +curr1_max Maximum current threshold (mA) +curr1_max_alarm Maximum current alarm + +energy1_input Energy measurement (uJ) + (SQ52206, INA237, and INA780 only) temp1_input Die temperature measurement (mC) temp1_max Maximum die temperature threshold (mC) temp1_max_alarm Maximum die temperature alarm ======================= ======================================================= - -Additional sysfs entries for sq52206 ------------------------------------- - -======================= ======================================================= -energy1_input Energy measurement (uJ) - -power1_input_highest Peak Power (uW) -======================= ======================================================= diff --git a/Documentation/hwmon/index.rst b/Documentation/hwmon/index.rst index d292a86ac5da..51a5bdf75b08 100644 --- a/Documentation/hwmon/index.rst +++ b/Documentation/hwmon/index.rst @@ -82,6 +82,7 @@ Hardware Monitoring Kernel Drivers gigabyte_waterforce gsc-hwmon gl518sm + gpd-fan gxp-fan-ctrl hih6130 hp-wmi-sensors @@ -173,8 +174,10 @@ Hardware Monitoring Kernel Drivers menf21bmc mlxreg-fan mp2856 + mp2869 mp2888 mp2891 + mp29502 mp2975 mp2993 mp5023 @@ -211,6 +214,7 @@ Hardware Monitoring Kernel Drivers q54sj108a2 qnap-mcu-hwmon raspberrypi-hwmon + sa67 sbrmi sbtsi_temp sch5627 diff --git a/Documentation/hwmon/isl68137.rst b/Documentation/hwmon/isl68137.rst index 0e71b22047f8..5bc029c98383 100644 --- a/Documentation/hwmon/isl68137.rst +++ b/Documentation/hwmon/isl68137.rst @@ -374,6 +374,26 @@ Supported chips: Publicly available (after August 2020 launch) at the Renesas website + * Renesas RAA228244 + + Prefix: 'raa228244' + + Addresses scanned: - + + Datasheet: + + Provided by Renesas upon request and NDA + + * Renesas RAA228246 + + Prefix: 'raa228246' + + Addresses scanned: - + + Datasheet: + + Provided by Renesas upon request and NDA + * Renesas RAA229001 Prefix: 'raa229001' diff --git a/Documentation/hwmon/lm75.rst b/Documentation/hwmon/lm75.rst index c6a54bbca3c5..908b3a9df06e 100644 --- a/Documentation/hwmon/lm75.rst +++ b/Documentation/hwmon/lm75.rst @@ -121,9 +121,9 @@ Supported chips: https://www.ti.com/product/TMP1075 - * NXP LM75B, P3T1755, PCT2075 + * NXP LM75B, P3T1750, P3T1755, PCT2075 - Prefix: 'lm75b', 'p3t1755', 'pct2075' + Prefix: 'lm75b', 'p3t1750', 'p3t1755', 'pct2075' Addresses scanned: none @@ -131,6 +131,8 @@ Supported chips: https://www.nxp.com/docs/en/data-sheet/LM75B.pdf + https://www.nxp.com/docs/en/data-sheet/P3T1750DP.pdf + https://www.nxp.com/docs/en/data-sheet/P3T1755.pdf https://www.nxp.com/docs/en/data-sheet/PCT2075.pdf diff --git a/Documentation/hwmon/mp2869.rst b/Documentation/hwmon/mp2869.rst new file mode 100644 index 000000000000..2d9d65fc86b6 --- /dev/null +++ b/Documentation/hwmon/mp2869.rst @@ -0,0 +1,175 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver mp2869 +==================== + +Supported chips: + + * MPS mp2869 + + Prefix: 'mp2869' + + * MPS mp29608 + + Prefix: 'mp29608' + + * MPS mp29612 + + Prefix: 'mp29612' + + * MPS mp29816 + + Prefix: 'mp29816' + +Author: + + Wensheng Wang <wenswang@yeah.net> + +Description +----------- + +This driver implements support for Monolithic Power Systems, Inc. (MPS) +MP2869 Dual Loop Digital Multi-phase Controller. + +Device compliant with: + +- PMBus rev 1.3 interface. + +The driver exports the following attributes via the 'sysfs' files +for input voltage: + +**in1_input** + +**in1_label** + +**in1_crit** + +**in1_crit_alarm** + +**in1_lcrit** + +**in1_lcrit_alarm** + +**in1_min** + +**in1_min_alarm** + +The driver provides the following attributes for output voltage: + +**in2_input** + +**in2_label** + +**in2_crit** + +**in2_crit_alarm** + +**in2_lcrit** + +**in2_lcrit_alarm** + +**in3_input** + +**in3_label** + +**in3_crit** + +**in3_crit_alarm** + +**in3_lcrit** + +**in3_lcrit_alarm** + +The driver provides the following attributes for input current: + +**curr1_input** + +**curr1_label** + +**curr2_input** + +**curr2_label** + +The driver provides the following attributes for output current: + +**curr3_input** + +**curr3_label** + +**curr3_crit** + +**curr3_crit_alarm** + +**curr3_max** + +**curr3_max_alarm** + +**curr4_input** + +**curr4_label** + +**curr4_crit** + +**curr4_crit_alarm** + +**curr4_max** + +**curr4_max_alarm** + +The driver provides the following attributes for input power: + +**power1_input** + +**power1_label** + +**power2_input** + +**power2_label** + +The driver provides the following attributes for output power: + +**power3_input** + +**power3_label** + +**power3_input** + +**power3_label** + +**power3_max** + +**power3_max_alarm** + +**power4_input** + +**power4_label** + +**power4_input** + +**power4_label** + +**power4_max** + +**power4_max_alarm** + +The driver provides the following attributes for temperature: + +**temp1_input** + +**temp1_crit** + +**temp1_crit_alarm** + +**temp1_max** + +**temp1_max_alarm** + +**temp2_input** + +**temp2_crit** + +**temp2_crit_alarm** + +**temp2_max** + +**temp2_max_alarm** diff --git a/Documentation/hwmon/mp29502.rst b/Documentation/hwmon/mp29502.rst new file mode 100644 index 000000000000..893e741a6b71 --- /dev/null +++ b/Documentation/hwmon/mp29502.rst @@ -0,0 +1,93 @@ +.. SPDX-License-Identifier: GPL-2.0 + +Kernel driver mp29502 +===================== + +Supported chips: + + * MPS mp29502 + + Prefix: 'mp29502' + +Author: + + Wensheng Wang <wenswang@yeah.net> + +Description +----------- + +This driver implements support for Monolithic Power Systems, Inc. (MPS) +MP29502 Digital Multi-phase Controller. + +Device compliant with: + +- PMBus rev 1.3 interface. + +The driver exports the following attributes via the 'sysfs' files +for input voltage: + +**in1_input** + +**in1_label** + +**in1_crit** + +**in1_crit_alarm** + +The driver provides the following attributes for output voltage: + +**in2_input** + +**in2_label** + +**in2_crit** + +**in2_crit_alarm** + +**in2_lcrit** + +**in2_lcrit_alarm** + +The driver provides the following attributes for input current: + +**curr1_input** + +**curr1_label** + +The driver provides the following attributes for output current: + +**curr2_input** + +**curr2_label** + +**curr2_crit** + +**curr2_crit_alarm** + +**curr2_max** + +**curr2_max_alarm** + +The driver provides the following attributes for input power: + +**power1_input** + +**power1_label** + +The driver provides the following attributes for output power: + +**power2_input** + +**power2_label** + +The driver provides the following attributes for temperature: + +**temp1_input** + +**temp1_crit** + +**temp1_crit_alarm** + +**temp1_max** + +**temp1_max_alarm** diff --git a/Documentation/hwmon/mp5990.rst b/Documentation/hwmon/mp5990.rst index 6f2f0c099d44..7fd536757ff2 100644 --- a/Documentation/hwmon/mp5990.rst +++ b/Documentation/hwmon/mp5990.rst @@ -9,9 +9,13 @@ Supported chips: Prefix: 'mp5990' - * Datasheet + Datasheet: Publicly available at the MPS website: https://www.monolithicpower.com/en/mp5990.html - Publicly available at the MPS website : https://www.monolithicpower.com/en/mp5990.html + * MPS MP5998 + + Prefix: 'mp5998' + + Datasheet: Not publicly available Author: @@ -21,7 +25,7 @@ Description ----------- This driver implements support for Monolithic Power Systems, Inc. (MPS) -MP5990 Hot-Swap Controller. +MP5990 and MP5998 Hot-Swap Controller. Device compliant with: @@ -53,7 +57,7 @@ The driver provides the following attributes for output voltage: **in2_alarm** -The driver provides the following attributes for output current: +The driver provides the following attributes for current: **curr1_input** @@ -63,6 +67,14 @@ The driver provides the following attributes for output current: **curr1_max** +**curr2_input** + +**curr2_label** + +**curr2_max** + +**curr2_max_alarm** + The driver provides the following attributes for input power: **power1_input** @@ -71,6 +83,16 @@ The driver provides the following attributes for input power: **power1_alarm** +The driver provides the following attributes for output power: + +**power2_input** + +**power2_label** + +**power2_max** + +**power2_max_alarm** + The driver provides the following attributes for temperature: **temp1_input** diff --git a/Documentation/hwmon/sa67.rst b/Documentation/hwmon/sa67.rst new file mode 100644 index 000000000000..029c7c169b7f --- /dev/null +++ b/Documentation/hwmon/sa67.rst @@ -0,0 +1,41 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +Kernel driver sa67mcu +===================== + +Supported chips: + + * Kontron sa67mcu + + Prefix: 'sa67mcu' + + Datasheet: not available + +Authors: Michael Walle <mwalle@kernel.org> + +Description +----------- + +The sa67mcu is a board management controller which also exposes a hardware +monitoring controller. + +The controller has two voltage and one temperature sensor. The values are +hold in two 8 bit registers to form one 16 bit value. Reading the lower byte +will also capture the high byte to make the access atomic. The unit of the +volatge sensors are 1mV and the unit of the temperature sensor is 0.1degC. + +Sysfs entries +------------- + +The following attributes are supported. + +======================= ======================================================== +in0_label "VDDIN" +in0_input Measured VDDIN voltage. + +in1_label "VDD_RTC" +in1_input Measured VDD_RTC voltage. + +temp1_input MCU temperature. Roughly the board temperature. +======================= ======================================================== + diff --git a/Documentation/hwmon/sht21.rst b/Documentation/hwmon/sht21.rst index 1bccc8e8aac8..d20e8a460ba6 100644 --- a/Documentation/hwmon/sht21.rst +++ b/Documentation/hwmon/sht21.rst @@ -3,6 +3,16 @@ Kernel driver sht21 Supported chips: + * Sensirion SHT20 + + Prefix: 'sht20' + + Addresses scanned: none + + Datasheet: Publicly available at the Sensirion website + + https://www.sensirion.com/file/datasheet_sht20 + * Sensirion SHT21 Prefix: 'sht21' @@ -13,8 +23,6 @@ Supported chips: https://www.sensirion.com/file/datasheet_sht21 - - * Sensirion SHT25 Prefix: 'sht25' @@ -25,8 +33,6 @@ Supported chips: https://www.sensirion.com/file/datasheet_sht25 - - Author: Urs Fleisch <urs.fleisch@sensirion.com> @@ -47,13 +53,11 @@ in the board setup code. sysfs-Interface --------------- -temp1_input - - temperature input - -humidity1_input - - humidity input -eic - - Electronic Identification Code +=================== ============================================================ +temp1_input Temperature input +humidity1_input Humidity input +eic Electronic Identification Code +=================== ============================================================ Notes ----- diff --git a/Documentation/i2c/busses/i2c-i801.rst b/Documentation/i2c/busses/i2c-i801.rst index 47e8ac5b7099..36c563ad3f06 100644 --- a/Documentation/i2c/busses/i2c-i801.rst +++ b/Documentation/i2c/busses/i2c-i801.rst @@ -50,6 +50,7 @@ Supported adapters: * Intel Birch Stream (SOC) * Intel Arrow Lake (SOC) * Intel Panther Lake (SOC) + * Intel Wildcat Lake (SOC) Datasheets: Publicly available at the Intel website diff --git a/Documentation/kbuild/kconfig-language.rst b/Documentation/kbuild/kconfig-language.rst index a91abb8f6840..abce88f15d7c 100644 --- a/Documentation/kbuild/kconfig-language.rst +++ b/Documentation/kbuild/kconfig-language.rst @@ -232,6 +232,38 @@ applicable everywhere (see syntax). enables the third modular state for all config symbols. At most one symbol may have the "modules" option set. +- transitional attribute: "transitional" + This declares the symbol as transitional, meaning it should be processed + during configuration but omitted from newly written .config files. + Transitional symbols are useful for backward compatibility during config + option migrations - they allow olddefconfig to process existing .config + files while ensuring the old option doesn't appear in new configurations. + + A transitional symbol: + - Has no prompt (is not visible to users in menus) + - Is processed normally during configuration (values are read and used) + - Can be referenced in default expressions of other symbols + - Is not written to new .config files + - Cannot have any other properties (it is a pass-through option) + + Example migration from OLD_NAME to NEW_NAME:: + + config NEW_NAME + bool "New option name" + default OLD_NAME + help + This replaces the old CONFIG_OLD_NAME option. + + config OLD_NAME + bool + transitional + help + Transitional config for OLD_NAME to NEW_NAME migration. + + With this setup, existing .config files with "CONFIG_OLD_NAME=y" will + result in "CONFIG_NEW_NAME=y" being set, while CONFIG_OLD_NAME will be + omitted from newly written .config files. + Menu dependencies ----------------- diff --git a/Documentation/kbuild/reproducible-builds.rst b/Documentation/kbuild/reproducible-builds.rst index f2dcc39044e6..96d208e578cd 100644 --- a/Documentation/kbuild/reproducible-builds.rst +++ b/Documentation/kbuild/reproducible-builds.rst @@ -61,6 +61,9 @@ supported. The Reproducible Builds web site has more information about these `prefix-map options`_. +Some CONFIG options such as `CONFIG_DEBUG_EFI` embed absolute paths in +object files. Such options should be disabled. + Generated files in source packages ---------------------------------- diff --git a/Documentation/mm/damon/design.rst b/Documentation/mm/damon/design.rst index 03f8137256f5..80354f4f42ba 100644 --- a/Documentation/mm/damon/design.rst +++ b/Documentation/mm/damon/design.rst @@ -67,7 +67,7 @@ processes, NUMA nodes, files, and backing memory devices would be supportable. Also, if some architectures or devices support special optimized access check features, those will be easily configurable. -DAMON currently provides below three operation sets. Below two subsections +DAMON currently provides below three operation sets. Below three subsections describe how those work. - vaddr: Monitor virtual address spaces of specific processes @@ -135,6 +135,20 @@ the interference is the responsibility of sysadmins. However, it solves the conflict with the reclaim logic using ``PG_idle`` and ``PG_young`` page flags, as Idle page tracking does. +.. _damon_design_addr_unit: + +Address Unit +------------ + +DAMON core layer uses ``unsinged long`` type for monitoring target address +ranges. In some cases, the address space for a given operations set could be +too large to be handled with the type. ARM (32-bit) with large physical +address extension is an example. For such cases, a per-operations set +parameter called ``address unit`` is provided. It represents the scale factor +that need to be multiplied to the core layer's address for calculating real +address on the given address space. Support of ``address unit`` parameter is +up to each operations set implementation. ``paddr`` is the only operations set +implementation that supports the parameter. .. _damon_core_logic: @@ -689,7 +703,7 @@ DAMOS accounts below statistics for each scheme, from the beginning of the scheme's execution. - ``nr_tried``: Total number of regions that the scheme is tried to be applied. -- ``sz_trtied``: Total size of regions that the scheme is tried to be applied. +- ``sz_tried``: Total size of regions that the scheme is tried to be applied. - ``sz_ops_filter_passed``: Total bytes that passed operations set layer-handled DAMOS filters. - ``nr_applied``: Total number of regions that the scheme is applied. diff --git a/Documentation/mm/damon/maintainer-profile.rst b/Documentation/mm/damon/maintainer-profile.rst index 5cd07905a193..58a3fb3c5762 100644 --- a/Documentation/mm/damon/maintainer-profile.rst +++ b/Documentation/mm/damon/maintainer-profile.rst @@ -89,18 +89,13 @@ the maintainer. Community meetup ---------------- -DAMON community is maintaining two bi-weekly meetup series for community -members who prefer synchronous conversations over mails. +DAMON community has a bi-weekly meetup series for members who prefer +synchronous conversations over mails. It is for discussions on specific topics +between a group of members including the maintainer. The maintainer shares the +available time slots, and attendees should reserve one of those at least 24 +hours before the time slot, by reaching out to the maintainer. -The first one is for any discussion between every community member. No -reservation is needed. - -The seconds one is for discussions on specific topics between restricted -members including the maintainer. The maintainer shares the available time -slots, and attendees should reserve one of those at least 24 hours before the -time slot, by reaching out to the maintainer. - -Schedules and available reservation time slots are available at the Google `doc +Schedules and reservation status are available at the Google `doc <https://docs.google.com/document/d/1v43Kcj3ly4CYqmAkMaZzLiM2GEnWfgdGbZAH3mi2vpM/edit?usp=sharing>`_. There is also a public Google `calendar <https://calendar.google.com/calendar/u/0?cid=ZDIwOTA4YTMxNjc2MDQ3NTIyMmUzYTM5ZmQyM2U4NDA0ZGIwZjBiYmJlZGQxNDM0MmY4ZTRjOTE0NjdhZDRiY0Bncm91cC5jYWxlbmRhci5nb29nbGUuY29t>`_ diff --git a/Documentation/mm/index.rst b/Documentation/mm/index.rst index fb45acba16ac..ba6a8872849b 100644 --- a/Documentation/mm/index.rst +++ b/Documentation/mm/index.rst @@ -20,6 +20,7 @@ see the :doc:`admin guide <../admin-guide/mm/index>`. highmem page_reclaim swap + swap-table page_cache shmfs oom diff --git a/Documentation/mm/swap-table.rst b/Documentation/mm/swap-table.rst new file mode 100644 index 000000000000..da10bb7a0dc3 --- /dev/null +++ b/Documentation/mm/swap-table.rst @@ -0,0 +1,69 @@ +.. SPDX-License-Identifier: GPL-2.0 + +:Author: Chris Li <chrisl@kernel.org>, Kairui Song <kasong@tencent.com> + +========== +Swap Table +========== + +Swap table implements swap cache as a per-cluster swap cache value array. + +Swap Entry +---------- + +A swap entry contains the information required to serve the anonymous page +fault. + +Swap entry is encoded as two parts: swap type and swap offset. + +The swap type indicates which swap device to use. +The swap offset is the offset of the swap file to read the page data from. + +Swap Cache +---------- + +Swap cache is a map to look up folios using swap entry as the key. The result +value can have three possible types depending on which stage of this swap entry +was in. + +1. NULL: This swap entry is not used. + +2. folio: A folio has been allocated and bound to this swap entry. This is + the transient state of swap out or swap in. The folio data can be in + the folio or swap file, or both. + +3. shadow: The shadow contains the working set information of the swapped + out folio. This is the normal state for a swapped out page. + +Swap Table Internals +-------------------- + +The previous swap cache is implemented by XArray. The XArray is a tree +structure. Each lookup will go through multiple nodes. Can we do better? + +Notice that most of the time when we look up the swap cache, we are either +in a swap in or swap out path. We should already have the swap cluster, +which contains the swap entry. + +If we have a per-cluster array to store swap cache value in the cluster. +Swap cache lookup within the cluster can be a very simple array lookup. + +We give such a per-cluster swap cache value array a name: the swap table. + +A swap table is an array of pointers. Each pointer is the same size as a +PTE. The size of a swap table for one swap cluster typically matches a PTE +page table, which is one page on modern 64-bit systems. + +With swap table, swap cache lookup can achieve great locality, simpler, +and faster. + +Locking +------- + +Swap table modification requires taking the cluster lock. If a folio +is being added to or removed from the swap table, the folio must be +locked prior to the cluster lock. After adding or removing is done, the +folio shall be unlocked. + +Swap table lookup is protected by RCU and atomic read. If the lookup +returns a folio, the user must lock the folio before use. diff --git a/Documentation/netlink/genetlink-legacy.yaml b/Documentation/netlink/genetlink-legacy.yaml index b29d62eefa16..66fb8653a344 100644 --- a/Documentation/netlink/genetlink-legacy.yaml +++ b/Documentation/netlink/genetlink-legacy.yaml @@ -154,7 +154,7 @@ properties: Optional format indicator that is intended only for choosing the right formatting mechanism when displaying values of this type. - enum: [ hex, mac, fddi, ipv4, ipv6, uuid ] + enum: [ hex, mac, fddi, ipv4, ipv6, ipv4-or-v6, uuid ] struct: description: Name of the nested struct type. type: string diff --git a/Documentation/netlink/specs/conntrack.yaml b/Documentation/netlink/specs/conntrack.yaml index c6832633ab7b..bef528633b17 100644 --- a/Documentation/netlink/specs/conntrack.yaml +++ b/Documentation/netlink/specs/conntrack.yaml @@ -4,7 +4,7 @@ name: conntrack protocol: netlink-raw protonum: 12 -doc: +doc: >- Netfilter connection tracking subsystem over nfnetlink definitions: @@ -575,8 +575,8 @@ operations: - nat-dst - timeout - mark - - counter-orig - - counter-reply + - counters-orig + - counters-reply - use - id - nat-dst @@ -591,7 +591,6 @@ operations: request: value: 0x101 attributes: - - nfgen-family - mark - filter - status @@ -608,8 +607,8 @@ operations: - nat-dst - timeout - mark - - counter-orig - - counter-reply + - counters-orig + - counters-reply - use - id - nat-dst diff --git a/Documentation/netlink/specs/devlink.yaml b/Documentation/netlink/specs/devlink.yaml index bb87111d5e16..3db59c965869 100644 --- a/Documentation/netlink/specs/devlink.yaml +++ b/Documentation/netlink/specs/devlink.yaml @@ -853,6 +853,10 @@ attribute-sets: type: nest multi-attr: true nested-attributes: dl-rate-tc-bws + - + name: health-reporter-burst-period + type: u64 + doc: Time (in msec) for recoveries before starting the grace period. - name: dl-dev-stats subset-of: devlink @@ -1216,6 +1220,8 @@ attribute-sets: name: health-reporter-dump-ts-ns - name: health-reporter-auto-dump + - + name: health-reporter-burst-period - name: dl-attr-stats @@ -1961,6 +1967,7 @@ operations: - health-reporter-graceful-period - health-reporter-auto-recover - health-reporter-auto-dump + - health-reporter-burst-period - name: health-reporter-recover diff --git a/Documentation/netlink/specs/dpll.yaml b/Documentation/netlink/specs/dpll.yaml index 5decee61a2c4..cafb4ec20447 100644 --- a/Documentation/netlink/specs/dpll.yaml +++ b/Documentation/netlink/specs/dpll.yaml @@ -315,6 +315,10 @@ attribute-sets: If enabled, dpll device shall monitor and notify all currently available inputs for changes of their phase offset against the dpll device. + - + name: phase-offset-avg-factor + type: u32 + doc: Averaging factor applied to calculation of reported phase offset. - name: pin enum-name: dpll_a_pin @@ -523,6 +527,7 @@ operations: - clock-id - type - phase-offset-monitor + - phase-offset-avg-factor dump: reply: *dev-attrs @@ -540,6 +545,7 @@ operations: attributes: - id - phase-offset-monitor + - phase-offset-avg-factor - name: device-create-ntf doc: Notification about device appearing diff --git a/Documentation/netlink/specs/ethtool.yaml b/Documentation/netlink/specs/ethtool.yaml index 1bc1bd7d33c2..6a0fb1974513 100644 --- a/Documentation/netlink/specs/ethtool.yaml +++ b/Documentation/netlink/specs/ethtool.yaml @@ -205,6 +205,9 @@ definitions: - name: gtp-teid - + name: ip6-fl + doc: IPv6 Flow Label + - name: discard value: 31 @@ -1217,6 +1220,30 @@ attribute-sets: type: nest nested-attributes: tunnel-udp - + name: fec-hist + attr-cnt-name: --ethtool-a-fec-hist-cnt + attributes: + - + name: pad + type: pad + - + name: bin-low + type: u32 + doc: Low bound of FEC bin (inclusive) + - + name: bin-high + type: u32 + doc: High bound of FEC bin (inclusive) + - + name: bin-val + type: uint + doc: Error count in the bin (optional if per-lane values exist) + - + name: bin-val-per-lane + type: binary + sub-type: u64 + doc: An array of per-lane error counters in the bin (optional) + - name: fec-stat attr-cnt-name: __ethtool-a-fec-stat-cnt attributes: @@ -1239,6 +1266,11 @@ attribute-sets: name: corr-bits type: binary sub-type: u64 + - + name: hist + type: nest + multi-attr: True + nested-attributes: fec-hist - name: fec attr-cnt-name: __ethtool-a-fec-cnt diff --git a/Documentation/netlink/specs/fou.yaml b/Documentation/netlink/specs/fou.yaml index 57735726262e..8e7974ec453f 100644 --- a/Documentation/netlink/specs/fou.yaml +++ b/Documentation/netlink/specs/fou.yaml @@ -52,7 +52,7 @@ attribute-sets: name: local-v6 type: binary checks: - min-len: 16 + exact-len: 16 - name: peer-v4 type: u32 @@ -60,7 +60,7 @@ attribute-sets: name: peer-v6 type: binary checks: - min-len: 16 + exact-len: 16 - name: peer-port type: u16 diff --git a/Documentation/netlink/specs/index.rst b/Documentation/netlink/specs/index.rst new file mode 100644 index 000000000000..7f7cf4a096f2 --- /dev/null +++ b/Documentation/netlink/specs/index.rst @@ -0,0 +1,13 @@ +.. SPDX-License-Identifier: GPL-2.0 + +.. _specs: + +============================= +Netlink Family Specifications +============================= + +.. toctree:: + :maxdepth: 1 + :glob: + + * diff --git a/Documentation/netlink/specs/mptcp_pm.yaml b/Documentation/netlink/specs/mptcp_pm.yaml index 02f1ddcfbf1c..ba30a40b9dbf 100644 --- a/Documentation/netlink/specs/mptcp_pm.yaml +++ b/Documentation/netlink/specs/mptcp_pm.yaml @@ -28,13 +28,13 @@ definitions: traffic-patterns it can take a long time until the MPTCP_EVENT_ESTABLISHED is sent. Attributes: token, family, saddr4 | saddr6, daddr4 | daddr6, sport, - dport, server-side. + dport, [server-side], [flags]. - name: established doc: >- A MPTCP connection is established (can start new subflows). Attributes: token, family, saddr4 | saddr6, daddr4 | daddr6, sport, - dport, server-side. + dport, [server-side], [flags]. - name: closed doc: >- @@ -256,7 +256,7 @@ attribute-sets: type: u32 - name: if-idx - type: u32 + type: s32 - name: reset-reason type: u32 @@ -266,6 +266,7 @@ attribute-sets: - name: server-side type: u8 + doc: "Deprecated: use 'flags'" operations: list: diff --git a/Documentation/netlink/specs/netdev.yaml b/Documentation/netlink/specs/netdev.yaml index c035dc0f64fd..e00d3fa1c152 100644 --- a/Documentation/netlink/specs/netdev.yaml +++ b/Documentation/netlink/specs/netdev.yaml @@ -2,7 +2,7 @@ --- name: netdev -doc: +doc: >- netdev configuration over generic netlink. definitions: @@ -13,33 +13,33 @@ definitions: entries: - name: basic - doc: + doc: >- XDP features set supported by all drivers (XDP_ABORTED, XDP_DROP, XDP_PASS, XDP_TX) - name: redirect - doc: + doc: >- The netdev supports XDP_REDIRECT - name: ndo-xmit - doc: + doc: >- This feature informs if netdev implements ndo_xdp_xmit callback. - name: xsk-zerocopy - doc: + doc: >- This feature informs if netdev supports AF_XDP in zero copy mode. - name: hw-offload - doc: + doc: >- This feature informs if netdev supports XDP hw offloading. - name: rx-sg - doc: + doc: >- This feature informs if netdev implements non-linear XDP buffer support in the driver napi callback. - name: ndo-xmit-sg - doc: + doc: >- This feature informs if netdev implements non-linear XDP buffer support in ndo_xdp_xmit callback. - @@ -67,15 +67,15 @@ definitions: entries: - name: tx-timestamp - doc: + doc: >- HW timestamping egress packets is supported by the driver. - name: tx-checksum - doc: + doc: >- L3 checksum HW offload is supported by the driver. - name: tx-launch-time-fifo - doc: + doc: >- Launch time HW offload is supported by the driver. - name: queue-type diff --git a/Documentation/netlink/specs/nftables.yaml b/Documentation/netlink/specs/nftables.yaml index 2ee10d92d644..cce88819ba71 100644 --- a/Documentation/netlink/specs/nftables.yaml +++ b/Documentation/netlink/specs/nftables.yaml @@ -4,7 +4,7 @@ name: nftables protocol: netlink-raw protonum: 12 -doc: +doc: >- Netfilter nftables configuration over netlink. definitions: diff --git a/Documentation/netlink/specs/nl80211.yaml b/Documentation/netlink/specs/nl80211.yaml index 610fdd5e000e..802097128bda 100644 --- a/Documentation/netlink/specs/nl80211.yaml +++ b/Documentation/netlink/specs/nl80211.yaml @@ -3,7 +3,7 @@ name: nl80211 protocol: genetlink-legacy -doc: +doc: >- Netlink API for 802.11 wireless devices definitions: diff --git a/Documentation/netlink/specs/ovs_datapath.yaml b/Documentation/netlink/specs/ovs_datapath.yaml index 0c0abf3f9f05..f7b3671991e6 100644 --- a/Documentation/netlink/specs/ovs_datapath.yaml +++ b/Documentation/netlink/specs/ovs_datapath.yaml @@ -5,7 +5,7 @@ version: 2 protocol: genetlink-legacy uapi-header: linux/openvswitch.h -doc: +doc: >- OVS datapath configuration over generic netlink. definitions: diff --git a/Documentation/netlink/specs/ovs_flow.yaml b/Documentation/netlink/specs/ovs_flow.yaml index 2dac9c8add57..951837b72e1d 100644 --- a/Documentation/netlink/specs/ovs_flow.yaml +++ b/Documentation/netlink/specs/ovs_flow.yaml @@ -5,7 +5,7 @@ version: 1 protocol: genetlink-legacy uapi-header: linux/openvswitch.h -doc: +doc: >- OVS flow configuration over generic netlink. definitions: diff --git a/Documentation/netlink/specs/ovs_vport.yaml b/Documentation/netlink/specs/ovs_vport.yaml index da47e65fd574..fa975f8821b6 100644 --- a/Documentation/netlink/specs/ovs_vport.yaml +++ b/Documentation/netlink/specs/ovs_vport.yaml @@ -5,7 +5,7 @@ version: 2 protocol: genetlink-legacy uapi-header: linux/openvswitch.h -doc: +doc: >- OVS vport configuration over generic netlink. definitions: diff --git a/Documentation/netlink/specs/psp.yaml b/Documentation/netlink/specs/psp.yaml new file mode 100644 index 000000000000..944429e5c9a8 --- /dev/null +++ b/Documentation/netlink/specs/psp.yaml @@ -0,0 +1,187 @@ +# SPDX-License-Identifier: ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) +--- +name: psp + +doc: + PSP Security Protocol Generic Netlink family. + +definitions: + - + type: enum + name: version + entries: [hdr0-aes-gcm-128, hdr0-aes-gcm-256, + hdr0-aes-gmac-128, hdr0-aes-gmac-256] + +attribute-sets: + - + name: dev + attributes: + - + name: id + doc: PSP device ID. + type: u32 + checks: + min: 1 + - + name: ifindex + doc: ifindex of the main netdevice linked to the PSP device. + type: u32 + - + name: psp-versions-cap + doc: Bitmask of PSP versions supported by the device. + type: u32 + enum: version + enum-as-flags: true + - + name: psp-versions-ena + doc: Bitmask of currently enabled (accepted on Rx) PSP versions. + type: u32 + enum: version + enum-as-flags: true + - + name: assoc + attributes: + - + name: dev-id + doc: PSP device ID. + type: u32 + checks: + min: 1 + - + name: version + doc: | + PSP versions (AEAD and protocol version) used by this association, + dictates the size of the key. + type: u32 + enum: version + - + name: rx-key + type: nest + nested-attributes: keys + - + name: tx-key + type: nest + nested-attributes: keys + - + name: sock-fd + doc: Sockets which should be bound to the association immediately. + type: u32 + - + name: keys + attributes: + - + name: key + type: binary + - + name: spi + doc: Security Parameters Index (SPI) of the association. + type: u32 + +operations: + list: + - + name: dev-get + doc: Get / dump information about PSP capable devices on the system. + attribute-set: dev + do: + request: + attributes: + - id + reply: &dev-all + attributes: + - id + - ifindex + - psp-versions-cap + - psp-versions-ena + pre: psp-device-get-locked + post: psp-device-unlock + dump: + reply: *dev-all + - + name: dev-add-ntf + doc: Notification about device appearing. + notify: dev-get + mcgrp: mgmt + - + name: dev-del-ntf + doc: Notification about device disappearing. + notify: dev-get + mcgrp: mgmt + - + name: dev-set + doc: Set the configuration of a PSP device. + attribute-set: dev + do: + request: + attributes: + - id + - psp-versions-ena + reply: + attributes: [] + pre: psp-device-get-locked + post: psp-device-unlock + - + name: dev-change-ntf + doc: Notification about device configuration being changed. + notify: dev-get + mcgrp: mgmt + + - + name: key-rotate + doc: Rotate the device key. + attribute-set: dev + do: + request: + attributes: + - id + reply: + attributes: + - id + pre: psp-device-get-locked + post: psp-device-unlock + - + name: key-rotate-ntf + doc: Notification about device key getting rotated. + notify: key-rotate + mcgrp: use + + - + name: rx-assoc + doc: Allocate a new Rx key + SPI pair, associate it with a socket. + attribute-set: assoc + do: + request: + attributes: + - dev-id + - version + - sock-fd + reply: + attributes: + - dev-id + - rx-key + pre: psp-assoc-device-get-locked + post: psp-device-unlock + - + name: tx-assoc + doc: Add a PSP Tx association. + attribute-set: assoc + do: + request: + attributes: + - dev-id + - version + - tx-key + - sock-fd + reply: + attributes: [] + pre: psp-assoc-device-get-locked + post: psp-device-unlock + +mcast-groups: + list: + - + name: mgmt + - + name: use + +... diff --git a/Documentation/netlink/specs/rt-addr.yaml b/Documentation/netlink/specs/rt-addr.yaml index bafe3bfeabfb..3a582eac1629 100644 --- a/Documentation/netlink/specs/rt-addr.yaml +++ b/Documentation/netlink/specs/rt-addr.yaml @@ -5,7 +5,7 @@ protocol: netlink-raw uapi-header: linux/rtnetlink.h protonum: 0 -doc: +doc: >- Address configuration over rtnetlink. definitions: diff --git a/Documentation/netlink/specs/rt-link.yaml b/Documentation/netlink/specs/rt-link.yaml index 210394c188a3..2a23e9699c0b 100644 --- a/Documentation/netlink/specs/rt-link.yaml +++ b/Documentation/netlink/specs/rt-link.yaml @@ -5,7 +5,7 @@ protocol: netlink-raw uapi-header: linux/rtnetlink.h protonum: 0 -doc: +doc: >- Link configuration over rtnetlink. definitions: @@ -1057,6 +1057,12 @@ attribute-sets: - name: netns-immutable type: u8 + - + name: headroom + type: u16 + - + name: tailroom + type: u16 - name: prop-list-link-attrs subset-of: link-attrs diff --git a/Documentation/netlink/specs/rt-neigh.yaml b/Documentation/netlink/specs/rt-neigh.yaml index 30a9ee16f128..2f568a6231c9 100644 --- a/Documentation/netlink/specs/rt-neigh.yaml +++ b/Documentation/netlink/specs/rt-neigh.yaml @@ -5,7 +5,7 @@ protocol: netlink-raw uapi-header: linux/rtnetlink.h protonum: 0 -doc: +doc: >- IP neighbour management over rtnetlink. definitions: diff --git a/Documentation/netlink/specs/rt-route.yaml b/Documentation/netlink/specs/rt-route.yaml index 5b514ddeff1d..1ecb3fadc067 100644 --- a/Documentation/netlink/specs/rt-route.yaml +++ b/Documentation/netlink/specs/rt-route.yaml @@ -5,7 +5,7 @@ protocol: netlink-raw uapi-header: linux/rtnetlink.h protonum: 0 -doc: +doc: >- Route configuration over rtnetlink. definitions: diff --git a/Documentation/netlink/specs/rt-rule.yaml b/Documentation/netlink/specs/rt-rule.yaml index 46b1d426e7e8..bebee452a950 100644 --- a/Documentation/netlink/specs/rt-rule.yaml +++ b/Documentation/netlink/specs/rt-rule.yaml @@ -5,7 +5,7 @@ protocol: netlink-raw uapi-header: linux/fib_rules.h protonum: 0 -doc: +doc: >- FIB rule management over rtnetlink. definitions: diff --git a/Documentation/netlink/specs/tc.yaml b/Documentation/netlink/specs/tc.yaml index b1afc7ab3539..b398f7a46dae 100644 --- a/Documentation/netlink/specs/tc.yaml +++ b/Documentation/netlink/specs/tc.yaml @@ -5,7 +5,7 @@ protocol: netlink-raw uapi-header: linux/pkt_cls.h protonum: 0 -doc: +doc: >- Netlink raw family for tc qdisc, chain, class and filter configuration over rtnetlink. diff --git a/Documentation/netlink/specs/team.yaml b/Documentation/netlink/specs/team.yaml index cf02d47d12a4..83a275b44c82 100644 --- a/Documentation/netlink/specs/team.yaml +++ b/Documentation/netlink/specs/team.yaml @@ -25,8 +25,9 @@ definitions: attribute-sets: - name: team - doc: - The team nested layout of get/set msg looks like + doc: | + The team nested layout of get/set msg looks like:: + [TEAM_ATTR_LIST_OPTION] [TEAM_ATTR_ITEM_OPTION] [TEAM_ATTR_OPTION_*], ... @@ -39,6 +40,7 @@ attribute-sets: [TEAM_ATTR_ITEM_PORT] [TEAM_ATTR_PORT_*], ... ... + name-prefix: team-attr- attributes: - diff --git a/Documentation/networking/bonding.rst b/Documentation/networking/bonding.rst index f8f5766703d4..e700bf1d095c 100644 --- a/Documentation/networking/bonding.rst +++ b/Documentation/networking/bonding.rst @@ -193,6 +193,15 @@ ad_actor_sys_prio This parameter has effect only in 802.3ad mode and is available through SysFs interface. +actor_port_prio + + In an AD system, this specifies the port priority. The allowed range + is 1 - 65535. If the value is not specified, it takes 255 as the + default value. + + This parameter has effect only in 802.3ad mode and is available through + netlink interface. + ad_actor_system In an AD system, this specifies the mac-address for the actor in @@ -241,10 +250,18 @@ ad_select ports (slaves). Reselection occurs as described under the "bandwidth" setting, above. - The bandwidth and count selection policies permit failover of - 802.3ad aggregations when partial failure of the active aggregator - occurs. This keeps the aggregator with the highest availability - (either in bandwidth or in number of ports) active at all times. + actor_port_prio or 3 + + The active aggregator is chosen by the highest total sum of + actor port priorities across its active ports. Note this + priority is actor_port_prio, not per port prio, which is + used for primary reselect. + + The bandwidth, count and actor_port_prio selection policies permit + failover of 802.3ad aggregations when partial failure of the active + aggregator occurs. This keeps the aggregator with the highest + availability (either in bandwidth, number of ports, or total value + of port priorities) active at all times. This option was added in bonding version 3.4.0. @@ -582,10 +599,8 @@ miimon This determines how often the link state of each slave is inspected for link failures. A value of zero disables MII link monitoring. A value of 100 is a good starting point. - The use_carrier option, below, affects how the link state is - determined. See the High Availability section for additional - information. The default value is 100 if arp_interval is not - set. + + The default value is 100 if arp_interval is not set. min_links @@ -896,25 +911,14 @@ updelay use_carrier - Specifies whether or not miimon should use MII or ETHTOOL - ioctls vs. netif_carrier_ok() to determine the link - status. The MII or ETHTOOL ioctls are less efficient and - utilize a deprecated calling sequence within the kernel. The - netif_carrier_ok() relies on the device driver to maintain its - state with netif_carrier_on/off; at this writing, most, but - not all, device drivers support this facility. - - If bonding insists that the link is up when it should not be, - it may be that your network device driver does not support - netif_carrier_on/off. The default state for netif_carrier is - "carrier on," so if a driver does not support netif_carrier, - it will appear as if the link is always up. In this case, - setting use_carrier to 0 will cause bonding to revert to the - MII / ETHTOOL ioctl method to determine the link state. - - A value of 1 enables the use of netif_carrier_ok(), a value of - 0 will use the deprecated MII / ETHTOOL ioctls. The default - value is 1. + Obsolete option that previously selected between MII / + ETHTOOL ioctls and netif_carrier_ok() to determine link + state. + + All link state checks are now done with netif_carrier_ok(). + + For backwards compatibility, this option's value may be inspected + or set. The only valid setting is 1. xmit_hash_policy @@ -2036,22 +2040,8 @@ depending upon the device driver to maintain its carrier state, by querying the device's MII registers, or by making an ethtool query to the device. -If the use_carrier module parameter is 1 (the default value), -then the MII monitor will rely on the driver for carrier state -information (via the netif_carrier subsystem). As explained in the -use_carrier parameter information, above, if the MII monitor fails to -detect carrier loss on the device (e.g., when the cable is physically -disconnected), it may be that the driver does not support -netif_carrier. - -If use_carrier is 0, then the MII monitor will first query the -device's (via ioctl) MII registers and check the link state. If that -request fails (not just that it returns carrier down), then the MII -monitor will make an ethtool ETHTOOL_GLINK request to attempt to obtain -the same information. If both methods fail (i.e., the driver either -does not support or had some error in processing both the MII register -and ethtool requests), then the MII monitor will assume the link is -up. +The MII monitor relies on the driver for carrier state information (via +the netif_carrier subsystem). 8. Potential Sources of Trouble =============================== @@ -2135,34 +2125,6 @@ This will load tg3 and e1000 modules before loading the bonding one. Full documentation on this can be found in the modprobe.d and modprobe manual pages. -8.3. Painfully Slow Or No Failed Link Detection By Miimon ---------------------------------------------------------- - -By default, bonding enables the use_carrier option, which -instructs bonding to trust the driver to maintain carrier state. - -As discussed in the options section, above, some drivers do -not support the netif_carrier_on/_off link state tracking system. -With use_carrier enabled, bonding will always see these links as up, -regardless of their actual state. - -Additionally, other drivers do support netif_carrier, but do -not maintain it in real time, e.g., only polling the link state at -some fixed interval. In this case, miimon will detect failures, but -only after some long period of time has expired. If it appears that -miimon is very slow in detecting link failures, try specifying -use_carrier=0 to see if that improves the failure detection time. If -it does, then it may be that the driver checks the carrier state at a -fixed interval, but does not cache the MII register values (so the -use_carrier=0 method of querying the registers directly works). If -use_carrier=0 does not improve the failover, then the driver may cache -the registers, or the problem may be elsewhere. - -Also, remember that miimon only checks for the device's -carrier state. It has no way to determine the state of devices on or -beyond other ports of a switch, or if a switch is refusing to pass -traffic while still maintaining carrier on. - 9. SNMP agents =============== diff --git a/Documentation/networking/can.rst b/Documentation/networking/can.rst index bc1b585355f7..7650c4b5be5f 100644 --- a/Documentation/networking/can.rst +++ b/Documentation/networking/can.rst @@ -742,7 +742,7 @@ The broadcast manager sends responses to user space in the same form: struct timeval ival1, ival2; /* count and subsequent interval */ canid_t can_id; /* unique can_id for task */ __u32 nframes; /* number of can_frames following */ - struct can_frame frames[0]; + struct can_frame frames[]; }; The aligned payload 'frames' uses the same basic CAN frame structure defined diff --git a/Documentation/networking/device_drivers/ethernet/index.rst b/Documentation/networking/device_drivers/ethernet/index.rst index 40ac552641a3..0b0a3eef6aae 100644 --- a/Documentation/networking/device_drivers/ethernet/index.rst +++ b/Documentation/networking/device_drivers/ethernet/index.rst @@ -50,6 +50,7 @@ Contents: neterion/s2io netronome/nfp pensando/ionic + qualcomm/ppe/ppe smsc/smc9 stmicro/stmmac ti/cpsw diff --git a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst index 754c81436408..cc498895f92e 100644 --- a/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst +++ b/Documentation/networking/device_drivers/ethernet/mellanox/mlx5/counters.rst @@ -1348,7 +1348,7 @@ Device Counters is in a congested state. If pci_bw_inbound_high == pci_bw_inbound_low then the device is not congested. If pci_bw_inbound_high > pci_bw_inbound_low then the device is congested. - - Tnformative + - Informative * - `pci_bw_inbound_low` - The number of times the device crossed the low inbound PCIe bandwidth @@ -1373,3 +1373,8 @@ Device Counters If pci_bw_outbound_high == pci_bw_outbound_low then the device is not congested. If pci_bw_outbound_high > pci_bw_outbound_low then the device is congested. - Informative + + * - `pci_bw_stale_event` + - The number of times the device fired a PCIe congestion event but on query + there was no change in state. + - Informative diff --git a/Documentation/networking/device_drivers/ethernet/meta/fbnic.rst b/Documentation/networking/device_drivers/ethernet/meta/fbnic.rst index afb8353daefd..1e82f90d9ad2 100644 --- a/Documentation/networking/device_drivers/ethernet/meta/fbnic.rst +++ b/Documentation/networking/device_drivers/ethernet/meta/fbnic.rst @@ -69,6 +69,25 @@ On host boot the latest UEFI driver is always used, no explicit activation is required. Firmware activation is required to run new control firmware. cmrt firmware can only be activated by power cycling the NIC. +Health reporters +---------------- + +fw reporter +~~~~~~~~~~~ + +The ``fw`` health reporter tracks FW crashes. Dumping the reporter will +show the core dump of the most recent FW crash, and if no FW crash has +happened since power cycle - a snapshot of the FW memory. Diagnose callback +shows FW uptime based on the most recently received heartbeat message +(the crashes are detected by checking if uptime goes down). + +otp reporter +~~~~~~~~~~~~ + +OTP memory ("fuses") are used for secure boot and anti-rollback +protection. The OTP memory is ECC protected, ECC errors indicate +either manufacturing defect or part deteriorating with age. + Statistics ---------- @@ -160,3 +179,14 @@ behavior and potential performance bottlenecks. credit exhaustion - ``pcie_ob_rd_no_np_cred``: Read requests dropped due to non-posted credit exhaustion + +XDP Length Error: +~~~~~~~~~~~~~~~~~ + +For XDP programs without frags support, fbnic tries to make sure that MTU fits +into a single buffer. If an oversized frame is received and gets fragmented, +it is dropped and the following netlink counters are updated + + - ``rx-length``: number of frames dropped due to lack of fragmentation + support in the attached XDP program + - ``rx-errors``: total number of packets with errors received on the interface diff --git a/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst b/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst new file mode 100644 index 000000000000..4ab299a28969 --- /dev/null +++ b/Documentation/networking/device_drivers/ethernet/qualcomm/ppe/ppe.rst @@ -0,0 +1,194 @@ +.. SPDX-License-Identifier: GPL-2.0 + +=============================================== +PPE Ethernet Driver for Qualcomm IPQ SoC Family +=============================================== + +Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. + +Author: Lei Wei <quic_leiwei@quicinc.com> + + +Contents +======== + +- `PPE Overview`_ +- `PPE Driver Overview`_ +- `PPE Driver Supported SoCs`_ +- `Enabling the Driver`_ +- `Debugging`_ + + +PPE Overview +============ + +IPQ (Qualcomm Internet Processor) SoC (System-on-Chip) series is Qualcomm's series of +networking SoC for Wi-Fi access points. The PPE (Packet Process Engine) is the Ethernet +packet process engine in the IPQ SoC. + +Below is a simplified hardware diagram of IPQ9574 SoC which includes the PPE engine and +other blocks which are in the SoC but outside the PPE engine. These blocks work together +to enable the Ethernet for the IPQ SoC:: + + +------+ +------+ +------+ +------+ +------+ +------+ start +-------+ + |netdev| |netdev| |netdev| |netdev| |netdev| |netdev|<------|PHYLINK| + +------+ +------+ +------+ +------+ +------+ +------+ stop +-+-+-+-+ + | | | ^ + +-------+ +-------------------------+--------+----------------------+ | | | + | GCC | | | EDMA | | | | | + +---+---+ | PPE +---+----+ | | | | + | clk | | | | | | + +-------->| +-----------------------+------+-----+---------------+ | | | | + | | Switch Core |Port0 | |Port7(EIP FIFO)| | | | | + | | +---+--+ +------+--------+ | | | | + | | | | | | | | | + +-------+ | | +------+---------------+----+ | | | | | + |CMN PLL| | | +---+ +---+ +----+ | +--------+ | | | | | | + +---+---+ | | |BM | |QM | |SCH | | | L2/L3 | ....... | | | | | | + | | | | +---+ +---+ +----+ | +--------+ | | | | | | + | | | | +------+--------------------+ | | | | | + | | | | | | | | | | + | v | | +-----+-+-----+-+-----+-+-+---+--+-----+-+-----+ | | | | | + | +------+ | | |Port1| |Port2| |Port3| |Port4| |Port5| |Port6| | | | | | + | |NSSCC | | | +-----+ +-----+ +-----+ +-----+ +-----+ +-----+ | | mac| | | + | +-+-+--+ | | |MAC0 | |MAC1 | |MAC2 | |MAC3 | |MAC4 | |MAC5 | | |<---+ | | + | ^ | |clk | | +-----+-+-----+-+-----+-+-----+--+-----+-+-----+ | | ops | | + | | | +------>| +----|------|-------|-------|---------|--------|-----+ | | | + | | | +---------------------------------------------------------+ | | + | | | | | | | | | | | + | | | MII clk | QSGMII USXGMII USXGMII | | + | | +--------------->| | | | | | | | + | | +-------------------------+ +---------+ +---------+ | | + | |125/312.5MHz clk| (PCS0) | | (PCS1) | | (PCS2) | pcs ops | | + | +----------------+ UNIPHY0 | | UNIPHY1 | | UNIPHY2 |<--------+ | + +----------------->| | | | | | | + | 31.25MHz ref clk +-------------------------+ +---------+ +---------+ | + | | | | | | | | + | +-----------------------------------------------------+ | + |25/50MHz ref clk| +-------------------------+ +------+ +------+ | link | + +--------------->| | QUAD PHY | | PHY4 | | PHY5 | |---------+ + | +-------------------------+ +------+ +------+ | change + | | + | MDIO bus | + +-----------------------------------------------------+ + +The CMN (Common) PLL, NSSCC (Networking Sub System Clock Controller) and GCC (Global +Clock Controller) blocks are in the SoC and act as clock providers. + +The UNIPHY block is in the SoC and provides the PCS (Physical Coding Sublayer) and +XPCS (10-Gigabit Physical Coding Sublayer) functions to support different interface +modes between the PPE MAC and the external PHY. + +This documentation focuses on the descriptions of PPE engine and the PPE driver. + +The Ethernet functionality in the PPE (Packet Process Engine) is comprised of three +components: the switch core, port wrapper and Ethernet DMA. + +The Switch core in the IPQ9574 PPE has maximum of 6 front panel ports and two FIFO +interfaces. One of the two FIFO interfaces is used for Ethernet port to host CPU +communication using Ethernet DMA. The other one is used to communicate to the EIP +engine which is used for IPsec offload. On the IPQ9574, the PPE includes 6 GMAC/XGMACs +that can be connected with external Ethernet PHY. Switch core also includes BM (Buffer +Management), QM (Queue Management) and SCH (Scheduler) modules for supporting the +packet processing. + +The port wrapper provides connections from the 6 GMAC/XGMACS to UNIPHY (PCS) supporting +various modes such as SGMII/QSGMII/PSGMII/USXGMII/10G-BASER. There are 3 UNIPHY (PCS) +instances supported on the IPQ9574. + +Ethernet DMA is used to transmit and receive packets between the Ethernet subsystem +and ARM host CPU. + +The following lists the main blocks in the PPE engine which will be driven by this +PPE driver: + +- BM + BM is the hardware buffer manager for the PPE switch ports. +- QM + Queue Manager for managing the egress hardware queues of the PPE switch ports. +- SCH + The scheduler which manages the hardware traffic scheduling for the PPE switch ports. +- L2 + The L2 block performs the packet bridging in the switch core. The bridge domain is + represented by the VSI (Virtual Switch Instance) domain in PPE. FDB learning can be + enabled based on the VSI domain and bridge forwarding occurs within the VSI domain. +- MAC + The PPE in the IPQ9574 supports up to six MACs (MAC0 to MAC5) which are corresponding + to six switch ports (port1 to port6). The MAC block is connected with external PHY + through the UNIPHY PCS block. Each MAC block includes the GMAC and XGMAC blocks and + the switch port can select to use GMAC or XMAC through a MUX selection according to + the external PHY's capability. +- EDMA (Ethernet DMA) + The Ethernet DMA is used to transmit and receive Ethernet packets between the PPE + ports and the ARM cores. + +The received packet on a PPE MAC port can be forwarded to another PPE MAC port. It can +be also forwarded to internal switch port0 so that the packet can be delivered to the +ARM cores using the Ethernet DMA (EDMA) engine. The Ethernet DMA driver will deliver the +packet to the corresponding 'netdevice' interface. + +The software instantiations of the PPE MAC (netdevice), PCS and external PHYs interact +with the Linux PHYLINK framework to manage the connectivity between the PPE ports and +the connected PHYs, and the port link states. This is also illustrated in above diagram. + + +PPE Driver Overview +=================== +PPE driver is Ethernet driver for the Qualcomm IPQ SoC. It is a single platform driver +which includes the PPE part and Ethernet DMA part. The PPE part initializes and drives the +various blocks in PPE switch core such as BM/QM/L2 blocks and the PPE MACs. The EDMA part +drives the Ethernet DMA for packet transfer between PPE ports and ARM cores, and enables +the netdevice driver for the PPE ports. + +The PPE driver files in drivers/net/ethernet/qualcomm/ppe/ are listed as below: + +- Makefile +- ppe.c +- ppe.h +- ppe_config.c +- ppe_config.h +- ppe_debugfs.c +- ppe_debugfs.h +- ppe_regs.h + +The ppe.c file contains the main PPE platform driver and undertakes the initialization of +PPE switch core blocks such as QM, BM and L2. The configuration APIs for these hardware +blocks are provided in the ppe_config.c file. + +The ppe.h defines the PPE device data structure which will be used by PPE driver functions. + +The ppe_debugfs.c enables the PPE statistics counters such as PPE port Rx and Tx counters, +CPU code counters and queue counters. + + +PPE Driver Supported SoCs +========================= + +The PPE driver supports the following IPQ SoC: + +- IPQ9574 + + +Enabling the Driver +=================== + +The driver is located in the menu structure at:: + + -> Device Drivers + -> Network device support (NETDEVICES [=y]) + -> Ethernet driver support + -> Qualcomm devices + -> Qualcomm Technologies, Inc. PPE Ethernet support + +If the driver is built as a module, the module will be called qcom-ppe. + +The PPE driver functionally depends on the CMN PLL and NSSCC clock controller drivers. +Please make sure the dependent modules are installed before installing the PPE driver +module. + + +Debugging +========= + +The PPE hardware counters can be accessed using debugfs interface from the +``/sys/kernel/debug/ppe/`` directory. diff --git a/Documentation/networking/devlink/devlink-health.rst b/Documentation/networking/devlink/devlink-health.rst index e0b8cfed610a..4d10536377ab 100644 --- a/Documentation/networking/devlink/devlink-health.rst +++ b/Documentation/networking/devlink/devlink-health.rst @@ -50,7 +50,7 @@ Once an error is reported, devlink health will perform the following actions: * Auto recovery attempt is being done. Depends on: - Auto-recovery configuration - - Grace period vs. time passed since last recover + - Grace period (and burst period) vs. time passed since last recover Devlink formatted message ========================= diff --git a/Documentation/networking/devlink/devlink-params.rst b/Documentation/networking/devlink/devlink-params.rst index 211b58177e12..0a9c20d70122 100644 --- a/Documentation/networking/devlink/devlink-params.rst +++ b/Documentation/networking/devlink/devlink-params.rst @@ -143,3 +143,11 @@ own name. * - ``clock_id`` - u64 - Clock ID used by the device for registering DPLL devices and pins. + * - ``total_vfs`` + - u32 + - The max number of Virtual Functions (VFs) exposed by the PF. + after reboot/pci reset, 'sriov_totalvfs' entry under the device's sysfs + directory will report this value. + * - ``num_doorbells`` + - u32 + - Controls the number of doorbells used by the device. diff --git a/Documentation/networking/devlink/index.rst b/Documentation/networking/devlink/index.rst index 270a65a01411..0c58e5c729d9 100644 --- a/Documentation/networking/devlink/index.rst +++ b/Documentation/networking/devlink/index.rst @@ -56,18 +56,18 @@ general. :maxdepth: 1 devlink-dpipe + devlink-eswitch-attr + devlink-flash devlink-health devlink-info - devlink-flash + devlink-linecard devlink-params devlink-port devlink-region - devlink-resource devlink-reload + devlink-resource devlink-selftests devlink-trap - devlink-linecard - devlink-eswitch-attr Driver-specific documentation ----------------------------- @@ -78,12 +78,14 @@ parameters, info versions, and other features it supports. .. toctree:: :maxdepth: 1 + am65-nuss-cpsw-switch bnxt etas_es58x hns3 i40e - ionic ice + ionic + iosm ixgbe kvaser_pciefd kvaser_usb @@ -93,11 +95,9 @@ parameters, info versions, and other features it supports. mv88e6xxx netdevsim nfp - qed - ti-cpsw-switch - am65-nuss-cpsw-switch - prestera - iosm octeontx2 + prestera + qed sfc + ti-cpsw-switch zl3073x diff --git a/Documentation/networking/devlink/mlx5.rst b/Documentation/networking/devlink/mlx5.rst index 7febe0aecd53..0e5f9c76e514 100644 --- a/Documentation/networking/devlink/mlx5.rst +++ b/Documentation/networking/devlink/mlx5.rst @@ -15,23 +15,62 @@ Parameters * - Name - Mode - Validation + - Notes * - ``enable_roce`` - driverinit - - Type: Boolean - - If the device supports RoCE disablement, RoCE enablement state controls + - Boolean + - If the device supports RoCE disablement, RoCE enablement state controls device support for RoCE capability. Otherwise, the control occurs in the driver stack. When RoCE is disabled at the driver level, only raw ethernet QPs are supported. * - ``io_eq_size`` - driverinit - The range is between 64 and 4096. + - * - ``event_eq_size`` - driverinit - The range is between 64 and 4096. + - * - ``max_macs`` - driverinit - The range is between 1 and 2^31. Only power of 2 values are supported. + - + * - ``enable_sriov`` + - permanent + - Boolean + - Applies to each physical function (PF) independently, if the device + supports it. Otherwise, it applies symmetrically to all PFs. + * - ``total_vfs`` + - permanent + - The range is between 1 and a device-specific max. + - Applies to each physical function (PF) independently, if the device + supports it. Otherwise, it applies symmetrically to all PFs. + +Note: permanent parameters such as ``enable_sriov`` and ``total_vfs`` require FW reset to take effect + +.. code-block:: bash + + # setup parameters + devlink dev param set pci/0000:01:00.0 name enable_sriov value true cmode permanent + devlink dev param set pci/0000:01:00.0 name total_vfs value 8 cmode permanent + + # Fw reset + devlink dev reload pci/0000:01:00.0 action fw_activate + + # for PCI related config such as sriov PCI reset/rescan is required: + echo 1 >/sys/bus/pci/devices/0000:01:00.0/remove + echo 1 >/sys/bus/pci/rescan + grep ^ /sys/bus/pci/devices/0000:01:00.0/sriov_* + + * - ``num_doorbells`` + - driverinit + - This controls the number of channel doorbells used by the netdev. In all + cases, an additional doorbell is allocated and used for non-channel + communication (e.g. for PTP, HWS, etc.). Supported values are: + + - 0: No channel-specific doorbells, use the global one for everything. + - [1, max_num_channels]: Spread netdev channels equally across these + doorbells. The ``mlx5`` driver also implements the following driver-specific parameters. @@ -116,6 +155,68 @@ parameters. - u32 - driverinit - Control the size (in packets) of the hairpin queues. + * - ``pcie_cong_inbound_high`` + - u16 + - driverinit + - High threshold configuration for PCIe congestion events. The firmware + will send an event once device side inbound PCIe traffic went + above the configured high threshold for a long enough period (at least + 200ms). + + See pci_bw_inbound_high ethtool stat. + + Units are 0.01 %. Accepted values are in range [0, 10000]. + pcie_cong_inbound_low < pcie_cong_inbound_high. + Default value: 9000 (Corresponds to 90%). + * - ``pcie_cong_inbound_low`` + - u16 + - driverinit + - Low threshold configuration for PCIe congestion events. The firmware + will send an event once device side inbound PCIe traffic went + below the configured low threshold, only after having been previously in + a congested state. + + See pci_bw_inbound_low ethtool stat. + + Units are 0.01 %. Accepted values are in range [0, 10000]. + pcie_cong_inbound_low < pcie_cong_inbound_high. + Default value: 7500. + * - ``pcie_cong_outbound_high`` + - u16 + - driverinit + - High threshold configuration for PCIe congestion events. The firmware + will send an event once device side outbound PCIe traffic went + above the configured high threshold for a long enough period (at least + 200ms). + + See pci_bw_outbound_high ethtool stat. + + Units are 0.01 %. Accepted values are in range [0, 10000]. + pcie_cong_outbound_low < pcie_cong_outbound_high. + Default value: 9000 (Corresponds to 90%). + * - ``pcie_cong_outbound_low`` + - u16 + - driverinit + - Low threshold configuration for PCIe congestion events. The firmware + will send an event once device side outbound PCIe traffic went + below the configured low threshold, only after having been previously in + a congested state. + + See pci_bw_outbound_low ethtool stat. + + Units are 0.01 %. Accepted values are in range [0, 10000]. + pcie_cong_outbound_low < pcie_cong_outbound_high. + Default value: 7500. + + * - ``cqe_compress_type`` + - string + - permanent + - Configure which mechanism/algorithm should be used by the NIC that will + affect the rate (aggressiveness) of compressed CQEs depending on PCIe bus + conditions and other internal NIC factors. This mode affects all queues + that enable compression. + * ``balanced`` : Merges fewer CQEs, resulting in a moderate compression ratio but maintaining a balance between bandwidth savings and performance + * ``aggressive`` : Merges more CQEs into a single entry, achieving a higher compression rate and maximizing performance, particularly under high traffic loads The ``mlx5`` driver supports reloading via ``DEVLINK_CMD_RELOAD`` @@ -284,6 +385,12 @@ Description of the vnic counters: amount of Interconnect Host Memory (ICM) consumed by the vnic in granularity of 4KB. ICM is host memory allocated by SW upon HCA request and is used for storing data structures that control HCA operation. +- bar_uar_access + number of WRITE or READ access operations to the UAR on the PCIe BAR. +- odp_local_triggered_page_fault + number of locally-triggered page-faults due to ODP. +- odp_remote_triggered_page_fault + number of remotly-triggered page-faults due to ODP. User commands examples: diff --git a/Documentation/networking/devlink/zl3073x.rst b/Documentation/networking/devlink/zl3073x.rst index 4b6cfaf38643..fc5a8dc272a7 100644 --- a/Documentation/networking/devlink/zl3073x.rst +++ b/Documentation/networking/devlink/zl3073x.rst @@ -49,3 +49,17 @@ The ``zl3073x`` driver reports the following versions - running - 1.3.0.1 - Device configuration version customized by OEM + +Flash Update +============ + +The ``zl3073x`` driver implements support for flash update using the +``devlink-flash`` interface. It supports updating the device flash using a +combined flash image ("bundle") that contains multiple components (firmware +parts and configurations). + +During the flash procedure, the standard firmware interface is not available, +so the driver unregisters all DPLLs and associated pins, and re-registers them +once the flash procedure is complete. + +The driver does not support any overwrite mask flags. diff --git a/Documentation/networking/dns_resolver.rst b/Documentation/networking/dns_resolver.rst index c0364f7070af..52f298834db6 100644 --- a/Documentation/networking/dns_resolver.rst +++ b/Documentation/networking/dns_resolver.rst @@ -25,11 +25,11 @@ These routines must be supported by userspace tools dns.upcall, cifs.upcall and request-key. It is under development and does not yet provide the full feature set. The features it does support include: - (*) Implements the dns_resolver key_type to contact userspace. + * Implements the dns_resolver key_type to contact userspace. It does not yet support the following AFS features: - (*) Dns query support for AFSDB resource record. + * DNS query support for AFSDB resource record. This code is extracted from the CIFS filesystem. @@ -64,44 +64,42 @@ before the more general line given above as the first match is the one taken:: Usage ===== -To make use of this facility, one of the following functions that are -implemented in the module can be called after doing:: +To make use of this facility, first ``dns_resolver.h`` must be included:: #include <linux/dns_resolver.h> - :: +Then queries may be made by calling:: int dns_query(const char *type, const char *name, size_t namelen, const char *options, char **_result, time_t *_expiry); - This is the basic access function. It looks for a cached DNS query and if - it doesn't find it, it upcalls to userspace to make a new DNS query, which - may then be cached. The key description is constructed as a string of the - form:: +This is the basic access function. It looks for a cached DNS query and if +it doesn't find it, it upcalls to userspace to make a new DNS query, which +may then be cached. The key description is constructed as a string of the +form:: [<type>:]<name> - where <type> optionally specifies the particular upcall program to invoke, - and thus the type of query to do, and <name> specifies the string to be - looked up. The default query type is a straight hostname to IP address - set lookup. +where <type> optionally specifies the particular upcall program to invoke, +and thus the type of query, and <name> specifies the string to be looked up. +The default query type is a straight hostname to IP address set lookup. - The name parameter is not required to be a NUL-terminated string, and its - length should be given by the namelen argument. +The name parameter is not required to be a NUL-terminated string, and its +length should be given by the namelen argument. - The options parameter may be NULL or it may be a set of options - appropriate to the query type. +The options parameter may be NULL or it may be a set of options +appropriate to the query type. - The return value is a string appropriate to the query type. For instance, - for the default query type it is just a list of comma-separated IPv4 and - IPv6 addresses. The caller must free the result. +The return value is a string appropriate to the query type. For instance, +for the default query type it is just a list of comma-separated IPv4 and +IPv6 addresses. The caller must free the result. - The length of the result string is returned on success, and a negative - error code is returned otherwise. -EKEYREJECTED will be returned if the - DNS lookup failed. +The length of the result string is returned on success, and a negative +error code is returned otherwise. -EKEYREJECTED will be returned if the +DNS lookup failed. - If _expiry is non-NULL, the expiry time (TTL) of the result will be - returned also. +If _expiry is non-NULL, the expiry time (TTL) of the result will be +returned also. The kernel maintains an internal keyring in which it caches looked up keys. This can be cleared by any process that has the CAP_SYS_ADMIN capability by @@ -142,8 +140,8 @@ the key will be discarded and recreated when the data it holds has expired. dns_query() returns a copy of the value attached to the key, or an error if that is indicated instead. -See <file:Documentation/security/keys/request-key.rst> for further -information about request-key function. +See Documentation/security/keys/request-key.rst for further information about +request-key function. Debugging diff --git a/Documentation/networking/ethtool-netlink.rst b/Documentation/networking/ethtool-netlink.rst index ab20c644af24..b270886c5f5d 100644 --- a/Documentation/networking/ethtool-netlink.rst +++ b/Documentation/networking/ethtool-netlink.rst @@ -1541,6 +1541,11 @@ Drivers fill in the statistics in the following structure: .. kernel-doc:: include/linux/ethtool.h :identifiers: ethtool_fec_stats +Statistics may have FEC bins histogram attribute ``ETHTOOL_A_FEC_STAT_HIST`` +as defined in IEEE 802.3ck-2022 and 802.3df-2024. Nested attributes will have +the range of FEC errors in the bin (inclusive) and the amount of error events +in the bin. + FEC_SET ======= diff --git a/Documentation/networking/index.rst b/Documentation/networking/index.rst index ac90b82f3ce9..c775cababc8c 100644 --- a/Documentation/networking/index.rst +++ b/Documentation/networking/index.rst @@ -57,7 +57,7 @@ Contents: filter generic-hdlc generic_netlink - netlink_spec/index + ../netlink/specs/index gen_stats gtp ila @@ -101,6 +101,7 @@ Contents: ppp_generic proc_net_tcp pse-pd/index + psp radiotap-headers rds regulatory diff --git a/Documentation/networking/iou-zcrx.rst b/Documentation/networking/iou-zcrx.rst index 0127319b30bb..54a72e172bdc 100644 --- a/Documentation/networking/iou-zcrx.rst +++ b/Documentation/networking/iou-zcrx.rst @@ -75,7 +75,7 @@ Create an io_uring instance with the following required setup flags:: IORING_SETUP_SINGLE_ISSUER IORING_SETUP_DEFER_TASKRUN - IORING_SETUP_CQE32 + IORING_SETUP_CQE32 or IORING_SETUP_CQE_MIXED Create memory area ------------------ diff --git a/Documentation/networking/ip-sysctl.rst b/Documentation/networking/ip-sysctl.rst index 9756d16e3df1..a06cb99d66dc 100644 --- a/Documentation/networking/ip-sysctl.rst +++ b/Documentation/networking/ip-sysctl.rst @@ -209,7 +209,7 @@ neigh/default/unres_qlen_bytes - INTEGER Setting negative value is meaningless and will return error. - Default: SK_WMEM_MAX, (same as net.core.wmem_default). + Default: SK_WMEM_DEFAULT, (same as net.core.wmem_default). Exact value depends on architecture and kernel options, but should be enough to allow queuing 256 packets @@ -443,23 +443,56 @@ tcp_early_retrans - INTEGER tcp_ecn - INTEGER Control use of Explicit Congestion Notification (ECN) by TCP. - ECN is used only when both ends of the TCP connection indicate - support for it. This feature is useful in avoiding losses due - to congestion by allowing supporting routers to signal - congestion before having to drop packets. + ECN is used only when both ends of the TCP connection indicate support + for it. This feature is useful in avoiding losses due to congestion by + allowing supporting routers to signal congestion before having to drop + packets. A host that supports ECN both sends ECN at the IP layer and + feeds back ECN at the TCP layer. The highest variant of ECN feedback + that both peers support is chosen by the ECN negotiation (Accurate ECN, + ECN, or no ECN). + + The highest negotiated variant for incoming connection requests + and the highest variant requested by outgoing connection + attempts: + + ===== ==================== ==================== + Value Incoming connections Outgoing connections + ===== ==================== ==================== + 0 No ECN No ECN + 1 ECN ECN + 2 ECN No ECN + 3 AccECN AccECN + 4 AccECN ECN + 5 AccECN No ECN + ===== ==================== ==================== + + Default: 2 + +tcp_ecn_option - INTEGER + Control Accurate ECN (AccECN) option sending when AccECN has been + successfully negotiated during handshake. Send logic inhibits + sending AccECN options regarless of this setting when no AccECN + option has been seen for the reverse direction. Possible values are: - = ===================================================== - 0 Disable ECN. Neither initiate nor accept ECN. - 1 Enable ECN when requested by incoming connections and - also request ECN on outgoing connection attempts. - 2 Enable ECN when requested by incoming connections - but do not request ECN on outgoing connections. - = ===================================================== + = ============================================================ + 0 Never send AccECN option. This also disables sending AccECN + option in SYN/ACK during handshake. + 1 Send AccECN option sparingly according to the minimum option + rules outlined in draft-ietf-tcpm-accurate-ecn. + 2 Send AccECN option on every packet whenever it fits into TCP + option space. + = ============================================================ Default: 2 +tcp_ecn_option_beacon - INTEGER + Control Accurate ECN (AccECN) option sending frequency per RTT and it + takes effect only when tcp_ecn_option is set to 2. + + Default: 3 (AccECN will be send at least 3 times per RTT) + tcp_ecn_fallback - BOOLEAN If the kernel detects that ECN connection misbehaves, enable fall back to non-ECN. Currently, this knob implements the fallback @@ -805,8 +838,8 @@ tcp_rmem - vector of 3 INTEGERs: min, default, max This value results in initial window of 65535. max: maximal size of receive buffer allowed for automatically - selected receiver buffers for TCP socket. This value does not override - net.core.rmem_max. Calling setsockopt() with SO_RCVBUF disables + selected receiver buffers for TCP socket. + Calling setsockopt() with SO_RCVBUF disables automatic tuning of that socket's receive buffer size, in which case this value is ignored. Default: between 131072 and 32MB, depending on RAM size. @@ -3508,16 +3541,10 @@ cookie_hmac_alg - STRING a listening sctp socket to a connecting client in the INIT-ACK chunk. Valid values are: - * md5 - * sha1 + * sha256 * none - Ability to assign md5 or sha1 as the selected alg is predicated on the - configuration of those algorithms at build time (CONFIG_CRYPTO_MD5 and - CONFIG_CRYPTO_SHA1). - - Default: Dependent on configuration. MD5 if available, else SHA1 if - available, else none. + Default: sha256 rcvbuf_policy - INTEGER Determines if the receive buffer is attributed to the socket or to diff --git a/Documentation/networking/mptcp-sysctl.rst b/Documentation/networking/mptcp-sysctl.rst index 1683c139821e..1eb6af26b4a7 100644 --- a/Documentation/networking/mptcp-sysctl.rst +++ b/Documentation/networking/mptcp-sysctl.rst @@ -8,9 +8,11 @@ MPTCP Sysfs variables =============================== add_addr_timeout - INTEGER (seconds) - Set the timeout after which an ADD_ADDR control message will be - resent to an MPTCP peer that has not acknowledged a previous - ADD_ADDR message. + Set the maximum value of timeout after which an ADD_ADDR control message + will be resent to an MPTCP peer that has not acknowledged a previous + ADD_ADDR message. A dynamically estimated retransmission timeout based + on the estimated connection round-trip-time is used if this value is + lower than the maximum one. Do not retransmit if set to 0. diff --git a/Documentation/networking/mptcp.rst b/Documentation/networking/mptcp.rst index 17f2bab61164..b6753ffb9c9a 100644 --- a/Documentation/networking/mptcp.rst +++ b/Documentation/networking/mptcp.rst @@ -60,13 +60,13 @@ address announcements. Typically, it is the client side that initiates subflows, and the server side that announces additional addresses via the ``ADD_ADDR`` and ``REMOVE_ADDR`` options. -Path managers are controlled by the ``net.mptcp.pm_type`` sysctl knob -- see -mptcp-sysctl.rst. There are two types: the in-kernel one (type ``0``) where the -same rules are applied for all the connections (see: ``ip mptcp``) ; and the -userspace one (type ``1``), controlled by a userspace daemon (i.e. `mptcpd +Path managers are controlled by the ``net.mptcp.path_manager`` sysctl knob -- +see mptcp-sysctl.rst. There are two types: the in-kernel one (``kernel``) where +the same rules are applied for all the connections (see: ``ip mptcp``) ; and the +userspace one (``userspace``), controlled by a userspace daemon (i.e. `mptcpd <https://mptcpd.mptcp.dev/>`_) where different rules can be applied for each connection. The path managers can be controlled via a Netlink API; see -netlink_spec/mptcp_pm.rst. +../netlink/specs/mptcp_pm.rst. To be able to use multiple IP addresses on a host to create multiple *subflows* (paths), the default in-kernel MPTCP path-manager needs to know which IP diff --git a/Documentation/networking/napi.rst b/Documentation/networking/napi.rst index a15754adb041..7dd60366f4ff 100644 --- a/Documentation/networking/napi.rst +++ b/Documentation/networking/napi.rst @@ -433,9 +433,8 @@ Threaded NAPI Threaded NAPI is an operating mode that uses dedicated kernel threads rather than software IRQ context for NAPI processing. -The configuration is per netdevice and will affect all -NAPI instances of that device. Each NAPI instance will spawn a separate -thread (called ``napi/${ifc-name}-${napi-id}``). +Each threaded NAPI instance will spawn a separate thread +(called ``napi/${ifc-name}-${napi-id}``). It is recommended to pin each kernel thread to a single CPU, the same CPU as the CPU which services the interrupt. Note that the mapping diff --git a/Documentation/networking/net_cachelines/tcp_sock.rst b/Documentation/networking/net_cachelines/tcp_sock.rst index 7bbda5944ee2..26f32dbcf6ec 100644 --- a/Documentation/networking/net_cachelines/tcp_sock.rst +++ b/Documentation/networking/net_cachelines/tcp_sock.rst @@ -26,8 +26,8 @@ u64 bytes_acked read_w u32 dsack_dups u32 snd_una read_mostly read_write tcp_wnd_end,tcp_urg_mode,tcp_minshall_check,tcp_cwnd_validate(tx);tcp_ack,tcp_may_update_window,tcp_clean_rtx_queue(write),tcp_ack_tstamp(rx) u32 snd_sml read_write tcp_minshall_check,tcp_minshall_update -u32 rcv_tstamp read_mostly tcp_ack -void * tcp_clean_acked read_mostly tcp_ack +u32 rcv_tstamp read_write read_write tcp_ack +void * tcp_clean_acked read_mostly tcp_ack u32 lsndtime read_write tcp_slow_start_after_idle_check,tcp_event_data_sent u32 last_oow_ack_time u32 compressed_ack_rcv_nxt @@ -57,7 +57,7 @@ u8:1 is_sack_reneg read_m u8:2 fastopen_client_fail u8:4 nonagle read_write tcp_skb_entail,tcp_push_pending_frames u8:1 thin_lto -u8:1 recvmsg_inq +u8:1 recvmsg_inq read_mostly tcp_recvmsg u8:1 repair read_mostly tcp_write_xmit u8:1 frto u8 repair_queue @@ -101,6 +101,18 @@ u32 prr_delivered u32 prr_out read_mostly read_mostly tcp_rate_skb_sent,tcp_newly_delivered(tx);tcp_ack,tcp_rate_gen,tcp_clean_rtx_queue(rx) u32 delivered read_mostly read_write tcp_rate_skb_sent, tcp_newly_delivered(tx);tcp_ack, tcp_rate_gen, tcp_clean_rtx_queue (rx) u32 delivered_ce read_mostly read_write tcp_rate_skb_sent(tx);tcp_rate_gen(rx) +u32 received_ce read_mostly read_write +u32[3] received_ecn_bytes read_mostly read_write +u8:4 received_ce_pending read_mostly read_write +u32[3] delivered_ecn_bytes read_write +u8:2 syn_ect_snt write_mostly read_write +u8:2 syn_ect_rcv read_mostly read_write +u8:2 accecn_minlen write_mostly read_write +u8:2 est_ecnfield read_write +u8:2 accecn_opt_demand read_mostly read_write +u8:2 prev_ecnfield read_write +u64 accecn_opt_tstamp read_write +u8:4 accecn_fail_mode u32 lost read_mostly tcp_ack u32 app_limited read_write read_mostly tcp_rate_check_app_limited,tcp_rate_skb_sent(tx);tcp_rate_gen(rx) u64 first_tx_mstamp read_write tcp_rate_skb_sent diff --git a/Documentation/networking/netlink_spec/.gitignore b/Documentation/networking/netlink_spec/.gitignore deleted file mode 100644 index 30d85567b592..000000000000 --- a/Documentation/networking/netlink_spec/.gitignore +++ /dev/null @@ -1 +0,0 @@ -*.rst diff --git a/Documentation/networking/netlink_spec/readme.txt b/Documentation/networking/netlink_spec/readme.txt deleted file mode 100644 index 030b44aca4e6..000000000000 --- a/Documentation/networking/netlink_spec/readme.txt +++ /dev/null @@ -1,4 +0,0 @@ -SPDX-License-Identifier: GPL-2.0 - -This file is populated during the build of the documentation (htmldocs) by the -tools/net/ynl/pyynl/ynl_gen_rst.py script. diff --git a/Documentation/networking/phy.rst b/Documentation/networking/phy.rst index 7f159043ad5a..b0f2ef83735d 100644 --- a/Documentation/networking/phy.rst +++ b/Documentation/networking/phy.rst @@ -20,7 +20,7 @@ sometimes quite different) ethernet controllers connected to the same management bus, it is difficult to ensure safe use of the bus. Since the PHYs are devices, and the management busses through which they are -accessed are, in fact, busses, the PHY Abstraction Layer treats them as such. +accessed are, in fact, busses, the PHY Abstraction Layer (PAL) treats them as such. In doing so, it has these goals: #. Increase code-reuse diff --git a/Documentation/networking/psp.rst b/Documentation/networking/psp.rst new file mode 100644 index 000000000000..4ac09e64e95a --- /dev/null +++ b/Documentation/networking/psp.rst @@ -0,0 +1,183 @@ +.. SPDX-License-Identifier: GPL-2.0-only + +===================== +PSP Security Protocol +===================== + +Protocol +======== + +PSP Security Protocol (PSP) was defined at Google and published in: + +https://raw.githubusercontent.com/google/psp/main/doc/PSP_Arch_Spec.pdf + +This section briefly covers protocol aspects crucial for understanding +the kernel API. Refer to the protocol specification for further details. + +Note that the kernel implementation and documentation uses the term +"device key" in place of "master key", it is both less confusing +to an average developer and is less likely to run afoul any naming +guidelines. + +Derived Rx keys +--------------- + +PSP borrows some terms and mechanisms from IPsec. PSP was designed +with HW offloads in mind. The key feature of PSP is that Rx keys for every +connection do not have to be stored by the receiver but can be derived +from device key and information present in packet headers. +This makes it possible to implement receivers which require a constant +amount of memory regardless of the number of connections (``O(1)`` scaling). + +Tx keys have to be stored like with any other protocol, but Tx is much +less latency sensitive than Rx, and delays in fetching keys from slow +memory is less likely to cause packet drops. Preferably, the Tx keys +should be provided with the packet (e.g. as part of the descriptors). + +Key rotation +------------ + +The device key known only to the receiver is fundamental to the design. +Per specification this state cannot be directly accessible (it must be +impossible to read it out of the hardware of the receiver NIC). +Moreover, it has to be "rotated" periodically (usually daily). Rotation +means that new device key gets generated (by a random number generator +of the device), and used for all new connections. To avoid disrupting +old connections the old device key remains in the NIC. A phase bit +carried in the packet headers indicates which generation of device key +the packet has been encrypted with. + +User facing API +=============== + +PSP is designed primarily for hardware offloads. There is currently +no software fallback for systems which do not have PSP capable NICs. +There is also no standard (or otherwise defined) way of establishing +a PSP-secured connection or exchanging the symmetric keys. + +The expectation is that higher layer protocols will take care of +protocol and key negotiation. For example one may use TLS key exchange, +announce the PSP capability, and switch to PSP if both endpoints +are PSP-capable. + +All configuration of PSP is performed via the PSP netlink family. + +Device discovery +---------------- + +The PSP netlink family defines operations to retrieve information +about the PSP devices available on the system, configure them and +access PSP related statistics. + +Securing a connection +--------------------- + +PSP encryption is currently only supported for TCP connections. +Rx and Tx keys are allocated separately. First the ``rx-assoc`` +Netlink command needs to be issued, specifying a target TCP socket. +Kernel will allocate a new PSP Rx key from the NIC and associate it +with given socket. At this stage socket will accept both PSP-secured +and plain text TCP packets. + +Tx keys are installed using the ``tx-assoc`` Netlink command. +Once the Tx keys are installed, all data read from the socket will +be PSP-secured. In other words act of installing Tx keys has a secondary +effect on the Rx direction. + +There is an intermediate period after ``tx-assoc`` successfully +returns and before the TCP socket encounters it's first PSP +authenticated packet, where the TCP stack will allow certain nondata +packets, i.e. ACKs, FINs, and RSTs, to enter TCP receive processing +even if not PSP authenticated. During the ``tx-assoc`` call, the TCP +socket's ``rcv_nxt`` field is recorded. At this point, ACKs and RSTs +will be accepted with any sequence number, while FINs will only be +accepted at the latched value of ``rcv_nxt``. Once the TCP stack +encounters the first TCP packet containing PSP authenticated data, the +other end of the connection must have executed the ``tx-assoc`` +command, so any TCP packet, including those without data, will be +dropped before receive processing if it is not successfully +authenticated. This is summarized in the table below. The +aforementioned state of rejecting all non-PSP packets is labeled "PSP +Full". + ++----------------+------------+------------+-------------+-------------+ +| Event | Normal TCP | Rx PSP | Tx PSP | PSP Full | ++================+============+============+=============+=============+ +| Rx plain | accept | accept | drop | drop | +| (data) | | | | | ++----------------+------------+------------+-------------+-------------+ +| Rx plain | accept | accept | accept | drop | +| (ACK|FIN|RST) | | | | | ++----------------+------------+------------+-------------+-------------+ +| Rx PSP (good) | drop | accept | accept | accept | ++----------------+------------+------------+-------------+-------------+ +| Rx PSP (bad | drop | drop | drop | drop | +| crypt, !=SPI) | | | | | ++----------------+------------+------------+-------------+-------------+ +| Tx | plain text | plain text | encrypted | encrypted | +| | | | (excl. rtx) | (excl. rtx) | ++----------------+------------+------------+-------------+-------------+ + +To ensure that any data read from the socket after the ``tx-assoc`` +call returns success has been authenticated, the kernel will scan the +receive and ofo queues of the socket at ``tx-assoc`` time. If any +enqueued packet was received in clear text, the Tx association will +fail, and the application should retry installing the Tx key after +draining the socket (this should not be necessary if both endpoints +are well behaved). + +Because TCP sequence numbers are not integrity protected prior to +upgrading to PSP, it is possible that a MITM could offset sequence +numbers in a way that deletes a prefix of the PSP protected part of +the TCP stream. If userspace cares to mitigate this type of attack, a +special "start of PSP" message should be exchanged after ``tx-assoc``. + +Rotation notifications +---------------------- + +The rotations of device key happen asynchronously and are usually +performed by management daemons, not under application control. +The PSP netlink family will generate a notification whenever keys +are rotated. The applications are expected to re-establish connections +before keys are rotated again. + +Kernel implementation +===================== + +Driver notes +------------ + +Drivers are expected to start with no PSP enabled (``psp-versions-ena`` +in ``dev-get`` set to ``0``) whenever possible. The user space should +not depend on this behavior, as future extension may necessitate creation +of devices with PSP already enabled, nonetheless drivers should not enable +PSP by default. Enabling PSP should be the responsibility of the system +component which also takes care of key rotation. + +Note that ``psp-versions-ena`` is expected to be used only for enabling +receive processing. The device is not expected to reject transmit requests +after ``psp-versions-ena`` has been disabled. User may also disable +``psp-versions-ena`` while there are active associations, which will +break all PSP Rx processing. + +Drivers are expected to ensure that a device key is usable and secure +upon init, without explicit key rotation by the user space. It must be +possible to allocate working keys, and that no duplicate keys must be +generated. If the device allows the host to request the key for an +arbitrary SPI - driver should discard both device keys (rotate the +device key twice), to avoid potentially using a SPI+key which previous +OS instance already had access to. + +Drivers must use ``psp_skb_get_assoc_rcu()`` to check if PSP Tx offload +was requested for given skb. On Rx drivers should allocate and populate +the ``SKB_EXT_PSP`` skb extension, and set the skb->decrypted bit to 1. + +Kernel implementation notes +--------------------------- + +PSP implementation follows the TLS offload more closely than the IPsec +offload, with per-socket state, and the use of skb->decrypted to prevent +clear text leaks. + +PSP device is separate from netdev, to make it possible to "delegate" +PSP offload capabilities to software devices (e.g. ``veth``). diff --git a/Documentation/networking/rxrpc.rst b/Documentation/networking/rxrpc.rst index d63e3e27dd06..8926dab8e2e6 100644 --- a/Documentation/networking/rxrpc.rst +++ b/Documentation/networking/rxrpc.rst @@ -437,8 +437,7 @@ message type supported. At run time this can be queried by means of the RXRPC_SUPPORTED_CMSG socket option (see below). -============== -SOCKET OPTIONS +Socket Options ============== AF_RXRPC sockets support a few socket options at the SOL_RXRPC level: @@ -495,8 +494,7 @@ AF_RXRPC sockets support a few socket options at the SOL_RXRPC level: the highest control message type supported. -======== -SECURITY +Security ======== Currently, only the kerberos 4 equivalent protocol has been implemented @@ -540,8 +538,7 @@ be found at: http://people.redhat.com/~dhowells/rxrpc/listen.c -==================== -EXAMPLE CLIENT USAGE +Example Client Usage ==================== A client would issue an operation by: diff --git a/Documentation/networking/segmentation-offloads.rst b/Documentation/networking/segmentation-offloads.rst index 085e8fab03fd..72f69b22b28c 100644 --- a/Documentation/networking/segmentation-offloads.rst +++ b/Documentation/networking/segmentation-offloads.rst @@ -43,10 +43,19 @@ also point to the TCP header of the packet. For IPv4 segmentation we support one of two types in terms of the IP ID. The default behavior is to increment the IP ID with every segment. If the GSO type SKB_GSO_TCP_FIXEDID is specified then we will not increment the IP -ID and all segments will use the same IP ID. If a device has -NETIF_F_TSO_MANGLEID set then the IP ID can be ignored when performing TSO -and we will either increment the IP ID for all frames, or leave it at a -static value based on driver preference. +ID and all segments will use the same IP ID. + +For encapsulated packets, SKB_GSO_TCP_FIXEDID refers only to the outer header. +SKB_GSO_TCP_FIXEDID_INNER can be used to specify the same for the inner header. +Any combination of these two GSO types is allowed. + +If a device has NETIF_F_TSO_MANGLEID set then the IP ID can be ignored when +performing TSO and we will either increment the IP ID for all frames, or leave +it at a static value based on driver preference. For encapsulated packets, +NETIF_F_TSO_MANGLEID is relevant for both outer and inner headers, unless the +DF bit is not set on the outer header, in which case the device driver must +guarantee that the IP ID field is incremented in the outer header with every +segment. UDP Fragmentation Offload @@ -124,10 +133,7 @@ Generic Receive Offload Generic receive offload is the complement to GSO. Ideally any frame assembled by GRO should be segmented to create an identical sequence of frames using GSO, and any sequence of frames segmented by GSO should be -able to be reassembled back to the original by GRO. The only exception to -this is IPv4 ID in the case that the DF bit is set for a given IP header. -If the value of the IPv4 ID is not sequentially incrementing it will be -altered so that it is when a frame assembled via GRO is segmented via GSO. +able to be reassembled back to the original by GRO. Partial Generic Segmentation Offload diff --git a/Documentation/power/regulator/consumer.rst b/Documentation/power/regulator/consumer.rst index 9d2416f63f6e..c01675b25a90 100644 --- a/Documentation/power/regulator/consumer.rst +++ b/Documentation/power/regulator/consumer.rst @@ -23,10 +23,18 @@ To release the regulator the consumer driver should call :: regulator_put(regulator); Consumers can be supplied by more than one regulator e.g. codec consumer with -analog and digital supplies :: +analog and digital supplies by means of bulk operations :: + + struct regulator_bulk_data supplies[2]; + + supplies[0].supply = "Vcc"; /* digital core */ + supplies[1].supply = "Avdd"; /* analog */ + + ret = regulator_bulk_get(dev, ARRAY_SIZE(supplies), supplies); + + // convenience helper to call regulator_put() on multiple regulators + regulator_bulk_free(ARRAY_SIZE(supplies), supplies); - digital = regulator_get(dev, "Vcc"); /* digital core */ - analog = regulator_get(dev, "Avdd"); /* analog */ The regulator access functions regulator_get() and regulator_put() will usually be called in your device drivers probe() and remove() respectively. @@ -51,11 +59,21 @@ A consumer can determine if a regulator is enabled by calling:: This will return > zero when the regulator is enabled. +A set of regulators can be enabled with a single bulk operation :: + + int regulator_bulk_enable(int num_consumers, + struct regulator_bulk_data *consumers); + A consumer can disable its supply when no longer needed by calling:: int regulator_disable(regulator); +Or a number of them :: + + int regulator_bulk_disable(int num_consumers, + struct regulator_bulk_data *consumers); + NOTE: This may not disable the supply if it's shared with other consumers. The regulator will only be disabled when the enabled reference count is zero. @@ -64,11 +82,15 @@ Finally, a regulator can be forcefully disabled in the case of an emergency:: int regulator_force_disable(regulator); +This operation is also supported for multiple regulators :: + + int regulator_bulk_force_disable(int num_consumers, + struct regulator_bulk_data *consumers); + NOTE: this will immediately and forcefully shutdown the regulator output. All consumers will be powered off. - 3. Regulator Voltage Control & Status (dynamic drivers) ======================================================= diff --git a/Documentation/process/changes.rst b/Documentation/process/changes.rst index bccfa19b45df..b38622b0d525 100644 --- a/Documentation/process/changes.rst +++ b/Documentation/process/changes.rst @@ -30,7 +30,7 @@ you probably needn't concern yourself with pcmciautils. Program Minimal version Command to check the version ====================== =============== ======================================== GNU C 8.1 gcc --version -Clang/LLVM (optional) 13.0.1 clang --version +Clang/LLVM (optional) 15.0.0 clang --version Rust (optional) 1.78.0 rustc --version bindgen (optional) 0.65.1 bindgen --version GNU make 4.0 make --version diff --git a/Documentation/process/maintainer-netdev.rst b/Documentation/process/maintainer-netdev.rst index e1755610b4bc..989192421cc9 100644 --- a/Documentation/process/maintainer-netdev.rst +++ b/Documentation/process/maintainer-netdev.rst @@ -407,7 +407,7 @@ Clean-up patches Netdev discourages patches which perform simple clean-ups, which are not in the context of other work. For example: -* Addressing ``checkpatch.pl`` warnings +* Addressing ``checkpatch.pl``, and other trivial coding style warnings * Addressing :ref:`Local variable ordering<rcs>` issues * Conversions to device-managed APIs (``devm_`` helpers) diff --git a/Documentation/process/maintainer-soc.rst b/Documentation/process/maintainer-soc.rst index fe9d8bcfbd2b..3ba886f52a51 100644 --- a/Documentation/process/maintainer-soc.rst +++ b/Documentation/process/maintainer-soc.rst @@ -10,7 +10,7 @@ Overview The SoC subsystem is a place of aggregation for SoC-specific code. The main components of the subsystem are: -* devicetrees for 32- & 64-bit ARM and RISC-V +* devicetrees (DTS) for 32- & 64-bit ARM and RISC-V * 32-bit ARM board files (arch/arm/mach*) * 32- & 64-bit ARM defconfigs * SoC-specific drivers across architectures, in particular for 32- & 64-bit @@ -97,8 +97,8 @@ Perhaps one of the most important things to highlight is that dt-bindings document the ABI between the devicetree and the kernel. Please read Documentation/devicetree/bindings/ABI.rst. -If changes are being made to a devicetree that are incompatible with old -kernels, the devicetree patch should not be applied until the driver is, or an +If changes are being made to a DTS that are incompatible with old +kernels, the DTS patch should not be applied until the driver is, or an appropriate time later. Most importantly, any incompatible changes should be clearly pointed out in the patch description and pull request, along with the expected impact on existing users, such as bootloaders or other operating diff --git a/Documentation/scsi/scsi_mid_low_api.rst b/Documentation/scsi/scsi_mid_low_api.rst index 3ac4c7fafb55..634f5c28a849 100644 --- a/Documentation/scsi/scsi_mid_low_api.rst +++ b/Documentation/scsi/scsi_mid_low_api.rst @@ -380,7 +380,7 @@ Details:: /** * scsi_bios_ptable - return copy of block device's partition table - * @dev: pointer to block device + * @dev: pointer to gendisk * * Returns pointer to partition table, or NULL for failure * @@ -390,7 +390,7 @@ Details:: * * Defined in: drivers/scsi/scsicam.c **/ - unsigned char *scsi_bios_ptable(struct block_device *dev) + unsigned char *scsi_bios_ptable(struct gendisk *dev) /** @@ -623,7 +623,7 @@ Details:: * bios_param - fetch head, sector, cylinder info for a disk * @sdev: pointer to scsi device context (defined in * include/scsi/scsi_device.h) - * @bdev: pointer to block device context (defined in fs.h) + * @disk: pointer to gendisk (defined in blkdev.h) * @capacity: device size (in 512 byte sectors) * @params: three element array to place output: * params[0] number of heads (max 255) @@ -643,7 +643,7 @@ Details:: * * Optionally defined in: LLD **/ - int bios_param(struct scsi_device * sdev, struct block_device *bdev, + int bios_param(struct scsi_device * sdev, struct gendisk *disk, sector_t capacity, int params[3]) diff --git a/Documentation/sound/alsa-configuration.rst b/Documentation/sound/alsa-configuration.rst index a45174d165eb..0a4eaa7d66dd 100644 --- a/Documentation/sound/alsa-configuration.rst +++ b/Documentation/sound/alsa-configuration.rst @@ -2253,8 +2253,15 @@ device_setup Default: 0x0000 ignore_ctl_error Ignore any USB-controller regarding mixer interface (default: no) + ``ignore_ctl_error=1`` may help when you get an error at accessing + the mixer element such as URB error -22. This happens on some + buggy USB device or the controller. This workaround corresponds to + the ``quirk_flags`` bit 14, too. autoclock Enable auto-clock selection for UAC2 devices (default: yes) +lowlatency + Enable low latency playback mode (default: yes). + Could disable it to switch back to the old mode if face a regression. quirk_alias Quirk alias list, pass strings like ``0123abcd:5678beef``, which applies the existing quirk for the device 5678:beef to a new @@ -2284,29 +2291,87 @@ delayed_register The driver prints a message like "Found post-registration device assignment: 1234abcd:04" for such a device, so that user can notice the need. +skip_validation + Skip unit descriptor validation (default: no). + The option is used to ignore the validation errors with the hexdump + of the unit descriptor instead of a driver probe error, so that we + can check its details. quirk_flags - Contains the bit flags for various device specific workarounds. - Applied to the corresponding card index. - - * bit 0: Skip reading sample rate for devices - * bit 1: Create Media Controller API entries - * bit 2: Allow alignment on audio sub-slot at transfer - * bit 3: Add length specifier to transfers - * bit 4: Start playback stream at first in implement feedback mode - * bit 5: Skip clock selector setup - * bit 6: Ignore errors from clock source search - * bit 7: Indicates ITF-USB DSD based DACs - * bit 8: Add a delay of 20ms at each control message handling - * bit 9: Add a delay of 1-2ms at each control message handling - * bit 10: Add a delay of 5-6ms at each control message handling - * bit 11: Add a delay of 50ms at each interface setup - * bit 12: Perform sample rate validations at probe - * bit 13: Disable runtime PM autosuspend - * bit 14: Ignore errors for mixer access - * bit 15: Support generic DSD raw U32_BE format - * bit 16: Set up the interface at first like UAC1 - * bit 17: Apply the generic implicit feedback sync mode - * bit 18: Don't apply implicit feedback sync mode + The option provides a refined and flexible control for applying quirk + flags. It allows to specify the quirk flags for each device, and can + be modified dynamically via sysfs. + The old usage accepts an array of integers, each of which applies quirk + flags on the device in the order of probing. + E.g., ``quirk_flags=0x01,0x02`` applies get_sample_rate to the first + device, and share_media_device to the second device. + The new usage accepts a string in the format of + ``VID1:PID1:FLAGS1;VID2:PID2:FLAGS2;...``, where ``VIDx`` and ``PIDx`` + specify the device, and ``FLAGSx`` specify the flags to be applied. + ``VIDx`` and ``PIDx`` are 4-digit hexadecimal numbers, and can be + specified as ``*`` to match any value. ``FLAGSx`` can be a set of + flags given by name, separated by ``|``, or a hexadecimal number + representing the bit flags. The available flag names are listed below. + An exclamation mark can be prefixed to a flag name to negate the flag. + For example, ``1234:abcd:mixer_playback_min_mute|!ignore_ctl_error;*:*:0x01;`` + applies the ``mixer_playback_min_mute`` flag and clears the + ``ignore_ctl_error`` flag for the device 1234:abcd, and applies the + ``skip_sample_rate`` flag for all devices. + + * bit 0: ``get_sample_rate`` + Skip reading sample rate for devices + * bit 1: ``share_media_device`` + Create Media Controller API entries + * bit 2: ``align_transfer`` + Allow alignment on audio sub-slot at transfer + * bit 3: ``tx_length`` + Add length specifier to transfers + * bit 4: ``playback_first`` + Start playback stream at first in implement feedback mode + * bit 5: ``skip_clock_selector`` + Skip clock selector setup + * bit 6: ``ignore_clock_source`` + Ignore errors from clock source search + * bit 7: ``itf_usb_dsd_dac`` + Indicates ITF-USB DSD-based DACs + * bit 8: ``ctl_msg_delay`` + Add a delay of 20ms at each control message handling + * bit 9: ``ctl_msg_delay_1m`` + Add a delay of 1-2ms at each control message handling + * bit 10: ``ctl_msg_delay_5m`` + Add a delay of 5-6ms at each control message handling + * bit 11: ``iface_delay`` + Add a delay of 50ms at each interface setup + * bit 12: ``validate_rates`` + Perform sample rate validations at probe + * bit 13: ``disable_autosuspend`` + Disable runtime PM autosuspend + * bit 14: ``ignore_ctl_error`` + Ignore errors for mixer access + * bit 15: ``dsd_raw`` + Support generic DSD raw U32_BE format + * bit 16: ``set_iface_first`` + Set up the interface at first like UAC1 + * bit 17: ``generic_implicit_fb`` + Apply the generic implicit feedback sync mode + * bit 18: ``skip_implicit_fb`` + Don't apply implicit feedback sync mode + * bit 19: ``iface_skip_close`` + Don't close interface during setting sample rate + * bit 20: ``force_iface_reset`` + Force an interface reset whenever stopping & restarting a stream + * bit 21: ``fixed_rate`` + Do not set PCM rate (frequency) when only one rate is available + for the given endpoint + * bit 22: ``mic_res_16`` + Set the fixed resolution 16 for Mic Capture Volume + * bit 23: ``mic_res_384`` + Set the fixed resolution 384 for Mic Capture Volume + * bit 24: ``mixer_playback_min_mute`` + Set minimum volume control value as mute for devices where the + lowest playback value represents muted state instead of minimum + audible volume + * bit 25: ``mixer_capture_min_mute`` + Similar to bit 24 but for capture streams This module supports multiple devices, autoprobe and hotplugging. @@ -2314,10 +2379,9 @@ NB: ``nrpacks`` parameter can be modified dynamically via sysfs. Don't put the value over 20. Changing via sysfs has no sanity check. -NB: ``ignore_ctl_error=1`` may help when you get an error at accessing -the mixer element such as URB error -22. This happens on some -buggy USB device or the controller. This workaround corresponds to -the ``quirk_flags`` bit 14, too. +NB: ``ignore_ctl_error=1`` just provides a quick way to work around the +issues. If you have a buggy device that requires these quirks, please +report it to the upstream. NB: ``quirk_alias`` option is provided only for testing / development. If you want to have a proper support, contact to upstream for diff --git a/Documentation/sound/soc/codec.rst b/Documentation/sound/soc/codec.rst index af973c4cac93..b9d87a4f929b 100644 --- a/Documentation/sound/soc/codec.rst +++ b/Documentation/sound/soc/codec.rst @@ -131,8 +131,8 @@ The codec driver also supports the following ALSA PCM operations:- int (*prepare)(struct snd_pcm_substream *); }; -Please refer to the ALSA driver PCM documentation for details. -https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-alsa-driver.html +Please refer to the :doc:`ALSA driver PCM documentation +<../kernel-api/writing-an-alsa-driver>` for details. DAPM description diff --git a/Documentation/sound/soc/platform.rst b/Documentation/sound/soc/platform.rst index 7036630eaf01..bd21d0a4dd9b 100644 --- a/Documentation/sound/soc/platform.rst +++ b/Documentation/sound/soc/platform.rst @@ -45,8 +45,8 @@ snd_soc_component_driver:- ... }; -Please refer to the ALSA driver documentation for details of audio DMA. -https://www.kernel.org/doc/html/latest/sound/kernel-api/writing-an-alsa-driver.html +Please refer to the :doc:`ALSA driver documentation +<../kernel-api/writing-an-alsa-driver>` for details of audio DMA. An example DMA driver is soc/pxa/pxa2xx-pcm.c diff --git a/Documentation/sphinx/parser_yaml.py b/Documentation/sphinx/parser_yaml.py new file mode 100755 index 000000000000..634d84a202fc --- /dev/null +++ b/Documentation/sphinx/parser_yaml.py @@ -0,0 +1,123 @@ +# SPDX-License-Identifier: GPL-2.0 +# Copyright 2025 Mauro Carvalho Chehab <mchehab+huawei@kernel.org> + +""" +Sphinx extension for processing YAML files +""" + +import os +import re +import sys + +from pprint import pformat + +from docutils import statemachine +from docutils.parsers.rst import Parser as RSTParser +from docutils.parsers.rst import states +from docutils.statemachine import ViewList + +from sphinx.util import logging +from sphinx.parsers import Parser + +srctree = os.path.abspath(os.environ["srctree"]) +sys.path.insert(0, os.path.join(srctree, "tools/net/ynl/pyynl/lib")) + +from doc_generator import YnlDocGenerator # pylint: disable=C0413 + +logger = logging.getLogger(__name__) + +class YamlParser(Parser): + """ + Kernel parser for YAML files. + + This is a simple sphinx.Parser to handle yaml files inside the + Kernel tree that will be part of the built documentation. + + The actual parser function is not contained here: the code was + written in a way that parsing yaml for different subsystems + can be done from a single dispatcher. + + All it takes to have parse YAML patches is to have an import line: + + from some_parser_code import NewYamlGenerator + + To this module. Then add an instance of the parser with: + + new_parser = NewYamlGenerator() + + and add a logic inside parse() to handle it based on the path, + like this: + + if "/foo" in fname: + msg = self.new_parser.parse_yaml_file(fname) + """ + + supported = ('yaml', ) + + netlink_parser = YnlDocGenerator() + + re_lineno = re.compile(r"\.\. LINENO ([0-9]+)$") + + tab_width = 8 + + def rst_parse(self, inputstring, document, msg): + """ + Receives a ReST content that was previously converted by the + YAML parser, adding it to the document tree. + """ + + self.setup_parse(inputstring, document) + + result = ViewList() + + self.statemachine = states.RSTStateMachine(state_classes=states.state_classes, + initial_state='Body', + debug=document.reporter.debug_flag) + + try: + # Parse message with RSTParser + lineoffset = 0; + + lines = statemachine.string2lines(msg, self.tab_width, + convert_whitespace=True) + + for line in lines: + match = self.re_lineno.match(line) + if match: + lineoffset = int(match.group(1)) + continue + + result.append(line, document.current_source, lineoffset) + + self.statemachine.run(result, document) + + except Exception as e: + document.reporter.error("YAML parsing error: %s" % pformat(e)) + + self.finish_parse() + + # Overrides docutils.parsers.Parser. See sphinx.parsers.RSTParser + def parse(self, inputstring, document): + """Check if a YAML is meant to be parsed.""" + + fname = document.current_source + + # Handle netlink yaml specs + if "/netlink/specs/" in fname: + msg = self.netlink_parser.parse_yaml_file(fname) + self.rst_parse(inputstring, document, msg) + + # All other yaml files are ignored + +def setup(app): + """Setup function for the Sphinx extension.""" + + # Add YAML parser + app.add_source_parser(YamlParser) + app.add_source_suffix('.yaml', 'yaml') + + return { + 'version': '1.0', + 'parallel_read_safe': True, + 'parallel_write_safe': True, + } diff --git a/Documentation/staging/crc32.rst b/Documentation/staging/crc32.rst index 7542220967cb..64f3dd430a6c 100644 --- a/Documentation/staging/crc32.rst +++ b/Documentation/staging/crc32.rst @@ -34,7 +34,7 @@ do it in the right order, matching the endianness. Just like with ordinary division, you proceed one digit (bit) at a time. Each step of the division you take one more digit (bit) of the dividend and append it to the current remainder. Then you figure out the -appropriate multiple of the divisor to subtract to being the remainder +appropriate multiple of the divisor to subtract to bring the remainder back into range. In binary, this is easy - it has to be either 0 or 1, and to make the XOR cancel, it's just a copy of bit 32 of the remainder. @@ -116,7 +116,7 @@ for any fractional bytes at the end. To reduce the number of conditional branches, software commonly uses the byte-at-a-time table method, popularized by Dilip V. Sarwate, "Computation of Cyclic Redundancy Checks via Table Look-Up", Comm. ACM -v.31 no.8 (August 1998) p. 1008-1013. +v.31 no.8 (August 1988) p. 1008-1013. Here, rather than just shifting one bit of the remainder to decide in the correct multiple to subtract, we can shift a byte at a time. diff --git a/Documentation/tee/index.rst b/Documentation/tee/index.rst index 4be6e69d7837..62afb7ee9b52 100644 --- a/Documentation/tee/index.rst +++ b/Documentation/tee/index.rst @@ -11,6 +11,7 @@ TEE Subsystem op-tee amd-tee ts-tee + qtee .. only:: subproject and html diff --git a/Documentation/tee/qtee.rst b/Documentation/tee/qtee.rst new file mode 100644 index 000000000000..2fa2c1bf6384 --- /dev/null +++ b/Documentation/tee/qtee.rst @@ -0,0 +1,96 @@ +.. SPDX-License-Identifier: GPL-2.0 + +============================================= +QTEE (Qualcomm Trusted Execution Environment) +============================================= + +The QTEE driver handles communication with Qualcomm TEE [1]. + +The lowest level of communication with QTEE builds on the ARM SMC Calling +Convention (SMCCC) [2], which is the foundation for QTEE's Secure Channel +Manager (SCM) [3] used internally by the driver. + +In a QTEE-based system, services are represented as objects with a series of +operations that can be called to produce results, including other objects. + +When an object is hosted within QTEE, executing its operations is referred +to as "direct invocation". QTEE can also invoke objects hosted in the non-secure +world using a method known as "callback request". + +The SCM provides two functions to support direct invocation and callback requests: + +- QCOM_SCM_SMCINVOKE_INVOKE: Used for direct invocation. It can return either + a result or initiate a callback request. +- QCOM_SCM_SMCINVOKE_CB_RSP: Used to submit a response to a callback request + triggered by a previous direct invocation. + +The QTEE Transport Message [4] is stacked on top of the SCM driver functions. + +A message consists of two buffers shared with QTEE: inbound and outbound +buffers. The inbound buffer is used for direct invocation, and the outbound +buffer is used to make callback requests. This picture shows the contents of +a QTEE transport message:: + + +---------------------+ + | v + +-----------------+-------+-------+------+--------------------------+ + | qcomtee_msg_ |object | buffer | | + | object_invoke | id | offset, size | | (inbound buffer) + +-----------------+-------+--------------+--------------------------+ + <---- header -----><---- arguments ------><- in/out buffer payload -> + + +-----------+ + | v + +-----------------+-------+-------+------+----------------------+ + | qcomtee_msg_ |object | buffer | | + | callback | id | offset, size | | (outbound buffer) + +-----------------+-------+--------------+----------------------+ + +Each buffer is started with a header and array of arguments. + +QTEE Transport Message supports four types of arguments: + +- Input Object (IO) is an object parameter to the current invocation + or callback request. +- Output Object (OO) is an object parameter from the current invocation + or callback request. +- Input Buffer (IB) is (offset, size) pair to the inbound or outbound region + to store parameter to the current invocation or callback request. +- Output Buffer (OB) is (offset, size) pair to the inbound or outbound region + to store parameter from the current invocation or callback request. + +Picture of the relationship between the different components in the QTEE +architecture:: + + User space Kernel Secure world + ~~~~~~~~~~ ~~~~~~ ~~~~~~~~~~~~ + +--------+ +----------+ +--------------+ + | Client | |callback | | Trusted | + +--------+ |server | | Application | + /\ +----------+ +--------------+ + || +----------+ /\ /\ + || |callback | || || + || |server | || \/ + || +----------+ || +--------------+ + || /\ || | TEE Internal | + || || || | API | + \/ \/ \/ +--------+--------+ +--------------+ + +---------------------+ | TEE | QTEE | | QTEE | + | libqcomtee [5] | | subsys | driver | | Trusted OS | + +-------+-------------+--+----+-------+----+-------------+--------------+ + | Generic TEE API | | QTEE MSG | + | IOCTL (TEE_IOC_*) | | SMCCC (QCOM_SCM_SMCINVOKE_*) | + +-----------------------------+ +---------------------------------+ + +References +========== + +[1] https://docs.qualcomm.com/bundle/publicresource/topics/80-70015-11/qualcomm-trusted-execution-environment.html + +[2] http://infocenter.arm.com/help/topic/com.arm.doc.den0028a/index.html + +[3] drivers/firmware/qcom/qcom_scm.c + +[4] drivers/tee/qcomtee/qcomtee_msg.h + +[5] https://github.com/quic/quic-teec diff --git a/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst b/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst index 4b3432753eb9..f20bf5be4cf9 100644 --- a/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst +++ b/Documentation/translations/zh_CN/admin-guide/bug-hunting.rst @@ -239,7 +239,7 @@ objdump 例如，您在gspca的sonixj.c文件中发现一个缺陷，则可以通过以下方法找到它的维护者:: $ ./scripts/get_maintainer.pl -f drivers/media/usb/gspca/sonixj.c - Hans Verkuil <hverkuil@xs4all.nl> (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) + Hans Verkuil <hverkuil@kernel.org> (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) Mauro Carvalho Chehab <mchehab@kernel.org> (maintainer:MEDIA INPUT INFRASTRUCTURE (V4L/DVB),commit_signer:1/1=100%) Tejun Heo <tj@kernel.org> (commit_signer:1/1=100%) Bhaktipriya Shridhar <bhaktipriya96@gmail.com> (commit_signer:1/1=100%,authored:1/1=100%,added_lines:4/4=100%,removed_lines:9/9=100%) diff --git a/Documentation/translations/zh_CN/video4linux/v4l2-framework.txt b/Documentation/translations/zh_CN/video4linux/v4l2-framework.txt index 9cc97ec75d7a..f0be21a60a0f 100644 --- a/Documentation/translations/zh_CN/video4linux/v4l2-framework.txt +++ b/Documentation/translations/zh_CN/video4linux/v4l2-framework.txt @@ -775,11 +775,6 @@ v4l2_fh 结构体提供一个保存用于 V4L2 框架的文件句柄特定数据 如果 video_device 标志，新驱动 必须使用 v4l2_fh 结构体，因为它也用于实现优先级处理（VIDIOC_G/S_PRIORITY）。 -v4l2_fh 的用户（位于 V4l2 框架中，并非驱动）可通过测试 -video_device->flags 中的 V4L2_FL_USES_V4L2_FH 位得知驱动是否使用 -v4l2_fh 作为他的 file->private_data 指针。这个位会在调用 v4l2_fh_init() -时被设置。 - v4l2_fh 结构体作为驱动自身文件句柄结构体的一部分被分配，且驱动在 其打开函数中将 file->private_data 指向它。 @@ -812,18 +807,17 @@ int my_open(struct file *file) ... - file->private_data = &my_fh->fh; - v4l2_fh_add(&my_fh->fh); + v4l2_fh_add(&my_fh->fh, file); return 0; } int my_release(struct file *file) { - struct v4l2_fh *fh = file->private_data; + struct v4l2_fh *fh = file_to_v4l2_fh(file); struct my_fh *my_fh = container_of(fh, struct my_fh, fh); ... - v4l2_fh_del(&my_fh->fh); + v4l2_fh_del(&my_fh->fh, file); v4l2_fh_exit(&my_fh->fh); kfree(my_fh); return 0; @@ -836,12 +830,12 @@ void v4l2_fh_init(struct v4l2_fh *fh, struct video_device *vdev) 初始化文件句柄。这*必须*在驱动的 v4l2_file_operations->open() 函数中执行。 -void v4l2_fh_add(struct v4l2_fh *fh) +void v4l2_fh_add(struct v4l2_fh *fh, struct file *filp) 添加一个 v4l2_fh 到 video_device 文件句柄列表。一旦文件句柄 初始化完成就必须调用。 -void v4l2_fh_del(struct v4l2_fh *fh) +void v4l2_fh_del(struct v4l2_fh *fh, struct file *filp) 从 video_device() 中解除文件句柄的关联。文件句柄的退出函数也 将被调用。 diff --git a/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst b/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst index 80ea5677ee52..c677dff826f5 100644 --- a/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst +++ b/Documentation/translations/zh_TW/admin-guide/bug-hunting.rst @@ -242,7 +242,7 @@ objdump 例如，您在gspca的sonixj.c文件中發現一個缺陷，則可以通過以下方法找到它的維護者:: $ ./scripts/get_maintainer.pl -f drivers/media/usb/gspca/sonixj.c - Hans Verkuil <hverkuil@xs4all.nl> (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) + Hans Verkuil <hverkuil@kernel.org> (odd fixer:GSPCA USB WEBCAM DRIVER,commit_signer:1/1=100%) Mauro Carvalho Chehab <mchehab@kernel.org> (maintainer:MEDIA INPUT INFRASTRUCTURE (V4L/DVB),commit_signer:1/1=100%) Tejun Heo <tj@kernel.org> (commit_signer:1/1=100%) Bhaktipriya Shridhar <bhaktipriya96@gmail.com> (commit_signer:1/1=100%,authored:1/1=100%,added_lines:4/4=100%,removed_lines:9/9=100%) diff --git a/Documentation/userspace-api/ioctl/ioctl-number.rst b/Documentation/userspace-api/ioctl/ioctl-number.rst index 406a9f4d0869..7c527a01d1cf 100644 --- a/Documentation/userspace-api/ioctl/ioctl-number.rst +++ b/Documentation/userspace-api/ioctl/ioctl-number.rst @@ -374,6 +374,8 @@ Code Seq# Include File Comments <mailto:linuxppc-dev@lists.ozlabs.org> 0xB2 08 arch/powerpc/include/uapi/asm/papr-physical-attestation.h powerpc/pseries Physical Attestation API <mailto:linuxppc-dev@lists.ozlabs.org> +0xB2 09 arch/powerpc/include/uapi/asm/papr-hvpipe.h powerpc/pseries HVPIPE API + <mailto:linuxppc-dev@lists.ozlabs.org> 0xB3 00 linux/mmc/ioctl.h 0xB4 00-0F linux/gpio.h <mailto:linux-gpio@vger.kernel.org> 0xB5 00-0F uapi/linux/rpmsg.h <mailto:linux-remoteproc@vger.kernel.org> diff --git a/Documentation/userspace-api/media/cec/cec-api.rst b/Documentation/userspace-api/media/cec/cec-api.rst index 578303d484f3..594f0ec420a2 100644 --- a/Documentation/userspace-api/media/cec/cec-api.rst +++ b/Documentation/userspace-api/media/cec/cec-api.rst @@ -26,7 +26,7 @@ Revision and Copyright ********************** Authors: -- Verkuil, Hans <hverkuil-cisco@xs4all.nl> +- Verkuil, Hans <hverkuil@kernel.org> - Initial version. diff --git a/Documentation/userspace-api/media/drivers/camera-sensor.rst b/Documentation/userspace-api/media/drivers/camera-sensor.rst index 919a50e8b9d9..75fd9166383f 100644 --- a/Documentation/userspace-api/media/drivers/camera-sensor.rst +++ b/Documentation/userspace-api/media/drivers/camera-sensor.rst @@ -10,11 +10,13 @@ used to control the camera sensor drivers. You may also find :ref:`media_writing_camera_sensor_drivers` useful. -Frame size ----------- +Sensor internal pipeline configuration +-------------------------------------- -There are two distinct ways to configure the frame size produced by camera -sensors. +Camera sensors have an internal processing pipeline including cropping and +binning functionality. The sensor drivers belong to two distinct classes, freely +configurable and register list-based drivers, depending on how the driver +configures this functionality. Freely configurable camera sensor drivers ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ @@ -26,10 +28,10 @@ of cropping and scaling operations from the device's pixel array's size. An example of such a driver is the CCS driver. -Register list based drivers +Register list-based drivers ~~~~~~~~~~~~~~~~~~~~~~~~~~~ -Register list based drivers generally, instead of able to configure the device +Register list-based drivers generally, instead of able to configure the device they control based on user requests, are limited to a number of preset configurations that combine a number of different parameters that on hardware level are independent. How a driver picks such configuration is based on the @@ -67,7 +69,7 @@ is pixels and the unit of the ``V4L2_CID_VBLANK`` is lines. The pixel rate in the sensor's **pixel array** is specified by ``V4L2_CID_PIXEL_RATE`` in the same sub-device. The unit of that control is pixels per second. -Register list based drivers need to implement read-only sub-device nodes for the +Register list-based drivers need to implement read-only sub-device nodes for the purpose. Devices that are not register list based need these to configure the device's internal processing pipeline. diff --git a/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst b/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst index debde65fb8cd..b617c988b915 100644 --- a/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst +++ b/Documentation/userspace-api/media/drivers/cx2341x-uapi.rst @@ -130,7 +130,7 @@ Raw format c example Format of embedded V4L2_MPEG_STREAM_VBI_FMT_IVTV VBI data --------------------------------------------------------- -Author: Hans Verkuil <hverkuil@xs4all.nl> +Author: Hans Verkuil <hverkuil@kernel.org> This section describes the V4L2_MPEG_STREAM_VBI_FMT_IVTV format of the VBI data diff --git a/Documentation/userspace-api/media/dvb/fe-diseqc-send-burst.rst b/Documentation/userspace-api/media/dvb/fe-diseqc-send-burst.rst index 8fb73ee29951..6ac1e5cd50ce 100644 --- a/Documentation/userspace-api/media/dvb/fe-diseqc-send-burst.rst +++ b/Documentation/userspace-api/media/dvb/fe-diseqc-send-burst.rst @@ -26,7 +26,7 @@ Arguments File descriptor returned by :c:func:`open()`. ``tone`` - An integer enumered value described at :c:type:`fe_sec_mini_cmd`. + An integer enumerated value described at :c:type:`fe_sec_mini_cmd`. Description =========== diff --git a/Documentation/userspace-api/media/dvb/fe-set-tone.rst b/Documentation/userspace-api/media/dvb/fe-set-tone.rst index 9f44bf946183..41cd7111a243 100644 --- a/Documentation/userspace-api/media/dvb/fe-set-tone.rst +++ b/Documentation/userspace-api/media/dvb/fe-set-tone.rst @@ -26,7 +26,7 @@ Arguments File descriptor returned by :c:func:`open()`. ``tone`` - an integer enumered value described at :c:type:`fe_sec_tone_mode` + An integer enumerated value described at :c:type:`fe_sec_tone_mode` Description =========== diff --git a/Documentation/userspace-api/media/dvb/fe-set-voltage.rst b/Documentation/userspace-api/media/dvb/fe-set-voltage.rst index c66771830be1..4d09ca5876f0 100644 --- a/Documentation/userspace-api/media/dvb/fe-set-voltage.rst +++ b/Documentation/userspace-api/media/dvb/fe-set-voltage.rst @@ -26,7 +26,7 @@ Arguments File descriptor returned by :c:func:`open()`. ``voltage`` - an integer enumered value described at :c:type:`fe_sec_voltage` + An integer enumerated value described at :c:type:`fe_sec_voltage` Description =========== diff --git a/Documentation/userspace-api/media/dvb/fe_property_parameters.rst b/Documentation/userspace-api/media/dvb/fe_property_parameters.rst index 1717a0565fe8..ce962d4a02c0 100644 --- a/Documentation/userspace-api/media/dvb/fe_property_parameters.rst +++ b/Documentation/userspace-api/media/dvb/fe_property_parameters.rst @@ -72,11 +72,11 @@ DTV_MODULATION ============== Specifies the frontend modulation type for delivery systems that -supports more multiple modulations. +support multiple modulations. The modulation can be one of the types defined by enum :c:type:`fe_modulation`. -Most of the digital TV standards offers more than one possible +Most of the digital TV standards offer more than one possible modulation type. The table below presents a summary of the types of modulation types @@ -143,9 +143,8 @@ ISDB-T 5MHz, 6MHz, 7MHz and 8MHz, although most places (DTV_ISDBT_SB_SEGMENT_IDX, DTV_ISDBT_SB_SEGMENT_COUNT). #. On Satellite and Cable delivery systems, the bandwidth depends on - the symbol rate. So, the Kernel will silently ignore any setting - :ref:`DTV-BANDWIDTH-HZ`. I will however fill it back with a - bandwidth estimation. + the symbol rate. The kernel will silently ignore any :ref:`DTV-BANDWIDTH-HZ` + setting and overwrites it with bandwidth estimation. Such bandwidth estimation takes into account the symbol rate set with :ref:`DTV-SYMBOL-RATE`, and the rolloff factor, with is fixed for @@ -200,7 +199,7 @@ DTV_VOLTAGE Used on satellite delivery systems. The voltage is usually used with non-DiSEqC capable LNBs to switch the -polarzation (horizontal/vertical). When using DiSEqC epuipment this +polarization (horizontal/vertical). When using DiSEqC equipment this voltage has to be switched consistently to the DiSEqC commands as described in the DiSEqC spec. @@ -280,7 +279,7 @@ DTV_ISDBT_PARTIAL_RECEPTION Used only on ISDB. -If ``DTV_ISDBT_SOUND_BROADCASTING`` is '0' this bit-field represents +If ``DTV_ISDBT_SOUND_BROADCASTING`` is '0' this bit field represents whether the channel is in partial reception mode or not. If '1' ``DTV_ISDBT_LAYERA_*`` values are assigned to the center segment @@ -331,8 +330,8 @@ broadcaster has several possibilities to put those channels in the air: Assuming a normal 13-segment ISDB-T spectrum he can align the 8 segments from position 1-8 to 5-13 or anything in between. -The underlying layer of segments are subchannels: each segment is -consisting of several subchannels with a predefined IDs. A sub-channel +The underlying layer of segments are sub-channels: each segment is +consisting of several sub-channels with a predefined IDs. A sub-channel is used to help the demodulator to synchronize on the channel. An ISDB-T channel is always centered over all sub-channels. As for the @@ -728,7 +727,7 @@ DTV_ATSCMH_RS_FRAME_ENSEMBLE Used only on ATSC-MH. -Reed Solomon(RS) frame ensemble. +Reed Solomon (RS) frame ensemble. The acceptable values are defined by :c:type:`atscmh_rs_frame_ensemble`. @@ -954,14 +953,14 @@ DTV_ENUM_DELSYS A Multi standard frontend needs to advertise the delivery systems provided. Applications need to enumerate the provided delivery systems, -before using any other operation with the frontend. Prior to it's +before using any other operation with the frontend. Prior to its introduction, FE_GET_INFO was used to determine a frontend type. A frontend which provides more than a single delivery system, FE_GET_INFO doesn't help much. Applications which intends to use a multistandard frontend must enumerate the delivery systems associated with it, rather than trying to use FE_GET_INFO. In the case of a legacy frontend, the result is just the same as with FE_GET_INFO, but -in a more structured format +in a more structured format. The acceptable values are defined by :c:type:`fe_delivery_system`. diff --git a/Documentation/userspace-api/media/dvb/frontend-property-terrestrial-systems.rst b/Documentation/userspace-api/media/dvb/frontend-property-terrestrial-systems.rst index 8cd461ceeea7..8aad9ea817f2 100644 --- a/Documentation/userspace-api/media/dvb/frontend-property-terrestrial-systems.rst +++ b/Documentation/userspace-api/media/dvb/frontend-property-terrestrial-systems.rst @@ -52,7 +52,7 @@ DVB-T2 delivery system ====================== DVB-T2 support is currently in the early stages of development, so -expect that this section maygrow and become more detailed with time. +expect that this section may grow and become more detailed with time. The following parameters are valid for DVB-T2: diff --git a/Documentation/userspace-api/media/dvb/intro.rst b/Documentation/userspace-api/media/dvb/intro.rst index 6784ae79657c..854c2073e69a 100644 --- a/Documentation/userspace-api/media/dvb/intro.rst +++ b/Documentation/userspace-api/media/dvb/intro.rst @@ -1,6 +1,6 @@ .. SPDX-License-Identifier: GFDL-1.1-no-invariants-or-later -.. _dvb_introdution: +.. _dvb_introduction: ************ Introduction @@ -125,7 +125,7 @@ demux, CA and IP-over-DVB networking. The video and audio devices control the MPEG2 decoder hardware, the frontend device the tuner and the Digital TV demodulator. The demux device gives you control over the PES and section filters of the hardware. If the hardware does not support -filtering these filters can be implemented in software. Finally, the CA +filtering, these filters can be implemented in software. Finally, the CA device controls all the conditional access capabilities of the hardware. It can depend on the individual security requirements of the platform, if and how many of the CA functions are made available to the diff --git a/Documentation/userspace-api/media/dvb/legacy_dvb_audio.rst b/Documentation/userspace-api/media/dvb/legacy_dvb_audio.rst index b46fe2becd02..81b762ef17c4 100644 --- a/Documentation/userspace-api/media/dvb/legacy_dvb_audio.rst +++ b/Documentation/userspace-api/media/dvb/legacy_dvb_audio.rst @@ -195,7 +195,7 @@ Description ~~~~~~~~~~~ The audio channel selected via `AUDIO_CHANNEL_SELECT`_ is determined by -this values. +this value. ----- @@ -413,7 +413,7 @@ Constants - ``AUDIO_CAP_MP3`` - The hardware accepts MPEG-1 Audio Layer III. - Commomly known as .mp3. + Commonly known as .mp3. - .. diff --git a/Documentation/userspace-api/media/v4l/dev-subdev.rst b/Documentation/userspace-api/media/v4l/dev-subdev.rst index 161b43f1ce66..225a45fef994 100644 --- a/Documentation/userspace-api/media/v4l/dev-subdev.rst +++ b/Documentation/userspace-api/media/v4l/dev-subdev.rst @@ -509,7 +509,7 @@ source pads. .. _subdev-routing: Streams, multiplexed media pads and internal routing ----------------------------------------------------- +==================================================== Simple V4L2 sub-devices do not support multiple, unrelated video streams, and only a single stream can pass through a media link and a media pad. @@ -534,7 +534,7 @@ does not support streams, then only stream 0 of source end may be captured. There may be additional limitations specific to the sink device. Understanding streams -^^^^^^^^^^^^^^^^^^^^^ +--------------------- A stream is a stream of content (e.g. pixel data or metadata) flowing through the media pipeline from a source (e.g. a sensor) towards the final sink (e.g. a @@ -554,7 +554,7 @@ sub-device and a (pad, stream) pair. For sub-devices that do not support multiplexed streams the 'stream' field is always 0. Interaction between routes, streams, formats and selections -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +----------------------------------------------------------- The addition of streams to the V4L2 sub-device interface moves the sub-device formats and selections from pads to (pad, stream) pairs. Besides the @@ -573,7 +573,7 @@ are independent of similar configurations on other streams. This is subject to change in the future. Device types and routing setup -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +------------------------------ Different kinds of sub-devices have differing behaviour for route activation, depending on the hardware. In all cases, however, only routes that have the @@ -596,7 +596,7 @@ called on the sub-device. Such newly created routes have the device's default configuration for format and selection rectangles. Configuring streams -^^^^^^^^^^^^^^^^^^^ +------------------- The configuration of the streams is done individually for each sub-device and the validity of the streams between sub-devices is validated when the pipeline @@ -619,7 +619,7 @@ There are three steps in configuring the streams: :ref:`VIDIOC_SUBDEV_S_ROUTING <VIDIOC_SUBDEV_G_ROUTING>` ioctl. Multiplexed streams setup example -^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ +--------------------------------- A simple example of a multiplexed stream setup might be as follows: diff --git a/Documentation/userspace-api/media/v4l/metafmt-generic.rst b/Documentation/userspace-api/media/v4l/metafmt-generic.rst index 78ab56b21682..39d529c910a8 100644 --- a/Documentation/userspace-api/media/v4l/metafmt-generic.rst +++ b/Documentation/userspace-api/media/v4l/metafmt-generic.rst @@ -71,7 +71,7 @@ This format is little endian. **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_10.** Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding. -.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{.8cm}| +.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.8cm}| .. flat-table:: Sample 4x2 Metadata Frame :header-rows: 0 @@ -115,7 +115,7 @@ This format is little endian. **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_12.** Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding. -.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{.8cm}|p{.8cm}| +.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.8cm}|p{1.2cm}|p{1.2cm}|p{1.8cm}| .. flat-table:: Sample 4x2 Metadata Frame :header-rows: 0 @@ -156,7 +156,7 @@ This format is little endian. **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_14.** Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding. -.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{.8cm}|p{.8cm}|p{.8cm}| +.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.8cm}|p{1.8cm}|p{1.8cm}| .. flat-table:: Sample 4x2 Metadata Frame :header-rows: 0 @@ -252,7 +252,7 @@ This format is little endian. **Byte Order Of V4L2_META_FMT_GENERIC_CSI2_20.** Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding. -.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{.8cm}|p{1.2cm}|p{.8cm}|p{.8cm}|p{1.2cm}|p{.8cm}|p{1.2cm}|p{.8cm}|p{.8cm}| +.. tabularcolumns:: |p{2.4cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.8cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.2cm}|p{1.8cm} .. flat-table:: Sample 4x2 Metadata Frame :header-rows: 0 diff --git a/Documentation/userspace-api/media/v4l/v4l2.rst b/Documentation/userspace-api/media/v4l/v4l2.rst index cf8ae56a008c..64fb264fb6c4 100644 --- a/Documentation/userspace-api/media/v4l/v4l2.rst +++ b/Documentation/userspace-api/media/v4l/v4l2.rst @@ -86,7 +86,7 @@ Authors, in alphabetical order: - Documented the fielded V4L2_MPEG_STREAM_VBI_FMT_IVTV MPEG stream embedded, sliced VBI data format in this specification. -- Verkuil, Hans <hverkuil@xs4all.nl> +- Verkuil, Hans <hverkuil@kernel.org> - Designed and documented the VIDIOC_LOG_STATUS ioctl, the extended control ioctls, major parts of the sliced VBI API, the MPEG encoder and decoder APIs and the DV Timings API. diff --git a/Documentation/userspace-api/netlink/index.rst b/Documentation/userspace-api/netlink/index.rst index c1b6765cc963..83ae25066591 100644 --- a/Documentation/userspace-api/netlink/index.rst +++ b/Documentation/userspace-api/netlink/index.rst @@ -18,4 +18,4 @@ Netlink documentation for users. See also: - :ref:`Documentation/core-api/netlink.rst <kernel_netlink>` - - :ref:`Documentation/networking/netlink_spec/index.rst <specs>` + - :ref:`Documentation/netlink/specs/index.rst <specs>` diff --git a/Documentation/userspace-api/netlink/netlink-raw.rst b/Documentation/userspace-api/netlink/netlink-raw.rst index 31fc91020eb3..aae296c170c5 100644 --- a/Documentation/userspace-api/netlink/netlink-raw.rst +++ b/Documentation/userspace-api/netlink/netlink-raw.rst @@ -62,8 +62,8 @@ Sub-messages ------------ Several raw netlink families such as -:doc:`rt-link<../../networking/netlink_spec/rt-link>` and -:doc:`tc<../../networking/netlink_spec/tc>` use attribute nesting as an +:ref:`rt-link<netlink-rt-link>` and +:ref:`tc<netlink-tc>` use attribute nesting as an abstraction to carry module specific information. Conceptually it looks as follows:: @@ -162,7 +162,7 @@ then this is an error. Nested struct definitions ------------------------- -Many raw netlink families such as :doc:`tc<../../networking/netlink_spec/tc>` +Many raw netlink families such as :ref:`tc<netlink-tc>` make use of nested struct definitions. The ``netlink-raw`` schema makes it possible to embed a struct within a struct definition using the ``struct`` property. For example, the following struct definition embeds the diff --git a/Documentation/userspace-api/netlink/specs.rst b/Documentation/userspace-api/netlink/specs.rst index 1b50d97d8d7c..debb4bfca5c4 100644 --- a/Documentation/userspace-api/netlink/specs.rst +++ b/Documentation/userspace-api/netlink/specs.rst @@ -15,7 +15,7 @@ kernel headers directly. Internally kernel uses the YAML specs to generate: - the C uAPI header - - documentation of the protocol as a ReST file - see :ref:`Documentation/networking/netlink_spec/index.rst <specs>` + - documentation of the protocol as a ReST file - see :ref:`Documentation/netlink/specs/index.rst <specs>` - policy tables for input attribute validation - operation tables |