diff options
Diffstat (limited to 'arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi')
| -rw-r--r-- | arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi | 115 |
1 files changed, 113 insertions, 2 deletions
diff --git a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi index 04e99cd7e74b..a5c2025a616e 100644 --- a/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi +++ b/arch/arm64/boot/dts/intel/socfpga_agilex5.dtsi @@ -37,6 +37,7 @@ reg = <0x0>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu1: cpu@1 { @@ -44,6 +45,7 @@ reg = <0x100>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu2: cpu@2 { @@ -51,6 +53,7 @@ reg = <0x200>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; }; cpu3: cpu@3 { @@ -58,6 +61,30 @@ reg = <0x300>; device_type = "cpu"; enable-method = "psci"; + next-level-cache = <&L2>; + }; + + L2: l2-cache { + compatible = "cache"; + cache-level = <2>; + next-level-cache = <&L3>; + cache-unified; + }; + + L3: l3-cache { + compatible = "cache"; + cache-level = <3>; + cache-unified; + }; + + }; + + firmware { + svc { + compatible = "intel,agilex5-svc"; + method = "smc"; + memory-region = <&service_reserved>; + iommus = <&smmu 10>; }; }; @@ -75,8 +102,11 @@ #address-cells = <2>; #size-cells = <2>; interrupt-controller; + interrupt-parent = <&intc>; #redistributor-regions = <1>; redistributor-stride = <0x0 0x20000>; + /* VGIC maintenance interrupt */ + interrupts = <GIC_PPI 25 IRQ_TYPE_LEVEL_HIGH>; its: msi-controller@1d040000 { compatible = "arm,gic-v3-its"; @@ -133,6 +163,12 @@ compatible = "usb-nop-xceiv"; }; + pmu0: pmu { + compatible = "arm,armv8-pmuv3"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; + }; + soc: soc@0 { compatible = "simple-bus"; ranges = <0 0 0 0xffffffff>; @@ -203,7 +239,8 @@ }; i3c0: i3c@10da0000 { - compatible = "snps,dw-i3c-master-1.00a"; + compatible = "altr,agilex5-dw-i3c-master", + "snps,dw-i3c-master-1.00a"; reg = <0x10da0000 0x1000>; #address-cells = <3>; #size-cells = <0>; @@ -213,7 +250,8 @@ }; i3c1: i3c@10da1000 { - compatible = "snps,dw-i3c-master-1.00a"; + compatible = "altr,agilex5-dw-i3c-master", + "snps,dw-i3c-master-1.00a"; reg = <0x10da1000 0x1000>; #address-cells = <3>; #size-cells = <0>; @@ -271,7 +309,9 @@ #size-cells = <0>; interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clkmgr AGILEX5_NAND_NF_CLK>; + clock-names = "nf_clk"; cdns,board-delay-ps = <4830>; + iommus = <&smmu 4>; status = "disabled"; }; @@ -298,6 +338,7 @@ snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; + iommus = <&smmu 8>; }; dmac1: dma-controller@10dc0000 { @@ -315,6 +356,7 @@ snps,block-size = <32767 32767 32767 32767>; snps,priority = <0 1 2 3>; snps,axi-max-burst-len = <8>; + iommus = <&smmu 9>; }; rst: rstmgr@10d11000 { @@ -323,6 +365,18 @@ #reset-cells = <1>; }; + smmu: iommu@16000000 { + compatible = "arm,smmu-v3"; + reg = <0x16000000 0x30000>; + interrupts = <GIC_SPI 134 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 129 IRQ_TYPE_EDGE_RISING>, + <GIC_SPI 132 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "eventq", "gerror", "priq"; + dma-coherent; + #iommu-cells = <1>; + status = "disabled"; + }; + spi0: spi@10da4000 { compatible = "snps,dw-apb-ssi"; reg = <0x10da4000 0x1000>; @@ -423,6 +477,7 @@ phy-names = "usb2-phy"; resets = <&rst USB0_RESET>, <&rst USB0_OCP_RESET>; reset-names = "dwc2", "dwc2-ecc"; + iommus = <&smmu 6>; clocks = <&clkmgr AGILEX5_USB2OTG_HCLK>; clock-names = "otg"; status = "disabled"; @@ -822,5 +877,61 @@ }; }; }; + + pmu0_tcu: pmu@16002000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16002000 0x1000>, + <0x16022000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 136 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu0: pmu@16042000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16042000 0x1000>, + <0x16052000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 138 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu1: pmu@16062000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16062000 0x1000>, + <0x16072000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 140 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu2: pmu@16082000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x16082000 0x1000>, + <0x16092000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 142 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu3: pmu@160a2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160A2000 0x1000>, + <0x160B2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 144 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu4: pmu@160c2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160C2000 0x1000>, + <0x160D2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 146 IRQ_TYPE_EDGE_RISING>; + }; + + pmu0_tbu5: pmu@160e2000 { + compatible = "arm,smmu-v3-pmcg"; + reg = <0x160E2000 0x1000>, + <0x160F2000 0x1000>; + interrupt-parent = <&intc>; + interrupts = <GIC_SPI 150 IRQ_TYPE_EDGE_RISING>; + }; }; }; |