diff options
Diffstat (limited to 'include/asm-ppc/processor.h')
| -rw-r--r-- | include/asm-ppc/processor.h | 165 |
1 files changed, 130 insertions, 35 deletions
diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f5b55b80e247..0ed0a0070075 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.processor.h 1.31 10/05/01 16:26:22 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef __ASM_PPC_PROCESSOR_H @@ -12,6 +12,7 @@ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) #include <linux/config.h> +#include <linux/stringify.h> #include <asm/ptrace.h> #include <asm/types.h> @@ -136,10 +137,32 @@ #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#define DBSR_IC 0x80000000 /* Instruction Completion */ -#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ +#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ +#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ +#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ +#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ +#define DBCR0_RST_NONE 0x00000000 /* No Reset */ +#define DBCR0_IC 0x08000000 /* Instruction Completion */ +#define DBCR0_BT 0x04000000 /* Branch Taken */ +#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ +#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ +#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ +#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ +#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ +#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ +#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ +#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ +#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ +#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#define DBSR_IC 0x80000000 /* Instruction Completion */ +#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ @@ -191,12 +214,17 @@ #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ #define HID0_SBCLK (1<<27) #define HID0_EICE (1<<26) +#define HID0_TBEN (1<<26) /* Timebase enable - 7450 */ #define HID0_ECLK (1<<25) #define HID0_PAR (1<<24) +#define HID0_STEN (1<<24) /* S/W Tablewalk enable - 7450 */ #define HID0_DOZE (1<<23) #define HID0_NAP (1<<22) #define HID0_SLEEP (1<<21) #define HID0_DPM (1<<20) +#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ +#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ +#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ #define HID0_ICE (1<<15) /* Instruction Cache Enable */ #define HID0_DCE (1<<14) /* Data Cache Enable */ #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ @@ -207,11 +235,23 @@ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ +#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ +#define HID0_LRSTK (1<<4) /* Link Stack enable - 7450 */ #define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_FOLD (1<<3) /* Branch Folding enable - 7450 */ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ +#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ + #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ +#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ +#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ +#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ +#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ +#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ +#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ @@ -229,6 +269,10 @@ #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ +#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ +#define ICTRL_EDCE 0x04000000 /* enable dcache parity errs */ +#define ICTRL_EICP 0x00000100 /* enable icache par. check */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ @@ -261,6 +305,13 @@ #define L2CR_L2DF 0x00004000 /* L2 differential clock */ #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ +#define SPRN_L2CR2 0x3f8 +#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter (7450) */ +#define L3CR_L3E 0x80000000 /* L3 enable */ +#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ +#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ +#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ +#define SPRN_LDSTDB 0x3f4 /* */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ @@ -275,6 +326,8 @@ #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ +#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ #define SPRN_PVR 0x11F /* Processor Version Register */ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ @@ -295,17 +348,23 @@ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_TBHI 0x3DC /* Time Base High (4xx) */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode (4xx) */ +#define SPRN_TBLO 0x3DD /* Time Base Low (4xx) */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode (4xx) */ #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ -#define SPRN_TBWL 0x11C /* Time Base Lower Register (supervisor, R/W) */ -#define SPRN_TBWU 0x11D /* Time Base Upper Register (supervisor, R/W) */ +#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ +#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ #define SPRN_TCR 0x3DA /* Timer Control Register */ #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define TCR_WP_MASK TCR_WP(3) #define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ #define WP_2_25 2 /* 2^25 clocks */ #define WP_2_29 3 /* 2^29 clocks */ #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define TCR_WRC_MASK TCR_WRC(3) #define WRC_NONE 0 /* No reset will occur */ #define WRC_CORE 1 /* Core reset will occur */ #define WRC_CHIP 2 /* Chip reset will occur */ @@ -313,6 +372,7 @@ #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define TCR_FP_MASK TCR_FP(3) #define FP_2_9 0 /* 2^9 clocks */ #define FP_2_13 1 /* 2^13 clocks */ #define FP_2_17 2 /* 2^17 clocks */ @@ -331,6 +391,7 @@ #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ #define THRM3_E (1<<0) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ #define SPRN_TSR 0x3D8 /* Timer Status Register */ #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ @@ -387,6 +448,7 @@ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define L3CR SPRN_L3CR /* PPC 7450 L3 Cache control register */ #define LR SPRN_LR #define PVR SPRN_PVR /* Processor Version */ #define RPA SPRN_RPA /* Required Physical Address Register */ @@ -445,7 +507,9 @@ #define PVR_403GC 0x00200200 #define PVR_403GCX 0x00201400 #define PVR_405GP 0x40110000 -#define PVR_STB03XXX 0x40310000 +#define PVR_STB03XXX 0x40310000 +#define PVR_NP405H 0x41410000 +#define PVR_NP405L 0x41610000 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -462,6 +526,7 @@ #define PVR_750P PVR_740P #define PVR_7400 0x000C0000 #define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be @@ -473,6 +538,7 @@ #define PVR_850 PVR_821 #define PVR_860 PVR_821 #define PVR_8240 0x00810100 +#define PVR_8245 0x80811014 #define PVR_8260 PVR_8240 /* We only need to define a new _MACH_xxx for machines which are part of @@ -494,6 +560,7 @@ #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ #define _GLOBAL(n)\ + .stabs __stringify(n:F-1),N_FUN,0,0,n;\ .globl n;\ n: @@ -502,11 +569,6 @@ n: #define stringify(s) tostring(s) #define tostring(s) #s -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) - #define mfmsr() ({unsigned int rval; \ asm volatile("mfmsr %0" : "=r" (rval)); rval;}) #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) @@ -516,6 +578,35 @@ n: : "=r" (rval)); rval;}) #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) +#define mfsrin(v) ({unsigned int rval; \ + asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ + rval;}) + +#define proc_trap() asm volatile("trap") + +#ifdef CONFIG_PPC_ISERIES +/* Macros for adjusting thread priority (hardware multi-threading) */ +#define HMT_PRIO_LOW "or 1,1,1\n" /* low prio, used for spin loops */ +#define HMT_PRIO_MED "or 2,2,2\n" /* medium prio, for normal code */ +#define HMT_PRIO_HIGH "or 3,3,3\n" /* high priority */ + +#define HMT_low() asm volatile("or 1,1,1") +#define HMT_medium() asm volatile("or 2,2,2") +#define HMT_high() asm volatile("or 3,3,3") + +/* iSeries CTRL register (for runlatch) */ + +#define CTRLT 0x098 +#define CTRLF 0x088 +#define RUNLATCH 0x0001 + +#else /* !CONFIG_PPC_ISERIES */ +#define HMT_PRIO_LOW +#define HMT_PRIO_MED +#define HMT_PRIO_HIGH + +#endif /* CONFIG_PPC_ISERIES */ + /* Segment Registers */ #define SR0 0 @@ -580,7 +671,11 @@ extern struct task_struct *last_task_used_altivec; * as soon as I get around to remapping the io areas with the BATs * to match the mac we can raise this. -- Cort */ +#ifdef CONFIG_TASK_SIZE_BOOL +#define TASK_SIZE CONFIG_TASK_SIZE +#else #define TASK_SIZE (0x80000000UL) +#endif /* This decides where the kernel will search for a free chunk of vm * space during mmap's. @@ -593,10 +688,10 @@ typedef struct { struct thread_struct { unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ struct pt_regs *regs; /* Pointer to saved register state */ mm_segment_t fs; /* for get_fs() validation */ void *pgdir; /* root of page-table tree */ + int fpexc_mode; /* floating-point exception mode */ signed long last_syscall; double fpr[32]; /* Complete floating point set */ unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ @@ -611,13 +706,9 @@ struct thread_struct { #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) #define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - 0, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ + ksp: INIT_SP, \ + fs: KERNEL_DS, \ + pgdir: swapper_pg_dir, \ } /* @@ -636,25 +727,31 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) +/* Get/set floating-point exception mode */ +#define GET_FP_EXC_MODE(tsk) __unpack_fe01((tsk)->thread.fpexc_mode) +#define SET_FP_EXC_MODE(tsk, val) set_fpexc_mode((tsk), (val)) + +extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); + +static inline unsigned int __unpack_fe01(unsigned int msr_bits) +{ + return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); +} + +static inline unsigned int __pack_fe01(unsigned int fpmode) +{ + return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); +} /* in process.c - for early bootup debug -- Cort */ int ll_printk(const char *, ...); void ll_puts(const char *); -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - /* In misc.c */ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); +#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac) + #define cpu_relax() do { } while (0) /* @@ -678,7 +775,5 @@ extern inline void prefetchw(const void *x) #endif /* !__ASSEMBLY__ */ -#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac) - #endif /* __ASM_PPC_PROCESSOR_H */ #endif /* __KERNEL__ */ |