diff options
Diffstat (limited to 'include')
115 files changed, 10153 insertions, 2145 deletions
diff --git a/include/asm-ppc/8xx_immap.h b/include/asm-ppc/8xx_immap.h index b0377a911d6f..731a24ffba6c 100644 --- a/include/asm-ppc/8xx_immap.h +++ b/include/asm-ppc/8xx_immap.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.8xx_immap.h 1.5 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* @@ -178,7 +178,7 @@ typedef struct cark { */ #define KAPWR_KEY ((unsigned int)0x55ccaa33) -/* LCD interface. MPC821 Only. +/* LCD interface. MPC821 and MPC823 Only. */ typedef struct lcd { ushort lcd_lcolr[16]; @@ -353,6 +353,12 @@ typedef struct fec { uint res9[0x1e]; } fec_t; +/* We need this as the fec and fb cmap use the same address space */ +union fec_lcd { + fec_t fl_un_fec; + u_char fl_un_cmap[0x200]; +}; + typedef struct comm_proc { /* General control and status registers. */ @@ -424,8 +430,12 @@ typedef struct comm_proc { /* The fast ethernet controller is not really part of the CPM, * but it resides in the address space. + * + * The colormap for the LCD controller is also located here */ - fec_t cp_fec; + union fec_lcd fl_un; +#define cp_fec fl_un.fl_un_fec +#define lcd_cmap fl_un.fl_un_cmap char res18[0x1000]; /* Dual Ported RAM follows. @@ -447,7 +457,7 @@ typedef struct immap { car8xx_t im_clkrst; /* Clocks and reset */ sitk8xx_t im_sitk; /* Sys int timer keys */ cark8xx_t im_clkrstk; /* Clocks and reset keys */ - lcd8xx_t im_lcd; /* LCD (821 only) */ + lcd8xx_t im_lcd; /* LCD (821 and 823 only) */ i2c8xx_t im_i2c; /* I2C control/status */ sdma8xx_t im_sdma; /* SDMA control/status */ cpic8xx_t im_cpic; /* CPM Interrupt Controller */ diff --git a/include/asm-ppc/amigaints.h b/include/asm-ppc/amigaints.h index 672491b10aa6..2e0077946d4c 100644 --- a/include/asm-ppc/amigaints.h +++ b/include/asm-ppc/amigaints.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.amigaints.h 1.5 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* ** amigaints.h -- Amiga Linux interrupt handling structs and prototypes @@ -110,12 +110,8 @@ #define IF_DSKBLK 0x0002 /* diskblock DMA finished */ #define IF_TBE 0x0001 /* serial transmit buffer empty interrupt */ -struct irq_server { - unsigned short count, reentrance; -}; - extern void amiga_do_irq(int irq, struct pt_regs *fp); -extern void amiga_do_irq_list(int irq, struct pt_regs *fp, struct irq_server *server); +extern void amiga_do_irq_list(int irq, struct pt_regs *fp); /* CIA interrupt control register bits */ diff --git a/include/asm-ppc/ans-lcd.h b/include/asm-ppc/ans-lcd.h new file mode 100644 index 000000000000..d795b9fd2db6 --- /dev/null +++ b/include/asm-ppc/ans-lcd.h @@ -0,0 +1,11 @@ +#ifndef _PPC_ANS_LCD_H +#define _PPC_ANS_LCD_H + +#define ANSLCD_MINOR 156 + +#define ANSLCD_CLEAR 0x01 +#define ANSLCD_SENDCTRL 0x02 +#define ANSLCD_SETSHORTDELAY 0x03 +#define ANSLCD_SETLONGDELAY 0x04 + +#endif diff --git a/include/asm-ppc/atomic.h b/include/asm-ppc/atomic.h index 2b4f9f06babe..63e194a43944 100644 --- a/include/asm-ppc/atomic.h +++ b/include/asm-ppc/atomic.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.atomic.h 1.15 10/28/01 10:37:22 trini + * BK Id: %F% %I% %G% %U% %#% */ /* * PowerPC atomic operations @@ -18,7 +18,6 @@ typedef struct { volatile int counter; } atomic_t; #define atomic_set(v,i) (((v)->counter) = (i)) extern void atomic_clear_mask(unsigned long mask, unsigned long *addr); -extern void atomic_set_mask(unsigned long mask, unsigned long *addr); #ifdef CONFIG_SMP #define SMP_ISYNC "\n\tisync" @@ -26,14 +25,24 @@ extern void atomic_set_mask(unsigned long mask, unsigned long *addr); #define SMP_ISYNC #endif +/* Erratum #77 on the 405 means we need a sync or dcbt before every stwcx. + * The old ATOMIC_SYNC_FIX covered some but not all of this. + */ +#ifdef CONFIG_IBM405_ERR77 +#define PPC405_ERR77(ra,rb) "dcbt " #ra "," #rb ";" +#else +#define PPC405_ERR77(ra,rb) +#endif + static __inline__ void atomic_add(int a, atomic_t *v) { int t; __asm__ __volatile__( "1: lwarx %0,0,%3 # atomic_add\n\ - add %0,%2,%0\n\ - stwcx. %0,0,%3\n\ + add %0,%2,%0\n" + PPC405_ERR77(0,%3) +" stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (t), "=m" (v->counter) : "r" (a), "r" (&v->counter), "m" (v->counter) @@ -46,8 +55,9 @@ static __inline__ int atomic_add_return(int a, atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%2 # atomic_add_return\n\ - add %0,%1,%0\n\ - stwcx. %0,0,%2\n\ + add %0,%1,%0\n" + PPC405_ERR77(0,%2) +" stwcx. %0,0,%2 \n\ bne- 1b" SMP_ISYNC : "=&r" (t) @@ -63,8 +73,9 @@ static __inline__ void atomic_sub(int a, atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%3 # atomic_sub\n\ - subf %0,%2,%0\n\ - stwcx. %0,0,%3\n\ + subf %0,%2,%0\n" + PPC405_ERR77(0,%3) +" stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (t), "=m" (v->counter) : "r" (a), "r" (&v->counter), "m" (v->counter) @@ -77,8 +88,9 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%2 # atomic_sub_return\n\ - subf %0,%1,%0\n\ - stwcx. %0,0,%2\n\ + subf %0,%1,%0\n" + PPC405_ERR77(0,%2) +" stwcx. %0,0,%2 \n\ bne- 1b" SMP_ISYNC : "=&r" (t) @@ -94,8 +106,9 @@ static __inline__ void atomic_inc(atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%2 # atomic_inc\n\ - addic %0,%0,1\n\ - stwcx. %0,0,%2\n\ + addic %0,%0,1\n" + PPC405_ERR77(0,%2) +" stwcx. %0,0,%2 \n\ bne- 1b" : "=&r" (t), "=m" (v->counter) : "r" (&v->counter), "m" (v->counter) @@ -108,8 +121,9 @@ static __inline__ int atomic_inc_return(atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%1 # atomic_inc_return\n\ - addic %0,%0,1\n\ - stwcx. %0,0,%1\n\ + addic %0,%0,1\n" + PPC405_ERR77(0,%1) +" stwcx. %0,0,%1 \n\ bne- 1b" SMP_ISYNC : "=&r" (t) @@ -125,8 +139,9 @@ static __inline__ void atomic_dec(atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%2 # atomic_dec\n\ - addic %0,%0,-1\n\ - stwcx. %0,0,%2\n\ + addic %0,%0,-1\n" + PPC405_ERR77(0,%2)\ +" stwcx. %0,0,%2\n\ bne- 1b" : "=&r" (t), "=m" (v->counter) : "r" (&v->counter), "m" (v->counter) @@ -139,8 +154,9 @@ static __inline__ int atomic_dec_return(atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%1 # atomic_dec_return\n\ - addic %0,%0,-1\n\ - stwcx. %0,0,%1\n\ + addic %0,%0,-1\n" + PPC405_ERR77(0,%1) +" stwcx. %0,0,%1\n\ bne- 1b" SMP_ISYNC : "=&r" (t) @@ -164,8 +180,9 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v) __asm__ __volatile__( "1: lwarx %0,0,%1 # atomic_dec_if_positive\n\ addic. %0,%0,-1\n\ - blt- 2f\n\ - stwcx. %0,0,%1\n\ + blt- 2f\n" + PPC405_ERR77(0,%1) +" stwcx. %0,0,%1\n\ bne- 1b" SMP_ISYNC "\n\ diff --git a/include/asm-ppc/bitops.h b/include/asm-ppc/bitops.h index 3d93c47dd223..8dbd9c4ac057 100644 --- a/include/asm-ppc/bitops.h +++ b/include/asm-ppc/bitops.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.bitops.h 1.9 05/26/01 14:48:14 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * bitops.h: Bit string operations on the ppc @@ -11,6 +11,7 @@ #include <linux/config.h> #include <asm/byteorder.h> +#include <asm/atomic.h> /* * The test_and_*_bit operations are taken to imply a memory barrier @@ -36,8 +37,9 @@ static __inline__ void set_bit(int nr, volatile void * addr) __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ - or %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ + or %0,%0,%2 \n" + PPC405_ERR77(0,%3) +" stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) @@ -69,8 +71,9 @@ static __inline__ void clear_bit(int nr, volatile void *addr) __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ - andc %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ + andc %0,%0,%2 \n" + PPC405_ERR77(0,%3) +" stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) @@ -96,8 +99,9 @@ static __inline__ void change_bit(int nr, volatile void *addr) __asm__ __volatile__("\n\ 1: lwarx %0,0,%3 \n\ - xor %0,%0,%2 \n\ - stwcx. %0,0,%3 \n\ + xor %0,%0,%2 \n" + PPC405_ERR77(0,%3) +" stwcx. %0,0,%3 \n\ bne- 1b" : "=&r" (old), "=m" (*p) : "r" (mask), "r" (p), "m" (*p) @@ -126,8 +130,9 @@ static __inline__ int test_and_set_bit(int nr, volatile void *addr) __asm__ __volatile__(SMP_WMB "\n\ 1: lwarx %0,0,%4 \n\ - or %1,%0,%3 \n\ - stwcx. %1,0,%4 \n\ + or %1,%0,%3 \n" + PPC405_ERR77(0,%4) +" stwcx. %1,0,%4 \n\ bne 1b" SMP_MB : "=&r" (old), "=&r" (t), "=m" (*p) @@ -158,8 +163,9 @@ static __inline__ int test_and_clear_bit(int nr, volatile void *addr) __asm__ __volatile__(SMP_WMB "\n\ 1: lwarx %0,0,%4 \n\ - andc %1,%0,%3 \n\ - stwcx. %1,0,%4 \n\ + andc %1,%0,%3 \n" + PPC405_ERR77(0,%4) +" stwcx. %1,0,%4 \n\ bne 1b" SMP_MB : "=&r" (old), "=&r" (t), "=m" (*p) @@ -190,8 +196,9 @@ static __inline__ int test_and_change_bit(int nr, volatile void *addr) __asm__ __volatile__(SMP_WMB "\n\ 1: lwarx %0,0,%4 \n\ - xor %1,%0,%3 \n\ - stwcx. %1,0,%4 \n\ + xor %1,%0,%3 \n" + PPC405_ERR77(0,%4) +" stwcx. %1,0,%4 \n\ bne 1b" SMP_MB : "=&r" (old), "=&r" (t), "=m" (*p) @@ -239,6 +246,11 @@ static __inline__ int ffz(unsigned int x) #ifdef __KERNEL__ +static inline int __ffs(unsigned long x) +{ + return __ilog2(x & -x); +} + /* * ffs: find first bit set. This is defined the same way as * the libc and compiler builtin ffs routines, therefore diff --git a/include/asm-ppc/board.h b/include/asm-ppc/board.h deleted file mode 100644 index f10e17bf3a8a..000000000000 --- a/include/asm-ppc/board.h +++ /dev/null @@ -1,47 +0,0 @@ -/* - * BK Id: SCCS/s.board.h 1.5 05/17/01 18:14:24 cort - */ -/* - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: board.h - * - * Description: - * A generic include file which pulls in appropriate include files - * for specific board types based on configuration settings. - * - */ - -#ifdef __KERNEL__ -#ifndef __BOARD_H__ -#define __BOARD_H__ - -#include <linux/config.h> - -#if defined(CONFIG_OAK) -#include <asm/oak.h> -#endif - -#if defined(CONFIG_WALNUT) -#include <asm/walnut.h> -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ - -extern unsigned char __res[]; - - -#ifdef __cplusplus -} -#endif - -#endif /* __BOARD_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/bootinfo.h b/include/asm-ppc/bootinfo.h index 1eaf18c87c5c..8be46d7fd3fc 100644 --- a/include/asm-ppc/bootinfo.h +++ b/include/asm-ppc/bootinfo.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.bootinfo.h 1.11 08/17/01 15:23:17 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * Non-machine dependent bootinfo structure. Basic idea @@ -19,9 +19,9 @@ #else struct bi_record { - unsigned long tag; /* tag ID */ - unsigned long size; /* size of record (in bytes) */ - unsigned long data[0]; /* data */ + unsigned long tag; /* tag ID */ + unsigned long size; /* size of record (in bytes) */ + unsigned long data[0]; /* data */ }; #define BI_FIRST 0x1010 /* first record - marker */ @@ -33,6 +33,9 @@ struct bi_record { #define BI_MACHTYPE 0x1016 #define BI_MEMSIZE 0x1017 +extern struct bi_record *find_bootinfo(void); +extern void parse_bootinfo(struct bi_record *rec); + #endif /* CONFIG_APUS */ diff --git a/include/asm-ppc/btext.h b/include/asm-ppc/btext.h index efdea49d509c..7fc031e1641f 100644 --- a/include/asm-ppc/btext.h +++ b/include/asm-ppc/btext.h @@ -17,11 +17,11 @@ extern void btext_flushscreen(void); extern unsigned long disp_BAT[2]; -extern boot_infos_t *disp_bi; +extern boot_infos_t disp_bi; extern int boot_text_mapped; void btext_init(boot_infos_t *bi); -void btext_welcome(boot_infos_t* bi); +void btext_welcome(void); void btext_prepare_BAT(void); void btext_setup_display(int width, int height, int depth, int pitch, unsigned long address); diff --git a/include/asm-ppc/byteorder.h b/include/asm-ppc/byteorder.h index 1a5f6094882f..3d0b62e6d59c 100644 --- a/include/asm-ppc/byteorder.h +++ b/include/asm-ppc/byteorder.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.byteorder.h 1.8 10/11/01 13:02:49 trini + * BK Id: %F% %I% %G% %U% %#% */ #ifndef _PPC_BYTEORDER_H #define _PPC_BYTEORDER_H @@ -35,17 +35,11 @@ extern __inline__ void st_le32(volatile unsigned *addr, const unsigned val) __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*addr) : "r" (val), "r" (addr)); } -/* alas, egcs sounds like it has a bug in this code that doesn't use the - inline asm correctly, and can cause file corruption. Until I hear that - it's fixed, I can live without the extra speed. I hope. */ -#if 0 static __inline__ __const__ __u16 ___arch__swab16(__u16 value) { __u16 result; - __asm__("rlwimi %0,%1,8,16,23" - : "=r" (result) - : "r" (value), "0" (value >> 8)); + __asm__("rlwimi %0,%2,8,16,23" : "=&r" (result) : "0" (value >> 8), "r" (value)); return result; } @@ -53,16 +47,14 @@ static __inline__ __const__ __u32 ___arch__swab32(__u32 value) { __u32 result; - __asm__("rlwimi %0,%1,24,16,23\n\t" - "rlwimi %0,%1,8,8,15\n\t" - "rlwimi %0,%1,24,0,7" - : "=r" (result) - : "r" (value), "0" (value >> 24)); + __asm__("rlwimi %0,%2,24,16,23" : "=&r" (result) : "0" (value>>24), "r" (value)); + __asm__("rlwimi %0,%2,8,8,15" : "=&r" (result) : "0" (result), "r" (value)); + __asm__("rlwimi %0,%2,24,0,7" : "=&r" (result) : "0" (result), "r" (value)); + return result; } #define __arch__swab32(x) ___arch__swab32(x) #define __arch__swab16(x) ___arch__swab16(x) -#endif /* 0 */ /* The same, but returns converted value from the location pointer by addr. */ #define __arch__swab16p(addr) ld_le16(addr) diff --git a/include/asm-ppc/cache.h b/include/asm-ppc/cache.h index 3a0e34caf683..54c2d4c366ed 100644 --- a/include/asm-ppc/cache.h +++ b/include/asm-ppc/cache.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.cache.h 1.10 10/18/01 15:02:09 trini + * BK Id: %F% %I% %G% %U% %#% */ /* * include/asm-ppc/cache.h @@ -15,15 +15,15 @@ #if defined(CONFIG_8xx) || defined(CONFIG_403GCX) #define L1_CACHE_LINE_SIZE 16 #define LG_L1_CACHE_LINE_SIZE 4 -#define MAX_L1_COPY_PREFETCH 1 +#define MAX_COPY_PREFETCH 1 #elif defined(CONFIG_PPC64BRIDGE) #define L1_CACHE_LINE_SIZE 128 #define LG_L1_CACHE_LINE_SIZE 7 -#define MAX_L1_COPY_PREFETCH 1 +#define MAX_COPY_PREFETCH 1 #else #define L1_CACHE_LINE_SIZE 32 #define LG_L1_CACHE_LINE_SIZE 5 -#define MAX_L1_COPY_PREFETCH 4 +#define MAX_COPY_PREFETCH 4 #endif #define L1_CACHE_BYTES L1_CACHE_LINE_SIZE @@ -41,7 +41,10 @@ #endif #if defined(__KERNEL__) && !defined(__ASSEMBLY__) +extern void clean_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache_range(unsigned long start, unsigned long stop); +extern void invalidate_dcache_range(unsigned long start, unsigned long stop); +extern void flush_dcache_all(void); #endif /* __ASSEMBLY__ */ diff --git a/include/asm-ppc/dbdma.h b/include/asm-ppc/dbdma.h index 63b463c6a4f8..0a4d8a3e4b7d 100644 --- a/include/asm-ppc/dbdma.h +++ b/include/asm-ppc/dbdma.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.dbdma.h 1.5 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * Definitions for using the Apple Descriptor-Based DMA controller @@ -93,5 +93,13 @@ struct dbdma_cmd { /* Align an address for a DBDMA command structure */ #define DBDMA_ALIGN(x) (((unsigned)(x) + sizeof(struct dbdma_cmd) - 1) \ & -sizeof(struct dbdma_cmd)) + +/* Useful macros */ +#define DBDMA_DO_STOP(regs) do { \ + out_le32(&((regs)->control), (RUN|FLUSH)<<16); \ + while(in_le32(&((regs)->status)) & (ACTIVE|FLUSH)) \ + ; \ +} while(0) + #endif /* _ASM_DBDMA_H_ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/delay.h b/include/asm-ppc/delay.h index a43505c4ec38..72bfaa2c1f80 100644 --- a/include/asm-ppc/delay.h +++ b/include/asm-ppc/delay.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.delay.h 1.7 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _PPC_DELAY_H @@ -18,35 +18,36 @@ extern unsigned long loops_per_jiffy; -/* maximum permitted argument to udelay */ -#define __MAX_UDELAY 1000000 - extern void __delay(unsigned int loops); -/* N.B. the `secs' parameter here is a fixed-point number with - the binary point to the left of the most-significant bit. */ -extern __inline__ void __const_udelay(unsigned int secs) -{ - unsigned int loops; - - __asm__("mulhwu %0,%1,%2" : "=r" (loops) : - "r" (secs), "r" (loops_per_jiffy)); - __delay(loops * HZ); -} - /* - * note that 4294 == 2^32 / 10^6, multiplying by 4294 converts from - * microseconds to a 32-bit fixed-point number of seconds. + * Note that 19 * 226 == 4294 ==~ 2^32 / 10^6, so + * loops = (4294 * usecs * loops_per_jiffy * HZ) / 2^32. + * + * The mulhwu instruction gives us loops = (a * b) / 2^32. + * We choose a = usecs * 19 * HZ and b = loops_per_jiffy * 226 + * because this lets us support a wide range of HZ and + * loops_per_jiffy values without either a or b overflowing 2^32. + * Thus we need usecs * HZ <= (2^32 - 1) / 19 = 226050910 and + * loops_per_jiffy <= (2^32 - 1) / 226 = 19004280 + * (which corresponds to ~3800 bogomips at HZ = 100). + * -- paulus */ +#define __MAX_UDELAY (226050910/HZ) /* maximum udelay argument */ + extern __inline__ void __udelay(unsigned int usecs) { - __const_udelay(usecs * 4294); + unsigned int loops; + + __asm__("mulhwu %0,%1,%2" : "=r" (loops) : + "r" (usecs * (19 * HZ)), "r" (loops_per_jiffy * 226)); + __delay(loops); } extern void __bad_udelay(void); /* deliberately undefined */ #define udelay(n) (__builtin_constant_p(n)? \ - ((n) > __MAX_UDELAY? __bad_udelay(): __const_udelay((n) * 4294u)) : \ + ((n) > __MAX_UDELAY? __bad_udelay(): __udelay((n))) : \ __udelay(n)) #endif /* defined(_PPC_DELAY_H) */ diff --git a/include/asm-ppc/dma.h b/include/asm-ppc/dma.h index e7e1655cc765..af24e03b564b 100644 --- a/include/asm-ppc/dma.h +++ b/include/asm-ppc/dma.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.dma.h 1.8 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * linux/include/asm/dma.h: Defines for using and allocating dma channels. @@ -27,7 +27,7 @@ * not valid for the PReP platform. Take what you read * with a grain of salt. */ - + #ifndef _ASM_DMA_H #define _ASM_DMA_H @@ -38,13 +38,12 @@ /* The maximum address that we can perform a DMA transfer to on this platform */ /* Doesn't really apply... */ -#define MAX_DMA_ADDRESS 0xFFFFFFFF +#define MAX_DMA_ADDRESS 0xFFFFFFFF /* in arch/ppc/kernel/setup.c -- Cort */ extern unsigned long DMA_MODE_WRITE, DMA_MODE_READ; extern unsigned long ISA_DMA_THRESHOLD; - #ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER #define dma_outb outb_p #else @@ -69,7 +68,7 @@ extern unsigned long ISA_DMA_THRESHOLD; * - page registers for 5-7 don't use data bit 0, represent 128K pages * - page registers for 0-3 use bit 0, represent 64K pages * - * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. + * On PReP, DMA transfers are limited to the lower 16MB of _physical_ memory. * On CHRP, the W83C553F (and VLSI Tollgate?) support full 32 bit addressing. * Note that addresses loaded into registers must be _physical_ addresses, * not logical addresses (which may differ if paging is active). @@ -80,7 +79,7 @@ extern unsigned long ISA_DMA_THRESHOLD; * | ... | | ... | | ... | * | ... | | ... | | ... | * | ... | | ... | | ... | - * P7 ... P0 A7 ... A0 A7 ... A0 + * P7 ... P0 A7 ... A0 A7 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Address mapping for channels 5-7: @@ -89,7 +88,7 @@ extern unsigned long ISA_DMA_THRESHOLD; * | ... | \ \ ... \ \ \ ... \ \ * | ... | \ \ ... \ \ \ ... \ (not used) * | ... | \ \ ... \ \ \ ... \ - * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 + * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0 * | Page | Addr MSB | Addr LSB | (DMA registers) * * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses @@ -98,23 +97,15 @@ extern unsigned long ISA_DMA_THRESHOLD; * * Transfer count (_not # bytes_) is limited to 64K, represented as actual * count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more, - * and up to 128K bytes may be transferred on channels 5-7 in one operation. + * and up to 128K bytes may be transferred on channels 5-7 in one operation. * */ -/* used in nasty hack for sound - see prep_setup_arch() -- Cort */ +/* see prep_setup_arch() for detailed informations */ +#if defined(CONFIG_SOUND_CS4232) && defined(CONFIG_ALL_PPC) extern long ppc_cs4232_dma, ppc_cs4232_dma2; -#if defined(CONFIG_CS4232) -#if defined(CONFIG_ALL_PPC) #define SND_DMA1 ppc_cs4232_dma #define SND_DMA2 ppc_cs4232_dma2 -#else /* !CONFIG_ALL_PPC */ -#define SND_DMA1 -1 -#define SND_DMA2 -1 -#endif /* CONFIG_ALL_PPC */ -#elif defined(CONFIG_MSS) -#define SND_DMA1 CONFIG_MSS_DMA -#define SND_DMA2 CONFIG_MSS_DMA2 #else #define SND_DMA1 -1 #define SND_DMA2 -1 @@ -127,67 +118,67 @@ extern long ppc_cs4232_dma, ppc_cs4232_dma2; /* DMA controller registers */ #define DMA1_CMD_REG 0x08 /* command register (w) */ #define DMA1_STAT_REG 0x08 /* status register (r) */ -#define DMA1_REQ_REG 0x09 /* request register (w) */ +#define DMA1_REQ_REG 0x09 /* request register (w) */ #define DMA1_MASK_REG 0x0A /* single-channel mask (w) */ #define DMA1_MODE_REG 0x0B /* mode register (w) */ #define DMA1_CLEAR_FF_REG 0x0C /* clear pointer flip-flop (w) */ -#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ +#define DMA1_TEMP_REG 0x0D /* Temporary Register (r) */ #define DMA1_RESET_REG 0x0D /* Master Clear (w) */ -#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ -#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ +#define DMA1_CLR_MASK_REG 0x0E /* Clear Mask */ +#define DMA1_MASK_ALL_REG 0x0F /* all-channels mask (w) */ #define DMA2_CMD_REG 0xD0 /* command register (w) */ #define DMA2_STAT_REG 0xD0 /* status register (r) */ -#define DMA2_REQ_REG 0xD2 /* request register (w) */ +#define DMA2_REQ_REG 0xD2 /* request register (w) */ #define DMA2_MASK_REG 0xD4 /* single-channel mask (w) */ #define DMA2_MODE_REG 0xD6 /* mode register (w) */ #define DMA2_CLEAR_FF_REG 0xD8 /* clear pointer flip-flop (w) */ -#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ +#define DMA2_TEMP_REG 0xDA /* Temporary Register (r) */ #define DMA2_RESET_REG 0xDA /* Master Clear (w) */ -#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ -#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ - -#define DMA_ADDR_0 0x00 /* DMA address registers */ -#define DMA_ADDR_1 0x02 -#define DMA_ADDR_2 0x04 -#define DMA_ADDR_3 0x06 -#define DMA_ADDR_4 0xC0 -#define DMA_ADDR_5 0xC4 -#define DMA_ADDR_6 0xC8 -#define DMA_ADDR_7 0xCC - -#define DMA_CNT_0 0x01 /* DMA count registers */ -#define DMA_CNT_1 0x03 -#define DMA_CNT_2 0x05 -#define DMA_CNT_3 0x07 -#define DMA_CNT_4 0xC2 -#define DMA_CNT_5 0xC6 -#define DMA_CNT_6 0xCA -#define DMA_CNT_7 0xCE - -#define DMA_LO_PAGE_0 0x87 /* DMA page registers */ -#define DMA_LO_PAGE_1 0x83 -#define DMA_LO_PAGE_2 0x81 -#define DMA_LO_PAGE_3 0x82 -#define DMA_LO_PAGE_5 0x8B -#define DMA_LO_PAGE_6 0x89 -#define DMA_LO_PAGE_7 0x8A - -#define DMA_HI_PAGE_0 0x487 /* DMA page registers */ -#define DMA_HI_PAGE_1 0x483 -#define DMA_HI_PAGE_2 0x481 -#define DMA_HI_PAGE_3 0x482 -#define DMA_HI_PAGE_5 0x48B -#define DMA_HI_PAGE_6 0x489 -#define DMA_HI_PAGE_7 0x48A - -#define DMA1_EXT_REG 0x40B -#define DMA2_EXT_REG 0x4D6 - -#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ -#define DMA_AUTOINIT 0x10 - -extern spinlock_t dma_spin_lock; +#define DMA2_CLR_MASK_REG 0xDC /* Clear Mask */ +#define DMA2_MASK_ALL_REG 0xDE /* all-channels mask (w) */ + +#define DMA_ADDR_0 0x00 /* DMA address registers */ +#define DMA_ADDR_1 0x02 +#define DMA_ADDR_2 0x04 +#define DMA_ADDR_3 0x06 +#define DMA_ADDR_4 0xC0 +#define DMA_ADDR_5 0xC4 +#define DMA_ADDR_6 0xC8 +#define DMA_ADDR_7 0xCC + +#define DMA_CNT_0 0x01 /* DMA count registers */ +#define DMA_CNT_1 0x03 +#define DMA_CNT_2 0x05 +#define DMA_CNT_3 0x07 +#define DMA_CNT_4 0xC2 +#define DMA_CNT_5 0xC6 +#define DMA_CNT_6 0xCA +#define DMA_CNT_7 0xCE + +#define DMA_LO_PAGE_0 0x87 /* DMA page registers */ +#define DMA_LO_PAGE_1 0x83 +#define DMA_LO_PAGE_2 0x81 +#define DMA_LO_PAGE_3 0x82 +#define DMA_LO_PAGE_5 0x8B +#define DMA_LO_PAGE_6 0x89 +#define DMA_LO_PAGE_7 0x8A + +#define DMA_HI_PAGE_0 0x487 /* DMA page registers */ +#define DMA_HI_PAGE_1 0x483 +#define DMA_HI_PAGE_2 0x481 +#define DMA_HI_PAGE_3 0x482 +#define DMA_HI_PAGE_5 0x48B +#define DMA_HI_PAGE_6 0x489 +#define DMA_HI_PAGE_7 0x48A + +#define DMA1_EXT_REG 0x40B +#define DMA2_EXT_REG 0x4D6 + +#define DMA_MODE_CASCADE 0xC0 /* pass thru DREQ->HRQ, DACK<-HLDA only */ +#define DMA_AUTOINIT 0x10 + +extern spinlock_t dma_spin_lock; static __inline__ unsigned long claim_dma_lock(void) { @@ -206,27 +197,23 @@ static __inline__ void enable_dma(unsigned int dmanr) { unsigned char ucDmaCmd=0x00; - if (dmanr != 4) - { - dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ - dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ + if (dmanr != 4) { + dma_outb(0, DMA2_MASK_REG); /* This may not be enabled */ + dma_outb(ucDmaCmd, DMA2_CMD_REG); /* Enable group */ } - if (dmanr<=3) - { - dma_outb(dmanr, DMA1_MASK_REG); - dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ + if (dmanr <= 3) { + dma_outb(dmanr, DMA1_MASK_REG); + dma_outb(ucDmaCmd, DMA1_CMD_REG); /* Enable group */ } else - { - dma_outb(dmanr & 3, DMA2_MASK_REG); - } + dma_outb(dmanr & 3, DMA2_MASK_REG); } static __inline__ void disable_dma(unsigned int dmanr) { - if (dmanr<=3) - dma_outb(dmanr | 4, DMA1_MASK_REG); + if (dmanr <= 3) + dma_outb(dmanr | 4, DMA1_MASK_REG); else - dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); + dma_outb((dmanr & 3) | 4, DMA2_MASK_REG); } /* Clear the 'DMA Pointer Flip Flop'. @@ -238,19 +225,19 @@ static __inline__ void disable_dma(unsigned int dmanr) */ static __inline__ void clear_dma_ff(unsigned int dmanr) { - if (dmanr<=3) - dma_outb(0, DMA1_CLEAR_FF_REG); + if (dmanr <= 3) + dma_outb(0, DMA1_CLEAR_FF_REG); else - dma_outb(0, DMA2_CLEAR_FF_REG); + dma_outb(0, DMA2_CLEAR_FF_REG); } /* set mode (above) for a specific DMA channel */ static __inline__ void set_dma_mode(unsigned int dmanr, char mode) { - if (dmanr<=3) - dma_outb(mode | dmanr, DMA1_MODE_REG); + if (dmanr <= 3) + dma_outb(mode | dmanr, DMA1_MODE_REG); else - dma_outb(mode | (dmanr&3), DMA2_MODE_REG); + dma_outb(mode | (dmanr & 3), DMA2_MODE_REG); } /* Set only the page register bits of the transfer address. @@ -263,41 +250,41 @@ static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) switch(dmanr) { case 0: dma_outb(pagenr, DMA_LO_PAGE_0); - dma_outb(pagenr>>8, DMA_HI_PAGE_0); + dma_outb(pagenr >> 8, DMA_HI_PAGE_0); break; case 1: dma_outb(pagenr, DMA_LO_PAGE_1); - dma_outb(pagenr>>8, DMA_HI_PAGE_1); + dma_outb(pagenr >> 8, DMA_HI_PAGE_1); break; case 2: dma_outb(pagenr, DMA_LO_PAGE_2); - dma_outb(pagenr>>8, DMA_HI_PAGE_2); + dma_outb(pagenr >> 8, DMA_HI_PAGE_2); break; case 3: dma_outb(pagenr, DMA_LO_PAGE_3); - dma_outb(pagenr>>8, DMA_HI_PAGE_3); + dma_outb(pagenr >> 8, DMA_HI_PAGE_3); break; - case 5: - if (SND_DMA1 == 5 || SND_DMA2 == 5) + case 5: + if (SND_DMA1 == 5 || SND_DMA2 == 5) dma_outb(pagenr, DMA_LO_PAGE_5); else dma_outb(pagenr & 0xfe, DMA_LO_PAGE_5); - dma_outb(pagenr>>8, DMA_HI_PAGE_5); + dma_outb(pagenr >> 8, DMA_HI_PAGE_5); break; case 6: - if (SND_DMA1 == 6 || SND_DMA2 == 6) + if (SND_DMA1 == 6 || SND_DMA2 == 6) dma_outb(pagenr, DMA_LO_PAGE_6); else dma_outb(pagenr & 0xfe, DMA_LO_PAGE_6); - dma_outb(pagenr>>8, DMA_HI_PAGE_6); + dma_outb(pagenr >> 8, DMA_HI_PAGE_6); break; case 7: if (SND_DMA1 == 7 || SND_DMA2 == 7) dma_outb(pagenr, DMA_LO_PAGE_7); else dma_outb(pagenr & 0xfe, DMA_LO_PAGE_7); - dma_outb(pagenr>>8, DMA_HI_PAGE_7); - break; + dma_outb(pagenr >> 8, DMA_HI_PAGE_7); + break; } } @@ -307,20 +294,19 @@ static __inline__ void set_dma_page(unsigned int dmanr, int pagenr) */ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) { - if (dmanr <= 3) { - dma_outb( phys & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE ); - } else { - if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { - dma_outb( phys & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (phys>>8) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (dmanr&3), DMA2_EXT_REG); - } else { - dma_outb( (phys>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - dma_outb( (phys>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE ); - } + if (dmanr <= 3) { + dma_outb(phys & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE ); + dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 1) + IO_DMA1_BASE); + } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { + dma_outb(phys & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE ); + dma_outb((phys >> 8) & 0xff, ((dmanr & 3) << 2) + + IO_DMA2_BASE); + dma_outb((dmanr & 3), DMA2_EXT_REG); + } else { + dma_outb((phys >> 1) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); + dma_outb((phys >> 9) & 0xff, ((dmanr & 3) << 2) + IO_DMA2_BASE); } - set_dma_page(dmanr, phys>>16); + set_dma_page(dmanr, phys >> 16); } @@ -334,22 +320,23 @@ static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int phys) */ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) { - count--; - if (dmanr <= 3) { - dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE ); - } else { - if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { - dma_outb( count & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - dma_outb( (count>>8) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } else { - dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE ); - } - } + count--; + if (dmanr <= 3) { + dma_outb(count & 0xff, ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE); + dma_outb((count >> 8) & 0xff, ((dmanr & 3) << 1) + 1 + + IO_DMA1_BASE); + } else if (dmanr == SND_DMA1 || dmanr == SND_DMA2) { + dma_outb( count & 0xff, ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE); + dma_outb( (count >> 8) & 0xff, ((dmanr & 3) << 2) + 2 + + IO_DMA2_BASE); + } else { + dma_outb((count >> 1) & 0xff, ((dmanr & 3) << 2) + 2 + + IO_DMA2_BASE); + dma_outb((count >> 9) & 0xff, ((dmanr & 3) << 2) + 2 + + IO_DMA2_BASE); + } } - /* Get DMA residue count. After a DMA transfer, this * should return zero. Reading this while a DMA transfer is * still in progress will return unpredictable results. @@ -360,27 +347,32 @@ static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count) */ static __inline__ int get_dma_residue(unsigned int dmanr) { - unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE - : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE; + unsigned int io_port = (dmanr <= 3) ? + ((dmanr & 3) << 1) + 1 + IO_DMA1_BASE + : ((dmanr & 3) << 2) + 2 + IO_DMA2_BASE; /* using short to get 16-bit wrap around */ unsigned short count; count = 1 + dma_inb(io_port); count += dma_inb(io_port) << 8; - + return (dmanr <= 3 || dmanr == SND_DMA1 || dmanr == SND_DMA2) - ? count : (count<<1); + ? count : (count<<1); + } /* These are in kernel/dma.c: */ -extern int request_dma(unsigned int dmanr, const char * device_id); /* reserve a DMA channel */ -extern void free_dma(unsigned int dmanr); /* release it again */ + +/* reserve a DMA channel */ +extern int request_dma(unsigned int dmanr, const char * device_id); +/* release it again */ +extern void free_dma(unsigned int dmanr); #ifdef CONFIG_PCI -extern int isa_dma_bridge_buggy; -#else -#define isa_dma_bridge_buggy (0) +extern int isa_dma_bridge_buggy; +#else +#define isa_dma_bridge_buggy (0) #endif #endif /* _ASM_DMA_H */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/est8260.h b/include/asm-ppc/est8260.h deleted file mode 100644 index 1bfe42865cb0..000000000000 --- a/include/asm-ppc/est8260.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * BK Id: SCCS/s.est8260.h 1.5 05/17/01 18:14:24 cort - */ - -/* Board information for the EST8260, which should be generic for - * all 8260 boards. The IMMR is now given to us so the hard define - * will soon be removed. All of the clock values are computed from - * the configuration SCMR and the Power-On-Reset word. - */ - -#define IMAP_ADDR ((uint)0xf0000000) - - -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in MHz */ - unsigned int bi_cpmfreq; /* CPM Freq, in MHz */ - unsigned int bi_brgfreq; /* BRG Freq, in MHz */ - unsigned int bi_vco; /* VCO Out from PLL */ - unsigned int bi_baudrate; /* Default console baud rate */ - unsigned int bi_immr; /* IMMR when called from boot rom */ - unsigned char bi_enetaddr[6]; -} bd_t; - -extern bd_t m8xx_board_info; - diff --git a/include/asm-ppc/fads.h b/include/asm-ppc/fads.h deleted file mode 100644 index 386024c9f286..000000000000 --- a/include/asm-ppc/fads.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * BK Id: SCCS/s.fads.h 1.14 10/26/01 10:14:09 trini - */ - -/* - * A collection of structures, addresses, and values associated with - * the Motorola 860T FADS board. Copied from the MBX stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __ASM_FADS_H__ -#define __ASM_FADS_H__ - -#include <linux/config.h> - -#include <asm/ppcboot.h> - -/* Memory map is configured by the PROM startup. - * I tried to follow the FADS manual, although the startup PROM - * dictates this and we simply have to move some of the physical - * addresses for Linux. - */ -#define BCSR_ADDR ((uint)0xff010000) -#define BCSR_SIZE ((uint)(64 * 1024)) -#define BCSR0 ((uint)0xff010000) -#define BCSR1 ((uint)0xff010004) -#define BCSR2 ((uint)0xff010008) -#define BCSR3 ((uint)0xff01000c) -#define BCSR4 ((uint)0xff010010) - -#define IMAP_ADDR ((uint)0xff000000) -#define IMAP_SIZE ((uint)(64 * 1024)) - -#define PCMCIA_MEM_ADDR ((uint)0xff020000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -/* Bits of interest in the BCSRs. - */ -#define BCSR1_ETHEN ((uint)0x20000000) -#define BCSR1_RS232EN_1 ((uint)0x01000000) -#define BCSR1_RS232EN_2 ((uint)0x00040000) -#define BCSR4_ETHLOOP ((uint)0x80000000) /* EEST Loopback */ -#define BCSR4_EEFDX ((uint)0x40000000) /* EEST FDX enable */ -#define BCSR4_FETH_EN ((uint)0x08000000) /* PHY enable */ -#define BCSR4_FETHCFG0 ((uint)0x04000000) /* PHY autoneg mode */ -#define BCSR4_FETHCFG1 ((uint)0x00400000) /* PHY autoneg mode */ -#define BCSR4_FETHFDE ((uint)0x02000000) /* PHY FDX advertise */ -#define BCSR4_FETHRST ((uint)0x00200000) /* PHY Reset */ - -/* Interrupt level assignments. - */ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ -#define PHY_INTERRUPT SIU_IRQ2 /* PHY link change interrupt */ - -/* We don't use the 8259. - */ -#define NR_8259_INTS 0 - -#endif /* __ASM_FADS_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/feature.h b/include/asm-ppc/feature.h deleted file mode 100644 index 3e7007bce88c..000000000000 --- a/include/asm-ppc/feature.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * BK Id: SCCS/s.feature.h 1.13 08/19/01 22:23:04 paulus - */ -/* - * Definitions for accessing the Feature Control Register (FCR) - * on Power Macintoshes and similar machines. The FCR lets us - * enable/disable, reset, and power up/down various peripherals. - * - * This file is subject to the terms and conditions of the GNU General Public - * License. See the file "COPYING" in the main directory of this archive - * for more details. - * - * Copyright (C) 1998 Paul Mackerras & - * Ben. Herrenschmidt. - * - * - */ -#ifdef __KERNEL__ -#ifndef __ASM_PPC_FEATURE_H -#define __ASM_PPC_FEATURE_H - -/* - * The FCR selector for particular features vary somewhat between - * different machines. So we abstract a list of features here - * and let the feature_* routines map them to the actual bits. - */ -enum system_feature { - FEATURE_null, - FEATURE_Serial_reset, - FEATURE_Serial_enable, - FEATURE_Serial_IO_A, - FEATURE_Serial_IO_B, - FEATURE_SWIM3_enable, - FEATURE_MESH_enable, - FEATURE_IDE0_enable, /* Internal IDE */ - FEATURE_IDE0_reset, /* Internal IDE */ - FEATURE_IOBUS_enable, /* Internal IDE */ - FEATURE_Mediabay_reset, - FEATURE_Mediabay_power, - FEATURE_Mediabay_PCI_enable, - FEATURE_IDE1_enable, /* MediaBay IDE */ - FEATURE_IDE1_reset, /* MediaBay IDE */ - FEATURE_Mediabay_floppy_enable, - FEATURE_BMac_reset, - FEATURE_BMac_IO_enable, - FEATURE_Modem_power, - FEATURE_Slow_SCC_PCLK, - FEATURE_Sound_power, - FEATURE_Sound_CLK_enable, - FEATURE_IDE2_enable, - FEATURE_IDE2_reset, - FEATURE_Mediabay_IDE_switch, /* MB IDE bus switch */ - FEATURE_Mediabay_content, /* MB content indicator enable */ - FEATURE_Airport_reset, /* Is it actually a reset ? */ - FEATURE_last, -}; - -/* Note about the device parameter: Each device gives it's own entry. If NULL, - the feature function will just do nothing and return -EINVAL. - The feature management will walk up the device tree until in reaches a recognized - chip for which features can be changed and it will then apply the necessary - features to that chip. If it's not found, -ENODEV is returned. - Note also that feature_test/set/clear are interrupt-safe provided that they are - called _after_ feature_init() is completed. - */ - -/* Test whether a particular feature is enabled. May return -ENODEV*/ -extern int feature_test(struct device_node* device, enum system_feature f); - -/* Set a particular feature. Returns 0 or -ENODEV */ -extern int feature_set(struct device_node* device, enum system_feature f); - -/* Clear a particular feature */ -extern int feature_clear(struct device_node* device, enum system_feature f); - -/* Initialize feature stuff */ -extern void feature_init(void); - - -/* - * Additional functions related to Core99 machines. We should extend the - * feature mecanism to make those fit into it. For now, they are still - * separate functions. - */ -extern void feature_set_gmac_power(struct device_node* device, int power); - - /* use constants in KeyLargo.h for the reset parameter */ -extern void feature_gmac_phy_reset(struct device_node* device); - -extern void feature_set_usb_power(struct device_node* device, int power); - -extern void feature_set_firewire_power(struct device_node* device, int power); -extern void feature_set_firewire_cable_power(struct device_node* device, int power); - -extern void feature_set_modem_power(struct device_node* device, int power); - -extern void feature_set_airport_power(struct device_node* device, int power); - -extern void feature_core99_kick_cpu(int cpu_nr); - -/* - * Sleep related functions. At term, they should be high-priority notifiers, - * but this would require some changes to the current sleep scheme that won't - * be done in 2.4. - */ -extern void feature_prepare_for_sleep(void); -extern void feature_wake_up(void); -extern int feature_can_sleep(void); - -#endif /* __ASM_PPC_FEATURE_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/gemini.h b/include/asm-ppc/gemini.h deleted file mode 100644 index 9c978322870d..000000000000 --- a/include/asm-ppc/gemini.h +++ /dev/null @@ -1,171 +0,0 @@ -/* - * BK Id: SCCS/s.gemini.h 1.5 05/17/01 18:14:24 cort - */ -/* - * include/asm-ppc/gemini.h - * - * - * Onboard registers and descriptions for Synergy Microsystems' - * "Gemini" boards. - * - */ -#ifdef __KERNEL__ -#ifndef __PPC_GEMINI_H -#define __PPC_GEMINI_H - -/* Registers */ - -#define GEMINI_SERIAL_B (0xffeffb00) -#define GEMINI_SERIAL_A (0xffeffb08) -#define GEMINI_USWITCH (0xffeffd00) -#define GEMINI_BREV (0xffeffe00) -#define GEMINI_BECO (0xffeffe08) -#define GEMINI_FEAT (0xffeffe10) -#define GEMINI_BSTAT (0xffeffe18) -#define GEMINI_CPUSTAT (0xffeffe20) -#define GEMINI_L2CFG (0xffeffe30) -#define GEMINI_MEMCFG (0xffeffe38) -#define GEMINI_FLROM (0xffeffe40) -#define GEMINI_P0PCI (0xffeffe48) -#define GEMINI_FLWIN (0xffeffe50) -#define GEMINI_P0INTMASK (0xffeffe60) -#define GEMINI_P0INTAP (0xffeffe68) -#define GEMINI_PCIERR (0xffeffe70) -#define GEMINI_LEDBASE (0xffeffe80) -#define GEMINI_RTC (0xffe9fff8) -#define GEMINI_LEDS 8 -#define GEMINI_SWITCHES 8 - - -/* Flash ROM bit definitions */ -#define GEMINI_FLS_WEN (1<<0) -#define GEMINI_FLS_JMP (1<<6) -#define GEMINI_FLS_BOOT (1<<7) - -/* Memory bit definitions */ -#define GEMINI_MEM_TYPE_MASK 0xc0 -#define GEMINI_MEM_SIZE_MASK 0x38 -#define GEMINI_MEM_BANK_MASK 0x07 - -/* L2 cache bit definitions */ -#define GEMINI_L2_SIZE_MASK 0xc0 -#define GEMINI_L2_RATIO_MASK 0x03 - -/* Timebase register bit definitons */ -#define GEMINI_TIMEB0_EN (1<<0) -#define GEMINI_TIMEB1_EN (1<<1) -#define GEMINI_TIMEB2_EN (1<<2) -#define GEMINI_TIMEB3_EN (1<<3) - -/* CPU status bit definitions */ -#define GEMINI_CPU_ID_MASK 0x03 -#define GEMINI_CPU_COUNT_MASK 0x0c -#define GEMINI_CPU0_HALTED (1<<4) -#define GEMINI_CPU1_HALTED (1<<5) -#define GEMINI_CPU2_HALTED (1<<6) -#define GEMINI_CPU3_HALTED (1<<7) - -/* Board status bit definitions */ -#define GEMINI_BRD_FAIL (1<<0) /* FAIL led is lit */ -#define GEMINI_BRD_BUS_MASK 0x0c /* PowerPC bus speed */ - -/* Board family/feature bit descriptions */ -#define GEMINI_FEAT_HAS_FLASH (1<<0) -#define GEMINI_FEAT_HAS_ETH (1<<1) -#define GEMINI_FEAT_HAS_SCSI (1<<2) -#define GEMINI_FEAT_HAS_P0 (1<<3) -#define GEMINI_FEAT_FAM_MASK 0xf0 - -/* Mod/ECO bit definitions */ -#define GEMINI_ECO_LEVEL_MASK 0x0f -#define GEMINI_MOD_MASK 0xf0 - -/* Type/revision bit definitions */ -#define GEMINI_REV_MASK 0x0f -#define GEMINI_TYPE_MASK 0xf0 - -/* User switch definitions */ -#define GEMINI_SWITCH_VERBOSE 1 /* adds "debug" to boot cmd line */ -#define GEMINI_SWITCH_SINGLE_USER 7 /* boots into "single-user" mode */ - -#define SGS_RTC_CONTROL 0 -#define SGS_RTC_SECONDS 1 -#define SGS_RTC_MINUTES 2 -#define SGS_RTC_HOURS 3 -#define SGS_RTC_DAY 4 -#define SGS_RTC_DAY_OF_MONTH 5 -#define SGS_RTC_MONTH 6 -#define SGS_RTC_YEAR 7 - -#define SGS_RTC_SET 0x80 -#define SGS_RTC_IS_STOPPED 0x80 - -#define GRACKLE_CONFIG_ADDR_ADDR (0xfec00000) -#define GRACKLE_CONFIG_DATA_ADDR (0xfee00000) - -#define GEMINI_BOOT_INIT (0xfff00100) - -#ifndef __ASSEMBLY__ - -static inline void grackle_write( unsigned long addr, unsigned long data ) -{ - __asm__ __volatile__( - " stwbrx %1, 0, %0\n \ - sync\n \ - stwbrx %3, 0, %2\n \ - sync " - : /* no output */ - : "r" (GRACKLE_CONFIG_ADDR_ADDR), "r" (addr), - "r" (GRACKLE_CONFIG_DATA_ADDR), "r" (data)); -} - -static inline unsigned long grackle_read( unsigned long addr ) -{ - unsigned long val; - - __asm__ __volatile__( - " stwbrx %1, 0, %2\n \ - sync\n \ - lwbrx %0, 0, %3\n \ - sync " - : "=r" (val) - : "r" (addr), "r" (GRACKLE_CONFIG_ADDR_ADDR), - "r" (GRACKLE_CONFIG_DATA_ADDR)); - - return val; -} - -static inline void gemini_led_on( int led ) -{ - if (led >= 0 && led < GEMINI_LEDS) - *(unsigned char *)(GEMINI_LEDBASE + (led<<3)) = 1; -} - -static inline void gemini_led_off(int led) -{ - if (led >= 0 && led < GEMINI_LEDS) - *(unsigned char *)(GEMINI_LEDBASE + (led<<3)) = 0; -} - -static inline int gemini_led_val(int led) -{ - int val = 0; - if (led >= 0 && led < GEMINI_LEDS) - val = *(unsigned char *)(GEMINI_LEDBASE + (led<<3)); - return (val & 0x1); -} - -/* returns processor id from the board */ -static inline int gemini_processor(void) -{ - unsigned char cpu = *(unsigned char *)(GEMINI_CPUSTAT); - return (int) ((cpu == 0) ? 4 : (cpu & GEMINI_CPU_ID_MASK)); -} - - -extern void _gemini_reboot(void); -extern void gemini_prom_init(void); -extern void gemini_init_l2(void); -#endif /* __ASSEMBLY__ */ -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/gemini_serial.h b/include/asm-ppc/gemini_serial.h deleted file mode 100644 index 925024df4db8..000000000000 --- a/include/asm-ppc/gemini_serial.h +++ /dev/null @@ -1,44 +0,0 @@ -/* - * BK Id: SCCS/s.gemini_serial.h 1.5 05/17/01 18:14:24 cort - */ -#ifdef __KERNEL__ -#ifndef __ASMPPC_GEMINI_SERIAL_H -#define __ASMPPC_GEMINI_SERIAL_H - -#include <linux/config.h> -#include <asm/gemini.h> - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -/* Rate for the 24.576 Mhz clock for the onboard serial chip */ -#define BASE_BAUD (24576000 / 16) - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST|ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF|ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF) -#endif - -#define STD_SERIAL_PORT_DEFNS \ - { 0, BASE_BAUD, GEMINI_SERIAL_A, 15, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, GEMINI_SERIAL_B, 14, STD_COM_FLAGS }, /* ttyS1 */ \ - -#ifdef CONFIG_GEMINI_PU32 -#define PU32_SERIAL_PORT_DEFNS \ - { 0, BASE_BAUD, NULL, 0, STD_COM_FLAGS }, -#else -#define PU32_SERIAL_PORT_DEFNS -#endif - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DEFNS \ - PU32_SERIAL_PORT_DEFNS - -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/gg2.h b/include/asm-ppc/gg2.h index c7dab2ad5131..75bee9608e57 100644 --- a/include/asm-ppc/gg2.h +++ b/include/asm-ppc/gg2.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.gg2.h 1.5 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * asm-ppc/gg2.h -- VLSI VAS96011/12 `Golden Gate 2' register definitions @@ -37,6 +37,8 @@ * GG2 specific PCI Registers */ +extern unsigned long gg2_pci_config_base; /* kernel virtual address */ + #define GG2_PCI_BUSNO 0x40 /* Bus number */ #define GG2_PCI_SUBBUSNO 0x41 /* Subordinate bus number */ #define GG2_PCI_DISCCTR 0x42 /* Disconnect counter */ diff --git a/include/asm-ppc/gt64260.h b/include/asm-ppc/gt64260.h new file mode 100644 index 000000000000..90ddb3d457e3 --- /dev/null +++ b/include/asm-ppc/gt64260.h @@ -0,0 +1,324 @@ +/* + * include/asm-ppc/gt64260.h + * + * Prototypes, etc. for the Marvell/Galileo GT64260 host bridge routines. + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __ASMPPC_GT64260_H +#define __ASMPPC_GT64260_H + +#include <linux/kernel.h> +#include <linux/init.h> +#include <linux/pci.h> +#include <linux/slab.h> + +#include <asm/byteorder.h> +#include <asm/io.h> +#include <asm/irq.h> +#include <asm/uaccess.h> +#include <asm/machdep.h> +#include <asm/pci-bridge.h> +#include <asm/gt64260_defs.h> + + +extern u32 gt64260_base; +extern u32 gt64260_irq_base; /* We handle the next 96 IRQs from here */ +extern u32 gt64260_revision; +extern u8 gt64260_pci_exclude_bridge; + +#ifndef TRUE +#define TRUE 1 +#endif + +#ifndef FALSE +#define FALSE 0 +#endif + +/* IRQs defined by the 64260 */ +#define GT64260_IRQ_MPSC0 40 +#define GT64260_IRQ_MPSC1 42 +#define GT64260_IRQ_SDMA 36 + +/* + * Define a default physical memory map to be set up on the bridge. + * Also define a struct to pass that info from board-specific routines to + * GT64260 generic set up routines. By passing this info in, the board + * support developer can modify it at will. + */ + +/* + * This is the default memory map: + * CPU PCI + * --- --- + * PCI 0 I/O: 0xfa000000-0xfaffffff 0x00000000-0x00ffffff + * PCI 1 I/O: 0xfb000000-0xfbffffff 0x01000000-0x01ffffff + * PCI 0 MEM: 0x80000000-0x8fffffff 0x80000000-0x8fffffff + * PCI 1 MEM: 0x90000000-0x9fffffff 0x90000000-0x9fffffff + */ + +/* Default physical memory map for the GT64260 bridge */ + +/* + * PCI Bus 0 Definitions + */ +#define GT64260_PCI_0_IO_SIZE 0x01000000U +#define GT64260_PCI_0_MEM_SIZE 0x10000000U + +/* Processor Physical addresses */ +#define GT64260_PCI_0_IO_START_PROC 0xfa000000U +#define GT64260_PCI_0_IO_END_PROC (GT64260_PCI_0_IO_START_PROC + \ + GT64260_PCI_0_IO_SIZE - 1) + +/* PCI 0 addresses */ +#define GT64260_PCI_0_IO_START 0x00000000U +#define GT64260_PCI_0_IO_END (GT64260_PCI_0_IO_START + \ + GT64260_PCI_0_IO_SIZE - 1) + +/* Processor Physical addresses */ +#define GT64260_PCI_0_MEM_START_PROC 0x80000000U +#define GT64260_PCI_0_MEM_END_PROC (GT64260_PCI_0_MEM_START_PROC + \ + GT64260_PCI_0_MEM_SIZE - 1) + +/* PCI 0 addresses */ +#define GT64260_PCI_0_MEM_START 0x80000000U +#define GT64260_PCI_0_MEM_END (GT64260_PCI_0_MEM_START + \ + GT64260_PCI_0_MEM_SIZE - 1) + +/* + * PCI Bus 1 Definitions + */ +#define GT64260_PCI_1_IO_SIZE 0x01000000U +#define GT64260_PCI_1_MEM_SIZE 0x10000000U + +/* PCI 1 addresses */ +#define GT64260_PCI_1_IO_START 0x01000000U +#define GT64260_PCI_1_IO_END (GT64260_PCI_1_IO_START + \ + GT64260_PCI_1_IO_SIZE - 1) + +/* Processor Physical addresses */ +#define GT64260_PCI_1_IO_START_PROC 0xfb000000U +#define GT64260_PCI_1_IO_END_PROC (GT64260_PCI_1_IO_START_PROC + \ + GT64260_PCI_1_IO_SIZE - 1) + +/* PCI 1 addresses */ +#define GT64260_PCI_1_MEM_START 0x90000000U +#define GT64260_PCI_1_MEM_END (GT64260_PCI_1_MEM_START + \ + GT64260_PCI_1_MEM_SIZE - 1) + +/* Processor Physical addresses */ +#define GT64260_PCI_1_MEM_START_PROC 0x90000000U +#define GT64260_PCI_1_MEM_END_PROC (GT64260_PCI_1_MEM_START_PROC + \ + GT64260_PCI_1_MEM_SIZE - 1) + +/* Define struct to pass mem-map info into gt64260_common.c code */ +typedef struct { + struct pci_controller *hose_a; + struct pci_controller *hose_b; + + u32 mem_size; + + u32 pci_0_io_start_proc; + u32 pci_0_io_start_pci; + u32 pci_0_io_size; + u32 pci_0_io_swap; + + u32 pci_0_mem_start_proc; + u32 pci_0_mem_start_pci_hi; + u32 pci_0_mem_start_pci_lo; + u32 pci_0_mem_size; + u32 pci_0_mem_swap; + + u32 pci_1_io_start_proc; + u32 pci_1_io_start_pci; + u32 pci_1_io_size; + u32 pci_1_io_swap; + + u32 pci_1_mem_start_proc; + u32 pci_1_mem_start_pci_hi; + u32 pci_1_mem_start_pci_lo; + u32 pci_1_mem_size; + u32 pci_1_mem_swap; +} gt64260_bridge_info_t; + +#define GT64260_BRIDGE_INFO_DEFAULT(ip, ms) { \ + (ip)->mem_size = (ms); \ + \ + (ip)->pci_0_io_start_proc = GT64260_PCI_0_IO_START_PROC; \ + (ip)->pci_0_io_start_pci = GT64260_PCI_0_IO_START; \ + (ip)->pci_0_io_size = GT64260_PCI_0_IO_SIZE; \ + (ip)->pci_0_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ + \ + (ip)->pci_0_mem_start_proc = GT64260_PCI_0_MEM_START_PROC; \ + (ip)->pci_0_mem_start_pci_hi = 0x00000000; \ + (ip)->pci_0_mem_start_pci_lo = GT64260_PCI_0_MEM_START; \ + (ip)->pci_0_mem_size = GT64260_PCI_0_MEM_SIZE; \ + (ip)->pci_0_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ + \ + (ip)->pci_1_io_start_proc = GT64260_PCI_1_IO_START_PROC; \ + (ip)->pci_1_io_start_pci = GT64260_PCI_1_IO_START; \ + (ip)->pci_1_io_size = GT64260_PCI_1_IO_SIZE; \ + (ip)->pci_1_io_swap = GT64260_CPU_PCI_SWAP_NONE; \ + \ + (ip)->pci_1_mem_start_proc = GT64260_PCI_1_MEM_START_PROC; \ + (ip)->pci_1_mem_start_pci_hi = 0x00000000; \ + (ip)->pci_1_mem_start_pci_lo = GT64260_PCI_1_MEM_START; \ + (ip)->pci_1_mem_size = GT64260_PCI_1_MEM_SIZE; \ + (ip)->pci_1_mem_swap = GT64260_CPU_PCI_SWAP_NONE; \ +} + +/* + ***************************************************************************** + * + * I/O macros to access the 64260's registers + * + ***************************************************************************** + */ + +extern inline uint32_t gt_read(uint32_t offs){ + return (in_le32((volatile uint *)(gt64260_base + offs))); +} +extern inline void gt_write(uint32_t offs, uint32_t d){ + out_le32((volatile uint *)(gt64260_base + offs), d); +} + +#if 0 /* paranoid SMP version */ +extern inline void gt_modify(u32 offs, u32 data, u32 mask) \ +{ + uint32_t reg; + spin_lock(>64260_lock); + reg = gt_read(offs) & (~mask); /* zero any bits we care about*/ + reg |= data & mask; /* set bits from the data */ + gt_write(offs, reg); + spin_unlock(>64260_lock); +} +#else +extern inline void gt_modify(uint32_t offs, uint32_t data, uint32_t mask) +{ + uint32_t reg; + reg = gt_read(offs) & (~(mask)); /* zero any bits we care about*/ + reg |= (data) & (mask); /* set bits from the data */ + gt_write(offs, reg); +} +#endif +#define gt_set_bits(offs, bits) gt_modify(offs, ~0, bits) + +#define gt_clr_bits(offs, bits) gt_modify(offs, 0, bits) + + +/* + ***************************************************************************** + * + * Function Prototypes + * + ***************************************************************************** + */ + +int gt64260_find_bridges(u32 phys_base_addr, gt64260_bridge_info_t *info, + int ((*map_irq)(struct pci_dev *, unsigned char, unsigned char))); +int gt64260_bridge_init(gt64260_bridge_info_t *info); +int gt64260_cpu_scs_set_window(u32 window, + u32 base_addr, + u32 size); +int gt64260_cpu_cs_set_window(u32 window, + u32 base_addr, + u32 size); +int gt64260_cpu_boot_set_window(u32 base_addr, + u32 size); +int gt64260_cpu_set_pci_io_window(u32 pci_bus, + u32 cpu_base_addr, + u32 pci_base_addr, + u32 size, + u32 swap); +int gt64260_cpu_set_pci_mem_window(u32 pci_bus, + u32 window, + u32 cpu_base_addr, + u32 pci_base_addr_hi, + u32 pci_base_addr_lo, + u32 size, + u32 swap_64bit); +int gt64260_cpu_prot_set_window(u32 window, + u32 base_addr, + u32 size, + u32 access_bits); +int gt64260_cpu_snoop_set_window(u32 window, + u32 base_addr, + u32 size, + u32 snoop_type); +void gt64260_cpu_disable_all_windows(void); +int gt64260_pci_bar_enable(u32 pci_bus, u32 enable_bits); +int gt64260_pci_slave_scs_set_window(struct pci_controller *hose, + u32 window, + u32 pci_base_addr, + u32 cpu_base_addr, + u32 size); +int gt64260_pci_slave_cs_set_window(struct pci_controller *hose, + u32 window, + u32 pci_base_addr, + u32 cpu_base_addr, + u32 size); +int gt64260_pci_slave_boot_set_window(struct pci_controller *hose, + u32 pci_base_addr, + u32 cpu_base_addr, + u32 size); +int gt64260_pci_slave_p2p_mem_set_window(struct pci_controller *hose, + u32 window, + u32 pci_base_addr, + u32 other_bus_base_addr, + u32 size); +int gt64260_pci_slave_p2p_io_set_window(struct pci_controller *hose, + u32 pci_base_addr, + u32 other_bus_base_addr, + u32 size); +int gt64260_pci_slave_dac_scs_set_window(struct pci_controller *hose, + u32 window, + u32 pci_base_addr_hi, + u32 pci_base_addr_lo, + u32 cpu_base_addr, + u32 size); +int gt64260_pci_slave_dac_cs_set_window(struct pci_controller *hose, + u32 window, + u32 pci_base_addr_hi, + u32 pci_base_addr_lo, + u32 cpu_base_addr, + u32 size); +int gt64260_pci_slave_dac_boot_set_window(struct pci_controller *hose, + u32 pci_base_addr_hi, + u32 pci_base_addr_lo, + u32 cpu_base_addr, + u32 size); +int gt64260_pci_slave_dac_p2p_mem_set_window(struct pci_controller *hose, + u32 window, + u32 pci_base_addr_hi, + u32 pci_base_addr_lo, + u32 other_bus_base_addr, + u32 size); +int gt64260_pci_acc_cntl_set_window(u32 pci_bus, + u32 window, + u32 base_addr_hi, + u32 base_addr_lo, + u32 size, + u32 features); +int gt64260_pci_snoop_set_window(u32 pci_bus, + u32 window, + u32 base_addr_hi, + u32 base_addr_lo, + u32 size, + u32 snoop_type); +int gt64260_set_base(u32 new_base); +int gt64260_get_base(u32 *base); +int gt64260_pci_exclude_device(u8 bus, u8 devfn); + +void gt64260_init_irq(void); +int gt64260_get_irq(struct pt_regs *regs); + +void gt64260_mpsc_progress(char *s, unsigned short hex); + +#endif /* __ASMPPC_GT64260_H */ diff --git a/include/asm-ppc/gt64260_defs.h b/include/asm-ppc/gt64260_defs.h new file mode 100644 index 000000000000..3ad58564be78 --- /dev/null +++ b/include/asm-ppc/gt64260_defs.h @@ -0,0 +1,1012 @@ +/* + * include/asm-ppc/gt64260_defs.h + * + * Register definitions for the Marvell/Galileo GT64260 host bridge. + * + * Author: Mark A. Greer <mgreer@mvista.com> + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __ASMPPC_GT64260_DEFS_H +#define __ASMPPC_GT64260_DEFS_H + +/* + * Define a macro to represent the supported version of the 64260. + */ +#define GT64260 0x01 +#define GT64260A 0x10 + +/* + ***************************************************************************** + * + * CPU Interface Registers + * + ***************************************************************************** + */ + +/* CPU physical address of 64260's registers */ +#define GT64260_INTERNAL_SPACE_DECODE 0x0068 +#define GT64260_INTERNAL_SPACE_SIZE 0x10000 +#define GT64260_INTERNAL_SPACE_DEFAULT_ADDR 0x14000000 + +/* CPU Memory Controller Window Registers (4 windows) */ +#define GT64260_CPU_SCS_DECODE_WINDOWS 4 + +#define GT64260_CPU_SCS_DECODE_0_BOT 0x0008 +#define GT64260_CPU_SCS_DECODE_0_TOP 0x0010 +#define GT64260_CPU_SCS_DECODE_1_BOT 0x0208 +#define GT64260_CPU_SCS_DECODE_1_TOP 0x0210 +#define GT64260_CPU_SCS_DECODE_2_BOT 0x0018 +#define GT64260_CPU_SCS_DECODE_2_TOP 0x0020 +#define GT64260_CPU_SCS_DECODE_3_BOT 0x0218 +#define GT64260_CPU_SCS_DECODE_3_TOP 0x0220 + +/* CPU Device Controller Window Registers (4 windows) */ +#define GT64260_CPU_CS_DECODE_WINDOWS 4 + +#define GT64260_CPU_CS_DECODE_0_BOT 0x0028 +#define GT64260_CPU_CS_DECODE_0_TOP 0x0030 +#define GT64260_CPU_CS_DECODE_1_BOT 0x0228 +#define GT64260_CPU_CS_DECODE_1_TOP 0x0230 +#define GT64260_CPU_CS_DECODE_2_BOT 0x0248 +#define GT64260_CPU_CS_DECODE_2_TOP 0x0250 +#define GT64260_CPU_CS_DECODE_3_BOT 0x0038 +#define GT64260_CPU_CS_DECODE_3_TOP 0x0040 + +#define GT64260_CPU_BOOT_CS_DECODE_0_BOT 0x0238 +#define GT64260_CPU_BOOT_CS_DECODE_0_TOP 0x0240 + +/* CPU Windows to PCI space (2 PCI buses each w/ 1 I/O & 4 MEM windows) */ +#define GT64260_PCI_BUSES 2 +#define GT64260_PCI_IO_WINDOWS_PER_BUS 1 +#define GT64260_PCI_MEM_WINDOWS_PER_BUS 4 + +#define GT64260_CPU_PCI_SWAP_BYTE 0x00000000 +#define GT64260_CPU_PCI_SWAP_NONE 0x01000000 +#define GT64260_CPU_PCI_SWAP_BYTE_WORD 0x02000000 +#define GT64260_CPU_PCI_SWAP_WORD 0x03000000 +#define GT64260_CPU_PCI_SWAP_MASK 0x07000000 + +#define GT64260_CPU_PCI_MEM_REQ64 (1<<27) + +#define GT64260_CPU_PCI_0_IO_DECODE_BOT 0x0048 +#define GT64260_CPU_PCI_0_IO_DECODE_TOP 0x0050 +#define GT64260_CPU_PCI_0_MEM_0_DECODE_BOT 0x0058 +#define GT64260_CPU_PCI_0_MEM_0_DECODE_TOP 0x0060 +#define GT64260_CPU_PCI_0_MEM_1_DECODE_BOT 0x0080 +#define GT64260_CPU_PCI_0_MEM_1_DECODE_TOP 0x0088 +#define GT64260_CPU_PCI_0_MEM_2_DECODE_BOT 0x0258 +#define GT64260_CPU_PCI_0_MEM_2_DECODE_TOP 0x0260 +#define GT64260_CPU_PCI_0_MEM_3_DECODE_BOT 0x0280 +#define GT64260_CPU_PCI_0_MEM_3_DECODE_TOP 0x0288 + +#define GT64260_CPU_PCI_0_IO_REMAP 0x00f0 +#define GT64260_CPU_PCI_0_MEM_0_REMAP_LO 0x00f8 +#define GT64260_CPU_PCI_0_MEM_0_REMAP_HI 0x0320 +#define GT64260_CPU_PCI_0_MEM_1_REMAP_LO 0x0100 +#define GT64260_CPU_PCI_0_MEM_1_REMAP_HI 0x0328 +#define GT64260_CPU_PCI_0_MEM_2_REMAP_LO 0x02f8 +#define GT64260_CPU_PCI_0_MEM_2_REMAP_HI 0x0330 +#define GT64260_CPU_PCI_0_MEM_3_REMAP_LO 0x0300 +#define GT64260_CPU_PCI_0_MEM_3_REMAP_HI 0x0338 + +#define GT64260_CPU_PCI_1_IO_DECODE_BOT 0x0090 +#define GT64260_CPU_PCI_1_IO_DECODE_TOP 0x0098 +#define GT64260_CPU_PCI_1_MEM_0_DECODE_BOT 0x00a0 +#define GT64260_CPU_PCI_1_MEM_0_DECODE_TOP 0x00a8 +#define GT64260_CPU_PCI_1_MEM_1_DECODE_BOT 0x00b0 +#define GT64260_CPU_PCI_1_MEM_1_DECODE_TOP 0x00b8 +#define GT64260_CPU_PCI_1_MEM_2_DECODE_BOT 0x02a0 +#define GT64260_CPU_PCI_1_MEM_2_DECODE_TOP 0x02a8 +#define GT64260_CPU_PCI_1_MEM_3_DECODE_BOT 0x02b0 +#define GT64260_CPU_PCI_1_MEM_3_DECODE_TOP 0x02b8 + +#define GT64260_CPU_PCI_1_IO_REMAP 0x0108 +#define GT64260_CPU_PCI_1_MEM_0_REMAP_LO 0x0110 +#define GT64260_CPU_PCI_1_MEM_0_REMAP_HI 0x0340 +#define GT64260_CPU_PCI_1_MEM_1_REMAP_LO 0x0118 +#define GT64260_CPU_PCI_1_MEM_1_REMAP_HI 0x0348 +#define GT64260_CPU_PCI_1_MEM_2_REMAP_LO 0x0310 +#define GT64260_CPU_PCI_1_MEM_2_REMAP_HI 0x0350 +#define GT64260_CPU_PCI_1_MEM_3_REMAP_LO 0x0318 +#define GT64260_CPU_PCI_1_MEM_3_REMAP_HI 0x0358 + +/* CPU Control Registers */ +#define GT64260_CPU_CONFIG 0x0000 +#define GT64260_CPU_MODE 0x0120 +#define GT64260_CPU_MASTER_CNTL 0x0160 +#define GT64260_CPU_XBAR_CNTL_LO 0x0150 +#define GT64260_CPU_XBAR_CNTL_HI 0x0158 +#define GT64260_CPU_XBAR_TO 0x0168 +#define GT64260_CPU_RR_XBAR_CNTL_LO 0x0170 +#define GT64260_CPU_RR_XBAR_CNTL_HI 0x0178 + +/* CPU Sync Barrier Registers */ +#define GT64260_CPU_SYNC_BARRIER_PCI_0 0x00c0 +#define GT64260_CPU_SYNC_BARRIER_PCI_1 0x00c8 + +/* CPU Access Protection Registers */ +#define GT64260_CPU_PROT_WINDOWS 8 + +#define GT64260_CPU_PROT_ACCPROTECT (1<<16) +#define GT64260_CPU_PROT_WRPROTECT (1<<17) +#define GT64260_CPU_PROT_CACHEPROTECT (1<<18) + +#define GT64260_CPU_PROT_BASE_0 0x0180 +#define GT64260_CPU_PROT_TOP_0 0x0188 +#define GT64260_CPU_PROT_BASE_1 0x0190 +#define GT64260_CPU_PROT_TOP_1 0x0198 +#define GT64260_CPU_PROT_BASE_2 0x01a0 +#define GT64260_CPU_PROT_TOP_2 0x01a8 +#define GT64260_CPU_PROT_BASE_3 0x01b0 +#define GT64260_CPU_PROT_TOP_3 0x01b8 +#define GT64260_CPU_PROT_BASE_4 0x01c0 +#define GT64260_CPU_PROT_TOP_4 0x01c8 +#define GT64260_CPU_PROT_BASE_5 0x01d0 +#define GT64260_CPU_PROT_TOP_5 0x01d8 +#define GT64260_CPU_PROT_BASE_6 0x01e0 +#define GT64260_CPU_PROT_TOP_6 0x01e8 +#define GT64260_CPU_PROT_BASE_7 0x01f0 +#define GT64260_CPU_PROT_TOP_7 0x01f8 + +/* CPU Snoop Control Registers */ +#define GT64260_CPU_SNOOP_WINDOWS 4 + +#define GT64260_CPU_SNOOP_NONE 0x00000000 +#define GT64260_CPU_SNOOP_WT 0x00010000 +#define GT64260_CPU_SNOOP_WB 0x00020000 +#define GT64260_CPU_SNOOP_MASK 0x00030000 +#define GT64260_CPU_SNOOP_ALL_BITS GT64260_CPU_SNOOP_MASK + +#define GT64260_CPU_SNOOP_BASE_0 0x0380 +#define GT64260_CPU_SNOOP_TOP_0 0x0388 +#define GT64260_CPU_SNOOP_BASE_1 0x0390 +#define GT64260_CPU_SNOOP_TOP_1 0x0398 +#define GT64260_CPU_SNOOP_BASE_2 0x03a0 +#define GT64260_CPU_SNOOP_TOP_2 0x03a8 +#define GT64260_CPU_SNOOP_BASE_3 0x03b0 +#define GT64260_CPU_SNOOP_TOP_3 0x03b8 + +/* CPU Error Report Registers */ +#define GT64260_CPU_ERR_ADDR_LO 0x0070 +#define GT64260_CPU_ERR_ADDR_HI 0x0078 +#define GT64260_CPU_ERR_DATA_LO 0x0128 +#define GT64260_CPU_ERR_DATA_HI 0x0130 +#define GT64260_CPU_ERR_PARITY 0x0138 +#define GT64260_CPU_ERR_CAUSE 0x0140 +#define GT64260_CPU_ERR_MASK 0x0148 + + +/* + ***************************************************************************** + * + * SDRAM Cotnroller Registers + * + ***************************************************************************** + */ + +/* SDRAM Config Registers */ +#define GT64260_SDRAM_CONFIG 0x0448 +#define GT64260_SDRAM_OPERATION_MODE 0x0474 +#define GT64260_SDRAM_ADDR_CNTL 0x047c +#define GT64260_SDRAM_TIMING_PARAMS 0x04b4 +#define GT64260_SDRAM_UMA_CNTL 0x04a4 +#define GT64260_SDRAM_XBAR_CNTL_LO 0x04a8 +#define GT64260_SDRAM_XBAR_CNTL_HI 0x04ac +#define GT64260_SDRAM_XBAR_CNTL_TO 0x04b0 + +/* SDRAM Banks Parameters Registers */ +#define GT64260_SDRAM_BANK_PARAMS_0 0x044c +#define GT64260_SDRAM_BANK_PARAMS_1 0x0450 +#define GT64260_SDRAM_BANK_PARAMS_2 0x0454 +#define GT64260_SDRAM_BANK_PARAMS_3 0x0458 + +/* SDRAM Error Report Registers */ +#define GT64260_SDRAM_ERR_DATA_LO 0x0484 +#define GT64260_SDRAM_ERR_DATA_HI 0x0480 +#define GT64260_SDRAM_ERR_ADDR 0x0490 +#define GT64260_SDRAM_ERR_ECC_RCVD 0x0488 +#define GT64260_SDRAM_ERR_ECC_CALC 0x048c +#define GT64260_SDRAM_ERR_ECC_CNTL 0x0494 +#define GT64260_SDRAM_ERR_ECC_ERR_CNT 0x0498 + + +/* + ***************************************************************************** + * + * Device/BOOT Cotnroller Registers + * + ***************************************************************************** + */ + +/* Device Control Registers */ +#define GT64260_DEV_BANK_PARAMS_0 0x045c +#define GT64260_DEV_BANK_PARAMS_1 0x0460 +#define GT64260_DEV_BANK_PARAMS_2 0x0464 +#define GT64260_DEV_BANK_PARAMS_3 0x0468 +#define GT64260_DEV_BOOT_PARAMS 0x046c +#define GT64260_DEV_IF_CNTL 0x04c0 +#define GT64260_DEV_IF_XBAR_CNTL_LO 0x04c8 +#define GT64260_DEV_IF_XBAR_CNTL_HI 0x04cc +#define GT64260_DEV_IF_XBAR_CNTL_TO 0x04c4 + +/* Device Interrupt Registers */ +#define GT64260_DEV_INTR_CAUSE 0x04d0 +#define GT64260_DEV_INTR_MASK 0x04d4 +#define GT64260_DEV_INTR_ERR_ADDR 0x04d8 + + +/* + ***************************************************************************** + * + * PCI Bridge Interface Registers + * + ***************************************************************************** + */ + +/* PCI Configuration Access Registers */ +#define GT64260_PCI_0_CONFIG_ADDR 0x0cf8 +#define GT64260_PCI_0_CONFIG_DATA 0x0cfc +#define GT64260_PCI_0_IACK 0x0c34 + +#define GT64260_PCI_1_CONFIG_ADDR 0x0c78 +#define GT64260_PCI_1_CONFIG_DATA 0x0c7c +#define GT64260_PCI_1_IACK 0x0cb4 + +/* PCI Control Registers */ +#define GT64260_PCI_0_CMD 0x0c00 +#define GT64260_PCI_0_MODE 0x0d00 +#define GT64260_PCI_0_TO_RETRY 0x0c04 +#define GT64260_PCI_0_RD_BUF_DISCARD_TIMER 0x0d04 +#define GT64260_PCI_0_MSI_TRIGGER_TIMER 0x0c38 +#define GT64260_PCI_0_ARBITER_CNTL 0x1d00 +#define GT64260_PCI_0_XBAR_CNTL_LO 0x1d08 +#define GT64260_PCI_0_XBAR_CNTL_HI 0x1d0c +#define GT64260_PCI_0_XBAR_CNTL_TO 0x1d04 +#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_LO 0x1d18 +#define GT64260_PCI_0_RD_RESP_XBAR_CNTL_HI 0x1d1c +#define GT64260_PCI_0_SYNC_BARRIER 0x1d10 +#define GT64260_PCI_0_P2P_CONFIG 0x1d14 +#define GT64260_PCI_0_P2P_SWAP_CNTL 0x1d54 + +#define GT64260_PCI_1_CMD 0x0c80 +#define GT64260_PCI_1_MODE 0x0d80 +#define GT64260_PCI_1_TO_RETRY 0x0c84 +#define GT64260_PCI_1_RD_BUF_DISCARD_TIMER 0x0d84 +#define GT64260_PCI_1_MSI_TRIGGER_TIMER 0x0cb8 +#define GT64260_PCI_1_ARBITER_CNTL 0x1d80 +#define GT64260_PCI_1_XBAR_CNTL_LO 0x1d88 +#define GT64260_PCI_1_XBAR_CNTL_HI 0x1d8c +#define GT64260_PCI_1_XBAR_CNTL_TO 0x1d84 +#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_LO 0x1d98 +#define GT64260_PCI_1_RD_RESP_XBAR_CNTL_HI 0x1d9c +#define GT64260_PCI_1_SYNC_BARRIER 0x1d90 +#define GT64260_PCI_1_P2P_CONFIG 0x1d94 +#define GT64260_PCI_1_P2P_SWAP_CNTL 0x1dd4 + +/* PCI Access Control Regions Registers */ +#define GT64260_PCI_ACC_CNTL_WINDOWS 8 + +#define GT64260_PCI_ACC_CNTL_PREFETCHEN (1<<12) +#define GT64260_PCI_ACC_CNTL_DREADEN (1<<13) +#define GT64260_PCI_ACC_CNTL_RDPREFETCH (1<<16) +#define GT64260_PCI_ACC_CNTL_RDLINEPREFETCH (1<<17) +#define GT64260_PCI_ACC_CNTL_RDMULPREFETCH (1<<18) +#define GT64260_PCI_ACC_CNTL_MBURST_4_WORDS 0x00000000 +#define GT64260_PCI_ACC_CNTL_MBURST_8_WORDS 0x00100000 +#define GT64260_PCI_ACC_CNTL_MBURST_16_WORDS 0x00200000 +#define GT64260_PCI_ACC_CNTL_MBURST_MASK 0x00300000 +#define GT64260_PCI_ACC_CNTL_SWAP_BYTE 0x00000000 +#define GT64260_PCI_ACC_CNTL_SWAP_NONE 0x01000000 +#define GT64260_PCI_ACC_CNTL_SWAP_BYTE_WORD 0x02000000 +#define GT64260_PCI_ACC_CNTL_SWAP_WORD 0x03000000 +#define GT64260_PCI_ACC_CNTL_SWAP_MASK 0x03000000 +#define GT64260_PCI_ACC_CNTL_ACCPROT (1<<28) +#define GT64260_PCI_ACC_CNTL_WRPROT (1<<29) + +#define GT64260_PCI_ACC_CNTL_ALL_BITS (GT64260_PCI_ACC_CNTL_PREFETCHEN | \ + GT64260_PCI_ACC_CNTL_DREADEN | \ + GT64260_PCI_ACC_CNTL_RDPREFETCH | \ + GT64260_PCI_ACC_CNTL_RDLINEPREFETCH |\ + GT64260_PCI_ACC_CNTL_RDMULPREFETCH | \ + GT64260_PCI_ACC_CNTL_MBURST_MASK | \ + GT64260_PCI_ACC_CNTL_SWAP_MASK | \ + GT64260_PCI_ACC_CNTL_ACCPROT| \ + GT64260_PCI_ACC_CNTL_WRPROT) + +#define GT64260_PCI_0_ACC_CNTL_0_BASE_LO 0x1e00 +#define GT64260_PCI_0_ACC_CNTL_0_BASE_HI 0x1e04 +#define GT64260_PCI_0_ACC_CNTL_0_TOP 0x1e08 +#define GT64260_PCI_0_ACC_CNTL_1_BASE_LO 0x1e10 +#define GT64260_PCI_0_ACC_CNTL_1_BASE_HI 0x1e14 +#define GT64260_PCI_0_ACC_CNTL_1_TOP 0x1e18 +#define GT64260_PCI_0_ACC_CNTL_2_BASE_LO 0x1e20 +#define GT64260_PCI_0_ACC_CNTL_2_BASE_HI 0x1e24 +#define GT64260_PCI_0_ACC_CNTL_2_TOP 0x1e28 +#define GT64260_PCI_0_ACC_CNTL_3_BASE_LO 0x1e30 +#define GT64260_PCI_0_ACC_CNTL_3_BASE_HI 0x1e34 +#define GT64260_PCI_0_ACC_CNTL_3_TOP 0x1e38 +#define GT64260_PCI_0_ACC_CNTL_4_BASE_LO 0x1e40 +#define GT64260_PCI_0_ACC_CNTL_4_BASE_HI 0x1e44 +#define GT64260_PCI_0_ACC_CNTL_4_TOP 0x1e48 +#define GT64260_PCI_0_ACC_CNTL_5_BASE_LO 0x1e50 +#define GT64260_PCI_0_ACC_CNTL_5_BASE_HI 0x1e54 +#define GT64260_PCI_0_ACC_CNTL_5_TOP 0x1e58 +#define GT64260_PCI_0_ACC_CNTL_6_BASE_LO 0x1e60 +#define GT64260_PCI_0_ACC_CNTL_6_BASE_HI 0x1e64 +#define GT64260_PCI_0_ACC_CNTL_6_TOP 0x1e68 +#define GT64260_PCI_0_ACC_CNTL_7_BASE_LO 0x1e70 +#define GT64260_PCI_0_ACC_CNTL_7_BASE_HI 0x1e74 +#define GT64260_PCI_0_ACC_CNTL_7_TOP 0x1e78 + +#define GT64260_PCI_1_ACC_CNTL_0_BASE_LO 0x1e80 +#define GT64260_PCI_1_ACC_CNTL_0_BASE_HI 0x1e84 +#define GT64260_PCI_1_ACC_CNTL_0_TOP 0x1e88 +#define GT64260_PCI_1_ACC_CNTL_1_BASE_LO 0x1e90 +#define GT64260_PCI_1_ACC_CNTL_1_BASE_HI 0x1e94 +#define GT64260_PCI_1_ACC_CNTL_1_TOP 0x1e98 +#define GT64260_PCI_1_ACC_CNTL_2_BASE_LO 0x1ea0 +#define GT64260_PCI_1_ACC_CNTL_2_BASE_HI 0x1ea4 +#define GT64260_PCI_1_ACC_CNTL_2_TOP 0x1ea8 +#define GT64260_PCI_1_ACC_CNTL_3_BASE_LO 0x1eb0 +#define GT64260_PCI_1_ACC_CNTL_3_BASE_HI 0x1eb4 +#define GT64260_PCI_1_ACC_CNTL_3_TOP 0x1eb8 +#define GT64260_PCI_1_ACC_CNTL_4_BASE_LO 0x1ec0 +#define GT64260_PCI_1_ACC_CNTL_4_BASE_HI 0x1ec4 +#define GT64260_PCI_1_ACC_CNTL_4_TOP 0x1ec8 +#define GT64260_PCI_1_ACC_CNTL_5_BASE_LO 0x1ed0 +#define GT64260_PCI_1_ACC_CNTL_5_BASE_HI 0x1ed4 +#define GT64260_PCI_1_ACC_CNTL_5_TOP 0x1ed8 +#define GT64260_PCI_1_ACC_CNTL_6_BASE_LO 0x1ee0 +#define GT64260_PCI_1_ACC_CNTL_6_BASE_HI 0x1ee4 +#define GT64260_PCI_1_ACC_CNTL_6_TOP 0x1ee8 +#define GT64260_PCI_1_ACC_CNTL_7_BASE_LO 0x1ef0 +#define GT64260_PCI_1_ACC_CNTL_7_BASE_HI 0x1ef4 +#define GT64260_PCI_1_ACC_CNTL_7_TOP 0x1ef8 + +/* PCI Snoop Control Registers */ +#define GT64260_PCI_SNOOP_WINDOWS 4 + +#define GT64260_PCI_SNOOP_NONE 0x00000000 +#define GT64260_PCI_SNOOP_WT 0x00001000 +#define GT64260_PCI_SNOOP_WB 0x00002000 + +#define GT64260_PCI_0_SNOOP_0_BASE_LO 0x1f00 +#define GT64260_PCI_0_SNOOP_0_BASE_HI 0x1f04 +#define GT64260_PCI_0_SNOOP_0_TOP 0x1f08 +#define GT64260_PCI_0_SNOOP_1_BASE_LO 0x1f10 +#define GT64260_PCI_0_SNOOP_1_BASE_HI 0x1f14 +#define GT64260_PCI_0_SNOOP_1_TOP 0x1f18 +#define GT64260_PCI_0_SNOOP_2_BASE_LO 0x1f20 +#define GT64260_PCI_0_SNOOP_2_BASE_HI 0x1f24 +#define GT64260_PCI_0_SNOOP_2_TOP 0x1f28 +#define GT64260_PCI_0_SNOOP_3_BASE_LO 0x1f30 +#define GT64260_PCI_0_SNOOP_3_BASE_HI 0x1f34 +#define GT64260_PCI_0_SNOOP_3_TOP 0x1f38 + +#define GT64260_PCI_1_SNOOP_0_BASE_LO 0x1f80 +#define GT64260_PCI_1_SNOOP_0_BASE_HI 0x1f84 +#define GT64260_PCI_1_SNOOP_0_TOP 0x1f88 +#define GT64260_PCI_1_SNOOP_1_BASE_LO 0x1f90 +#define GT64260_PCI_1_SNOOP_1_BASE_HI 0x1f94 +#define GT64260_PCI_1_SNOOP_1_TOP 0x1f98 +#define GT64260_PCI_1_SNOOP_2_BASE_LO 0x1fa0 +#define GT64260_PCI_1_SNOOP_2_BASE_HI 0x1fa4 +#define GT64260_PCI_1_SNOOP_2_TOP 0x1fa8 +#define GT64260_PCI_1_SNOOP_3_BASE_LO 0x1fb0 +#define GT64260_PCI_1_SNOOP_3_BASE_HI 0x1fb4 +#define GT64260_PCI_1_SNOOP_3_TOP 0x1fb8 + +/* PCI Error Report Registers */ +#define GT64260_PCI_0_ERR_SERR_MASK 0x0c28 +#define GT64260_PCI_0_ERR_ADDR_LO 0x1d40 +#define GT64260_PCI_0_ERR_ADDR_HI 0x1d44 +#define GT64260_PCI_0_ERR_DATA_LO 0x1d48 +#define GT64260_PCI_0_ERR_DATA_HI 0x1d4c +#define GT64260_PCI_0_ERR_CMD 0x1d50 +#define GT64260_PCI_0_ERR_CAUSE 0x1d58 +#define GT64260_PCI_0_ERR_MASK 0x1d5c + +#define GT64260_PCI_1_ERR_SERR_MASK 0x0ca8 +#define GT64260_PCI_1_ERR_ADDR_LO 0x1dc0 +#define GT64260_PCI_1_ERR_ADDR_HI 0x1dc4 +#define GT64260_PCI_1_ERR_DATA_LO 0x1dc8 +#define GT64260_PCI_1_ERR_DATA_HI 0x1dcc +#define GT64260_PCI_1_ERR_CMD 0x1dd0 +#define GT64260_PCI_1_ERR_CAUSE 0x1dd8 +#define GT64260_PCI_1_ERR_MASK 0x1ddc + +/* PCI Slave Address Decoding Registers */ +#define GT64260_PCI_SCS_WINDOWS 4 +#define GT64260_PCI_CS_WINDOWS 4 +#define GT64260_PCI_BOOT_WINDOWS 1 +#define GT64260_PCI_P2P_MEM_WINDOWS 2 +#define GT64260_PCI_P2P_IO_WINDOWS 1 +#define GT64260_PCI_DAC_SCS_WINDOWS 4 +#define GT64260_PCI_DAC_CS_WINDOWS 4 +#define GT64260_PCI_DAC_BOOT_WINDOWS 1 +#define GT64260_PCI_DAC_P2P_MEM_WINDOWS 2 + +#define GT64260_PCI_0_SLAVE_SCS_0_SIZE 0x0c08 +#define GT64260_PCI_0_SLAVE_SCS_1_SIZE 0x0d08 +#define GT64260_PCI_0_SLAVE_SCS_2_SIZE 0x0c0c +#define GT64260_PCI_0_SLAVE_SCS_3_SIZE 0x0d0c +#define GT64260_PCI_0_SLAVE_CS_0_SIZE 0x0c10 +#define GT64260_PCI_0_SLAVE_CS_1_SIZE 0x0d10 +#define GT64260_PCI_0_SLAVE_CS_2_SIZE 0x0d18 +#define GT64260_PCI_0_SLAVE_CS_3_SIZE 0x0c14 +#define GT64260_PCI_0_SLAVE_BOOT_SIZE 0x0d14 +#define GT64260_PCI_0_SLAVE_P2P_MEM_0_SIZE 0x0d1c +#define GT64260_PCI_0_SLAVE_P2P_MEM_1_SIZE 0x0d20 +#define GT64260_PCI_0_SLAVE_P2P_IO_SIZE 0x0d24 +#define GT64260_PCI_0_SLAVE_CPU_SIZE 0x0d28 + +#define GT64260_PCI_0_SLAVE_DAC_SCS_0_SIZE 0x0e00 +#define GT64260_PCI_0_SLAVE_DAC_SCS_1_SIZE 0x0e04 +#define GT64260_PCI_0_SLAVE_DAC_SCS_2_SIZE 0x0e08 +#define GT64260_PCI_0_SLAVE_DAC_SCS_3_SIZE 0x0e0c +#define GT64260_PCI_0_SLAVE_DAC_CS_0_SIZE 0x0e10 +#define GT64260_PCI_0_SLAVE_DAC_CS_1_SIZE 0x0e14 +#define GT64260_PCI_0_SLAVE_DAC_CS_2_SIZE 0x0e18 +#define GT64260_PCI_0_SLAVE_DAC_CS_3_SIZE 0x0e1c +#define GT64260_PCI_0_SLAVE_DAC_BOOT_SIZE 0x0e20 +#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_SIZE 0x0e24 +#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_SIZE 0x0e28 +#define GT64260_PCI_0_SLAVE_DAC_CPU_SIZE 0x0e2c + +#define GT64260_PCI_0_SLAVE_EXP_ROM_SIZE 0x0d2c + +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_0 (1<<0) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_1 (1<<1) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_2 (1<<2) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_SCS_3 (1<<3) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_0 (1<<4) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_1 (1<<5) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_2 (1<<6) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CS_3 (1<<7) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_BOOT (1<<8) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_MEM (1<<9) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_REG_IO (1<<10) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_0 (1<<11) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_MEM_1 (1<<12) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_P2P_IO (1<<13) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_CPU (1<<14) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_0 (1<<15) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_1 (1<<16) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_2 (1<<17) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_SCS_3 (1<<18) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_0 (1<<19) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_1 (1<<20) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_2 (1<<21) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CS_3 (1<<22) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_BOOT (1<<23) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_0 (1<<24) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_P2P_MEM_1 (1<<25) +#define GT64260_PCI_SLAVE_BAR_REG_ENABLES_DAC_CPU (1<<26) + +#define GT64260_PCI_0_SLAVE_BAR_REG_ENABLES 0x0c3c +#define GT64260_PCI_0_SLAVE_SCS_0_REMAP 0x0c48 +#define GT64260_PCI_0_SLAVE_SCS_1_REMAP 0x0d48 +#define GT64260_PCI_0_SLAVE_SCS_2_REMAP 0x0c4c +#define GT64260_PCI_0_SLAVE_SCS_3_REMAP 0x0d4c +#define GT64260_PCI_0_SLAVE_CS_0_REMAP 0x0c50 +#define GT64260_PCI_0_SLAVE_CS_1_REMAP 0x0d50 +#define GT64260_PCI_0_SLAVE_CS_2_REMAP 0x0d58 +#define GT64260_PCI_0_SLAVE_CS_3_REMAP 0x0c54 +#define GT64260_PCI_0_SLAVE_BOOT_REMAP 0x0d54 +#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_LO 0x0d5c +#define GT64260_PCI_0_SLAVE_P2P_MEM_0_REMAP_HI 0x0d60 +#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_LO 0x0d64 +#define GT64260_PCI_0_SLAVE_P2P_MEM_1_REMAP_HI 0x0d68 +#define GT64260_PCI_0_SLAVE_P2P_IO_REMAP 0x0d6c +#define GT64260_PCI_0_SLAVE_CPU_REMAP 0x0d70 + +#define GT64260_PCI_0_SLAVE_DAC_SCS_0_REMAP 0x0f00 +#define GT64260_PCI_0_SLAVE_DAC_SCS_1_REMAP 0x0f04 +#define GT64260_PCI_0_SLAVE_DAC_SCS_2_REMAP 0x0f08 +#define GT64260_PCI_0_SLAVE_DAC_SCS_3_REMAP 0x0f0c +#define GT64260_PCI_0_SLAVE_DAC_CS_0_REMAP 0x0f10 +#define GT64260_PCI_0_SLAVE_DAC_CS_1_REMAP 0x0f14 +#define GT64260_PCI_0_SLAVE_DAC_CS_2_REMAP 0x0f18 +#define GT64260_PCI_0_SLAVE_DAC_CS_3_REMAP 0x0f1c +#define GT64260_PCI_0_SLAVE_DAC_BOOT_REMAP 0x0f20 +#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0f24 +#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0f28 +#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0f2c +#define GT64260_PCI_0_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0f30 +#define GT64260_PCI_0_SLAVE_DAC_CPU_REMAP 0x0f34 + +#define GT64260_PCI_0_SLAVE_EXP_ROM_REMAP 0x0f38 +#define GT64260_PCI_0_SLAVE_PCI_DECODE_CNTL 0x0d3c + +#define GT64260_PCI_1_SLAVE_SCS_0_SIZE 0x0c88 +#define GT64260_PCI_1_SLAVE_SCS_1_SIZE 0x0d88 +#define GT64260_PCI_1_SLAVE_SCS_2_SIZE 0x0c8c +#define GT64260_PCI_1_SLAVE_SCS_3_SIZE 0x0d8c +#define GT64260_PCI_1_SLAVE_CS_0_SIZE 0x0c90 +#define GT64260_PCI_1_SLAVE_CS_1_SIZE 0x0d90 +#define GT64260_PCI_1_SLAVE_CS_2_SIZE 0x0d98 +#define GT64260_PCI_1_SLAVE_CS_3_SIZE 0x0c94 +#define GT64260_PCI_1_SLAVE_BOOT_SIZE 0x0d94 +#define GT64260_PCI_1_SLAVE_P2P_MEM_0_SIZE 0x0d9c +#define GT64260_PCI_1_SLAVE_P2P_MEM_1_SIZE 0x0da0 +#define GT64260_PCI_1_SLAVE_P2P_IO_SIZE 0x0da4 +#define GT64260_PCI_1_SLAVE_CPU_SIZE 0x0da8 + +#define GT64260_PCI_1_SLAVE_DAC_SCS_0_SIZE 0x0e80 +#define GT64260_PCI_1_SLAVE_DAC_SCS_1_SIZE 0x0e84 +#define GT64260_PCI_1_SLAVE_DAC_SCS_2_SIZE 0x0e88 +#define GT64260_PCI_1_SLAVE_DAC_SCS_3_SIZE 0x0e8c +#define GT64260_PCI_1_SLAVE_DAC_CS_0_SIZE 0x0e90 +#define GT64260_PCI_1_SLAVE_DAC_CS_1_SIZE 0x0e94 +#define GT64260_PCI_1_SLAVE_DAC_CS_2_SIZE 0x0e98 +#define GT64260_PCI_1_SLAVE_DAC_CS_3_SIZE 0x0e9c +#define GT64260_PCI_1_SLAVE_DAC_BOOT_SIZE 0x0ea0 +#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_SIZE 0x0ea4 +#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_SIZE 0x0ea8 +#define GT64260_PCI_1_SLAVE_DAC_CPU_SIZE 0x0eac + +#define GT64260_PCI_1_SLAVE_EXP_ROM_SIZE 0x0dac + +#define GT64260_PCI_1_SLAVE_BAR_REG_ENABLES 0x0cbc +#define GT64260_PCI_1_SLAVE_SCS_0_REMAP 0x0cc8 +#define GT64260_PCI_1_SLAVE_SCS_1_REMAP 0x0dc8 +#define GT64260_PCI_1_SLAVE_SCS_2_REMAP 0x0ccc +#define GT64260_PCI_1_SLAVE_SCS_3_REMAP 0x0dcc +#define GT64260_PCI_1_SLAVE_CS_0_REMAP 0x0cd0 +#define GT64260_PCI_1_SLAVE_CS_1_REMAP 0x0dd0 +#define GT64260_PCI_1_SLAVE_CS_2_REMAP 0x0dd8 +#define GT64260_PCI_1_SLAVE_CS_3_REMAP 0x0cd4 +#define GT64260_PCI_1_SLAVE_BOOT_REMAP 0x0dd4 +#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_LO 0x0ddc +#define GT64260_PCI_1_SLAVE_P2P_MEM_0_REMAP_HI 0x0de0 +#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_LO 0x0de4 +#define GT64260_PCI_1_SLAVE_P2P_MEM_1_REMAP_HI 0x0de8 +#define GT64260_PCI_1_SLAVE_P2P_IO_REMAP 0x0dec +#define GT64260_PCI_1_SLAVE_CPU_REMAP 0x0df0 + +#define GT64260_PCI_1_SLAVE_DAC_SCS_0_REMAP 0x0f80 +#define GT64260_PCI_1_SLAVE_DAC_SCS_1_REMAP 0x0f84 +#define GT64260_PCI_1_SLAVE_DAC_SCS_2_REMAP 0x0f88 +#define GT64260_PCI_1_SLAVE_DAC_SCS_3_REMAP 0x0f8c +#define GT64260_PCI_1_SLAVE_DAC_CS_0_REMAP 0x0f90 +#define GT64260_PCI_1_SLAVE_DAC_CS_1_REMAP 0x0f94 +#define GT64260_PCI_1_SLAVE_DAC_CS_2_REMAP 0x0f98 +#define GT64260_PCI_1_SLAVE_DAC_CS_3_REMAP 0x0f9c +#define GT64260_PCI_1_SLAVE_DAC_BOOT_REMAP 0x0fa0 +#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_LO 0x0fa4 +#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_0_REMAP_HI 0x0fa8 +#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_LO 0x0fac +#define GT64260_PCI_1_SLAVE_DAC_P2P_MEM_1_REMAP_HI 0x0fb0 +#define GT64260_PCI_1_SLAVE_DAC_CPU_REMAP 0x0fb4 + +#define GT64260_PCI_1_SLAVE_EXP_ROM_REMAP 0x0fb8 +#define GT64260_PCI_1_SLAVE_PCI_DECODE_CNTL 0x0dbc + + +/* + ***************************************************************************** + * + * I2O Controller Interface Registers + * + ***************************************************************************** + */ + +/* FIXME: fill in */ + + + +/* + ***************************************************************************** + * + * DMA Controller Interface Registers + * + ***************************************************************************** + */ + +/* FIXME: fill in */ + + +/* + ***************************************************************************** + * + * Timer/Counter Interface Registers + * + ***************************************************************************** + */ + +/* FIXME: fill in */ + + +/* + ***************************************************************************** + * + * Communications Controller (Enet, Serial, etc.) Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_ENET_0_CNTL_LO 0xf200 +#define GT64260_ENET_0_CNTL_HI 0xf204 +#define GT64260_ENET_0_RX_BUF_PCI_ADDR_HI 0xf208 +#define GT64260_ENET_0_TX_BUF_PCI_ADDR_HI 0xf20c +#define GT64260_ENET_0_RX_DESC_ADDR_HI 0xf210 +#define GT64260_ENET_0_TX_DESC_ADDR_HI 0xf214 +#define GT64260_ENET_0_HASH_TAB_PCI_ADDR_HI 0xf218 +#define GT64260_ENET_1_CNTL_LO 0xf220 +#define GT64260_ENET_1_CNTL_HI 0xf224 +#define GT64260_ENET_1_RX_BUF_PCI_ADDR_HI 0xf228 +#define GT64260_ENET_1_TX_BUF_PCI_ADDR_HI 0xf22c +#define GT64260_ENET_1_RX_DESC_ADDR_HI 0xf230 +#define GT64260_ENET_1_TX_DESC_ADDR_HI 0xf234 +#define GT64260_ENET_1_HASH_TAB_PCI_ADDR_HI 0xf238 +#define GT64260_ENET_2_CNTL_LO 0xf240 +#define GT64260_ENET_2_CNTL_HI 0xf244 +#define GT64260_ENET_2_RX_BUF_PCI_ADDR_HI 0xf248 +#define GT64260_ENET_2_TX_BUF_PCI_ADDR_HI 0xf24c +#define GT64260_ENET_2_RX_DESC_ADDR_HI 0xf250 +#define GT64260_ENET_2_TX_DESC_ADDR_HI 0xf254 +#define GT64260_ENET_2_HASH_TAB_PCI_ADDR_HI 0xf258 + +#define GT64260_MPSC_0_CNTL_LO 0xf280 +#define GT64260_MPSC_0_CNTL_HI 0xf284 +#define GT64260_MPSC_0_RX_BUF_PCI_ADDR_HI 0xf288 +#define GT64260_MPSC_0_TX_BUF_PCI_ADDR_HI 0xf28c +#define GT64260_MPSC_0_RX_DESC_ADDR_HI 0xf290 +#define GT64260_MPSC_0_TX_DESC_ADDR_HI 0xf294 +#define GT64260_MPSC_1_CNTL_LO 0xf2c0 +#define GT64260_MPSC_1_CNTL_HI 0xf2c4 +#define GT64260_MPSC_1_RX_BUF_PCI_ADDR_HI 0xf2c8 +#define GT64260_MPSC_1_TX_BUF_PCI_ADDR_HI 0xf2cc +#define GT64260_MPSC_1_RX_DESC_ADDR_HI 0xf2d0 +#define GT64260_MPSC_1_TX_DESC_ADDR_HI 0xf2d4 + +#define GT64260_SER_INIT_PCI_ADDR_HI 0xf320 +#define GT64260_SER_INIT_LAST_DATA 0xf324 +#define GT64260_SER_INIT_CONTROL 0xf328 +#define GT64260_SER_INIT_STATUS 0xf32c + +#define GT64260_COMM_ARBITER_CNTL 0xf300 +#define GT64260_COMM_CONFIG 0xb40c +#define GT64260_COMM_XBAR_TO 0xf304 +#define GT64260_COMM_INTR_CAUSE 0xf310 +#define GT64260_COMM_INTR_MASK 0xf314 +#define GT64260_COMM_ERR_ADDR 0xf318 + + +/* + ***************************************************************************** + * + * Fast Ethernet Controller Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_ENET_PHY_ADDR 0x2000 +#define GT64260_ENET_ESMIR 0x2010 + +#define GT64260_ENET_E0PCR 0x2400 +#define GT64260_ENET_E0PCXR 0x2408 +#define GT64260_ENET_E0PCMR 0x2410 +#define GT64260_ENET_E0PSR 0x2418 +#define GT64260_ENET_E0SPR 0x2420 +#define GT64260_ENET_E0HTPR 0x2428 +#define GT64260_ENET_E0FCSAL 0x2430 +#define GT64260_ENET_E0FCSAH 0x2438 +#define GT64260_ENET_E0SDCR 0x2440 +#define GT64260_ENET_E0SDCMR 0x2448 +#define GT64260_ENET_E0ICR 0x2450 +#define GT64260_ENET_E0IMR 0x2458 +#define GT64260_ENET_E0FRDP0 0x2480 +#define GT64260_ENET_E0FRDP1 0x2484 +#define GT64260_ENET_E0FRDP2 0x2488 +#define GT64260_ENET_E0FRDP3 0x248c +#define GT64260_ENET_E0CRDP0 0x24a0 +#define GT64260_ENET_E0CRDP1 0x24a4 +#define GT64260_ENET_E0CRDP2 0x24a8 +#define GT64260_ENET_E0CRDP3 0x24ac +#define GT64260_ENET_E0CTDP0 0x24e0 +#define GT64260_ENET_E0CTDP1 0x24e4 +#define GT64260_ENET_0_DSCP2P0L 0x2460 +#define GT64260_ENET_0_DSCP2P0H 0x2464 +#define GT64260_ENET_0_DSCP2P1L 0x2468 +#define GT64260_ENET_0_DSCP2P1H 0x246c +#define GT64260_ENET_0_VPT2P 0x2470 +#define GT64260_ENET_0_MIB_CTRS 0x2500 + +#define GT64260_ENET_E1PCR 0x2800 +#define GT64260_ENET_E1PCXR 0x2808 +#define GT64260_ENET_E1PCMR 0x2810 +#define GT64260_ENET_E1PSR 0x2818 +#define GT64260_ENET_E1SPR 0x2820 +#define GT64260_ENET_E1HTPR 0x2828 +#define GT64260_ENET_E1FCSAL 0x2830 +#define GT64260_ENET_E1FCSAH 0x2838 +#define GT64260_ENET_E1SDCR 0x2840 +#define GT64260_ENET_E1SDCMR 0x2848 +#define GT64260_ENET_E1ICR 0x2850 +#define GT64260_ENET_E1IMR 0x2858 +#define GT64260_ENET_E1FRDP0 0x2880 +#define GT64260_ENET_E1FRDP1 0x2884 +#define GT64260_ENET_E1FRDP2 0x2888 +#define GT64260_ENET_E1FRDP3 0x288c +#define GT64260_ENET_E1CRDP0 0x28a0 +#define GT64260_ENET_E1CRDP1 0x28a4 +#define GT64260_ENET_E1CRDP2 0x28a8 +#define GT64260_ENET_E1CRDP3 0x28ac +#define GT64260_ENET_E1CTDP0 0x28e0 +#define GT64260_ENET_E1CTDP1 0x28e4 +#define GT64260_ENET_1_DSCP2P0L 0x2860 +#define GT64260_ENET_1_DSCP2P0H 0x2864 +#define GT64260_ENET_1_DSCP2P1L 0x2868 +#define GT64260_ENET_1_DSCP2P1H 0x286c +#define GT64260_ENET_1_VPT2P 0x2870 +#define GT64260_ENET_1_MIB_CTRS 0x2900 + +#define GT64260_ENET_E2PCR 0x2c00 +#define GT64260_ENET_E2PCXR 0x2c08 +#define GT64260_ENET_E2PCMR 0x2c10 +#define GT64260_ENET_E2PSR 0x2c18 +#define GT64260_ENET_E2SPR 0x2c20 +#define GT64260_ENET_E2HTPR 0x2c28 +#define GT64260_ENET_E2FCSAL 0x2c30 +#define GT64260_ENET_E2FCSAH 0x2c38 +#define GT64260_ENET_E2SDCR 0x2c40 +#define GT64260_ENET_E2SDCMR 0x2c48 +#define GT64260_ENET_E2ICR 0x2c50 +#define GT64260_ENET_E2IMR 0x2c58 +#define GT64260_ENET_E2FRDP0 0x2c80 +#define GT64260_ENET_E2FRDP1 0x2c84 +#define GT64260_ENET_E2FRDP2 0x2c88 +#define GT64260_ENET_E2FRDP3 0x2c8c +#define GT64260_ENET_E2CRDP0 0x2ca0 +#define GT64260_ENET_E2CRDP1 0x2ca4 +#define GT64260_ENET_E2CRDP2 0x2ca8 +#define GT64260_ENET_E2CRDP3 0x2cac +#define GT64260_ENET_E2CTDP0 0x2ce0 +#define GT64260_ENET_E2CTDP1 0x2ce4 +#define GT64260_ENET_2_DSCP2P0L 0x2c60 +#define GT64260_ENET_2_DSCP2P0H 0x2c64 +#define GT64260_ENET_2_DSCP2P1L 0x2c68 +#define GT64260_ENET_2_DSCP2P1H 0x2c6c +#define GT64260_ENET_2_VPT2P 0x2c70 +#define GT64260_ENET_2_MIB_CTRS 0x2d00 + + +/* + ***************************************************************************** + * + * Multi-Protocol Serial Controller Interface Registers + * + ***************************************************************************** + */ + +/* Signal Routing */ +#define GT64260_MPSC_MRR 0xb400 +#define GT64260_MPSC_RCRR 0xb404 +#define GT64260_MPSC_TCRR 0xb408 + +/* Main Configuratino Registers */ +#define GT64260_MPSC_0_MMCRL 0x8000 +#define GT64260_MPSC_0_MMCRH 0x8004 +#define GT64260_MPSC_0_MPCR 0x8008 +#define GT64260_MPSC_0_CHR_1 0x800c +#define GT64260_MPSC_0_CHR_2 0x8010 +#define GT64260_MPSC_0_CHR_3 0x8014 +#define GT64260_MPSC_0_CHR_4 0x8018 +#define GT64260_MPSC_0_CHR_5 0x801c +#define GT64260_MPSC_0_CHR_6 0x8020 +#define GT64260_MPSC_0_CHR_7 0x8024 +#define GT64260_MPSC_0_CHR_8 0x8028 +#define GT64260_MPSC_0_CHR_9 0x802c +#define GT64260_MPSC_0_CHR_10 0x8030 +#define GT64260_MPSC_0_CHR_11 0x8034 + +#define GT64260_MPSC_1_MMCRL 0x9000 +#define GT64260_MPSC_1_MMCRH 0x9004 +#define GT64260_MPSC_1_MPCR 0x9008 +#define GT64260_MPSC_1_CHR_1 0x900c +#define GT64260_MPSC_1_CHR_2 0x9010 +#define GT64260_MPSC_1_CHR_3 0x9014 +#define GT64260_MPSC_1_CHR_4 0x9018 +#define GT64260_MPSC_1_CHR_5 0x901c +#define GT64260_MPSC_1_CHR_6 0x9020 +#define GT64260_MPSC_1_CHR_7 0x9024 +#define GT64260_MPSC_1_CHR_8 0x9028 +#define GT64260_MPSC_1_CHR_9 0x902c +#define GT64260_MPSC_1_CHR_10 0x9030 +#define GT64260_MPSC_1_CHR_11 0x9034 + +#define GT64260_MPSC_0_INTR_CAUSE 0xb804 +#define GT64260_MPSC_0_INTR_MASK 0xb884 +#define GT64260_MPSC_1_INTR_CAUSE 0xb80c +#define GT64260_MPSC_1_INTR_MASK 0xb88c + +#define GT64260_MPSC_UART_CR_TEV (1<<1) +#define GT64260_MPSC_UART_CR_TA (1<<7) +#define GT64260_MPSC_UART_CR_TTCS (1<<9) +#define GT64260_MPSC_UART_CR_REV (1<<17) +#define GT64260_MPSC_UART_CR_RA (1<<23) +#define GT64260_MPSC_UART_CR_CRD (1<<25) +#define GT64260_MPSC_UART_CR_EH (1<<31) + +#define GT64260_MPSC_UART_ESR_CTS (1<<0) +#define GT64260_MPSC_UART_ESR_CD (1<<1) +#define GT64260_MPSC_UART_ESR_TIDLE (1<<3) +#define GT64260_MPSC_UART_ESR_RHS (1<<5) +#define GT64260_MPSC_UART_ESR_RLS (1<<7) +#define GT64260_MPSC_UART_ESR_RLIDL (1<<11) + + +/* + ***************************************************************************** + * + * Serial DMA Controller Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_SDMA_0_SDC 0x4000 +#define GT64260_SDMA_0_SDCM 0x4008 +#define GT64260_SDMA_0_RX_DESC 0x4800 +#define GT64260_SDMA_0_RX_BUF_PTR 0x4808 +#define GT64260_SDMA_0_SCRDP 0x4810 +#define GT64260_SDMA_0_TX_DESC 0x4c00 +#define GT64260_SDMA_0_SCTDP 0x4c10 +#define GT64260_SDMA_0_SFTDP 0x4c14 + +#define GT64260_SDMA_1_SDC 0x6000 +#define GT64260_SDMA_1_SDCM 0x6008 +#define GT64260_SDMA_1_RX_DESC 0x6800 +#define GT64260_SDMA_1_RX_BUF_PTR 0x6808 +#define GT64260_SDMA_1_SCRDP 0x6810 +#define GT64260_SDMA_1_TX_DESC 0x6c00 +#define GT64260_SDMA_1_SCTDP 0x6c10 +#define GT64260_SDMA_1_SFTDP 0x6c14 + +#define GT64260_SDMA_INTR_CAUSE 0xb800 +#define GT64260_SDMA_INTR_MASK 0xb880 + +#define GT64260_SDMA_DESC_CMDSTAT_PE (1<<0) +#define GT64260_SDMA_DESC_CMDSTAT_CDL (1<<1) +#define GT64260_SDMA_DESC_CMDSTAT_FR (1<<3) +#define GT64260_SDMA_DESC_CMDSTAT_OR (1<<6) +#define GT64260_SDMA_DESC_CMDSTAT_BR (1<<9) +#define GT64260_SDMA_DESC_CMDSTAT_MI (1<<10) +#define GT64260_SDMA_DESC_CMDSTAT_A (1<<11) +#define GT64260_SDMA_DESC_CMDSTAT_AM (1<<12) +#define GT64260_SDMA_DESC_CMDSTAT_CT (1<<13) +#define GT64260_SDMA_DESC_CMDSTAT_C (1<<14) +#define GT64260_SDMA_DESC_CMDSTAT_ES (1<<15) +#define GT64260_SDMA_DESC_CMDSTAT_L (1<<16) +#define GT64260_SDMA_DESC_CMDSTAT_F (1<<17) +#define GT64260_SDMA_DESC_CMDSTAT_P (1<<18) +#define GT64260_SDMA_DESC_CMDSTAT_EI (1<<23) +#define GT64260_SDMA_DESC_CMDSTAT_O (1<<31) + +#define GT64260_SDMA_SDC_RFT (1<<0) +#define GT64260_SDMA_SDC_SFM (1<<1) +#define GT64260_SDMA_SDC_BLMR (1<<6) +#define GT64260_SDMA_SDC_BLMT (1<<7) +#define GT64260_SDMA_SDC_POVR (1<<8) +#define GT64260_SDMA_SDC_RIFB (1<<9) + +#define GT64260_SDMA_SDCM_ERD (1<<7) +#define GT64260_SDMA_SDCM_AR (1<<15) +#define GT64260_SDMA_SDCM_STD (1<<16) +#define GT64260_SDMA_SDCM_TXD (1<<23) +#define GT64260_SDMA_SDCM_AT (1<<31) + +#define GT64260_SDMA_0_CAUSE_RXBUF (1<<0) +#define GT64260_SDMA_0_CAUSE_RXERR (1<<1) +#define GT64260_SDMA_0_CAUSE_TXBUF (1<<2) +#define GT64260_SDMA_0_CAUSE_TXEND (1<<3) +#define GT64260_SDMA_1_CAUSE_RXBUF (1<<8) +#define GT64260_SDMA_1_CAUSE_RXERR (1<<9) +#define GT64260_SDMA_1_CAUSE_TXBUF (1<<10) +#define GT64260_SDMA_1_CAUSE_TXEND (1<<11) + + +/* + ***************************************************************************** + * + * Baud Rate Generator Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_BRG_0_BCR 0xb200 +#define GT64260_BRG_0_BTR 0xb204 +#define GT64260_BRG_1_BCR 0xb208 +#define GT64260_BRG_1_BTR 0xb20c +#define GT64260_BRG_2_BCR 0xb210 +#define GT64260_BRG_2_BTR 0xb214 + +#define GT64260_BRG_INTR_CAUSE 0xb834 +#define GT64260_BRG_INTR_MASK 0xb8b4 + + +/* + ***************************************************************************** + * + * Watchdog Timer Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_WDT_WDC 0xb410 +#define GT64260_WDT_WDV 0xb414 + + +/* + ***************************************************************************** + * + * General Purpose Pins Controller Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_GPP_IO_CNTL 0xf100 +#define GT64260_GPP_LEVEL_CNTL 0xf110 +#define GT64260_GPP_VALUE 0xf104 +#define GT64260_GPP_INTR_CAUSE 0xf108 +#define GT64260_GPP_INTR_MASK 0xf10c + + +/* + ***************************************************************************** + * + * Multi-Purpose Pins Controller Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_MPP_CNTL_0 0xf000 +#define GT64260_MPP_CNTL_1 0xf004 +#define GT64260_MPP_CNTL_2 0xf008 +#define GT64260_MPP_CNTL_3 0xf00c +#define GT64260_MPP_SERIAL_PORTS_MULTIPLEX 0xf010 + + +/* + ***************************************************************************** + * + * I2C Controller Interface Registers + * + ***************************************************************************** + */ + +/* FIXME: fill in */ + + +/* + ***************************************************************************** + * + * Interrupt Controller Interface Registers + * + ***************************************************************************** + */ + +#define GT64260_IC_MAIN_CAUSE_LO 0x0c18 +#define GT64260_IC_MAIN_CAUSE_HI 0x0c68 +#define GT64260_IC_CPU_INTR_MASK_LO 0x0c1c +#define GT64260_IC_CPU_INTR_MASK_HI 0x0c6c +#define GT64260_IC_CPU_SELECT_CAUSE 0x0c70 +#define GT64260_IC_PCI_0_INTR_MASK_LO 0x0c24 +#define GT64260_IC_PCI_0_INTR_MASK_HI 0x0c64 +#define GT64260_IC_PCI_0_SELECT_CAUSE 0x0c74 +#define GT64260_IC_PCI_1_INTR_MASK_LO 0x0ca4 +#define GT64260_IC_PCI_1_INTR_MASK_HI 0x0ce4 +#define GT64260_IC_PCI_1_SELECT_CAUSE 0x0cf4 +#define GT64260_IC_CPU_INT_0_MASK 0x0e60 +#define GT64260_IC_CPU_INT_1_MASK 0x0e64 +#define GT64260_IC_CPU_INT_2_MASK 0x0e68 +#define GT64260_IC_CPU_INT_3_MASK 0x0e6c + + +#endif /* __ASMPPC_GT64260_DEFS_H */ diff --git a/include/asm-ppc/hardirq.h b/include/asm-ppc/hardirq.h index 29522d2e0561..dcedb5213cd6 100644 --- a/include/asm-ppc/hardirq.h +++ b/include/asm-ppc/hardirq.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.hardirq.h 1.12 07/10/01 11:26:58 trini + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef __ASM_HARDIRQ_H @@ -44,6 +44,7 @@ typedef struct { #define hardirq_exit(cpu) (local_irq_count(cpu)--) #define synchronize_irq() do { } while (0) +#define release_irqlock(cpu) do { } while (0) #else /* CONFIG_SMP */ @@ -51,7 +52,16 @@ typedef struct { extern unsigned char global_irq_holder; extern unsigned volatile long global_irq_lock; -extern atomic_t global_irq_count; + +static inline int irqs_running (void) +{ + int i; + + for (i = 0; i < smp_num_cpus; i++) + if (local_irq_count(i)) + return 1; + return 0; +} static inline void release_irqlock(int cpu) { @@ -67,7 +77,6 @@ static inline void hardirq_enter(int cpu) unsigned int loops = 10000000; ++local_irq_count(cpu); - atomic_inc(&global_irq_count); while (test_bit(0,&global_irq_lock)) { if (cpu == global_irq_holder) { printk("uh oh, interrupt while we hold global irq lock! (CPU %d)\n", cpu); @@ -87,13 +96,12 @@ static inline void hardirq_enter(int cpu) static inline void hardirq_exit(int cpu) { - atomic_dec(&global_irq_count); --local_irq_count(cpu); } static inline int hardirq_trylock(int cpu) { - return !atomic_read(&global_irq_count) && !test_bit(0,&global_irq_lock); + return !test_bit(0,&global_irq_lock); } #define hardirq_endlock(cpu) do { } while (0) diff --git a/include/asm-ppc/harrier.h b/include/asm-ppc/harrier.h new file mode 100644 index 000000000000..ec0f19901ff7 --- /dev/null +++ b/include/asm-ppc/harrier.h @@ -0,0 +1,102 @@ +/* + * arch/ppc/kernel/harrier.h + * + * Definitions for Motorola MCG Harrier North Bridge & Memory controller + * + * Author: Dale Farnsworth + * dale.farnsworth@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASMPPC_HARRIER_H +#define __ASMPPC_HARRIER_H + +#include <asm/pci-bridge.h> + +#define HARRIER_VEND_DEV_ID 0x480b1057 + +/* + * Define outbound register offsets. + */ +#define HARRIER_OTAD0_OFF 0x220 +#define HARRIER_OTOF0_OFF 0x224 +#define HARRIER_OTAD1_OFF 0x228 +#define HARRIER_OTOF1_OFF 0x22c +#define HARRIER_OTAD2_OFF 0x230 +#define HARRIER_OTOF2_OFF 0x234 +#define HARRIER_OTAD3_OFF 0x238 +#define HARRIER_OTOF3_OFF 0x23c + +/* + * Define inbound register offsets. + */ +#define HARRIER_ITSZ0_OFF 0x348 +#define HARRIER_ITSZ1_OFF 0x350 +#define HARRIER_ITSZ2_OFF 0x358 +#define HARRIER_ITSZ3_OFF 0x360 + +/* + * Define the Memory Controller register offsets. + */ +#define HARRIER_SDBA_OFF 0x110 +#define HARRIER_SDBB_OFF 0x114 +#define HARRIER_SDBC_OFF 0x118 +#define HARRIER_SDBD_OFF 0x11c +#define HARRIER_SDBE_OFF 0x120 +#define HARRIER_SDBF_OFF 0x124 +#define HARRIER_SDBG_OFF 0x128 +#define HARRIER_SDBH_OFF 0x12c + +#define HARRIER_SDB_ENABLE 0x00000100 +#define HARRIER_SDB_SIZE_MASK 0xf +#define HARRIER_SDB_SIZE_SHIFT 16 +#define HARRIER_SDB_BASE_MASK 0xff +#define HARRIER_SDB_BASE_SHIFT 24 + +#define HARRIER_SERIAL_0_OFF 0xc0 + +#define HARRIER_REVI_OFF 0x05 +#define HARRIER_UCTL_OFF 0xd0 +#define HARRIER_XTAL64_MASK 0x02 + +#define HARRIER_MISC_CSR_OFF 0x1c +#define HARRIER_RSTOUT_MASK 0x01 + +#define HARRIER_MBAR_OFF 0xe0 +#define HARRIER_MPIC_CSR_OFF 0xe4 +#define HARRIER_MPIC_OPI_ENABLE 0x40 +#define HARRIER_MPIC_IFEVP_OFF 0x10200 +#define HARRIER_MPIC_IFEDE_OFF 0x10210 +#define HARRIER_FEEN_OFF 0x40 +#define HARRIER_FEST_OFF 0x44 +#define HARRIER_FEMA_OFF 0x48 + +#define HARRIER_FE_DMA 0x80 +#define HARRIER_FE_MIDB 0x40 +#define HARRIER_FE_MIM0 0x20 +#define HARRIER_FE_MIM1 0x10 +#define HARRIER_FE_MIP 0x08 +#define HARRIER_FE_UA0 0x04 +#define HARRIER_FE_UA1 0x02 +#define HARRIER_FE_ABT 0x01 + + +int harrier_init(struct pci_controller *hose, + uint ppc_reg_base, + ulong processor_pci_mem_start, + ulong processor_pci_mem_end, + ulong processor_pci_io_start, + ulong processor_pci_io_end, + ulong processor_mpic_base); + +unsigned long harrier_get_mem_size(uint smc_base); + +int harrier_mpic_init(unsigned int pci_mem_offset); + +#endif /* __ASMPPC_HARRIER_H */ diff --git a/include/asm-ppc/heathrow.h b/include/asm-ppc/heathrow.h index ba9fbbfbd114..9b202255e51f 100644 --- a/include/asm-ppc/heathrow.h +++ b/include/asm-ppc/heathrow.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.heathrow.h 1.7 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * heathrow.h: definitions for using the "Heathrow" I/O controller chip. @@ -17,7 +17,9 @@ #define HEATHROW_CONTRAST_CNTL 0x33 /* offset from ohare base for feature control register */ -#define HEATHROW_FEATURE_REG 0x38 +#define HEATHROW_MBCR 0x34 /* Media bay control */ +#define HEATHROW_FCR 0x38 /* Feature control */ +#define HEATHROW_AUX_CNTL_REG 0x3c /* Aux control */ /* * Bits in feature control register. @@ -30,6 +32,7 @@ #define HRW_BAY_FLOPPY_ENABLE 0x00000010 #define HRW_IDE0_ENABLE 0x00000020 #define HRW_IDE0_RESET_N 0x00000040 +#define HRW_BAY_DEV_MASK 0x0000001c #define HRW_BAY_RESET_N 0x00000080 #define HRW_IOBUS_ENABLE 0x00000100 /* Internal IDE ? */ #define HRW_SCC_ENABLE 0x00000200 @@ -45,7 +48,7 @@ #define HRW_SWIM_CLONE_FLOPPY 0x00080000 /* ??? (0) */ #define HRW_AUD_RUN22 0x00100000 /* ??? (1) */ #define HRW_SCSI_LINK_MODE 0x00200000 /* Read ??? (1) */ -#define HRW_ARB_BYPASS 0x00400000 /* ??? (0 on main, 1 on gatwick) */ +#define HRW_ARB_BYPASS 0x00400000 /* Disable internal PCI arbitrer */ #define HRW_IDE1_RESET_N 0x00800000 /* Media bay */ #define HRW_SLOW_SCC_PCLK 0x01000000 /* ??? (0) */ #define HRW_MODEM_POWER_N 0x02000000 /* Used by internal modem on wallstreet */ @@ -60,3 +63,7 @@ /* Those seem to be different on paddington */ #define PADD_MODEM_POWER_N 0x00000001 /* modem power on paddington */ #define PADD_RESET_SCC 0x02000000 /* check this please */ + +/* Looks like Heathrow has some sort of GPIOs as well... */ +#define HRW_GPIO_MODEM_RESET 0x6d + diff --git a/include/asm-ppc/highmem.h b/include/asm-ppc/highmem.h index c7d11722aa20..1e6efd66e4f7 100644 --- a/include/asm-ppc/highmem.h +++ b/include/asm-ppc/highmem.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.highmem.h 1.10 06/28/01 15:50:17 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * highmem.h: virtual kernel memory mappings for high memory @@ -44,13 +44,17 @@ extern void kmap_init(void) __init; * easily, subsequent pte tables have to be allocated in one physical * chunk of RAM. */ +#ifdef CONFIG_HIGHMEM_START_BOOL +#define PKMAP_BASE CONFIG_HIGHMEM_START +#else #define PKMAP_BASE (0xfe000000UL) +#endif /* CONFIG_HIGHMEM_START_BOOL */ #define LAST_PKMAP 1024 #define LAST_PKMAP_MASK (LAST_PKMAP-1) #define PKMAP_NR(virt) ((virt-PKMAP_BASE) >> PAGE_SHIFT) #define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT)) -#define KMAP_FIX_BEGIN (0xfe400000UL) +#define KMAP_FIX_BEGIN (PKMAP_BASE + 0x00400000UL) extern void *kmap_high(struct page *page); extern void kunmap_high(struct page *page); diff --git a/include/asm-ppc/hw_irq.h b/include/asm-ppc/hw_irq.h index 7c9f14b63414..71112a54a79b 100644 --- a/include/asm-ppc/hw_irq.h +++ b/include/asm-ppc/hw_irq.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.hw_irq.h 1.10 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> @@ -10,7 +10,48 @@ extern unsigned long timer_interrupt_intercept; extern unsigned long do_IRQ_intercept; -int timer_interrupt(struct pt_regs *); +extern int timer_interrupt(struct pt_regs *); +extern void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq); + +#define INLINE_IRQS + +#ifdef INLINE_IRQS + +#define mfmsr() ({unsigned int rval; \ + asm volatile("mfmsr %0" : "=r" (rval)); rval;}) +#define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) + +#define __save_flags(flags) ((flags) = mfmsr()) +#define __restore_flags(flags) mtmsr(flags) + +static inline void __cli(void) +{ + unsigned long msr; + msr = mfmsr(); + mtmsr(msr & ~MSR_EE); + __asm__ __volatile__("": : :"memory"); +} + +static inline void __sti(void) +{ + unsigned long msr; + __asm__ __volatile__("": : :"memory"); + msr = mfmsr(); + mtmsr(msr | MSR_EE); +} + +static inline void __do_save_and_cli(unsigned long *flags) +{ + unsigned long msr; + msr = mfmsr(); + *flags = msr; + mtmsr(msr & ~MSR_EE); + __asm__ __volatile__("": : :"memory"); +} + +#define __save_and_cli(flags) __do_save_and_cli(&flags) + +#else extern void __sti(void); extern void __cli(void); @@ -21,6 +62,8 @@ extern unsigned long __sti_end, __cli_end, __restore_flags_end, __save_flags_ptr #define __save_flags(flags) __save_flags_ptr((unsigned long *)&flags) #define __save_and_cli(flags) ({__save_flags(flags);__cli();}) +#endif + extern void do_lost_interrupts(unsigned long); #define mask_irq(irq) ({if (irq_desc[irq].handler && irq_desc[irq].handler->disable) irq_desc[irq].handler->disable(irq);}) diff --git a/include/asm-ppc/i8259.h b/include/asm-ppc/i8259.h new file mode 100644 index 000000000000..77214fdfe1e3 --- /dev/null +++ b/include/asm-ppc/i8259.h @@ -0,0 +1,16 @@ +/* + * BK Id: %F% %I% %G% %U% %#% + */ + +#ifndef _PPC_KERNEL_i8259_H +#define _PPC_KERNEL_i8259_H + +#include <linux/irq.h> + +extern struct hw_interrupt_type i8259_pic; + +void i8259_init(long); +int i8259_irq(void); +int i8259_poll(void); + +#endif /* _PPC_KERNEL_i8259_H */ diff --git a/include/asm-ppc/iSeries/HvCall.h b/include/asm-ppc/iSeries/HvCall.h new file mode 100644 index 000000000000..591c5bb8136a --- /dev/null +++ b/include/asm-ppc/iSeries/HvCall.h @@ -0,0 +1,209 @@ +/* + * HvCall.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//=========================================================================== +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from the OS. +// +//=========================================================================== + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include "HvCallSc.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +#include <asm/iSeries/Paca.h> + +//------------------------------------------------------------------- +// Constants +//------------------------------------------------------------------- +#ifndef _HVCALL_H +#define _HVCALL_H +/* +enum HvCall_ReturnCode +{ + HvCall_Good = 0, + HvCall_Partial = 1, + HvCall_NotOwned = 2, + HvCall_NotFreed = 3, + HvCall_UnspecifiedError = 4 +}; + +enum HvCall_TypeOfSIT +{ + HvCall_ReduceOnly = 0, + HvCall_Unconditional = 1 +}; + +enum HvCall_TypeOfYield +{ + HvCall_YieldTimed = 0, // Yield until specified time + HvCall_YieldToActive = 1, // Yield until all active procs have run + HvCall_YieldToProc = 2 // Yield until the specified processor has run +}; + +enum HvCall_InterruptMasks +{ + HvCall_MaskIPI = 0x00000001, + HvCall_MaskLpEvent = 0x00000002, + HvCall_MaskLpProd = 0x00000004, + HvCall_MaskTimeout = 0x00000008 +}; + +enum HvCall_VaryOffChunkRc +{ + HvCall_VaryOffSucceeded = 0, + HvCall_VaryOffWithdrawn = 1, + HvCall_ChunkInLoadArea = 2, + HvCall_ChunkInHPT = 3, + HvCall_ChunkNotAccessible = 4, + HvCall_ChunkInUse = 5 +}; +*/ + +/* Type of yield for HvCallBaseYieldProcessor */ +#define HvCall_YieldTimed 0 // Yield until specified time (tb) +#define HvCall_YieldToActive 1 // Yield until all active procs have run +#define HvCall_YieldToProc 2 // Yield until the specified processor has run + +/* interrupt masks for setEnabledInterrupts */ +#define HvCall_MaskIPI 0x00000001 +#define HvCall_MaskLpEvent 0x00000002 +#define HvCall_MaskLpProd 0x00000004 +#define HvCall_MaskTimeout 0x00000008 + +/* Log buffer formats */ +#define HvCall_LogBuffer_ASCII 0 +#define HvCall_LogBuffer_EBCDIC 1 + +#define HvCallBaseAckDeferredInts HvCallBase + 0 +#define HvCallBaseCpmPowerOff HvCallBase + 1 +#define HvCallBaseGetHwPatch HvCallBase + 2 +#define HvCallBaseReIplSpAttn HvCallBase + 3 +#define HvCallBaseSetASR HvCallBase + 4 +#define HvCallBaseSetASRAndRfi HvCallBase + 5 +#define HvCallBaseSetIMR HvCallBase + 6 +#define HvCallBaseSendIPI HvCallBase + 7 +#define HvCallBaseTerminateMachine HvCallBase + 8 +#define HvCallBaseTerminateMachineSrc HvCallBase + 9 +#define HvCallBaseProcessPlicInterrupts HvCallBase + 10 +#define HvCallBaseIsPrimaryCpmOrMsdIpl HvCallBase + 11 +#define HvCallBaseSetVirtualSIT HvCallBase + 12 +#define HvCallBaseVaryOffThisProcessor HvCallBase + 13 +#define HvCallBaseVaryOffMemoryChunk HvCallBase + 14 +#define HvCallBaseVaryOffInteractivePercentage HvCallBase + 15 +#define HvCallBaseSendLpProd HvCallBase + 16 +#define HvCallBaseSetEnabledInterrupts HvCallBase + 17 +#define HvCallBaseYieldProcessor HvCallBase + 18 +#define HvCallBaseVaryOffSharedProcUnits HvCallBase + 19 +#define HvCallBaseSetVirtualDecr HvCallBase + 20 +#define HvCallBaseClearLogBuffer HvCallBase + 21 +#define HvCallBaseGetLogBufferCodePage HvCallBase + 22 +#define HvCallBaseGetLogBufferFormat HvCallBase + 23 +#define HvCallBaseGetLogBufferLength HvCallBase + 24 +#define HvCallBaseReadLogBuffer HvCallBase + 25 +#define HvCallBaseSetLogBufferFormatAndCodePage HvCallBase + 26 +#define HvCallBaseWriteLogBuffer HvCallBase + 27 +#define HvCallBaseRouter28 HvCallBase + 28 +#define HvCallBaseRouter29 HvCallBase + 29 +#define HvCallBaseRouter30 HvCallBase + 30 +//===================================================================================== +static inline void HvCall_setVirtualDecr(void) +{ + // Ignore any error return codes - most likely means that the target value for the + // LP has been increased and this vary off would bring us below the new target. + HvCall0(HvCallBaseSetVirtualDecr); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//===================================================================== +static inline void HvCall_yieldProcessor(unsigned typeOfYield, u64 yieldParm) +{ + HvCall2( HvCallBaseYieldProcessor, typeOfYield, yieldParm ); +} +//===================================================================== +static inline void HvCall_setEnabledInterrupts(u64 enabledInterrupts) +{ + HvCall1(HvCallBaseSetEnabledInterrupts,enabledInterrupts); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} + +//===================================================================== +static inline void HvCall_clearLogBuffer(HvLpIndex lpindex) +{ + HvCall1(HvCallBaseClearLogBuffer,lpindex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} + +//===================================================================== +static inline u32 HvCall_getLogBufferCodePage(HvLpIndex lpindex) +{ + u32 retVal = HvCall1(HvCallBaseGetLogBufferCodePage,lpindex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} + +//===================================================================== +static inline int HvCall_getLogBufferFormat(HvLpIndex lpindex) +{ + int retVal = HvCall1(HvCallBaseGetLogBufferFormat,lpindex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} + +//===================================================================== +static inline u32 HvCall_getLogBufferLength(HvLpIndex lpindex) +{ + u32 retVal = HvCall1(HvCallBaseGetLogBufferLength,lpindex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} + +//===================================================================== +static inline void HvCall_setLogBufferFormatAndCodepage(int format, u32 codePage) +{ + HvCall2(HvCallBaseSetLogBufferFormatAndCodePage,format, codePage); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} + +//===================================================================== +int HvCall_readLogBuffer(HvLpIndex lpindex, void *buffer, u64 bufLen); +void HvCall_writeLogBuffer(const void *buffer, u64 bufLen); + +//===================================================================== +static inline void HvCall_sendIPI(struct Paca * targetPaca) +{ + HvCall1( HvCallBaseSendIPI, targetPaca->xPacaIndex ); +} + +//===================================================================== +static inline void HvCall_terminateMachineSrc(void) +{ + HvCall0( HvCallBaseTerminateMachineSrc ); +} + + +#endif // _HVCALL_H + diff --git a/include/asm-ppc/iSeries/HvCallCfg.h b/include/asm-ppc/iSeries/HvCallCfg.h new file mode 100644 index 000000000000..45e047f1c19a --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallCfg.h @@ -0,0 +1,219 @@ +/* + * HvCallCfg.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//===================================================================================== +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from the OS. +// +//===================================================================================== + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include "HvCallSc.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +//------------------------------------------------------------------------------------- +// Constants +//------------------------------------------------------------------------------------- +#ifndef _HVCALLCFG_H +#define _HVCALLCFG_H + +enum HvCallCfg_ReqQual +{ + HvCallCfg_Cur = 0, + HvCallCfg_Init = 1, + HvCallCfg_Max = 2, + HvCallCfg_Min = 3 +}; + +#define HvCallCfgGetLps HvCallCfg + 0 +#define HvCallCfgGetActiveLpMap HvCallCfg + 1 +#define HvCallCfgGetLpVrmIndex HvCallCfg + 2 +#define HvCallCfgGetLpMinSupportedPlicVrmIndex HvCallCfg + 3 +#define HvCallCfgGetLpMinCompatablePlicVrmIndex HvCallCfg + 4 +#define HvCallCfgGetLpVrmName HvCallCfg + 5 +#define HvCallCfgGetSystemPhysicalProcessors HvCallCfg + 6 +#define HvCallCfgGetPhysicalProcessors HvCallCfg + 7 +#define HvCallCfgGetSystemMsChunks HvCallCfg + 8 +#define HvCallCfgGetMsChunks HvCallCfg + 9 +#define HvCallCfgGetInteractivePercentage HvCallCfg + 10 +#define HvCallCfgIsBusDedicated HvCallCfg + 11 +#define HvCallCfgGetBusOwner HvCallCfg + 12 +#define HvCallCfgGetBusAllocation HvCallCfg + 13 +#define HvCallCfgGetBusUnitOwner HvCallCfg + 14 +#define HvCallCfgGetBusUnitAllocation HvCallCfg + 15 +#define HvCallCfgGetVirtualBusPool HvCallCfg + 16 +#define HvCallCfgGetBusUnitInterruptProc HvCallCfg + 17 +#define HvCallCfgGetConfiguredBusUnitsForIntProc HvCallCfg + 18 +#define HvCallCfgGetRioSanBusPool HvCallCfg + 19 +#define HvCallCfgGetSharedPoolIndex HvCallCfg + 20 +#define HvCallCfgGetSharedProcUnits HvCallCfg + 21 +#define HvCallCfgGetNumProcsInSharedPool HvCallCfg + 22 +#define HvCallCfgRouter23 HvCallCfg + 23 +#define HvCallCfgRouter24 HvCallCfg + 24 +#define HvCallCfgRouter25 HvCallCfg + 25 +#define HvCallCfgRouter26 HvCallCfg + 26 +#define HvCallCfgRouter27 HvCallCfg + 27 +#define HvCallCfgGetMinRuntimeMsChunks HvCallCfg + 28 +#define HvCallCfgSetMinRuntimeMsChunks HvCallCfg + 29 +#define HvCallCfgGetVirtualLanIndexMap HvCallCfg + 30 +#define HvCallCfgGetLpExecutionMode HvCallCfg + 31 +#define HvCallCfgGetHostingLpIndex HvCallCfg + 32 + +//==================================================================== +static inline HvLpIndex HvCallCfg_getLps(void) +{ + HvLpIndex retVal = HvCall0(HvCallCfgGetLps); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline int HvCallCfg_isBusDedicated(u64 busIndex) +{ + int retVal = HvCall1(HvCallCfgIsBusDedicated,busIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline HvLpIndex HvCallCfg_getBusOwner(u64 busIndex) +{ + HvLpIndex retVal = HvCall1(HvCallCfgGetBusOwner,busIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline HvLpIndexMap HvCallCfg_getBusAllocation(u64 busIndex) +{ + HvLpIndexMap retVal = HvCall1(HvCallCfgGetBusAllocation,busIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline HvLpIndexMap HvCallCfg_getActiveLpMap(void) +{ + HvLpIndexMap retVal = HvCall0(HvCallCfgGetActiveLpMap); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline HvLpVirtualLanIndexMap HvCallCfg_getVirtualLanIndexMap(HvLpIndex lp) +{ + // This is a new function in V5R1 so calls to this on older + // hypervisors will return -1 + u64 retVal = HvCall1(HvCallCfgGetVirtualLanIndexMap, lp); + if(retVal == -1) + retVal = 0; + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_getSystemMsChunks(void) +{ + u64 retVal = HvCall0(HvCallCfgGetSystemMsChunks); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_getMsChunks(HvLpIndex lp,enum HvCallCfg_ReqQual qual) +{ + u64 retVal = HvCall2(HvCallCfgGetMsChunks,lp,qual); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_getMinRuntimeMsChunks(HvLpIndex lp) +{ + // NOTE: This function was added in v5r1 so older hypervisors will return a -1 value + u64 retVal = HvCall1(HvCallCfgGetMinRuntimeMsChunks,lp); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_setMinRuntimeMsChunks(u64 chunks) +{ + u64 retVal = HvCall1(HvCallCfgSetMinRuntimeMsChunks,chunks); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_getSystemPhysicalProcessors(void) +{ + u64 retVal = HvCall0(HvCallCfgGetSystemPhysicalProcessors); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_getPhysicalProcessors(HvLpIndex lp,enum HvCallCfg_ReqQual qual) +{ + u64 retVal = HvCall2(HvCallCfgGetPhysicalProcessors,lp,qual); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline u64 HvCallCfg_getConfiguredBusUnitsForInterruptProc(HvLpIndex lp, + u16 hvLogicalProcIndex) +{ + u64 retVal = HvCall2(HvCallCfgGetConfiguredBusUnitsForIntProc,lp,hvLogicalProcIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; + +} +//================================================================== +static inline HvLpSharedPoolIndex HvCallCfg_getSharedPoolIndex(HvLpIndex lp) +{ + HvLpSharedPoolIndex retVal = + HvCall1(HvCallCfgGetSharedPoolIndex,lp); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; + +} +//================================================================== +static inline u64 HvCallCfg_getSharedProcUnits(HvLpIndex lp,enum HvCallCfg_ReqQual qual) +{ + u64 retVal = HvCall2(HvCallCfgGetSharedProcUnits,lp,qual); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; + +} +//================================================================== +static inline u64 HvCallCfg_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI) +{ + u16 retVal = HvCall1(HvCallCfgGetNumProcsInSharedPool,sPI); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; + +} +//================================================================== +static inline HvLpIndex HvCallCfg_getHostingLpIndex(HvLpIndex lp) +{ + u64 retVal = HvCall1(HvCallCfgGetHostingLpIndex,lp); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; + +} + +#endif // _HVCALLCFG_H + diff --git a/include/asm-ppc/iSeries/HvCallEvent.h b/include/asm-ppc/iSeries/HvCallEvent.h new file mode 100644 index 000000000000..8efce370fea3 --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallEvent.h @@ -0,0 +1,328 @@ +/* + * HvCallEvent.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//================================================================== +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from the OS. +// +//================================================================== + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include <asm/iSeries/HvCallSc.h> +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +#include <asm/iSeries/LparData.h> + +//------------------------------------------------------------------- +// Constants +//------------------------------------------------------------------- +#ifndef _HVCALLEVENT_H +#define _HVCALLEVENT_H + +struct HvLpEvent; + +typedef u8 HvLpEvent_Type; +typedef u8 HvLpEvent_AckInd; +typedef u8 HvLpEvent_AckType; + +struct HvCallEvent_PackedParms +{ + u8 xAckType:1; + u8 xAckInd:1; + u8 xRsvd:1; + u8 xTargetLp:5; + u8 xType; + u16 xSubtype; + HvLpInstanceId xSourceInstId; + HvLpInstanceId xTargetInstId; +}; + +typedef u8 HvLpDma_Direction; +typedef u8 HvLpDma_AddressType; + +struct HvCallEvent_PackedDmaParms +{ + u8 xDirection:1; + u8 xLocalAddrType:1; + u8 xRemoteAddrType:1; + u8 xRsvd1:5; + HvLpIndex xRemoteLp; + u8 xType; + u8 xRsvd2; + HvLpInstanceId xLocalInstId; + HvLpInstanceId xRemoteInstId; +}; + +typedef u64 HvLpEvent_Rc; +typedef u64 HvLpDma_Rc; + +#define HvCallEventAckLpEvent HvCallEvent + 0 +#define HvCallEventCancelLpEvent HvCallEvent + 1 +#define HvCallEventCloseLpEventPath HvCallEvent + 2 +#define HvCallEventDmaBufList HvCallEvent + 3 +#define HvCallEventDmaSingle HvCallEvent + 4 +#define HvCallEventDmaToSp HvCallEvent + 5 +#define HvCallEventGetOverflowLpEvents HvCallEvent + 6 +#define HvCallEventGetSourceLpInstanceId HvCallEvent + 7 +#define HvCallEventGetTargetLpInstanceId HvCallEvent + 8 +#define HvCallEventOpenLpEventPath HvCallEvent + 9 +#define HvCallEventSetLpEventStack HvCallEvent + 10 +#define HvCallEventSignalLpEvent HvCallEvent + 11 +#define HvCallEventSignalLpEventParms HvCallEvent + 12 +#define HvCallEventSetInterLpQueueIndex HvCallEvent + 13 +#define HvCallEventSetLpEventQueueInterruptProc HvCallEvent + 14 +#define HvCallEventRouter15 HvCallEvent + 15 + +//====================================================================== +static inline void HvCallEvent_getOverflowLpEvents(u8 queueIndex) +{ + HvCall1(HvCallEventGetOverflowLpEvents,queueIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//====================================================================== +static inline void HvCallEvent_setInterLpQueueIndex(u8 queueIndex) +{ + HvCall1(HvCallEventSetInterLpQueueIndex,queueIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//====================================================================== +static inline void HvCallEvent_setLpEventStack(u8 queueIndex, + char * eventStackAddr, + u32 eventStackSize) +{ + u64 abs_addr; + abs_addr = virt_to_absolute_outline( (unsigned long) eventStackAddr ); + + HvCall3(HvCallEventSetLpEventStack, queueIndex, abs_addr, eventStackSize); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//====================================================================== +static inline void HvCallEvent_setLpEventQueueInterruptProc(u8 queueIndex, + u16 lpLogicalProcIndex) +{ + HvCall2(HvCallEventSetLpEventQueueInterruptProc,queueIndex,lpLogicalProcIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//===================================================================== +static inline HvLpEvent_Rc HvCallEvent_signalLpEvent(struct HvLpEvent* event) +{ + u64 abs_addr; + HvLpEvent_Rc retVal; + abs_addr = virt_to_absolute_outline( (unsigned long) event ); + retVal = (HvLpEvent_Rc)HvCall1(HvCallEventSignalLpEvent, abs_addr); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//===================================================================== +static inline HvLpEvent_Rc HvCallEvent_signalLpEventFast(HvLpIndex targetLp, + HvLpEvent_Type type, + u16 subtype, + HvLpEvent_AckInd ackInd, + HvLpEvent_AckType ackType, + HvLpInstanceId sourceInstanceId, + HvLpInstanceId targetInstanceId, + u64 correlationToken, + u64 eventData1, + u64 eventData2, + u64 eventData3, + u64 eventData4, + u64 eventData5) +{ + HvLpEvent_Rc retVal; + + // Pack the misc bits into a single Dword to pass to PLIC + union + { + struct HvCallEvent_PackedParms parms; + u64 dword; + } packed; + packed.parms.xAckType = ackType; + packed.parms.xAckInd = ackInd; + packed.parms.xRsvd = 0; + packed.parms.xTargetLp = targetLp; + packed.parms.xType = type; + packed.parms.xSubtype = subtype; + packed.parms.xSourceInstId = sourceInstanceId; + packed.parms.xTargetInstId = targetInstanceId; + + retVal = (HvLpEvent_Rc)HvCall7(HvCallEventSignalLpEventParms, + packed.dword, + correlationToken, + eventData1,eventData2, + eventData3,eventData4, + eventData5); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline HvLpEvent_Rc HvCallEvent_ackLpEvent(struct HvLpEvent* event) +{ + u64 abs_addr; + HvLpEvent_Rc retVal; + abs_addr = virt_to_absolute_outline( (unsigned long) event ); + + retVal = (HvLpEvent_Rc)HvCall1(HvCallEventAckLpEvent, abs_addr); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//==================================================================== +static inline HvLpEvent_Rc HvCallEvent_cancelLpEvent(struct HvLpEvent* event) +{ + u64 abs_addr; + HvLpEvent_Rc retVal; + abs_addr = virt_to_absolute_outline( (unsigned long) event ); + + retVal = (HvLpEvent_Rc)HvCall1(HvCallEventCancelLpEvent, abs_addr); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline HvLpInstanceId HvCallEvent_getSourceLpInstanceId(HvLpIndex targetLp, HvLpEvent_Type type) +{ + HvLpInstanceId retVal; + retVal = HvCall2(HvCallEventGetSourceLpInstanceId,targetLp,type); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline HvLpInstanceId HvCallEvent_getTargetLpInstanceId(HvLpIndex targetLp, HvLpEvent_Type type) +{ + HvLpInstanceId retVal; + retVal = HvCall2(HvCallEventGetTargetLpInstanceId,targetLp,type); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//=================================================================== +static inline void HvCallEvent_openLpEventPath(HvLpIndex targetLp, + HvLpEvent_Type type) +{ + HvCall2(HvCallEventOpenLpEventPath,targetLp,type); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//=================================================================== +static inline void HvCallEvent_closeLpEventPath(HvLpIndex targetLp, + HvLpEvent_Type type) +{ + HvCall2(HvCallEventCloseLpEventPath,targetLp,type); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//=================================================================== +static inline HvLpDma_Rc HvCallEvent_dmaBufList(HvLpEvent_Type type, + HvLpIndex remoteLp, + HvLpDma_Direction direction, + HvLpInstanceId localInstanceId, + HvLpInstanceId remoteInstanceId, + HvLpDma_AddressType localAddressType, + HvLpDma_AddressType remoteAddressType, + // Do these need to be converted to + // absolute addresses? + u64 localBufList, + u64 remoteBufList, + + u32 transferLength) +{ + HvLpDma_Rc retVal; + // Pack the misc bits into a single Dword to pass to PLIC + union + { + struct HvCallEvent_PackedDmaParms parms; + u64 dword; + } packed; + packed.parms.xDirection = direction; + packed.parms.xLocalAddrType = localAddressType; + packed.parms.xRemoteAddrType = remoteAddressType; + packed.parms.xRsvd1 = 0; + packed.parms.xRemoteLp = remoteLp; + packed.parms.xType = type; + packed.parms.xRsvd2 = 0; + packed.parms.xLocalInstId = localInstanceId; + packed.parms.xRemoteInstId = remoteInstanceId; + + retVal = (HvLpDma_Rc)HvCall4(HvCallEventDmaBufList, + packed.dword, + localBufList, + remoteBufList, + transferLength); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//================================================================= +static inline HvLpDma_Rc HvCallEvent_dmaSingle(HvLpEvent_Type type, + HvLpIndex remoteLp, + HvLpDma_Direction direction, + HvLpInstanceId localInstanceId, + HvLpInstanceId remoteInstanceId, + HvLpDma_AddressType localAddressType, + HvLpDma_AddressType remoteAddressType, + u64 localAddrOrTce, + u64 remoteAddrOrTce, + u32 transferLength) +{ + HvLpDma_Rc retVal; + // Pack the misc bits into a single Dword to pass to PLIC + union + { + struct HvCallEvent_PackedDmaParms parms; + u64 dword; + } packed; + packed.parms.xDirection = direction; + packed.parms.xLocalAddrType = localAddressType; + packed.parms.xRemoteAddrType = remoteAddressType; + packed.parms.xRsvd1 = 0; + packed.parms.xRemoteLp = remoteLp; + packed.parms.xType = type; + packed.parms.xRsvd2 = 0; + packed.parms.xLocalInstId = localInstanceId; + packed.parms.xRemoteInstId = remoteInstanceId; + + retVal = (HvLpDma_Rc)HvCall4(HvCallEventDmaSingle, + packed.dword, + localAddrOrTce, + remoteAddrOrTce, + transferLength); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//================================================================= +static inline HvLpDma_Rc HvCallEvent_dmaToSp(void* local, u32 remote, u32 length, HvLpDma_Direction dir) +{ + u64 abs_addr; + HvLpDma_Rc retVal; + abs_addr = virt_to_absolute_outline( (unsigned long) local ); + + retVal = (HvLpDma_Rc)HvCall4(HvCallEventDmaToSp, + abs_addr, + remote, + length, + dir); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//================================================================ + +#endif // _HVCALLEVENT_H + diff --git a/include/asm-ppc/iSeries/HvCallHpt.h b/include/asm-ppc/iSeries/HvCallHpt.h new file mode 100644 index 000000000000..29757bf6fe1f --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallHpt.h @@ -0,0 +1,137 @@ +/* + * HvCallHpt.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================ +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from the OS. +// +//============================================================================ + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include "HvCallSc.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +//------------------------------------------------------------------- +// Other Includes +//------------------------------------------------------------------- + +#ifndef _PPC_MMU_H +#include <asm/mmu.h> +#endif + +//----------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------- +#ifndef _HVCALLHPT_H +#define _HVCALLHPT_H + +#define HvCallHptGetHptAddress HvCallHpt + 0 +#define HvCallHptGetHptPages HvCallHpt + 1 +#define HvCallHptSetPp HvCallHpt + 5 +#define HvCallHptUpdate HvCallHpt + 7 +#define HvCallHptInvalidateNoSyncICache HvCallHpt + 8 +#define HvCallHptGet HvCallHpt + 11 +#define HvCallHptFindNextValid HvCallHpt + 12 +#define HvCallHptFindValid HvCallHpt + 13 +#define HvCallHptAddValidate HvCallHpt + 16 +#define HvCallHptInvalidateSetSwBitsGet HvCallHpt + 18 + + + +//============================================================================ +static inline u64 HvCallHpt_getHptAddress(void) +{ + u64 retval = HvCall0(HvCallHptGetHptAddress); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retval; +} +//============================================================================ +static inline u64 HvCallHpt_getHptPages(void) +{ + u64 retval = HvCall0(HvCallHptGetHptPages); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retval; +} +//============================================================================= +static inline void HvCallHpt_setPp(u32 hpteIndex, u8 value) +{ + HvCall2( HvCallHptSetPp, hpteIndex, value ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//============================================================================= +static inline void HvCallHpt_invalidateNoSyncICache(u32 hpteIndex) + +{ + HvCall1( HvCallHptInvalidateNoSyncICache, hpteIndex ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//============================================================================= +static inline u64 HvCallHpt_invalidateSetSwBitsGet(u32 hpteIndex, u8 bitson, u8 bitsoff ) + +{ + u64 compressedStatus; + compressedStatus = HvCall4( HvCallHptInvalidateSetSwBitsGet, hpteIndex, bitson, bitsoff, 1 ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return compressedStatus; +} +//============================================================================= +static inline u64 HvCallHpt_findValid( PTE *hpte, u64 vpn ) +{ + u64 retIndex = HvCall1Ret16( HvCallHptFindValid, hpte, vpn ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retIndex; +} +//============================================================================= +static inline u64 HvCallHpt_findNextValid( PTE *hpte, u32 hpteIndex, u8 bitson, u8 bitsoff ) +{ + u64 retIndex = HvCall3Ret16( HvCallHptFindNextValid, hpte, hpteIndex, bitson, bitsoff ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retIndex; +} +//============================================================================= +static inline void HvCallHpt_get( PTE *hpte, u32 hpteIndex ) +{ + HvCall2Ret16( HvCallHptFindValid, hpte, hpteIndex, 0 ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} + +//============================================================================ +static inline void HvCallHpt_addValidate( u32 hpteIndex, + u32 hBit, + PTE *hpte ) + +{ + HvCall4( HvCallHptAddValidate, hpteIndex, + hBit, (*((u64 *)hpte)), (*(((u64 *)hpte)+1)) ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} + + +//============================================================================= + +#endif // _HVCALLHPT_H + diff --git a/include/asm-ppc/iSeries/HvCallPci.h b/include/asm-ppc/iSeries/HvCallPci.h new file mode 100644 index 000000000000..0569bf09fb5f --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallPci.h @@ -0,0 +1,689 @@ +/************************************************************************/ +/* Provides the Hypervisor PCI calls for iSeries Linux Parition. */ +/* Copyright (C) 20yy <Wayne G Holm> <IBM Corporation> */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the: */ +/* Free Software Foundation, Inc., */ +/* 59 Temple Place, Suite 330, */ +/* Boston, MA 02111-1307 USA */ +/************************************************************************/ +/* Change Activity: */ +/* Created, Jan 9, 2001 */ +/************************************************************************/ +//============================================================================ +// Header File Id +// Name______________: HvCallPci.H +// +// Description_______: +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from SLIC. +// +//============================================================================ + +//------------------------------------------------------------------- +// Forward declarations +//------------------------------------------------------------------- + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include "HvCallSc.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/as400/HvTypes.h> +#endif + +//------------------------------------------------------------------- +// Other Includes +//------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------- +#ifndef _HVCALLPCI_H +#define _HVCALLPCI_H + +struct HvCallPci_DsaAddr { // make sure this struct size is 64-bits total + u16 busNumber; + u8 subBusNumber; + u8 deviceId; + u8 barNumber; + u8 reserved[3]; +}; + +struct HvCallPci_LoadReturn { + u64 rc; + u64 value; +}; + +enum HvCallPci_DeviceType {HvCallPci_NodeDevice = 1, + HvCallPci_SpDevice = 2, + HvCallPci_IopDevice = 3, + HvCallPci_BridgeDevice = 4, + HvCallPci_MultiFunctionDevice = 5, + HvCallPci_IoaDevice = 6 +}; + + +struct HvCallPci_DeviceInfo { + u32 deviceType; // See DeviceType enum for values +}; + +struct HvCallPci_BusUnitInfo { + u32 sizeReturned; // length of data returned + u32 deviceType; // see DeviceType enum for values +}; + +struct HvCallPci_BridgeInfo { + struct HvCallPci_BusUnitInfo busUnitInfo; // Generic bus unit info + u8 subBusNumber; // Bus number of secondary bus + u8 maxAgents; // Max idsels on secondary bus +}; + + +// Maximum BusUnitInfo buffer size. Provided for clients so they can allocate +// a buffer big enough for any type of bus unit. Increase as needed. +enum {HvCallPci_MaxBusUnitInfoSize = 128}; + +struct HvCallPci_BarParms { + u64 vaddr; + u64 raddr; + u64 size; + u64 protectStart; + u64 protectEnd; + u64 relocationOffset; + u64 pciAddress; + u64 reserved[3]; +}; + +enum HvCallPci_VpdType { + HvCallPci_BusVpd = 1, + HvCallPci_BusAdapterVpd = 2 +}; + +#define HvCallPciConfigLoad8 HvCallPci + 0 +#define HvCallPciConfigLoad16 HvCallPci + 1 +#define HvCallPciConfigLoad32 HvCallPci + 2 +#define HvCallPciConfigStore8 HvCallPci + 3 +#define HvCallPciConfigStore16 HvCallPci + 4 +#define HvCallPciConfigStore32 HvCallPci + 5 +#define HvCallPciEoi HvCallPci + 16 +#define HvCallPciGetBarParms HvCallPci + 18 +#define HvCallPciMaskFisr HvCallPci + 20 +#define HvCallPciUnmaskFisr HvCallPci + 21 +#define HvCallPciSetSlotReset HvCallPci + 25 +#define HvCallPciGetDeviceInfo HvCallPci + 27 +#define HvCallPciGetCardVpd HvCallPci + 28 +#define HvCallPciBarLoad8 HvCallPci + 40 +#define HvCallPciBarLoad16 HvCallPci + 41 +#define HvCallPciBarLoad32 HvCallPci + 42 +#define HvCallPciBarLoad64 HvCallPci + 43 +#define HvCallPciBarStore8 HvCallPci + 44 +#define HvCallPciBarStore16 HvCallPci + 45 +#define HvCallPciBarStore32 HvCallPci + 46 +#define HvCallPciBarStore64 HvCallPci + 47 +#define HvCallPciMaskInterrupts HvCallPci + 48 +#define HvCallPciUnmaskInterrupts HvCallPci + 49 +#define HvCallPciGetBusUnitInfo HvCallPci + 50 + +//============================================================================ +static inline u64 HvCallPci_configLoad8(u16 busNumber, u8 subBusNumber, + u8 deviceId, u32 offset, + u8 *value) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumber; + dsa.subBusNumber = subBusNumber; + dsa.deviceId = deviceId; + + HvCall3Ret16(HvCallPciConfigLoad8, &retVal, *(u64 *)&dsa, offset, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *value = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_configLoad16(u16 busNumber, u8 subBusNumber, + u8 deviceId, u32 offset, + u16 *value) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumber; + dsa.subBusNumber = subBusNumber; + dsa.deviceId = deviceId; + + HvCall3Ret16(HvCallPciConfigLoad16, &retVal, *(u64 *)&dsa, offset, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *value = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_configLoad32(u16 busNumber, u8 subBusNumber, + u8 deviceId, u32 offset, + u32 *value) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumber; + dsa.subBusNumber = subBusNumber; + dsa.deviceId = deviceId; + + HvCall3Ret16(HvCallPciConfigLoad32, &retVal, *(u64 *)&dsa, offset, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *value = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_configStore8(u16 busNumber, u8 subBusNumber, + u8 deviceId, u32 offset, + u8 value) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumber; + dsa.subBusNumber = subBusNumber; + dsa.deviceId = deviceId; + + retVal = HvCall4(HvCallPciConfigStore8, *(u64 *)&dsa, offset, value, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_configStore16(u16 busNumber, u8 subBusNumber, + u8 deviceId, u32 offset, + u16 value) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumber; + dsa.subBusNumber = subBusNumber; + dsa.deviceId = deviceId; + + retVal = HvCall4(HvCallPciConfigStore16, *(u64 *)&dsa, offset, value, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_configStore32(u16 busNumber, u8 subBusNumber, + u8 deviceId, u32 offset, + u32 value) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumber; + dsa.subBusNumber = subBusNumber; + dsa.deviceId = deviceId; + + retVal = HvCall4(HvCallPciConfigStore32, *(u64 *)&dsa, offset, value, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_barLoad8(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u8* valueParm) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + HvCall3Ret16(HvCallPciBarLoad8, &retVal, *(u64 *)&dsa, offsetParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *valueParm = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_barLoad16(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u16* valueParm) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + HvCall3Ret16(HvCallPciBarLoad16, &retVal, *(u64 *)&dsa, offsetParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *valueParm = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_barLoad32(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u32* valueParm) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + HvCall3Ret16(HvCallPciBarLoad32, &retVal, *(u64 *)&dsa, offsetParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *valueParm = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_barLoad64(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u64* valueParm) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + HvCall3Ret16(HvCallPciBarLoad64, &retVal, *(u64 *)&dsa, offsetParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + *valueParm = retVal.value; + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_barStore8(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u8 valueParm) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + retVal = HvCall4(HvCallPciBarStore8, *(u64 *)&dsa, offsetParm, valueParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_barStore16(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u16 valueParm) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + retVal = HvCall4(HvCallPciBarStore16, *(u64 *)&dsa, offsetParm, valueParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_barStore32(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u32 valueParm) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + retVal = HvCall4(HvCallPciBarStore32, *(u64 *)&dsa, offsetParm, valueParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_barStore64(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 offsetParm, + u64 valueParm) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + retVal = HvCall4(HvCallPciBarStore64, *(u64 *)&dsa, offsetParm, valueParm, 0); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_eoi(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm) +{ + struct HvCallPci_DsaAddr dsa; + struct HvCallPci_LoadReturn retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + HvCall1Ret16(HvCallPciEoi, &retVal, *(u64*)&dsa); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal.rc; +} +//============================================================================ +static inline u64 HvCallPci_getBarParms(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u8 barNumberParm, + u64 parms, + u32 sizeofParms) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + dsa.barNumber = barNumberParm; + + retVal = HvCall3(HvCallPciGetBarParms, *(u64*)&dsa, parms, sizeofParms); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_maskFisr(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u64 fisrMask) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + retVal = HvCall2(HvCallPciMaskFisr, *(u64*)&dsa, fisrMask); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_unmaskFisr(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u64 fisrMask) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + retVal = HvCall2(HvCallPciUnmaskFisr, *(u64*)&dsa, fisrMask); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_setSlotReset(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u64 onNotOff) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + retVal = HvCall2(HvCallPciSetSlotReset, *(u64*)&dsa, onNotOff); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_getDeviceInfo(u16 busNumberParm, + u8 subBusParm, + u8 deviceNumberParm, + u64 parms, + u32 sizeofParms) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceNumberParm << 4; + + retVal = HvCall3(HvCallPciGetDeviceInfo, *(u64*)&dsa, parms, sizeofParms); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_maskInterrupts(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u64 interruptMask) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + retVal = HvCall2(HvCallPciMaskInterrupts, *(u64*)&dsa, interruptMask); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ +static inline u64 HvCallPci_unmaskInterrupts(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u64 interruptMask) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + retVal = HvCall2(HvCallPciUnmaskInterrupts, *(u64*)&dsa, interruptMask); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ + +static inline u64 HvCallPci_getBusUnitInfo(u16 busNumberParm, + u8 subBusParm, + u8 deviceIdParm, + u64 parms, + u32 sizeofParms) +{ + struct HvCallPci_DsaAddr dsa; + u64 retVal; + + *((u64*)&dsa) = 0; + + dsa.busNumber = busNumberParm; + dsa.subBusNumber = subBusParm; + dsa.deviceId = deviceIdParm; + + retVal = HvCall3(HvCallPciGetBusUnitInfo, *(u64*)&dsa, parms, sizeofParms); + + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + + return retVal; +} +//============================================================================ + +static inline int HvCallPci_getBusVpd(u16 busNumParm, u64 destParm, u16 sizeParm) { + int xRetSize; + u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm, sizeParm, HvCallPci_BusVpd); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + if (xRc == -1) + xRetSize = -1; + else + xRetSize = xRc & 0xFFFF; + return xRetSize; +} +//============================================================================ + +static inline int HvCallPci_getBusAdapterVpd(u16 busNumParm, u64 destParm, u16 sizeParm) { + int xRetSize; + u64 xRc = HvCall4(HvCallPciGetCardVpd, busNumParm, destParm, sizeParm, HvCallPci_BusAdapterVpd); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + if (xRc == -1) + xRetSize = -1; + else + xRetSize = xRc & 0xFFFF; + return xRetSize; +} +//============================================================================ +#endif // _HVCALLPCI_H diff --git a/include/asm-ppc/iSeries/HvCallSc.h b/include/asm-ppc/iSeries/HvCallSc.h new file mode 100644 index 000000000000..f51dce1d772c --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallSc.h @@ -0,0 +1,53 @@ +/* + * HvCallSc.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +#ifndef _HVCALLSC_H +#define _HVCALLSC_H + +#define HvCallBase 0x80000000 +#define HvCallCfg 0x80020000 +#define HvCallEvent 0x80030000 +#define HvCallHpt 0x80040000 +#define HvCallPci 0x80050000 +#define HvCallSm 0x80070000 +#define HvCallXm 0x80090000 + +u64 HvCall0( u32 ); +u64 HvCall1( u32, u64 ); +u64 HvCall2( u32, u64, u64 ); +u64 HvCall3( u32, u64, u64, u64 ); +u64 HvCall4( u32, u64, u64, u64, u64 ); +u64 HvCall5( u32, u64, u64, u64, u64, u64 ); +u64 HvCall6( u32, u64, u64, u64, u64, u64, u64 ); +u64 HvCall7( u32, u64, u64, u64, u64, u64, u64, u64 ); + +u64 HvCall0Ret16( u32, void * ); +u64 HvCall1Ret16( u32, void *, u64 ); +u64 HvCall2Ret16( u32, void *, u64, u64 ); +u64 HvCall3Ret16( u32, void *, u64, u64, u64 ); +u64 HvCall4Ret16( u32, void *, u64, u64, u64, u64 ); +u64 HvCall5Ret16( u32, void *, u64, u64, u64, u64, u64 ); +u64 HvCall6Ret16( u32, void *, u64, u64, u64, u64, u64, u64 ); +u64 HvCall7Ret16( u32, void *, u64, u64 ,u64 ,u64 ,u64 ,u64 ,u64 ); + +#endif /* _HVCALLSC_H */ diff --git a/include/asm-ppc/iSeries/HvCallSm.h b/include/asm-ppc/iSeries/HvCallSm.h new file mode 100644 index 000000000000..7b47ee181d3a --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallSm.h @@ -0,0 +1,58 @@ +/* + * HvCallSm.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================ +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from the OS. +// +//============================================================================ + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include "HvCallSc.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +//----------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------- +#ifndef _HVCALLSM_H +#define _HVCALLSM_H + +#define HvCallSmGet64BitsOfAccessMap HvCallSm + 11 + + +//============================================================================ +static inline u64 HvCallSm_get64BitsOfAccessMap( + HvLpIndex lpIndex, u64 indexIntoBitMap ) +{ + u64 retval = HvCall2(HvCallSmGet64BitsOfAccessMap, lpIndex, + indexIntoBitMap ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retval; +} +//============================================================================ +#endif // _HVCALLSM_H + diff --git a/include/asm-ppc/iSeries/HvCallXm.h b/include/asm-ppc/iSeries/HvCallXm.h new file mode 100644 index 000000000000..b4f55b74e240 --- /dev/null +++ b/include/asm-ppc/iSeries/HvCallXm.h @@ -0,0 +1,105 @@ +//============================================================================ +// Header File Id +// Name______________: HvCallXm.H +// +// Description_______: +// +// This file contains the "hypervisor call" interface which is used to +// drive the hypervisor from SLIC. +// +//============================================================================ + +//------------------------------------------------------------------- +// Forward declarations +//------------------------------------------------------------------- + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _HVCALLSC_H +#include "HvCallSc.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +//------------------------------------------------------------------- +// Other Includes +//------------------------------------------------------------------- + + +//----------------------------------------------------------------------------- +// Constants +//----------------------------------------------------------------------------- +#ifndef _HVCALLXM_H +#define _HVCALLXM_H + +#define HvCallXmGetTceTableParms HvCallXm + 0 +#define HvCallXmTestBus HvCallXm + 1 +#define HvCallXmConnectBusUnit HvCallXm + 2 +#define HvCallXmLoadTod HvCallXm + 8 +#define HvCallXmTestBusUnit HvCallXm + 9 +#define HvCallXmSetTce HvCallXm + 11 +#define HvCallXmSetTces HvCallXm + 13 + + + +//============================================================================ +static inline void HvCallXm_getTceTableParms(u64 cb) +{ + HvCall1(HvCallXmGetTceTableParms, cb); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); +} +//============================================================================ +static inline u64 HvCallXm_setTce(u64 tceTableToken, u64 tceOffset, u64 tce) +{ + u64 retval = HvCall3(HvCallXmSetTce, tceTableToken, tceOffset, tce ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retval; +} +//============================================================================ +static inline u64 HvCallXm_setTces(u64 tceTableToken, u64 tceOffset, u64 numTces, u64 tce1, u64 tce2, u64 tce3, u64 tce4) +{ + u64 retval = HvCall7(HvCallXmSetTces, tceTableToken, tceOffset, numTces, + tce1, tce2, tce3, tce4 ); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retval; +} +//============================================================================= +static inline u64 HvCallXm_testBus(u16 busNumber) +{ + u64 retVal = HvCall1(HvCallXmTestBus, busNumber); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//===================================================================================== +static inline u64 HvCallXm_testBusUnit(u16 busNumber, u8 subBusNumber, u8 deviceId) { + u64 busUnitNumber = (subBusNumber << 8) | deviceId; + u64 retVal = HvCall2(HvCallXmTestBusUnit, busNumber, busUnitNumber); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//===================================================================================== +static inline u64 HvCallXm_connectBusUnit(u16 busNumber, u8 subBusNumber, u8 deviceId, + u64 interruptToken) +{ + u64 busUnitNumber = (subBusNumber << 8) | deviceId; + u64 queueIndex = 0; // HvLpConfig::mapDsaToQueueIndex(HvLpDSA(busNumber, xBoard, xCard)); + + u64 retVal = HvCall5(HvCallXmConnectBusUnit, busNumber, busUnitNumber, + interruptToken, 0, queueIndex); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//===================================================================================== +static inline u64 HvCallXm_loadTod(void) +{ + u64 retVal = HvCall0(HvCallXmLoadTod); + // getPaca()->adjustHmtForNoOfSpinLocksHeld(); + return retVal; +} +//===================================================================================== + +#endif // _HVCALLXM_H + diff --git a/include/asm-ppc/iSeries/HvLpConfig.h b/include/asm-ppc/iSeries/HvLpConfig.h new file mode 100644 index 000000000000..ecf6cf92af03 --- /dev/null +++ b/include/asm-ppc/iSeries/HvLpConfig.h @@ -0,0 +1,292 @@ +/* + * HvLpConfig.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//=========================================================================== +// +// This file contains the interface to the LPAR configuration data +// to determine which resources should be allocated to each partition. +// +//=========================================================================== + +#ifndef _HVCALLCFG_H +#include "HvCallCfg.h" +#endif + +#ifndef _HVTYPES_H +#include <asm/iSeries/HvTypes.h> +#endif + +#ifndef _ITLPNACA_H +#include <asm/iSeries/ItLpNaca.h> +#endif + +#ifndef _LPARDATA_H +#include <asm/iSeries/LparData.h> +#endif + +#ifndef _HVLPCONFIG_H +#define _HVLPCONFIG_H + +//------------------------------------------------------------------- +// Constants +//------------------------------------------------------------------- + +extern HvLpIndex HvLpConfig_getLpIndex_outline(void); + +//=================================================================== +static inline HvLpIndex HvLpConfig_getLpIndex(void) +{ + return itLpNaca.xLpIndex; +} +//=================================================================== +static inline HvLpIndex HvLpConfig_getPrimaryLpIndex(void) +{ + return itLpNaca.xPrimaryLpIndex; +} +//================================================================= +static inline HvLpIndex HvLpConfig_getLps(void) +{ + return HvCallCfg_getLps(); +} +//================================================================= +static inline HvLpIndexMap HvLpConfig_getActiveLpMap(void) +{ + return HvCallCfg_getActiveLpMap(); +} +//================================================================= +static inline u64 HvLpConfig_getSystemMsMegs(void) +{ + return HvCallCfg_getSystemMsChunks() / HvChunksPerMeg; +} +//================================================================= +static inline u64 HvLpConfig_getSystemMsChunks(void) +{ + return HvCallCfg_getSystemMsChunks(); +} +//================================================================= +static inline u64 HvLpConfig_getSystemMsPages(void) +{ + return HvCallCfg_getSystemMsChunks() * HvPagesPerChunk; +} +//================================================================ +static inline u64 HvLpConfig_getMsMegs(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Cur) / HvChunksPerMeg; +} +//================================================================ +static inline u64 HvLpConfig_getMsChunks(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Cur); +} +//================================================================ +static inline u64 HvLpConfig_getMsPages(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Cur) * HvPagesPerChunk; +} +//================================================================ +static inline u64 HvLpConfig_getMinMsMegs(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Min) / HvChunksPerMeg; +} +//================================================================ +static inline u64 HvLpConfig_getMinMsChunks(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Min); +} +//================================================================ +static inline u64 HvLpConfig_getMinMsPages(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Min) * HvPagesPerChunk; +} +//================================================================ +static inline u64 HvLpConfig_getMinRuntimeMsMegs(void) +{ + return HvCallCfg_getMinRuntimeMsChunks(HvLpConfig_getLpIndex()) / HvChunksPerMeg; +} +//=============================================================== +static inline u64 HvLpConfig_getMinRuntimeMsChunks(void) +{ + return HvCallCfg_getMinRuntimeMsChunks(HvLpConfig_getLpIndex()); +} +//=============================================================== +static inline u64 HvLpConfig_getMinRuntimeMsPages(void) +{ + return HvCallCfg_getMinRuntimeMsChunks(HvLpConfig_getLpIndex()) * HvPagesPerChunk; +} +//=============================================================== +static inline u64 HvLpConfig_getMaxMsMegs(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Max) / HvChunksPerMeg; +} +//=============================================================== +static inline u64 HvLpConfig_getMaxMsChunks(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Max); +} +//=============================================================== +static inline u64 HvLpConfig_getMaxMsPages(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Max) * HvPagesPerChunk; +} +//=============================================================== +static inline u64 HvLpConfig_getInitMsMegs(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Init) / HvChunksPerMeg; +} +//=============================================================== +static inline u64 HvLpConfig_getInitMsChunks(void) +{ + return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Init); +} +//=============================================================== +static inline u64 HvLpConfig_getInitMsPages(void) +{ return HvCallCfg_getMsChunks(HvLpConfig_getLpIndex(),HvCallCfg_Init) * HvPagesPerChunk; +} +//=============================================================== +static inline u64 HvLpConfig_getSystemPhysicalProcessors(void) +{ + return HvCallCfg_getSystemPhysicalProcessors(); +} +//=============================================================== +static inline u64 HvLpConfig_getSystemLogicalProcessors(void) +{ + return HvCallCfg_getSystemPhysicalProcessors() * (/*getPaca()->getSecondaryThreadCount() +*/ 1); +} +//=============================================================== +static inline u64 HvLpConfig_getNumProcsInSharedPool(HvLpSharedPoolIndex sPI) +{ + return HvCallCfg_getNumProcsInSharedPool(sPI); +} +//=============================================================== +static inline u64 HvLpConfig_getPhysicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Cur); +} +//=============================================================== +static inline u64 HvLpConfig_getLogicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Cur) * (/*getPaca()->getSecondaryThreadCount() +*/ 1); +} +//=============================================================== +static inline HvLpSharedPoolIndex HvLpConfig_getSharedPoolIndex(void) +{ + return HvCallCfg_getSharedPoolIndex(HvLpConfig_getLpIndex()); +} +//=============================================================== +static inline u64 HvLpConfig_getSharedProcUnits(void) +{ + return HvCallCfg_getSharedProcUnits(HvLpConfig_getLpIndex(),HvCallCfg_Cur); +} +//=============================================================== +static inline u64 HvLpConfig_getMinSharedProcUnits(void) +{ + return HvCallCfg_getSharedProcUnits(HvLpConfig_getLpIndex(),HvCallCfg_Min); +} +//=============================================================== +static inline u64 HvLpConfig_getMaxSharedProcUnits(void) +{ + return HvCallCfg_getSharedProcUnits(HvLpConfig_getLpIndex(),HvCallCfg_Max); +} +//=============================================================== +static inline u64 HvLpConfig_getMinPhysicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Min); +} +//=============================================================== +static inline u64 HvLpConfig_getMinLogicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Min) * (/*getPaca()->getSecondaryThreadCount() +*/ 1); +} +//=============================================================== +static inline u64 HvLpConfig_getMaxPhysicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Max); +} +//=============================================================== +static inline u64 HvLpConfig_getMaxLogicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Max) * (/*getPaca()->getSecondaryThreadCount() +*/ 1); +} +//=============================================================== +static inline u64 HvLpConfig_getInitPhysicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Init); +} +//=============================================================== +static inline u64 HvLpConfig_getInitLogicalProcessors(void) +{ + return HvCallCfg_getPhysicalProcessors(HvLpConfig_getLpIndex(),HvCallCfg_Init) * (/*getPaca()->getSecondaryThreadCount() +*/ 1); +} +//================================================================ +static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMap(void) +{ + return HvCallCfg_getVirtualLanIndexMap(HvLpConfig_getLpIndex_outline()); +} +//=============================================================== +static inline HvLpVirtualLanIndexMap HvLpConfig_getVirtualLanIndexMapForLp(HvLpIndex lp) +{ + return HvCallCfg_getVirtualLanIndexMap(lp); +} +//================================================================ +static inline HvLpIndex HvLpConfig_getBusOwner(HvBusNumber busNumber) +{ + return HvCallCfg_getBusOwner(busNumber); +} +//=============================================================== +static inline int HvLpConfig_isBusDedicated(HvBusNumber busNumber) +{ + return HvCallCfg_isBusDedicated(busNumber); +} +//================================================================ +static inline HvLpIndexMap HvLpConfig_getBusAllocation(HvBusNumber busNumber) +{ + return HvCallCfg_getBusAllocation(busNumber); +} +//================================================================ +// returns the absolute real address of the load area +static inline u64 HvLpConfig_getLoadAddress(void) +{ + return itLpNaca.xLoadAreaAddr & 0x7fffffffffffffff; +} +//================================================================ +static inline u64 HvLpConfig_getLoadPages(void) +{ + return itLpNaca.xLoadAreaChunks * HvPagesPerChunk; +} +//================================================================ +static inline int HvLpConfig_isBusOwnedByThisLp(HvBusNumber busNumber) +{ + HvLpIndex busOwner = HvLpConfig_getBusOwner(busNumber); + return (busOwner == HvLpConfig_getLpIndex()); +} +//================================================================ +static inline int HvLpConfig_doLpsCommunicateOnVirtualLan(HvLpIndex lp1, HvLpIndex lp2) +{ + HvLpVirtualLanIndexMap virtualLanIndexMap1 = HvCallCfg_getVirtualLanIndexMap( lp1 ); + HvLpVirtualLanIndexMap virtualLanIndexMap2 = HvCallCfg_getVirtualLanIndexMap( lp2 ); + return ((virtualLanIndexMap1 & virtualLanIndexMap2) != 0); +} +//================================================================ +static inline HvLpIndex HvLpConfig_getHostingLpIndex(HvLpIndex lp) +{ + return HvCallCfg_getHostingLpIndex(lp); +} +//================================================================ + +#endif // _HVLPCONFIG_H diff --git a/include/asm-ppc/iSeries/HvLpEvent.h b/include/asm-ppc/iSeries/HvLpEvent.h new file mode 100644 index 000000000000..be2f08987efc --- /dev/null +++ b/include/asm-ppc/iSeries/HvLpEvent.h @@ -0,0 +1,144 @@ +/* + * HvLpEvent.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//====================================================================== +// +// This file contains the class for HV events in the system. +// +//===================================================================== +#ifndef _HVLPEVENT_H +#define _HVLPEVENT_H + +#include <asm/types.h> +#include <asm/ptrace.h> +#include <asm/iSeries/HvTypes.h> +#ifndef _HVCALLEVENT_H +#include <asm/iSeries/HvCallEvent.h> +#endif + + +//===================================================================== +// +// HvLpEvent is the structure for Lp Event messages passed between +// partitions through PLIC. +// +//===================================================================== + +struct HvEventFlags +{ + u8 xValid:1; // Indicates a valid request x00-x00 + u8 xRsvd1:4; // Reserved ... + u8 xAckType:1; // Immediate or deferred ... + u8 xAckInd:1; // Indicates if ACK required ... + u8 xFunction:1; // Interrupt or Acknowledge ... +}; + + +struct HvLpEvent +{ + struct HvEventFlags xFlags; // Event flags x00-x00 + u8 xType; // Type of message x01-x01 + u16 xSubtype; // Subtype for event x02-x03 + u8 xSourceLp; // Source LP x04-x04 + u8 xTargetLp; // Target LP x05-x05 + u8 xSizeMinus1; // Size of Derived class - 1 x06-x06 + u8 xRc; // RC for Ack flows x07-x07 + u16 xSourceInstanceId; // Source sides instance id x08-x09 + u16 xTargetInstanceId; // Target sides instance id x0A-x0B + union { + u32 xSubtypeData; // Data usable by the subtype x0C-x0F + u16 xSubtypeDataShort[2]; // Data as 2 shorts + u8 xSubtypeDataChar[4]; // Data as 4 chars + } x; + + u64 xCorrelationToken; // Unique value for source/type x10-x17 +}; + +// Lp Event handler function +typedef void (*LpEventHandler)(struct HvLpEvent *, struct pt_regs *); + +// Register a handler for an event type +// returns 0 on success +extern int HvLpEvent_registerHandler( HvLpEvent_Type eventType, LpEventHandler hdlr); + +// Unregister a handler for an event type +// returns 0 on success +// Unregister will fail if there are any paths open for the type +extern int HvLpEvent_unregisterHandler( HvLpEvent_Type eventType ); + +// Open an Lp Event Path for an event type +// returns 0 on success +// openPath will fail if there is no handler registered for the event type. +// The lpIndex specified is the partition index for the target partition +// (for VirtualIo, VirtualLan and SessionMgr) other types specify zero) +extern int HvLpEvent_openPath( HvLpEvent_Type eventType, HvLpIndex lpIndex ); + + +// Close an Lp Event Path for a type and partition +// returns 0 on sucess +extern int HvLpEvent_closePath( HvLpEvent_Type eventType, HvLpIndex lpIndex ); + +#define HvLpEvent_Type_Hypervisor 0 +#define HvLpEvent_Type_MachineFac 1 +#define HvLpEvent_Type_SessionMgr 2 +#define HvLpEvent_Type_SpdIo 3 +#define HvLpEvent_Type_VirtualBus 4 +#define HvLpEvent_Type_PciIo 5 +#define HvLpEvent_Type_RioIo 6 +#define HvLpEvent_Type_VirtualLan 7 +#define HvLpEvent_Type_VirtualIo 8 +#define HvLpEvent_Type_NumTypes 9 + +#define HvLpEvent_Rc_Good 0 +#define HvLpEvent_Rc_BufferNotAvailable 1 +#define HvLpEvent_Rc_Cancelled 2 +#define HvLpEvent_Rc_GenericError 3 +#define HvLpEvent_Rc_InvalidAddress 4 +#define HvLpEvent_Rc_InvalidPartition 5 +#define HvLpEvent_Rc_InvalidSize 6 +#define HvLpEvent_Rc_InvalidSubtype 7 +#define HvLpEvent_Rc_InvalidSubtypeData 8 +#define HvLpEvent_Rc_InvalidType 9 +#define HvLpEvent_Rc_PartitionDead 10 +#define HvLpEvent_Rc_PathClosed 11 +#define HvLpEvent_Rc_SubtypeError 12 + +#define HvLpEvent_Function_Ack 0 +#define HvLpEvent_Function_Int 1 + +#define HvLpEvent_AckInd_NoAck 0 +#define HvLpEvent_AckInd_DoAck 1 + +#define HvLpEvent_AckType_ImmediateAck 0 +#define HvLpEvent_AckType_DeferredAck 1 + +#define HvLpDma_Direction_LocalToRemote 0 +#define HvLpDma_Direction_RemoteToLocal 1 + +#define HvLpDma_AddressType_TceIndex 0 +#define HvLpDma_AddressType_RealAddress 1 + +#define HvLpDma_Rc_Good 0 +#define HvLpDma_Rc_Error 1 +#define HvLpDma_Rc_PartitionDead 2 +#define HvLpDma_Rc_PathClosed 3 +#define HvLpDma_Rc_InvalidAddress 4 +#define HvLpDma_Rc_InvalidLength 5 + +#endif // _HVLPEVENT_H diff --git a/include/asm-ppc/iSeries/HvReleaseData.h b/include/asm-ppc/iSeries/HvReleaseData.h new file mode 100644 index 000000000000..aa82e18f6d13 --- /dev/null +++ b/include/asm-ppc/iSeries/HvReleaseData.h @@ -0,0 +1,71 @@ +/* + * HvReleaseData.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================= +// +// This control block contains the critical information about the +// release so that it can be changed in the future (ie, the virtual +// address of the OS's NACA). +// +//----------------------------------------------------------------------------- +// Standard Includes +//----------------------------------------------------------------------------- +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +#ifndef _HVRELEASEDATA_H +#define _HVRELEASEDATA_H + +//============================================================================= +// +// When we IPL a secondary partition, we will check if if the +// secondary xMinPlicVrmIndex > the primary xVrmIndex. +// If it is then this tells PLIC that this secondary is not +// supported running on this "old" of a level of PLIC. +// +// Likewise, we will compare the primary xMinSlicVrmIndex to +// the secondary xVrmIndex. +// If the primary xMinSlicVrmDelta > secondary xVrmDelta then we +// know that this PLIC does not support running an OS "that old". +// +//============================================================================= + +struct HvReleaseData +{ + u32 xDesc; // Descriptor "HvRD" ebcdic x00-x03 + u16 xSize; // Size of this control block x04-x05 + u16 xVpdAreasPtrOffset; // Offset in NACA of ItVpdAreas x06-x07 + u32 xSlicNacaAddr64; // Virtual address of OS's NACA x08-x0F + struct Naca * xSlicNacaAddr; // Virtual address of OS's NACA x08-x0F + u32 xMsNucDataOffset; // Offset of Linux Mapping Data x10-x13 + u32 xRsvd1; // Reserved x14-x17 + u16 xTagsMode:1; // 0 == tags active, 1 == tags inactive + u16 xAddressSize:1; // 0 == 64-bit, 1 == 32-bit + u16 xNoSharedProcs:1; // 0 == shared procs, 1 == no shared + u16 xNoHMT:1; // 0 == allow HMT, 1 == no HMT + u16 xRsvd2:12; // Reserved x18-x19 + u16 xVrmIndex; // VRM Index of OS image x1A-x1B + u16 xMinSupportedPlicVrmIndex;// Min PLIC level (soft) x1C-x1D + u16 xMinCompatablePlicVrmIndex;// Min PLIC levelP (hard) x1E-x1F + char xVrmName[12]; // Displayable name x20-x2B + char xRsvd3[20]; // Reserved x2C-x3F +}; + +#endif // _HVRELEASEDATA_H diff --git a/include/asm-ppc/iSeries/HvTypes.h b/include/asm-ppc/iSeries/HvTypes.h new file mode 100644 index 000000000000..4c25828dacef --- /dev/null +++ b/include/asm-ppc/iSeries/HvTypes.h @@ -0,0 +1,161 @@ +/* + * HvTypes.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//=========================================================================== +// Header File Id +// Name______________: HvTypes.H +// +// Description_______: +// +// General typedefs for the hypervisor. +// +// Declared Class(es): +// +//=========================================================================== + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + + +#ifndef _HVTYPES_H +#define _HVTYPES_H + +//------------------------------------------------------------------- +// Typedefs +//------------------------------------------------------------------- +typedef u8 HvLpIndex; +typedef u16 HvLpInstanceId; +typedef u64 HvLpTOD; +typedef u64 HvLpSystemSerialNum; +typedef u8 HvLpDeviceSerialNum[12]; +typedef u16 HvLpSanHwSet; +typedef u16 HvLpBus; +typedef u16 HvLpBoard; +typedef u16 HvLpCard; +typedef u8 HvLpDeviceType[4]; +typedef u8 HvLpDeviceModel[3]; +typedef u64 HvIoToken; +typedef u8 HvLpName[8]; +typedef u32 HvIoId; +typedef u64 HvRealMemoryIndex; +typedef u32 HvLpIndexMap; // Must hold HvMaxArchitectedLps bits!!! +typedef u16 HvLpVrmIndex; +typedef u32 HvXmGenerationId; +typedef u8 HvLpBusPool; +typedef u8 HvLpSharedPoolIndex; +typedef u16 HvLpSharedProcUnitsX100; +typedef u8 HvLpVirtualLanIndex; +typedef u16 HvLpVirtualLanIndexMap; // Must hold HvMaxArchitectedVirtualLans bits!!! +typedef u16 HvBusNumber; // Hypervisor Bus Number +typedef u8 HvSubBusNumber; // Hypervisor SubBus Number +typedef u8 HvAgentId; // Hypervisor DevFn + + +#define HVMAXARCHITECTEDLPS 32 +#define HVCHUNKSIZE 256 * 1024 +#define HVPAGESIZE 4 * 1024 +#define HVLPMINMEGSPRIMARY 256 +#define HVLPMINMEGSSECONDARY 64 +#define HVCHUNKSPERMEG 4 +#define HVPAGESPERMEG 256 +#define HVPAGESPERCHUNK 64 + + +static const HvLpIndexMap HvLpIndexMapDefault = (1 << (sizeof(HvLpIndexMap) * 8 - 1)); +static const HvLpIndex HvHardcodedPrimaryLpIndex = 0; +static const HvLpIndex HvMaxArchitectedLps = HVMAXARCHITECTEDLPS; +static const HvLpVirtualLanIndex HvMaxArchitectedVirtualLans = 16; +static const HvLpSharedPoolIndex HvMaxArchitectedSharedPools = 16; +static const HvLpSharedPoolIndex HvMaxSupportedSharedPools = 1; +static const HvLpIndex HvMaxRuntimeLpsPreCondor = 12; +static const HvLpIndex HvMaxRuntimeLps = HVMAXARCHITECTEDLPS; +static const HvLpIndex HvLpIndexInvalid = 0xff; +static const u16 HvInvalidProcIndex = 0xffff; +static const u32 HvVirtualFlashSize = 0x200; +static const u32 HvMaxBusesPreCondor = 32; +static const u32 HvMaxBusesCondor = 256; +static const u32 HvMaxArchitectedBuses = 512; +static const HvLpBus HvCspBusNumber = 1; +static const u32 HvMaxSanHwSets = 16; +static const HvLpCard HvMaxSystemIops = 200; +static const HvLpCard HvMaxBusIops = 20; +static const u16 HvMaxUnitsPerIop = 100; +static const u64 HvPageSize = 4 * 1024; +static const u64 HvChunkSize = HVCHUNKSIZE; +static const u64 HvChunksPerMeg = HVCHUNKSPERMEG; +static const u64 HvPagesPerChunk = HVPAGESPERCHUNK; +static const u64 HvPagesPerMeg = HVPAGESPERMEG; +static const u64 HvLpMinMegsPrimary = HVLPMINMEGSPRIMARY; +static const u64 HvLpMinMegsSecondary = HVLPMINMEGSSECONDARY; +static const u64 HvLpMinChunksPrimary = HVLPMINMEGSPRIMARY * HVCHUNKSPERMEG; +static const u64 HvLpMinChunksSecondary = HVLPMINMEGSSECONDARY * HVCHUNKSPERMEG; +static const u64 HvLpMinPagesPrimary = HVLPMINMEGSPRIMARY * HVPAGESPERMEG; +static const u64 HvLpMinPagesSecondary = HVLPMINMEGSSECONDARY * HVPAGESPERMEG; +static const u8 HvLpMinProcs = 1; +static const u8 HvLpConfigMinInteract = 1; +static const u16 HvLpMinSharedProcUnitsX100 = 10; +static const u16 HvLpMaxSharedProcUnitsX100 = 100; +static const HvLpSharedPoolIndex HvLpSharedPoolIndexInvalid = 0xff; + + +//-------------------------------------------------------------------- +// Enums for the sub-components under PLIC +// Used in HvCall and HvPrimaryCall +//-------------------------------------------------------------------- +enum HvCallCompIds +{ + HvCallCompId = 0, + HvCallCpuCtlsCompId = 1, + HvCallCfgCompId = 2, + HvCallEventCompId = 3, + HvCallHptCompId = 4, + HvCallPciCompId = 5, + HvCallSlmCompId = 6, + HvCallSmCompId = 7, + HvCallSpdCompId = 8, + HvCallXmCompId = 9, + HvCallRioCompId = 10, + HvCallRsvd3CompId = 11, + HvCallRsvd2CompId = 12, + HvCallRsvd1CompId = 13, + HvCallMaxCompId = 14, + HvPrimaryCallCompId = 0, + HvPrimaryCallCfgCompId = 1, + HvPrimaryCallPciCompId = 2, + HvPrimaryCallSmCompId = 3, + HvPrimaryCallSpdCompId = 4, + HvPrimaryCallXmCompId = 5, + HvPrimaryCallRioCompId = 6, + HvPrimaryCallRsvd7CompId = 7, + HvPrimaryCallRsvd6CompId = 8, + HvPrimaryCallRsvd5CompId = 9, + HvPrimaryCallRsvd4CompId = 10, + HvPrimaryCallRsvd3CompId = 11, + HvPrimaryCallRsvd2CompId = 12, + HvPrimaryCallRsvd1CompId = 13, + HvPrimaryCallMaxCompId = HvCallMaxCompId +}; + +struct HvLpBufferList { + u64 addr; + u64 len; +}; + +#endif // _HVTYPES_H diff --git a/include/asm-ppc/iSeries/IoHriMainStore.h b/include/asm-ppc/iSeries/IoHriMainStore.h new file mode 100644 index 000000000000..76626e8af971 --- /dev/null +++ b/include/asm-ppc/iSeries/IoHriMainStore.h @@ -0,0 +1,65 @@ +/* + * IoHriMainStore.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _IOHRIMAINSTORE_H +#define _IOHRIMAINSTORE_H + +struct IoHriMainStoreSegment4 { + u8 msArea0Exists:1; + u8 msArea1Exists:1; + u8 msArea2Exists:1; + u8 msArea3Exists:1; + u8 reserved1:4; + u8 reserved2; + + u8 msArea0Functional:1; + u8 msArea1Functional:1; + u8 msArea2Functional:1; + u8 msArea3Functional:1; + u8 reserved3:4; + u8 reserved4; + + u32 totalMainStore; + + u64 msArea0Ptr; + u64 msArea1Ptr; + u64 msArea2Ptr; + u64 msArea3Ptr; + + u32 cardProductionLevel; + + u32 msAdrHole; + + u8 msArea0HasRiserVpd:1; + u8 msArea1HasRiserVpd:1; + u8 msArea2HasRiserVpd:1; + u8 msArea3HasRiserVpd:1; + u8 reserved5:4; + u8 reserved6; + u16 reserved7; + + u8 reserved8[28]; + + u64 nonInterleavedBlocksStartAdr; + u64 nonInterleavedBlocksEndAdr; +}; + + +#endif // _IOHRIMAINSTORE_H + diff --git a/include/asm-ppc/iSeries/IoHriProcessorVpd.h b/include/asm-ppc/iSeries/IoHriProcessorVpd.h new file mode 100644 index 000000000000..150d21204252 --- /dev/null +++ b/include/asm-ppc/iSeries/IoHriProcessorVpd.h @@ -0,0 +1,90 @@ +/* + * IoHriProcessorVpd.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//=================================================================== +// +// This struct maps Processor Vpd that is DMAd to SLIC by CSP +// + +#ifndef _TYPES_H +#include <asm/types.h> +#endif + +#ifndef _IOHRIPROCESSORVPD_H +#define _IOHRIPROCESSORVPD_H + +struct IoHriProcessorVpd +{ + + u8 xFormat; // VPD format indicator x00-x00 + u8 xProcStatus:8; // Processor State x01-x01 + u8 xSecondaryThreadCount; // Secondary thread cnt x02-x02 + u8 xSrcType:1; // Src Type x03-x03 + u8 xSrcSoft:1; // Src stay soft ... + u8 xSrcParable:1; // Src parable ... + u8 xRsvd1:5; // Reserved ... + u16 xHvPhysicalProcIndex; // Hypervisor physical proc index04-x05 + u16 xRsvd2; // Reserved x06-x07 + u32 xHwNodeId; // Hardware node id x08-x0B + u32 xHwProcId; // Hardware processor id x0C-x0F + + u32 xTypeNum; // Card Type/CCIN number x10-x13 + u32 xModelNum; // Model/Feature number x14-x17 + u64 xSerialNum; // Serial number x18-x1F + char xPartNum[12]; // Book Part or FPU number x20-x2B + char xMfgID[4]; // Manufacturing ID x2C-x2F + + u32 xProcFreq; // Processor Frequency x30-x33 + u32 xTimeBaseFreq; // Time Base Frequency x34-x37 + + u32 xChipEcLevel; // Chip EC Levels x38-x3B + u32 xProcIdReg; // PIR SPR value x3C-x3F + u32 xPVR; // PVR value x40-x43 + u8 xRsvd3[12]; // Reserved x44-x4F + + u32 xInstCacheSize; // Instruction cache size in KB x50-x53 + u32 xInstBlockSize; // Instruction cache block size x54-x57 + u32 xDataCacheOperandSize; // Data cache operand size x58-x5B + u32 xInstCacheOperandSize; // Inst cache operand size x5C-x5F + + u32 xDataL1CacheSizeKB; // L1 data cache size in KB x60-x63 + u32 xDataL1CacheLineSize; // L1 data cache block size x64-x67 + u64 xRsvd4; // Reserved x68-x6F + + u32 xDataL2CacheSizeKB; // L2 data cache size in KB x70-x73 + u32 xDataL2CacheLineSize; // L2 data cache block size x74-x77 + u64 xRsvd5; // Reserved x78-x7F + + u32 xDataL3CacheSizeKB; // L3 data cache size in KB x80-x83 + u32 xDataL3CacheLineSize; // L3 data cache block size x84-x87 + u64 xRsvd6; // Reserved x88-x8F + + u64 xFruLabel; // Card Location Label x90-x97 + u8 xSlotsOnCard; // Slots on card (0=no slots) x98-x98 + u8 xPartLocFlag; // Location flag (0-pluggable 1-imbedded) x99-x99 + u16 xSlotMapIndex; // Index in slot map table x9A-x9B + u8 xSmartCardPortNo; // Smart card port number x9C-x9C + u8 xRsvd7; // Reserved x9D-x9D + u16 xFrameIdAndRackUnit; // Frame ID and rack unit adr x9E-x9F + + u8 xRsvd8[24]; // Reserved xA0-xB7 + + char xProcSrc[72]; // CSP format SRC xB8-xFF +}; +#endif // _IOHRIPROCESSORVPD_H diff --git a/include/asm-ppc/iSeries/ItIplParmsReal.h b/include/asm-ppc/iSeries/ItIplParmsReal.h new file mode 100644 index 000000000000..dd7c772c5004 --- /dev/null +++ b/include/asm-ppc/iSeries/ItIplParmsReal.h @@ -0,0 +1,78 @@ +/* + * ItIplParmsReal.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================== +// +// This struct maps the IPL Parameters DMA'd from the SP. +// +// Warning: +// This data must map in exactly 64 bytes and match the architecture for +// the IPL parms +// +//============================================================================= + + +//------------------------------------------------------------------- +// Standard Includes +//------------------------------------------------------------------- +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +#ifndef _ITIPLPARMSREAL_H +#define _ITIPLPARMSREAL_H + +struct ItIplParmsReal +{ + u8 xFormat; // Defines format of IplParms x00-x00 + u8 xRsvd01:6; // Reserved x01-x01 + u8 xAlternateSearch:1; // Alternate search indicator ... + u8 xUaSupplied:1; // UA Supplied on programmed IPL ... + u8 xLsUaFormat; // Format byte for UA x02-x02 + u8 xRsvd02; // Reserved x03-x03 + u32 xLsUa; // LS UA x04-x07 + u32 xUnusedLsLid; // First OS LID to load x08-x0B + u16 xLsBusNumber; // LS Bus Number x0C-x0D + u8 xLsCardAdr; // LS Card Address x0E-x0E + u8 xLsBoardAdr; // LS Board Address x0F-x0F + u32 xRsvd03; // Reserved x10-x13 + u8 xSpcnPresent:1; // SPCN present x14-x14 + u8 xCpmPresent:1; // CPM present ... + u8 xRsvd04:6; // Reserved ... + u8 xRsvd05:4; // Reserved x15-x15 + u8 xKeyLock:4; // Keylock setting ... + u8 xRsvd06:6; // Reserved x16-x16 + u8 xIplMode:2; // Ipl mode (A|B|C|D) ... + u8 xHwIplType; // Fast v slow v slow EC HW IPL x17-x17 + u16 xCpmEnabledIpl:1; // CPM in effect when IPL initiated x18-x19 + u16 xPowerOnResetIpl:1; // Indicate POR condition ... + u16 xMainStorePreserved:1; // Main Storage is preserved ... + u16 xRsvd07:13; // Reserved ... + u16 xIplSource:16; // Ipl source x1A-x1B + u8 xIplReason:8; // Reason for this IPL x1C-x1C + u8 xRsvd08; // Reserved x1D-x1D + u16 xRsvd09; // Reserved x1E-x1F + u16 xSysBoxType; // System Box Type x20-x21 + u16 xSysProcType; // System Processor Type x22-x23 + u32 xRsvd10; // Reserved x24-x27 + u64 xRsvd11; // Reserved x28-x2F + u64 xRsvd12; // Reserved x30-x37 + u64 xRsvd13; // Reserved x38-x3F +}; +#endif // _ITIPLPARMSREAL_H diff --git a/include/asm-ppc/iSeries/ItLpNaca.h b/include/asm-ppc/iSeries/ItLpNaca.h new file mode 100644 index 000000000000..ebaa08fb7482 --- /dev/null +++ b/include/asm-ppc/iSeries/ItLpNaca.h @@ -0,0 +1,87 @@ +/* + * ItLpNaca.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================= +// +// This control block contains the data that is shared between the +// hypervisor (PLIC) and the OS. +// +//============================================================================= + + +#ifndef _ITLPNACA_H +#define _ITLPNACA_H + +struct ItLpNaca +{ +//============================================================================= +// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data +//============================================================================= + u32 xDesc; // Eye catcher x00-x03 + u16 xSize; // Size of this class x04-x05 + u16 xIntHdlrOffset; // Offset to IntHdlr array x06-x07 + u8 xMaxIntHdlrEntries; // Number of entries in array x08-x08 + u8 xPrimaryLpIndex; // LP Index of Primary x09-x09 + u8 xServiceLpIndex; // LP Ind of Service Focal Pointx0A-x0A + u8 xLpIndex; // LP Index x0B-x0B + u16 xMaxLpQueues; // Number of allocated queues x0C-x0D + u16 xLpQueueOffset; // Offset to start of LP queues x0E-x0F + u8 xPirEnvironMode:8; // Piranha or hardware x10-x10 + u8 xPirConsoleMode:8; // Piranha console indicator x11-x11 + u8 xPirDasdMode:8; // Piranha dasd indicator x12-x12 + u8 xRsvd1_0[5]; // Reserved for Piranha related x13-x17 + u8 xLparInstalled:1; // Is LPAR installed on system x18-x1F + u8 xSysPartitioned:1; // Is the system partitioned ... + u8 xHwSyncedTBs:1; // Hardware synced TBs ... + u8 xIntProcUtilHmt:1; // Utilize HMT for interrupts ... + u8 xRsvd1_1:4; // Reserved ... + u8 xSpVpdFormat:8; // VPD areas are in CSP format ... + u8 xIntProcRatio:8; // Ratio of int procs to procs ... + u8 xRsvd1_2[5]; // Reserved ... + u16 xRsvd1_3; // Reserved x20-x21 + u16 xPlicVrmIndex; // VRM index of PLIC x22-x23 + u16 xMinSupportedSlicVrmInd;// Min supported OS VRM index x24-x25 + u16 xMinCompatableSlicVrmInd;// Min compatable OS VRM index x26-x27 + u64 xLoadAreaAddr; // ER address of load area x28-x2F + u32 xLoadAreaChunks; // Chunks for the load area x30-x33 + u32 xRsvd1_4; // x34-x37 + u8 xRsvd1_5[72]; // x38-x7F + +//============================================================================= +// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data +//============================================================================= + u8 xRsvd2_0[128]; // Reserved x00-x7F + +//============================================================================= +// CACHE_LINE_3-6 0x0100 - 0x02FF Contains LP Queue indicators +// NB: Padding required to keep xInterrruptHdlr at x300 which is required +// for v4r4 PLIC. +//============================================================================= + u8 xOldLpQueue[128]; // LP Queue needed for v4r4 100-17F + u8 xRsvd3_0[384]; // Reserved 180-2FF +//============================================================================= +// CACHE_LINE_7-8 0x0300 - 0x03FF Contains the address of the OS interrupt +// handlers +//============================================================================= + u64 xInterruptHdlr[32]; // Interrupt handlers 300-x3FF +}; + +//============================================================================= + +#endif // _ITLPNACA_H diff --git a/include/asm-ppc/iSeries/ItLpPaca.h b/include/asm-ppc/iSeries/ItLpPaca.h new file mode 100644 index 000000000000..e5556b2f3070 --- /dev/null +++ b/include/asm-ppc/iSeries/ItLpPaca.h @@ -0,0 +1,122 @@ +/* + * ItLpPaca.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================= +// +// This control block contains the data that is shared between the +// hypervisor (PLIC) and the OS. +// +// +//---------------------------------------------------------------------------- +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +#ifndef _ITLPPACA_H +#define _ITLPPACA_H + + +struct ItLpPaca +{ +//============================================================================= +// CACHE_LINE_1 0x0000 - 0x007F Contains read-only data +// NOTE: The xDynXyz fields are fields that will be dynamically changed by +// PLIC when preparing to bring a processor online or when dispatching a +// virtual processor! +//============================================================================= + u32 xDesc; // Eye catcher 0xD397D781 x00-x03 + u16 xSize; // Size of this struct x04-x05 + u16 xRsvd1_0; // Reserved x06-x07 + u16 xRsvd1_1:14; // Reserved x08-x09 + u8 xSharedProc:1; // Shared processor indicator ... + u8 xSecondaryThread:1; // Secondary thread indicator ... + volatile u8 xDynProcStatus:8; // Dynamic Status of this proc x0A-x0A + u8 xSecondaryThreadCnt; // Secondary thread count x0B-x0B + volatile u16 xDynHvPhysicalProcIndex;// Dynamic HV Physical Proc Index0C-x0D + volatile u16 xDynHvLogicalProcIndex;// Dynamic HV Logical Proc Indexx0E-x0F + u32 xDecrVal; // Value for Decr programming x10-x13 + u32 xPMCVal; // Value for PMC regs x14-x17 + volatile u32 xDynHwNodeId; // Dynamic Hardware Node id x18-x1B + volatile u32 xDynHwProcId; // Dynamic Hardware Proc Id x1C-x1F + volatile u32 xDynPIR; // Dynamic ProcIdReg value x20-x23 + u32 xDseiData; // DSEI data x24-x27 + u64 xSPRG3; // SPRG3 value x28-x2F + u8 xRsvd1_3[80]; // Reserved x30-x7F + +//============================================================================= +// CACHE_LINE_2 0x0080 - 0x00FF Contains local read-write data +//============================================================================= + // This Dword contains a byte for each type of interrupt that can occur. + // The IPI is a count while the others are just a binary 1 or 0. + + u16 xRsvd; // Reserved - cleared by #mpasmbl + u8 xXirrInt; // Indicates xXirrValue is valid or Immed IO + u8 xIpiCnt; // IPI Count + u8 xDecrInt; // DECR interrupt occurred + u8 xPdcInt; // PDC interrupt occurred + u8 xQuantumInt; // Interrupt quantum reached + u8 xOldPlicDeferredExtInt; // Old PLIC has deferred XIRR pending + + u64 xPlicDeferIntsArea; + + // Used to pass the real SRR0/1 from PLIC to the OS as well as to + // pass the target SRR0/1 from the OS to PLIC on a SetAsrAndRfid. + u64 xSavedSrr0; // Saved SRR0 x10-x17 + u64 xSavedSrr1; // Saved SRR1 x18-x1F + + // Used to pass parms from the OS to PLIC for SetAsrAndRfid + u64 xSavedGpr3; // Saved GPR3 x20-x27 + u64 xSavedGpr4; // Saved GPR4 x28-x2F + u64 xSavedGpr5; // Saved GPR5 x30-x37 + + u8 xRsvd2_1; // Reserved x38-x38 + u8 xCpuCtlsTaskAttributes; // Task attributes for cpuctls x39-x39 + u8 xFPRegsInUse; // FP regs in use x3A-x3A + u8 xPMCRegsInUse; // PMC regs in use x3B-x3B + volatile u32 xSavedDecr; // Saved Decr Value x3C-x3F + volatile u64 xEmulatedTimeBase; // Emulated TB for this thread x40-x47 + volatile u64 xCurPLICLatency; // Unaccounted PLIC latency x48-x4F + u64 xTotPLICLatency; // Accumulated PLIC latency x50-x57 + u64 xWaitStateCycles; // Wait cycles for this proc x58-x5F + u64 xEndOfQuantum; // TB at end of quantum x60-x67 + u64 xPDCSavedSPRG1; // Saved SPRG1 for PMC int x68-x6F + u64 xPDCSavedSRR0; // Saved SRR0 for PMC int x70-x77 + volatile u32 xVirtualDecr; // Virtual DECR for shared procsx78-x7B + u32 xRsvd2_2; // Reserved x7C-x7F + +//============================================================================= +// CACHE_LINE_3 0x0100 - 0x007F: This line is shared with other processors +//============================================================================= + // This is the xYieldCount. An "odd" value (low bit on) means that + // the processor is yielded (either because of an OS yield or a PLIC + // preempt). An even value implies that the processor is currently + // executing. + // NOTE: This value will ALWAYS be zero for dedicated processors and + // will NEVER be zero for shared processors (ie, initialized to a 1). + volatile u32 xYieldCount; // PLIC increments each dispatchx00-x03 + u8 xRsvd3_0[124]; // Reserved x04-x7F + +//============================================================================= +// CACHE_LINE_4-5 0x0100 - 0x01FF Contains PMC interrupt data +//============================================================================= + u8 xPmcSaveArea[256]; // PMC interrupt Area x00-xFF + + +}; +#endif // _ITLPPACA_H diff --git a/include/asm-ppc/iSeries/ItLpQueue.h b/include/asm-ppc/iSeries/ItLpQueue.h new file mode 100644 index 000000000000..a9af28b6fe52 --- /dev/null +++ b/include/asm-ppc/iSeries/ItLpQueue.h @@ -0,0 +1,94 @@ +/* + * ItLpQueue.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//============================================================================= +// +// This control block defines the simple LP queue structure that is +// shared between the hypervisor (PLIC) and the OS in order to send +// events to an LP. +// + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif +#include <asm/ptrace.h> + + +struct HvLpEvent; + + +#ifndef _ITLPQUEUE_H +#define _ITLPQUEUE_H + +#define ITMaxLpQueues 8 + +#define NotUsed 0 // Queue will not be used by PLIC +#define DedicatedIo 1 // Queue dedicated to IO processor specified +#define DedicatedLp 2 // Queue dedicated to LP specified +#define Shared 3 // Queue shared for both IO and LP + +#define LpEventStackSize 4096 +#define LpEventMaxSize 256 +#define LpEventAlign 64 + +struct ItLpQueue +{ +// +// The xSlicCurEventPtr is the pointer to the next event stack entry that will +// become valid. The OS must peek at this entry to determine if it is valid. +// PLIC will set the valid indicator as the very last store into that entry. +// +// When the OS has completed processing of the event then it will mark the event +// as invalid so that PLIC knows it can store into that event location again. +// +// If the event stack fills and there are overflow events, then PLIC will set +// the xPlicOverflowIntPending flag in which case the OS will have to fetch the +// additional LP events once they have drained the event stack. +// +// The first 16-bytes are known by both the OS and PLIC. The remainder of the +// cache line is for use by the OS. +// +//============================================================================= + u8 xPlicOverflowIntPending; // 0x00 Overflow events are pending + u8 xPlicStatus; // 0x01 DedicatedIo or DedicatedLp or NotUsed + u16 xSlicLogicalProcIndex; // 0x02 Logical Proc Index for correlation + u8 xPlicRsvd[12]; // 0x04 + u32 xHSlicCurEventPtr; // 0x10 High 32 bits of ptr + char* xSlicCurEventPtr; // 0x14 Low 32 bits of ptr + u32 xHSlicLastValidEventPtr; // 0x18 High 32 bits of ptr + char* xSlicLastValidEventPtr; // 0x1C Low 32 bits of ptr + u32 xHSlicEventStackPtr; // 0x20 High 32 bits of ptr + char* xSlicEventStackPtr; // 0x24 Low 32 bits of ptr + u8 xIndex; // 0x28 unique sequential index. + u8 xSlicRsvd[3]; // 0x29-2B + u32 xInUseWord; // 0x2C + u64 xLpIntCount; // 0x30 Total Lp Int msgs processed + u64 xLpIntCountByType[9]; // 0x38-0x7F Event counts by type +}; + +extern struct ItLpQueue xItLpQueue; + +extern struct HvLpEvent * ItLpQueue_getNextLpEvent( struct ItLpQueue * ); +extern int ItLpQueue_isLpIntPending( struct ItLpQueue * ); +extern unsigned ItLpQueue_process( struct ItLpQueue *, struct pt_regs * ); +extern void ItLpQueue_clearValid( struct HvLpEvent * ); + + +//============================================================================= +#endif // _ITLPQUEUE_H diff --git a/include/asm-ppc/iSeries/ItLpRegSave.h b/include/asm-ppc/iSeries/ItLpRegSave.h new file mode 100644 index 000000000000..e836f65ab7e9 --- /dev/null +++ b/include/asm-ppc/iSeries/ItLpRegSave.h @@ -0,0 +1,87 @@ +/* + * ItLpRegSave.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//===================================================================================== +// +// This control block contains the data that is shared between PLIC +// and the OS +// +// + +#ifndef _ITLPREGSAVE_H +#define _ITLPREGSAVE_H + +struct ItLpRegSave +{ + u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003 + u16 xSize; // Size of this class 004-005 + u8 xInUse; // Area is live 006-007 + u8 xRsvd1[9]; // Reserved 007-00F + + u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F + u32 xCTRL; // Control Register 170-173 + u32 xDEC; // Decrementer 174-177 + u32 xFPSCR; // FP Status and Control Reg 178-17B + u32 xPVR; // Processor Version Number 17C-17F + + u64 xMMCR0; // Monitor Mode Control Reg 0 180-187 + u32 xPMC1; // Perf Monitor Counter 1 188-18B + u32 xPMC2; // Perf Monitor Counter 2 18C-18F + u32 xPMC3; // Perf Monitor Counter 3 190-193 + u32 xPMC4; // Perf Monitor Counter 4 194-197 + u32 xPIR; // Processor ID Reg 198-19B + + u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F + u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3 + u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7 + u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB + u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF + u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3 + u32 xTSC; // Thread Switch Control 1B4-1B7 + u32 xTST; // Thread Switch Timeout 1B8-1BB + u32 xRsvd; // Reserved 1BC-1BF + + u64 xACCR; // Address Compare Control Reg 1C0-1C7 + u64 xIMR; // Instruction Match Register 1C8-1CF + u64 xSDR1; // Storage Description Reg 1 1D0-1D7 + u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF + u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7 + u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF + u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7 + u64 xTB; // Time Base Register 1F8-1FF + + u64 xFPR[32]; // Floating Point Registers 200-2FF + + u64 xMSR; // Machine State Register 300-307 + u64 xNIA; // Next Instruction Address 308-30F + + u64 xDABR; // Data Address Breakpoint Reg 310-317 + u64 xIABR; // Inst Address Breakpoint Reg 318-31F + + u64 xHID0; // HW Implementation Dependent0 320-327 + + u64 xHID4; // HW Implementation Dependent4 328-32F + u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337 + u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F + u64 xSDAR; // Sample Data Address Register 340-347 + u64 xSIAR; // Sample Inst Address Register 348-34F + + u8 xRsvd3[176]; // Reserved 350-3FF +}; +#endif // _ITLPREGSAVE_H diff --git a/include/asm-ppc/iSeries/ItSpCommArea.h b/include/asm-ppc/iSeries/ItSpCommArea.h new file mode 100644 index 000000000000..475d3ecb309e --- /dev/null +++ b/include/asm-ppc/iSeries/ItSpCommArea.h @@ -0,0 +1,39 @@ +/* + * ItSpCommArea.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +#ifndef _ITSPCOMMAREA_H +#define _ITSPCOMMAREA_H + + +struct SpCommArea +{ + u32 xDesc; // Descriptor (only in new formats) 000-003 + u8 xFormat; // Format (only in new formats) 004-004 + u8 xRsvd1[11]; // Reserved 005-00F + u64 xRawTbAtIplStart; // Raw HW TB value when IPL is started 010-017 + u64 xRawTodAtIplStart; // Raw HW TOD value when IPL is started 018-01F + u64 xBcdTimeAtIplStart; // BCD time when IPL is started 020-027 + u64 xBcdTimeAtOsStart; // BCD time when OS passed control 028-02F + u8 xRsvd2[80]; // Reserved 030-07F +}; + +extern struct SpCommArea xSpCommArea; + +#endif /* _ITSPCOMMAREA_H */ diff --git a/include/asm-ppc/iSeries/ItVpdAreas.h b/include/asm-ppc/iSeries/ItVpdAreas.h new file mode 100644 index 000000000000..8958a0ca8ff6 --- /dev/null +++ b/include/asm-ppc/iSeries/ItVpdAreas.h @@ -0,0 +1,100 @@ +/* + * ItVpdAreas.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +//===================================================================================== +// +// This file defines the address and length of all of the VPD area passed to +// the OS from PLIC (most of which start from the SP). +// + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + + +#ifndef _ITVPDAREAS_H +#define _ITVPDAREAS_H + +// VPD Entry index is carved in stone - cannot be changed (easily). +#define ItVpdCecVpd 0 +#define ItVpdDynamicSpace 1 +#define ItVpdExtVpd 2 +#define ItVpdExtVpdOnPanel 3 +#define ItVpdFirstPaca 4 +#define ItVpdIoVpd 5 +#define ItVpdIplParms 6 +#define ItVpdMsVpd 7 +#define ItVpdPanelVpd 8 +#define ItVpdLpNaca 9 +#define ItVpdBackplaneAndMaybeClockCardVpd 10 +#define ItVpdRecoveryLogBuffer 11 +#define ItVpdSpCommArea 12 +#define ItVpdSpLogBuffer 13 +#define ItVpdSpLogBufferSave 14 +#define ItVpdSpCardVpd 15 +#define ItVpdFirstProcVpd 16 +#define ItVpdApModelVpd 17 +#define ItVpdClockCardVpd 18 +#define ItVpdBusExtCardVpd 19 +#define ItVpdProcCapacityVpd 20 +#define ItVpdInteractiveCapacityVpd 21 +#define ItVpdFirstSlotLabel 22 +#define ItVpdFirstLpQueue 23 +#define ItVpdFirstL3CacheVpd 24 +#define ItVpdFirstProcFruVpd 25 + +#define ItVpdMaxEntries 26 + + +#define ItDmaMaxEntries 10 + +#define ItVpdAreasMaxSlotLabels 192 + + +struct SlicVpdAdrs { + u32 pad1; + void * vpdAddr; +}; + + +struct ItVpdAreas +{ + u32 xSlicDesc; // Descriptor 000-003 + u16 xSlicSize; // Size of this control block 004-005 + u16 xPlicAdjustVpdLens:1; // Flag to indicate new interface 006-007 + u16 xRsvd1:15; // Reserved bits ... + u16 xSlicVpdEntries; // Number of VPD entries 008-009 + u16 xSlicDmaEntries; // Number of DMA entries 00A-00B + u16 xSlicMaxLogicalProcs; // Maximum logical processors 00C-00D + u16 xSlicMaxPhysicalProcs; // Maximum physical processors 00E-00F + u16 xSlicDmaToksOffset; // Offset into this of array 010-011 + u16 xSlicVpdAdrsOffset; // Offset into this of array 012-013 + u16 xSlicDmaLensOffset; // Offset into this of array 014-015 + u16 xSlicVpdLensOffset; // Offset into this of array 016-017 + u16 xSlicMaxSlotLabels; // Maximum number of slot labels 018-019 + u16 xSlicMaxLpQueues; // Maximum number of LP Queues 01A-01B + u8 xRsvd2[4]; // Reserved 01C-01F + u64 xRsvd3[12]; // Reserved 020-07F + u32 xPlicDmaLens[ItDmaMaxEntries];// Array of DMA lengths 080-0A7 + u32 xPlicDmaToks[ItDmaMaxEntries];// Array of DMA tokens 0A8-0CF + u32 xSlicVpdLens[ItVpdMaxEntries];// Array of VPD lengths 0D0-12F + struct SlicVpdAdrs xSlicVpdAdrs[ItVpdMaxEntries];// Array of VPD buffers 130-1EF +}; + +#endif // _ITVPDAREAS_H diff --git a/include/asm-ppc/iSeries/LparData.h b/include/asm-ppc/iSeries/LparData.h new file mode 100644 index 000000000000..63ed9a84955b --- /dev/null +++ b/include/asm-ppc/iSeries/LparData.h @@ -0,0 +1,75 @@ +/* + * LparData.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +#ifndef _LPARDATA_H +#define _LPARDATA_H + +#include <asm/page.h> + +extern u32 msChunks[]; + +#define phys_to_absolute( x ) (((u64)msChunks[((x)>>18)])<<18)+((u64)((x)&0x3ffff)) + +#define physRpn_to_absRpn( x ) (((u64)msChunks[((x)>>6)])<<6)+((u64)((x)&0x3f)) + +#define virt_to_absolute( x ) (((u64)msChunks[(((x)-KERNELBASE)>>18)])<<18)+((u64)((x)&0x3ffff)) + +extern u64 virt_to_absolute_outline(u32 address); + + +#include <asm/iSeries/Naca.h> +#include <asm/iSeries/ItLpNaca.h> +#include <asm/iSeries/ItLpPaca.h> +#include <asm/iSeries/ItLpRegSave.h> +#include <asm/iSeries/Paca.h> +#include <asm/iSeries/HvReleaseData.h> +#include <asm/iSeries/LparMap.h> +#include <asm/iSeries/ItVpdAreas.h> +#include <asm/iSeries/ItIplParmsReal.h> +#include <asm/iSeries/ItLpQueue.h> +#include <asm/iSeries/IoHriProcessorVpd.h> +#include <asm/page.h> + +extern struct LparMap xLparMap; +extern struct Naca xNaca; +extern struct Paca xPaca[]; +extern struct HvReleaseData hvReleaseData; +extern struct ItLpNaca itLpNaca; +extern struct ItIplParmsReal xItIplParmsReal; +extern struct IoHriProcessorVpd xIoHriProcessorVpd[]; +extern struct ItLpQueue xItLpQueue; +extern struct ItVpdAreas itVpdAreas; +extern u64 xMsVpd[]; +extern u32 msChunks[]; +extern u32 totalLpChunks; +extern unsigned maxPacas; + +/* +#define phys_to_absolute( x ) (((u64)msChunks[((x)>>18)])<<18)+((u64)((x)&0x3ffff)) + +#define physRpn_to_absRpn( x ) (((u64)msChunks[((x)>>6)])<<6)+((u64)((x)&0x3f)) + +#define virt_to_absolute( x ) (((u64)msChunks[(((x)-KERNELBASE)>>18)])<<18)+((u64)((x)&0x3ffff)) +*/ + +#endif /* _LPAR_DATA_H */ diff --git a/include/asm-ppc/iSeries/LparMap.h b/include/asm-ppc/iSeries/LparMap.h new file mode 100644 index 000000000000..179ab2c7209c --- /dev/null +++ b/include/asm-ppc/iSeries/LparMap.h @@ -0,0 +1,76 @@ +/* + * LparMap.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +#ifndef _LPARMAP_H +#define _LPARMAP_H + +/* The iSeries hypervisor will set up mapping for one or more + * ESID/VSID pairs (in SLB/segment registers) and will set up + * mappings of one or more ranges of pages to VAs. + * We will have the hypervisor set up the ESID->VSID mapping + * for the four kernel segments (C-F). With shared processors, + * the hypervisor will clear all segment registers and reload + * these four whenever the processor is switched from one + * partition to another. + */ + +/* The Vsid and Esid identified below will be used by the hypervisor + * to set up a memory mapping for part of the load area before giving + * control to the Linux kernel. The load area is 64 MB, but this must + * not attempt to map the whole load area. The Hashed Page Table may + * need to be located within the load area (if the total partition size + * is 64 MB), but cannot be mapped. Typically, this should specify + * to map half (32 MB) of the load area. + * + * The hypervisor will set up page table entries for the number of + * pages specified. + * + * In 32-bit mode, the hypervisor will load all four of the + * segment registers (identified by the low-order four bits of the + * Esid field. In 64-bit mode, the hypervisor will load one SLB + * entry to map the Esid to the Vsid. +*/ + +// Hypervisor initially maps 32MB of the load area +#define HvPagesToMap 8192 + +struct LparMap +{ + u64 xNumberEsids; // Number of ESID/VSID pairs (4) + u64 xNumberRanges; // Number of VA ranges to map (1) + u64 xSegmentTableOffs; // Page number within load area of seg table (0) + u64 xRsvd[5]; // Reserved (0) + u64 xKernelEsidC; // Esid used to map kernel load (0x0C) + u64 xKernelVsidC; // Vsid used to map kernel load (0x0C) + u64 xKernelEsidD; // Esid used to map kernel load (0x0D) + u64 xKernelVsidD; // Vsid used to map kernel load (0x0D) + u64 xKernelEsidE; // Esid used to map kernel load (0x0E) + u64 xKernelVsidE; // Vsid used to map kernel load (0x0E) + u64 xKernelEsidF; // Esid used to map kernel load (0x0F) + u64 xKernelVsidF; // Vsid used to map kernel load (0x0F) + u64 xPages; // Number of pages to be mapped (8192) + u64 xOffset; // Offset from start of load area (0) + u64 xVPN; // Virtual Page Number (0x00000000000C0000) +}; + +#endif /* _LPARMAP_H */ diff --git a/include/asm-ppc/iSeries/Naca.h b/include/asm-ppc/iSeries/Naca.h new file mode 100644 index 000000000000..c34294288717 --- /dev/null +++ b/include/asm-ppc/iSeries/Naca.h @@ -0,0 +1,38 @@ +/* + * Naca.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +#ifndef _NACA_H +#define _NACA_H + + +struct Naca +{ + u32 xItVpdAreas64; // Address of ItVpdAreas + void * xItVpdAreas; + u32 xRamDisk64; // Address of initial Ramdisk + u32 xRamDisk; + u32 xRamDiskSize64; // Size of initial Ramdisk + u32 xRamDiskSize; // in pages +}; + +#endif /* _NACA_H */ diff --git a/include/asm-ppc/iSeries/Paca.h b/include/asm-ppc/iSeries/Paca.h new file mode 100644 index 000000000000..f9ff68a97e91 --- /dev/null +++ b/include/asm-ppc/iSeries/Paca.h @@ -0,0 +1,137 @@ +/* + * Paca.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +//============================================================================ +// +// This control block defines the OS's PACA which defines the processor +// specific data for each logical processor on the system. +// There are some pointers defined that are utilized by PLIC. +// + +#ifndef _PPC_TYPES_H +#include <asm/types.h> +#endif + +//----------------------------------------------------------------------------- +// Other Includes +//----------------------------------------------------------------------------- +#ifndef _ITLPPACA_H +#include <asm/iSeries/ItLpPaca.h> +#endif + +#ifndef _ITLPREGSAVE_H +#include <asm/iSeries/ItLpRegSave.h> +#endif + +#ifndef _ITLPQUEUE_H +#include <asm/iSeries/ItLpQueue.h> +#endif + + +#ifndef _PACA_H +#define _PACA_H + +/* + * The bolted stack structure is at the head of each bolted stack + * and is simply a singly linked list + */ + +//============================================================================ +// +// Defines the layout of the Paca. +// +// This structure is not directly accessed by PLIC or the SP except +// for the first two pointers that point to the ItLpPaca area and the +// ItLpRegSave area for this processor. +// +//============================================================================ +struct Paca +{ +//=========================================================================== +// Following two fields are read by PLIC to find the LpPaca and LpRegSave area +//=========================================================================== + + u32 pad1; // Pointer to LpPaca for proc + struct ItLpPaca * xLpPacaPtr; // Pointer to LpPaca for proc + u32 pad2; // Pointer to LpRegSave for proc + struct ItLpRegSave * xLpRegSavePtr; // Pointer to LpRegSave for proc + + u64 xR21; // Savearea for GPR21 + u64 xR22; // Savearea for GPR22 + u64 xKsave; // Saved Kernel stack addr or zero + + u16 xPacaIndex; // Index into Paca array of this + // Paca. This is processor number + u8 xProcStart; // At startup, processor spins until + // xProcStart becomes non-zero. + u8 xProcEnabled; // 1 - soft enabled, 0 - soft disabled + u32 xrsvd2; // was bolted stacks + u32 xSavedMsr; // old msr saved here by HvCall + // and flush_hash_page. + // HvCall uses 64-bit registers + // so it must disable external + // interrupts to avoid the high + // half of the regs getting lost + // It can't stack a frame because + // some of the callers can't + // tolerate hpt faults (which might + // occur on the stack) + u32 xSavedLr; // link register saved here by + // flush_hash_page + u8 xContextOverflow; // 1 - context overflow - use temporary + // context = processor# + 1 + u8 rsvd4; + u16 rsvd5; + u32 xSRR0; // Used as bolted copies of stack fields + u32 xSRR1; + u32 xGPR0; + u32 xGPR2; + u32 default_decr; // Default decrementer value + u32 ext_ints; // ext ints processed + u32 rsvd6; + u64 rsvd1[5]; // Rest of cache line reserved + +//=========================================================================== +// CACHE_LINE_2-3 0x0080 - 0x0180 +//=========================================================================== + + struct ItLpQueue * lpQueuePtr; // LpQueue handled by this processor + u32 breakpoint_loop; // Loop until this field is set + // non-zero by user. Then set it + // back to zero before continuing + + u64 debug_regs; // Pointer to pt_regs at breakpoint + u64 rsvd3[30]; // To be used by Linux + +//=========================================================================== +// CACHE_LINE_4-8 0x0180 - 0x03FF Contains ItLpPaca +//=========================================================================== + + struct ItLpPaca xLpPaca; // Space for ItLpPaca + +//=========================================================================== +// CACHE_LINE_9-16 0x0400 - 0x07FF Contains ItLpRegSave +//=========================================================================== + + struct ItLpRegSave xRegSav; // Register save for proc + +}; + +#endif /* _PACA_H */ diff --git a/include/asm-ppc/iSeries/XmPciLpEvent.h b/include/asm-ppc/iSeries/XmPciLpEvent.h new file mode 100644 index 000000000000..a3d27f116e49 --- /dev/null +++ b/include/asm-ppc/iSeries/XmPciLpEvent.h @@ -0,0 +1,18 @@ + +#ifndef __XMPCILPEVENT_H__ +#define __XMPCILPEVENT_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +int XmPciLpEvent_init(void); +void ppc_irq_dispatch_handler(struct pt_regs *regs, int irq); + + +#ifdef __cplusplus +} +#endif + +#endif /* __XMPCILPEVENT_H__ */ diff --git a/include/asm-ppc/iSeries/iSeries_FlightRecorder.h b/include/asm-ppc/iSeries/iSeries_FlightRecorder.h new file mode 100644 index 000000000000..5cc1d7e7d876 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_FlightRecorder.h @@ -0,0 +1,85 @@ +#ifndef _ISERIES_FLIGHTRECORDER_H +#define _ISERIES_FLIGHTRECORDER_H +/************************************************************************/ +/* File iSeries_FlightRecorder.h created by Allan Trautman Jan 22 2001. */ +/************************************************************************/ +/* This code supports the pci interface on the IBM iSeries systems. */ +/* Copyright (C) 20yy <Allan H Trautman> <IBM Corp> */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the: */ +/* Free Software Foundation, Inc., */ +/* 59 Temple Place, Suite 330, */ +/* Boston, MA 02111-1307 USA */ +/************************************************************************/ +/* Change Activity: */ +/* Created, Jan 22, 2001 */ +/* Added Time stamp methods. Apr 12, 2001 */ +/* End Change Activity */ +/************************************************************************/ +/* This is a generic Flight Recorder, simply stuffs line entries into a */ +/* buffer for debug purposes. */ +/* */ +/* To use, */ +/* 1. Create one, make it global so it isn't on the stack. */ +/* FlightRecorder PciFlightRecorder; */ +/* */ +/* 2. Optionally create a pointer to it, just makes it easier to use. */ +/* FlightRecorder* PciFr = &PciFlightRecorder; */ +/* */ +/* 3. Initialize with you signature. */ +/* iSeries_Fr_Initialize(PciFr, "Pci Flight Recorder"); */ +/* */ +/* 4. Log entries. */ +/* PciFr->logEntry(PciFr,"In Main"); */ +/* */ +/* 5. Later, you can find the Flight Recorder by looking in the */ +/* System.map */ +/************************************************************************/ +struct iSeries_FlightRecorder; /* Forward declares */ +struct rtc_time; +void logEntry(struct iSeries_FlightRecorder*, char* Text); +void logTime( struct iSeries_FlightRecorder*, char* Text); +void logDate( struct iSeries_FlightRecorder*, char* Text); +#define FlightRecorderSize 4096 + +/************************************************************************/ +/* Generic Flight Recorder Structure */ +/************************************************************************/ +struct iSeries_FlightRecorder { /* Structure Defination */ + char Signature[16]; /* Eye Catcher */ + char* StartingPointer; /* Buffer Starting Address */ + char* CurrentPointer; /* Next Entry Address */ + int WrapCount; /* Number of Buffer Wraps */ + void (*logEntry)(struct iSeries_FlightRecorder*,char*); + void (*logTime) (struct iSeries_FlightRecorder*,char*); + void (*logDate) (struct iSeries_FlightRecorder*,char*); + char Buffer[FlightRecorderSize]; +}; + +typedef struct iSeries_FlightRecorder FlightRecorder; /* Short Name */ +extern void iSeries_Fr_Initialize(FlightRecorder*, char* Signature); +/************************************************************************/ +/* extern void iSeries_LogFr_Entry( FlightRecorder*, char* Text); */ +/* extern void iSeries_LogFr_Date( FlightRecorder*, char* Text); */ +/* extern void iSeries_LogFr_Time( FlightRecorder*, char* Text); */ +/************************************************************************/ +/* PCI Flight Recorder Helpers */ +/************************************************************************/ +extern FlightRecorder* PciFr; /* Ptr to Pci Fr */ +extern char* PciFrBuffer; /* Ptr to Fr Work Buffer */ +#define ISERIES_PCI_FR(buffer) PciFr->logEntry(PciFr,buffer); +#define ISERIES_PCI_FR_TIME(buffer) PciFr->logTime(PciFr,buffer); +#define ISERIES_PCI_FR_DATE(buffer) PciFr->logDate(PciFr,buffer); + +#endif /* _ISERIES_FLIGHTRECORDER_H */ diff --git a/include/asm-ppc/iSeries/iSeries_VpdInfo.h b/include/asm-ppc/iSeries/iSeries_VpdInfo.h new file mode 100644 index 000000000000..ed6b8e72762f --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_VpdInfo.h @@ -0,0 +1,56 @@ +#ifndef _ISERIES_VPDINFO_H +#define _ISERIES_VPDINFO_H +/************************************************************************/ +/* File iSeries_VpdInfo.h created by Allan Trautman Feb 08 2001. */ +/************************************************************************/ +/* This code supports the location data fon on the IBM iSeries systems. */ +/* Copyright (C) 20yy <Allan H Trautman> <IBM Corp> */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the: */ +/* Free Software Foundation, Inc., */ +/* 59 Temple Place, Suite 330, */ +/* Boston, MA 02111-1307 USA */ +/************************************************************************/ +/* Change Activity: */ +/* Created, Feg 8, 2001 */ +/* Reformated for Card, March 8, 2001 */ +/* End Change Activity */ +/************************************************************************/ + +struct pci_dev; /* Forward Declare */ +/************************************************************************/ +/* Location Data extracted from the VPD list and device info. */ +/************************************************************************/ +struct LocationDataStruct { /* Location data structure for device */ + u16 Bus; /* iSeries Bus Number 0x00*/ + u16 Board; /* iSeries Board 0x02*/ + u8 FrameId; /* iSeries spcn Frame Id 0x04*/ + u8 PhbId; /* iSeries Phb Location 0x05*/ + u16 Card; /* iSeries Card Slot 0x06*/ + char CardLocation[4]; /* Char format of planar vpd 0x08*/ + u8 AgentId; /* iSeries AgentId 0x0C*/ + u8 SecondaryAgentId; /* iSeries Secondary Agent Id 0x0D*/ + u8 LinuxBus; /* Linux Bus Number 0x0E*/ + u8 LinuxDevFn; /* Linux Device Function 0x0F*/ +}; +typedef struct LocationDataStruct LocationData; +#define LOCATION_DATA_SIZE 16 + +/************************************************************************/ +/* Protypes */ +/************************************************************************/ +extern LocationData* iSeries_GetLocationData(struct pci_dev* PciDev); +extern int iSeries_Device_Information(struct pci_dev*,char*, int); + +#endif /* _ISERIES_VPDINFO_H */ diff --git a/include/asm-ppc/iSeries/iSeries_dma.h b/include/asm-ppc/iSeries/iSeries_dma.h new file mode 100644 index 000000000000..8b1ad755ae82 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_dma.h @@ -0,0 +1,97 @@ +/* + * iSeries_dma.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef _ISERIES_DMA_H +#define _ISERIES_DMA_H + +#include <asm/types.h> +#ifndef __LINUX_SPINLOCK_H +#include <linux/spinlock.h> +#endif + +// NUM_TCE_LEVELS defines the largest contiguous block +// of dma (tce) space we can get. NUM_TCE_LEVELS = 10 +// allows up to 2**9 pages (512 * 4096) = 2 MB +#define NUM_TCE_LEVELS 10 + +#define NO_TCE ((dma_addr_t)-1) + +// Tces come in two formats, one for the virtual bus and a different +// format for PCI +#define TCE_VB 0 +#define TCE_PCI 1 + + +union Tce { + u64 wholeTce; + struct { + u64 cacheBits :6; /* Cache hash bits - not used */ + u64 rsvd :6; + u64 rpn :40; /* Absolute page number */ + u64 valid :1; /* Tce is valid (vb only) */ + u64 allIo :1; /* Tce is valid for all lps (vb only) */ + u64 lpIndex :8; /* LpIndex for user of TCE (vb only) */ + u64 pciWrite :1; /* Write allowed (pci only) */ + u64 readWrite :1; /* Read allowed (pci), Write allowed + (vb) */ + } tceBits; +}; + +struct Bitmap { + unsigned long numBits; + unsigned long numBytes; + unsigned char * map; +}; + +struct MultiLevelBitmap { + unsigned long maxLevel; + struct Bitmap level[NUM_TCE_LEVELS]; +}; + +struct TceTable { + u64 busNumber; + u64 size; + u64 startOffset; + u64 index; + spinlock_t lock; + struct MultiLevelBitmap mlbm; +}; + +struct HvTceTableManagerCB { + u64 busNumber; /* Bus number for this tce table */ + u64 start; /* Will be NULL for secondary */ + u64 totalSize; /* Size (in pages) of whole table */ + u64 startOffset; /* Index into real tce table of the + start of our section */ + u64 size; /* Size (in pages) of our section */ + u64 index; /* Index of this tce table (token?) */ + u16 maxTceTableIndex; /* Max number of tables for partition */ + u8 virtualBusFlag; /* Flag to indicate virtual bus */ + u8 rsvd[5]; +}; + +extern struct TceTable virtBusTceTable; /* Tce table for virtual bus */ + +extern struct TceTable * build_tce_table( struct HvTceTableManagerCB *, + struct TceTable *); +extern void create_virtual_bus_tce_table( void ); + +extern void create_pci_bus_tce_table( unsigned busNumber ); + +#endif // _ISERIES_DMA_H diff --git a/include/asm-ppc/iSeries/iSeries_fixup.h b/include/asm-ppc/iSeries/iSeries_fixup.h new file mode 100644 index 000000000000..5d1d33f16ba7 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_fixup.h @@ -0,0 +1,25 @@ + +#ifndef __ISERIES_FIXUP_H__ +#define __ISERIES_FIXUP_H__ +#include <linux/pci.h> + +#ifdef __cplusplus +extern "C" { +#endif + +void iSeries_fixup (void); +void iSeries_fixup_bus (struct pci_bus*); +unsigned int iSeries_scan_slot (struct pci_dev*, u16, u8, u8); + + +/* Need to store information related to the PHB bucc and make it accessible to the hose */ +struct iSeries_hose_arch_data { + u32 hvBusNumber; +}; + + +#ifdef __cplusplus +} +#endif + +#endif /* __ISERIES_FIXUP_H__ */ diff --git a/include/asm-ppc/iSeries/iSeries_io.h b/include/asm-ppc/iSeries/iSeries_io.h new file mode 100644 index 000000000000..0199ad4241d3 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_io.h @@ -0,0 +1,42 @@ +#ifdef CONFIG_PPC_ISERIES +#ifndef _ISERIES_IO_H +#define _ISERIES_IO_H +/************************************************************************/ +/* File iSeries_io.h created by Allan Trautman on Thu Dec 28 2000. */ +/************************************************************************/ +/* Remaps the io.h for the iSeries Io */ +/* Copyright (C) 20yy Allan H Trautman, IBM Corporation */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the: */ +/* Free Software Foundation, Inc., */ +/* 59 Temple Place, Suite 330, */ +/* Boston, MA 02111-1307 USA */ +/************************************************************************/ +/* Change Activity: */ +/* Created December 28, 2000 */ +/* End Change Activity */ +/************************************************************************/ +extern u8 iSeries_Readb(u32* IoAddress); +extern u16 iSeries_Readw(u32* IoAddress); +extern u32 iSeries_Readl(u32* IoAddress); +extern void iSeries_Writeb(u8 IoData,u32* IoAddress); +extern void iSeries_Writew(u16 IoData,u32* IoAddress); +extern void iSeries_Writel(u32 IoData,u32* IoAddress); + +extern void* iSeries_memcpy_toio(void *dest, void *source, int n); +extern void* iSeries_memcpy_fromio(void *dest, void *source, int n); + +#endif /* _ISERIES_IO_H */ +#endif /* CONFIG_PPC_ISERIES */ + diff --git a/include/asm-ppc/iSeries/iSeries_irq.h b/include/asm-ppc/iSeries/iSeries_irq.h new file mode 100644 index 000000000000..a2af15e44c87 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_irq.h @@ -0,0 +1,26 @@ + +#ifndef __ISERIES_IRQ_H__ +#define __ISERIES_IRQ_H__ + + +#ifdef __cplusplus +extern "C" { +#endif + +unsigned int iSeries_startup_IRQ(unsigned int); +void iSeries_shutdown_IRQ(unsigned int); +void iSeries_enable_IRQ(unsigned int); +void iSeries_disable_IRQ(unsigned int); +void iSeries_end_IRQ(unsigned int); +void iSeries_init_IRQ(void); +void iSeries_init_irqMap(int); +int iSeries_allocate_IRQ(HvBusNumber, HvSubBusNumber, HvAgentId); +int iSeries_assign_IRQ(int, HvBusNumber, HvSubBusNumber, HvAgentId); +void iSeries_activate_IRQs(void); + + +#ifdef __cplusplus +} +#endif + +#endif /* __ISERIES_IRQ_H__ */ diff --git a/include/asm-ppc/iSeries/iSeries_pci.h b/include/asm-ppc/iSeries/iSeries_pci.h new file mode 100644 index 000000000000..b85c597df959 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_pci.h @@ -0,0 +1,123 @@ +#ifndef _ISERIES_32_PCI_H +#define _ISERIES_32_PCI_H +/************************************************************************/ +/* File iSeries_pci.h created by Allan Trautman on Tue Feb 20, 2001. */ +/************************************************************************/ +/* Define some useful macros for the iSeries pci routines. */ +/* Copyright (C) 20yy Allan H Trautman, IBM Corporation */ +/* */ +/* This program is free software; you can redistribute it and/or modify */ +/* it under the terms of the GNU General Public License as published by */ +/* the Free Software Foundation; either version 2 of the License, or */ +/* (at your option) any later version. */ +/* */ +/* This program is distributed in the hope that it will be useful, */ +/* but WITHOUT ANY WARRANTY; without even the implied warranty of */ +/* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the */ +/* GNU General Public License for more details. */ +/* */ +/* You should have received a copy of the GNU General Public License */ +/* along with this program; if not, write to the: */ +/* Free Software Foundation, Inc., */ +/* 59 Temple Place, Suite 330, */ +/* Boston, MA 02111-1307 USA */ +/************************************************************************/ +/* Change Activity: */ +/* Created Feb 20, 2001 */ +/* Added device reset, March 22, 2001 */ +/* End Change Activity */ +/************************************************************************/ +#include <linux/config.h> +#include <asm/iSeries/HvCallPci.h> + +struct pci_dev; /* For Reference */ +/************************************************************************/ +/* Gets iSeries Bus, SubBus, of DevFn using pci_dev* structure */ +/************************************************************************/ +#define ISERIES_GET_BUS(DevPtr) iSeries_Get_Bus(DevPtr) +#define ISERIES_GET_SUBBUS(DevPtr) iSeries_Get_SubBus(DevPtr) +#define ISERIES_GET_DEVFUN(DevPtr) iSeries_Get_DevFn(DevPtr) +/************************************************************************/ +/* Functions */ +/************************************************************************/ +extern u8 iSeries_Get_Bus(struct pci_dev*); +extern u8 iSeries_Get_SubBus(struct pci_dev*); +extern u8 iSeries_Get_DevFn(struct pci_dev*); +/************************************************************************/ +/* Global Bus map */ +/************************************************************************/ +extern u8 iSeries_GlobalBusMap[256][2]; /* Global iSeries Bus Map */ + +/************************************************************************/ +/* iSeries Device Information */ +/************************************************************************/ +struct iSeries_Device_Struct { + struct pci_dev* PciDevPtr; /* Pointer to pci_dev structure */ + HvBusNumber BusNumber; /* Hypervisor Bus Number */ + HvSubBusNumber SubBus; /* Hypervisor SubBus Number */ + HvAgentId DevFn; /* Hypervisor DevFn */ + u8 BarNumber; /* Bar number on Xlates */ + u32 BarOffset; /* Offset within Bar on Xlates */ + int RCode; /* Return Code Holder */ +}; +typedef struct iSeries_Device_Struct iSeries_Device; +extern void build_iSeries_Device(iSeries_Device* Device, struct pci_dev* DevPtr); + +/************************************************************************/ +/* Formatting device information. */ +/************************************************************************/ +extern int iSeries_Device_Information(struct pci_dev*,char*,int ); + +/************************************************************************/ +/* Flight Recorder tracing */ +/************************************************************************/ +extern void iSeries_Set_PciFilter(struct pci_dev*); +extern int iSeries_Set_PciTraceFlag(int TraceFlag); +extern int iSeries_Get_PciTraceFlag(void); +extern int iSeries_Set_PciErpFlag(int ErpFlag); + +/************************************************************************/ +/* Structure to hold the data for PCI Register Save/Restore functions. */ +/************************************************************************/ +struct pci_config_reg_save_area { /* */ + u16 Flags; /* Control & Info Flags */ + u16 ByteCount; /* Number of Register Bytes to S*/ + struct pci_dev* PciDev; /* Pointer to device */ + u32 RCode; /* Holder for possible errors */ + u32 FailReg; /* Failing Register on error */ + u8 Regs[64]; /* Save Area */ +}; +typedef struct pci_config_reg_save_area PciReqsSaveArea; +/************************************************************************/ +/* Various flavors of reset device functions. */ +/************************************************************************/ +/* */ +/* iSeries_Device_Reset_NoIrq */ +/* IRQ is not disabled and default timings are used. */ +/* iSeries_Device_Reset_Generic */ +/* A generic reset, IRQ is disable and re-enabled. The assert and */ +/* wait timings will be the pci defaults. */ +/* iSeries_Device_Reset */ +/* A device Reset interface that client can control the timing of */ +/* the reset and wait delays. */ +/* */ +/* Parameters: */ +/* pci_dev = Device to reset. */ +/* AssertTime = Time in .1 seconds to hold the reset down. The */ +/* default (and minimum) is .5 seconds. */ +/* DelayTime = Time in .1 seconds to wait for device to come ready */ +/* after the reset. The default is 3 seconds. */ +/* IrgDisable = A non-zero will skip irq disable & enable. */ +/* */ +/* Return: */ +/* Zero return, reset is successful. */ +/* Non-zero return code indicates failure. */ +/************************************************************************/ +extern int iSeries_Device_Reset_NoIrq(struct pci_dev* PciDev); +extern int iSeries_Device_Reset_Generic(struct pci_dev* PciDev); +extern int iSeries_Device_Reset(struct pci_dev* PciDev, int AssertTime, int DelayTime, int IrqDisable); +extern int iSeries_Device_ToggleReset(struct pci_dev* PciDev, int AssertTime, int DelayTime); +extern int iSeries_Device_RestoreConfigRegs(PciReqsSaveArea* SaveArea); +extern PciReqsSaveArea* iSeries_Device_SaveConfigRegs(struct pci_dev* DevPtr); + +#endif /* _ISERIES_32_PCI_H */ diff --git a/include/asm-ppc/iSeries/iSeries_proc.h b/include/asm-ppc/iSeries/iSeries_proc.h new file mode 100644 index 000000000000..a1e146cb0cd1 --- /dev/null +++ b/include/asm-ppc/iSeries/iSeries_proc.h @@ -0,0 +1,37 @@ +/* + * iSeries_proc.h + * Copyright (C) 2001 Kyle A. Lucke IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* Change Activity: */ +/* End Change Activity */ + +#ifndef _ISERIES_PROC_H +#define _ISERIES_PROC_H + +#include <linux/proc_fs.h> + +extern void iSeries_proc_early_init(void); +extern void iSeries_proc_create(void); + +typedef void (*iSeriesProcFunction)(struct proc_dir_entry *iSeries_proc); + +extern void iSeries_proc_callback(iSeriesProcFunction initFunction); + +#endif /* _iSeries_PROC_H */ + diff --git a/include/asm-ppc/iSeries/mf.h b/include/asm-ppc/iSeries/mf.h new file mode 100644 index 000000000000..262936967622 --- /dev/null +++ b/include/asm-ppc/iSeries/mf.h @@ -0,0 +1,83 @@ +/* + * mf.h + * Copyright (C) 2001 Troy D. Armstrong IBM Corporation + * + * This modules exists as an interface between a Linux secondary partition + * running on an iSeries and the primary partition's Virtual Service + * Processor (VSP) object. The VSP has final authority over powering on/off + * all partitions in the iSeries. It also provides miscellaneous low-level + * machine facility type operations. + * + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#ifndef MF_H_INCLUDED +#define MF_H_INCLUDED + +#include <asm/iSeries/HvTypes.h> +#include <asm/iSeries/HvLpEvent.h> + +struct rtc_time; + +typedef void (*MFCompleteHandler)( void * clientToken, int returnCode ); + +extern void mf_allocateLpEvents( HvLpIndex targetLp, + HvLpEvent_Type type, + unsigned size, + unsigned amount, + MFCompleteHandler hdlr, + void * userToken ); + +extern void mf_deallocateLpEvents( HvLpIndex targetLp, + HvLpEvent_Type type, + unsigned count, + MFCompleteHandler hdlr, + void * userToken ); + +extern void mf_powerOff( void ); + +extern void mf_reboot( void ); + +extern void mf_displaySrc( u32 word ); +extern void mf_displayProgress( u16 value ); + +extern void mf_clearSrc( void ); + +extern void mf_init( void ); + +extern void mf_setSide(char side); + +extern char mf_getSide(void); + +extern void mf_setCmdLine(const char *cmdline, int size, u64 side); + +extern int mf_getCmdLine(char *cmdline, int *size, u64 side); + +extern void mf_getSrcHistory(char *buffer, int size); + +extern int mf_setVmlinuxChunk(const char *buffer, int size, int offset, u64 side); + +extern int mf_getVmlinuxChunk(char *buffer, int *size, int offset, u64 side); + +extern int mf_setRtcTime(unsigned long time); + +extern int mf_getRtcTime(unsigned long *time); + +extern int mf_getRtc( struct rtc_time * tm ); + +extern int mf_setRtc( struct rtc_time * tm ); + +#endif /* MF_H_INCLUDED */ diff --git a/include/asm-ppc/iSeries/mf_proc.h b/include/asm-ppc/iSeries/mf_proc.h new file mode 100644 index 000000000000..1e205cf49f85 --- /dev/null +++ b/include/asm-ppc/iSeries/mf_proc.h @@ -0,0 +1,33 @@ +/* + * mf_proc.h + * Copyright (C) 2001 Kyle A. Lucke IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* Change Activity: */ +/* End Change Activity */ + +#ifndef _MF_PROC_H +#define _MF_PROC_H + +#include <linux/proc_fs.h> + +void mf_proc_init(struct proc_dir_entry *iSeries_proc); + + +#endif /* _MF_PROC_H */ + diff --git a/include/asm-ppc/iSeries/pmc_proc.h b/include/asm-ppc/iSeries/pmc_proc.h new file mode 100644 index 000000000000..31d3b6a085da --- /dev/null +++ b/include/asm-ppc/iSeries/pmc_proc.h @@ -0,0 +1,33 @@ +/* + * pmc_proc.h + * Copyright (C) 2001 Mike Corrigan IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* Change Activity: */ +/* End Change Activity */ + +#ifndef _PMC_PROC_H +#define _PMC_PROC_H + +#include <linux/proc_fs.h> + +void pmc_proc_init(struct proc_dir_entry *iSeries_proc); + + +#endif /* _PMC_PROC_H */ + diff --git a/include/asm-ppc/iSeries/veth-proc.h b/include/asm-ppc/iSeries/veth-proc.h new file mode 100644 index 000000000000..c019ffd2b56e --- /dev/null +++ b/include/asm-ppc/iSeries/veth-proc.h @@ -0,0 +1,32 @@ +/* + * veth-proc.h + * Copyright (C) 2001 Kyle A. Lucke IBM Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + + +/* Change Activity: */ +/* End Change Activity */ + +#ifndef _VETH_PROC_H +#define _VETH_PROC_H + +#include <linux/proc_fs.h> + +void veth_proc_init(struct proc_dir_entry *iSeries_proc); + +#endif /* _VETH-PROC_H */ + diff --git a/include/asm-ppc/ibm403.h b/include/asm-ppc/ibm403.h new file mode 100644 index 000000000000..7845871bdc08 --- /dev/null +++ b/include/asm-ppc/ibm403.h @@ -0,0 +1,509 @@ +/* + * ibm403.h + * + * This was dirived from the ibm4xx.h and all 403 specific definitions + * where moved here. + * + * Armin Kuster <akuster@mvista.com> + * Tom Rini <trini@mvista.com> + * Oct, 2001 + * + * + * Copyright 2001 MontaVista Softare Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED + * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN + * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT + * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF + * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON + * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF + * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, write to the Free Software Foundation, Inc., + * 675 Mass Ave, Cambridge, MA 02139, USA. + * + * Version 1.0 Oct 10, 2001 - A. Kuster + * Initial version - moved 403 specific out of ibm4xx.h + * Version 1.1 Oct 25, 2001 - T. Rini + * Lots of cleanups. + */ + + +#ifdef __KERNEL__ +#ifndef __ASM_IBM403_H__ +#define __ASM_IBM403_H__ + +#include <linux/config.h> + +#if defined(CONFIG_403GCX) + +#define DCRN_BE_BASE 0x090 +#define DCRN_DMA0_BASE 0x0C0 +#define DCRN_DMA1_BASE 0x0C8 +#define DCRN_DMA2_BASE 0x0D0 +#define DCRN_DMA3_BASE 0x0D8 +#define DCRNCAP_DMA_CC 1 /* have DMA chained count capability */ +#define DCRN_DMASR_BASE 0x0E0 + +#define DCRN_EXIER_BASE 0x042 +#define DCRN_EXISR_BASE 0x040 +#define DCRN_IOCR_BASE 0x0A0 + + +/* ------------------------------------------------------------------------- */ +#endif + + + +#ifdef DCRN_BE_BASE +#define DCRN_BEAR (DCRN_BE_BASE + 0x0) /* Bus Error Address Register */ +#define DCRN_BESR (DCRN_BE_BASE + 0x1) /* Bus Error Syndrome Register*/ +#endif +/* DCRN_BESR */ +#define BESR_DSES 0x80000000 /* Data-Side Error Status */ +#define BESR_DMES 0x40000000 /* DMA Error Status */ +#define BESR_RWS 0x20000000 /* Read/Write Status */ +#define BESR_ETMASK 0x1C000000 /* Error Type */ +#define ET_PROT 0 +#define ET_PARITY 1 +#define ET_NCFG 2 +#define ET_BUSERR 4 +#define ET_BUSTO 6 + +#ifdef DCRN_CHCR_BASE +#define DCRN_CHCR0 (DCRN_CHCR_BASE + 0x0) /* Chip Control Register 1 */ +#define DCRN_CHCR1 (DCRN_CHCR_BASE + 0x1) /* Chip Control Register 2 */ +#endif +#define CHR1_CETE 0x00800000 /* CPU external timer enable */ +#define CHR1_PCIPW 0x00008000 /* PCI Int enable/Peripheral Write enable */ + +#ifdef DCRN_CHPSR_BASE +#define DCRN_CHPSR (DCRN_CHPSR_BASE + 0x0) /* Chip Pin Strapping */ +#endif + +#ifdef DCRN_CIC_BASE +#define DCRN_CICCR (DCRN_CIC_BASE + 0x0) /* CIC Control Register */ +#define DCRN_DMAS1 (DCRN_CIC_BASE + 0x1) /* DMA Select1 Register */ +#define DCRN_DMAS2 (DCRN_CIC_BASE + 0x2) /* DMA Select2 Register */ +#define DCRN_CICVCR (DCRN_CIC_BASE + 0x3) /* CIC Video COntro Register */ +#define DCRN_CICSEL3 (DCRN_CIC_BASE + 0x5) /* CIC Select 3 Register */ +#define DCRN_SGPO (DCRN_CIC_BASE + 0x6) /* CIC GPIO Output Register */ +#define DCRN_SGPOD (DCRN_CIC_BASE + 0x7) /* CIC GPIO OD Register */ +#define DCRN_SGPTC (DCRN_CIC_BASE + 0x8) /* CIC GPIO Tristate Ctrl Reg */ +#define DCRN_SGPI (DCRN_CIC_BASE + 0x9) /* CIC GPIO Input Reg */ +#endif + +#ifdef DCRN_CPMFR_BASE +#define DCRN_CPMFR (DCRN_CPMFR_BASE + 0x0) /* CPM Force */ +#endif + +#ifndef CPM_AUD +#define CPM_AUD 0x00000000 +#endif +#ifndef CPM_BRG +#define CPM_BRG 0x00000000 +#endif +#ifndef CPM_CBS +#define CPM_CBS 0x00000000 +#endif +#ifndef CPM_CPU +#define CPM_CPU 0x00000000 +#endif +#ifndef CPM_DCP +#define CPM_DCP 0x00000000 +#endif +#ifndef CPM_DCRX +#define CPM_DCRX 0x00000000 +#endif +#ifndef CPM_DENC +#define CPM_DENC 0x00000000 +#endif +#ifndef CPM_DMA +#define CPM_DMA 0x00000000 +#endif +#ifndef CPM_DSCR +#define CPM_DSCR 0x00000000 +#endif +#ifndef CPM_EBC +#define CPM_EBC 0x00000000 +#endif +#ifndef CPM_EBIU +#define CPM_EBIU 0x00000000 +#endif +#ifndef CPM_EMAC_MM +#define CPM_EMAC_MM 0x00000000 +#endif +#ifndef CPM_EMAC_RM +#define CPM_EMAC_RM 0x00000000 +#endif +#ifndef CPM_EMAC_TM +#define CPM_EMAC_TM 0x00000000 +#endif +#ifndef CPM_GPIO0 +#define CPM_GPIO0 0x00000000 +#endif +#ifndef CPM_GPT +#define CPM_GPT 0x00000000 +#endif +#ifndef CPM_I1284 +#define CPM_I1284 0x00000000 +#endif +#ifndef CPM_IIC0 +#define CPM_IIC0 0x00000000 +#endif +#ifndef CPM_IIC1 +#define CPM_IIC1 0x00000000 +#endif +#ifndef CPM_MSI +#define CPM_MSI 0x00000000 +#endif +#ifndef CPM_PCI +#define CPM_PCI 0x00000000 +#endif +#ifndef CPM_PLB +#define CPM_PLB 0x00000000 +#endif +#ifndef CPM_SC0 +#define CPM_SC0 0x00000000 +#endif +#ifndef CPM_SC1 +#define CPM_SC1 0x00000000 +#endif +#ifndef CPM_SDRAM0 +#define CPM_SDRAM0 0x00000000 +#endif +#ifndef CPM_SDRAM1 +#define CPM_SDRAM1 0x00000000 +#endif +#ifndef CPM_TMRCLK +#define CPM_TMRCLK 0x00000000 +#endif +#ifndef CPM_UART0 +#define CPM_UART0 0x00000000 +#endif +#ifndef CPM_UART1 +#define CPM_UART1 0x00000000 +#endif +#ifndef CPM_UART2 +#define CPM_UART2 0x00000000 +#endif +#ifndef CPM_UIC +#define CPM_UIC 0x00000000 +#endif +#ifndef CPM_VID2 +#define CPM_VID2 0x00000000 +#endif +#ifndef CPM_XPT27 +#define CPM_XPT27 0x00000000 +#endif +#ifndef CPM_XPT54 +#define CPM_XPT54 0x00000000 +#endif + +#ifdef DCRN_CPMSR_BASE +#define DCRN_CPMSR (DCRN_CPMSR_BASE + 0x0) /* CPM Status */ +#define DCRN_CPMER (DCRN_CPMSR_BASE + 0x1) /* CPM Enable */ +#endif + +#ifdef DCRN_DCP0_BASE +#define DCRN_DCP0_CFGADDR (DCRN_DCP0_BASE + 0x0) /* Decompression Controller Address */ +#define DCRN_DCP0_CFGDATA (DCRN_DCP0_BASE + 0x1) /* Decompression Controller Data */ +#endif + +#ifdef DCRN_DCRX_BASE +#define DCRN_DCRXICR (DCRN_DCRX_BASE + 0x0) /* Internal Control Register */ +#define DCRN_DCRXISR (DCRN_DCRX_BASE + 0x1) /* Internal Status Register */ +#define DCRN_DCRXECR (DCRN_DCRX_BASE + 0x2) /* External Control Register */ +#define DCRN_DCRXESR (DCRN_DCRX_BASE + 0x3) /* External Status Register */ +#define DCRN_DCRXTAR (DCRN_DCRX_BASE + 0x4) /* Target Address Register */ +#define DCRN_DCRXTDR (DCRN_DCRX_BASE + 0x5) /* Target Data Register */ +#define DCRN_DCRXIGR (DCRN_DCRX_BASE + 0x6) /* Interrupt Generation Register */ +#define DCRN_DCRXBCR (DCRN_DCRX_BASE + 0x7) /* Line Buffer Control Register */ +#endif + +#ifdef DCRN_DMA0_BASE +#define DCRN_DMACR0 (DCRN_DMA0_BASE + 0x0) /* DMA Channel Control Register 0 */ +#define DCRN_DMACT0 (DCRN_DMA0_BASE + 0x1) /* DMA Count Register 0 */ +#define DCRN_DMADA0 (DCRN_DMA0_BASE + 0x2) /* DMA Destination Address Register 0 */ +#define DCRN_DMASA0 (DCRN_DMA0_BASE + 0x3) /* DMA Source Address Register 0 */ +#ifdef DCRNCAP_DMA_CC +#define DCRN_DMACC0 (DCRN_DMA0_BASE + 0x4) /* DMA Chained Count Register 0 */ +#endif + +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASG0 (DCRN_DMA0_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 0 */ +#endif +#endif + +#ifdef DCRN_DMA1_BASE +#define DCRN_DMACR1 (DCRN_DMA1_BASE + 0x0) /* DMA Channel Control Register 1 */ +#define DCRN_DMACT1 (DCRN_DMA1_BASE + 0x1) /* DMA Count Register 1 */ +#define DCRN_DMADA1 (DCRN_DMA1_BASE + 0x2) /* DMA Destination Address Register 1 */ +#define DCRN_DMASA1 (DCRN_DMA1_BASE + 0x3) /* DMA Source Address Register 1 */ + +#ifdef DCRNCAP_DMA_CC +#define DCRN_DMACC1 (DCRN_DMA1_BASE + 0x4) /* DMA Chained Count Register 1 */ +#endif +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASG1 (DCRN_DMA1_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 1 */ +#endif +#endif + +#ifdef DCRN_DMA2_BASE +#define DCRN_DMACR2 (DCRN_DMA2_BASE + 0x0) /* DMA Channel Control Register 2 */ +#define DCRN_DMACT2 (DCRN_DMA2_BASE + 0x1) /* DMA Count Register 2 */ +#define DCRN_DMADA2 (DCRN_DMA2_BASE + 0x2) /* DMA Destination Address Register 2 */ +#define DCRN_DMASA2 (DCRN_DMA2_BASE + 0x3) /* DMA Source Address Register 2 */ +#ifdef DCRNCAP_DMA_CC +#define DCRN_DMACC2 (DCRN_DMA2_BASE + 0x4) /* DMA Chained Count Register 2 */ +#endif +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASG2 (DCRN_DMA2_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 2 */ +#endif +#endif + +#ifdef DCRN_DMA3_BASE +#define DCRN_DMACR3 (DCRN_DMA3_BASE + 0x0) /* DMA Channel Control Register 3 */ +#define DCRN_DMACT3 (DCRN_DMA3_BASE + 0x1) /* DMA Count Register 3 */ +#define DCRN_DMADA3 (DCRN_DMA3_BASE + 0x2) /* DMA Destination Address Register 3 */ +#define DCRN_DMASA3 (DCRN_DMA3_BASE + 0x3) /* DMA Source Address Register 3 */ +#ifdef DCRNCAP_DMA_CC +#define DCRN_DMACC3 (DCRN_DMA3_BASE + 0x4) /* DMA Chained Count Register 3 */ +#endif +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASG3 (DCRN_DMA3_BASE + 0x4) /* DMA Scatter/Gather Descriptor Addr 3 */ +#endif +#endif + +#ifdef DCRN_DMASR_BASE +#define DCRN_DMASR (DCRN_DMASR_BASE + 0x0) /* DMA Status Register */ +#ifdef DCRNCAP_DMA_SG +#define DCRN_ASGC (DCRN_DMASR_BASE + 0x3) /* DMA Scatter/Gather Command */ +/* don't know if these two registers always exist if scatter/gather exists */ +#define DCRN_POL (DCRN_DMASR_BASE + 0x6) /* DMA Polarity Register */ +#define DCRN_SLP (DCRN_DMASR_BASE + 0x5) /* DMA Sleep Register */ +#endif +#endif + +#ifdef DCRN_EBC_BASE +#define DCRN_EBCCFGADR (DCRN_EBC_BASE + 0x0) /* Peripheral Controller Address */ +#define DCRN_EBCCFGDATA (DCRN_EBC_BASE + 0x1) /* Peripheral Controller Data */ +#endif + +#ifdef DCRN_EXIER_BASE +#define DCRN_EXIER (DCRN_EXIER_BASE + 0x0) /* External Interrupt Enable Register */ +#endif + +#ifdef DCRN_EBIMC_BASE +#define DCRN_BRCRH0 (DCRN_EBIMC_BASE + 0x0) /* Bus Region Config High 0 */ +#define DCRN_BRCRH1 (DCRN_EBIMC_BASE + 0x1) /* Bus Region Config High 1 */ +#define DCRN_BRCRH2 (DCRN_EBIMC_BASE + 0x2) /* Bus Region Config High 2 */ +#define DCRN_BRCRH3 (DCRN_EBIMC_BASE + 0x3) /* Bus Region Config High 3 */ +#define DCRN_BRCRH4 (DCRN_EBIMC_BASE + 0x4) /* Bus Region Config High 4 */ +#define DCRN_BRCRH5 (DCRN_EBIMC_BASE + 0x5) /* Bus Region Config High 5 */ +#define DCRN_BRCRH6 (DCRN_EBIMC_BASE + 0x6) /* Bus Region Config High 6 */ +#define DCRN_BRCRH7 (DCRN_EBIMC_BASE + 0x7) /* Bus Region Config High 7 */ +#define DCRN_BRCR0 (DCRN_EBIMC_BASE + 0x10)/* BRC 0 */ +#define DCRN_BRCR1 (DCRN_EBIMC_BASE + 0x11)/* BRC 1 */ +#define DCRN_BRCR2 (DCRN_EBIMC_BASE + 0x12)/* BRC 2 */ +#define DCRN_BRCR3 (DCRN_EBIMC_BASE + 0x13)/* BRC 3 */ +#define DCRN_BRCR4 (DCRN_EBIMC_BASE + 0x14)/* BRC 4 */ +#define DCRN_BRCR5 (DCRN_EBIMC_BASE + 0x15)/* BRC 5 */ +#define DCRN_BRCR6 (DCRN_EBIMC_BASE + 0x16)/* BRC 6 */ +#define DCRN_BRCR7 (DCRN_EBIMC_BASE + 0x17)/* BRC 7 */ +#define DCRN_BEAR0 (DCRN_EBIMC_BASE + 0x20)/* Bus Error Address Register */ +#define DCRN_BESR0 (DCRN_EBIMC_BASE + 0x21)/* Bus Error Status Register */ +#define DCRN_BIUCR (DCRN_EBIMC_BASE + 0x2A)/* Bus Interfac Unit Ctrl Reg */ +#endif + +#ifdef DCRN_EXISR_BASE +#define DCRN_EXISR (DCRN_EXISR_BASE + 0x0) /* External Interrupt Status Register */ +#endif +#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ +#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ +#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ +#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ +#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ +#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ +#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ +#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ +#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ +#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ +#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ +#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ +#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ +#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ + +#ifdef DCRN_IOCR_BASE +#define DCRN_IOCR (DCRN_IOCR_BASE + 0x0) /* Input/Output Configuration Register */ +#endif +#define IOCR_E0TE 0x80000000 +#define IOCR_E0LP 0x40000000 +#define IOCR_E1TE 0x20000000 +#define IOCR_E1LP 0x10000000 +#define IOCR_E2TE 0x08000000 +#define IOCR_E2LP 0x04000000 +#define IOCR_E3TE 0x02000000 +#define IOCR_E3LP 0x01000000 +#define IOCR_E4TE 0x00800000 +#define IOCR_E4LP 0x00400000 +#define IOCR_EDT 0x00080000 +#define IOCR_SOR 0x00040000 +#define IOCR_EDO 0x00008000 +#define IOCR_2XC 0x00004000 +#define IOCR_ATC 0x00002000 +#define IOCR_SPD 0x00001000 +#define IOCR_BEM 0x00000800 +#define IOCR_PTD 0x00000400 +#define IOCR_ARE 0x00000080 +#define IOCR_DRC 0x00000020 +#define IOCR_RDM(x) (((x) & 0x3) << 3) +#define IOCR_TCS 0x00000004 +#define IOCR_SCS 0x00000002 +#define IOCR_SPC 0x00000001 + +#ifdef DCRN_MAL_BASE +#define DCRN_MALCR (DCRN_MAL_BASE + 0x0) /* MAL Configuration */ +#define DCRN_MALDBR (DCRN_MAL_BASE + 0x3) /* Debug Register */ +#define DCRN_MALESR (DCRN_MAL_BASE + 0x1) /* Error Status */ +#define DCRN_MALIER (DCRN_MAL_BASE + 0x2) /* Interrupt Enable */ +#define DCRN_MALTXCARR (DCRN_MAL_BASE + 0x5) /* TX Channed Active Reset Register */ +#define DCRN_MALTXCASR (DCRN_MAL_BASE + 0x4) /* TX Channel Active Set Register */ +#define DCRN_MALTXDEIR (DCRN_MAL_BASE + 0x7) /* Tx Descriptor Error Interrupt */ +#define DCRN_MALTXEOBISR (DCRN_MAL_BASE + 0x6) /* Tx End of Buffer Interrupt Status */ +#define DCRN_MALRXCARR (DCRN_MAL_BASE + 0x11) /* RX Channed Active Reset Register */ +#define DCRN_MALRXCASR (DCRN_MAL_BASE + 0x10) /* RX Channel Active Set Register */ +#define DCRN_MALRXDEIR (DCRN_MAL_BASE + 0x13) /* Rx Descriptor Error Interrupt */ +#define DCRN_MALRXEOBISR (DCRN_MAL_BASE + 0x12) /* Rx End of Buffer Interrupt Status */ +#define DCRN_MALRXCTP0R (DCRN_MAL_BASE + 0x40) /* Channel Rx 0 Channel Table Pointer */ +#define DCRN_MALTXCTP0R (DCRN_MAL_BASE + 0x20) /* Channel Tx 0 Channel Table Pointer */ +#define DCRN_MALTXCTP1R (DCRN_MAL_BASE + 0x21) /* Channel Tx 1 Channel Table Pointer */ +#define DCRN_MALRCBS0 (DCRN_MAL_BASE + 0x60) /* Channel Rx 0 Channel Buffer Size */ +#endif +/* DCRN_MALCR */ +#define MALCR_MMSR 0x80000000/* MAL Software reset */ +#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ +#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ +#define MALCR_PLBP_3 0x00C00000 /* highest */ +#define MALCR_GA 0x00200000 /* Guarded Active Bit */ +#define MALCR_OA 0x00100000 /* Ordered Active Bit */ +#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ +#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ +#define MALCR_PLBLT_2 0x00020000 +#define MALCR_PLBLT_3 0x00010000 +#define MALCR_PLBLT_4 0x00008000 +#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ +#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ +#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ +#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ +#define MALCR_LEA 0x00000002 /* Locked Error Active */ +#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ +/* DCRN_MALESR */ +#define MALESR_EVB 0x80000000 /* Error Valid Bit */ +#define MALESR_CIDRX 0x40000000 /* Channel ID Receive */ +#define MALESR_DE 0x00100000 /* Descriptor Error */ +#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ +#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ +#define MALESR_OSE 0x00020000 /* OPB Slave Error */ +#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ +#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ +#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ +#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ +#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ +#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ +/* DCRN_MALIER */ +#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ +#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ +#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ +#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ +#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ +/* DCRN_MALTXEOBISR */ +#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ +#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ + +#ifdef DCRN_OCM0_BASE +#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ +#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ +#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ +#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ +#endif + +#ifdef DCRN_PLB0_BASE +#define DCRN_PLB0_BESR (DCRN_PLB0_BASE + 0x0) +#define DCRN_PLB0_BEAR (DCRN_PLB0_BASE + 0x2) +/* doesn't exist on stb03xxx? */ +#define DCRN_PLB0_ACR (DCRN_PLB0_BASE + 0x3) +#endif + +#ifdef DCRN_PLB1_BASE +#define DCRN_PLB1_BESR (DCRN_PLB1_BASE + 0x0) +#define DCRN_PLB1_BEAR (DCRN_PLB1_BASE + 0x1) +/* doesn't exist on stb03xxx? */ +#define DCRN_PLB1_ACR (DCRN_PLB1_BASE + 0x2) +#endif + +#ifdef DCRN_PLLMR_BASE +#define DCRN_PLLMR (DCRN_PLLMR_BASE + 0x0) /* PL1 Mode */ +#endif + +#ifdef DCRN_POB0_BASE +#define DCRN_POB0_BESR0 (DCRN_POB0_BASE + 0x0) +#define DCRN_POB0_BEAR (DCRN_POB0_BASE + 0x2) +#define DCRN_POB0_BESR1 (DCRN_POB0_BASE + 0x4) +#endif + +#ifdef DCRN_SCCR_BASE +#define DCRN_SCCR (DCRN_SCCR_BASE + 0x0) +#endif + +#ifdef DCRN_SDRAM0_BASE +#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Mem Ctrlr Address */ +#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Mem Ctrlr Data */ +#endif + +#ifdef DCRN_UIC0_BASE +#define DCRN_UIC0_SR (DCRN_UIC0_BASE + 0x0) +#define DCRN_UIC0_ER (DCRN_UIC0_BASE + 0x2) +#define DCRN_UIC0_CR (DCRN_UIC0_BASE + 0x3) +#define DCRN_UIC0_PR (DCRN_UIC0_BASE + 0x4) +#define DCRN_UIC0_TR (DCRN_UIC0_BASE + 0x5) +#define DCRN_UIC0_MSR (DCRN_UIC0_BASE + 0x6) +#define DCRN_UIC0_VR (DCRN_UIC0_BASE + 0x7) +#define DCRN_UIC0_VCR (DCRN_UIC0_BASE + 0x8) +#endif + +#ifdef DCRN_UIC1_BASE +#define DCRN_UIC1_SR (DCRN_UIC1_BASE + 0x0) +#define DCRN_UIC1_SRS (DCRN_UIC1_BASE + 0x1) +#define DCRN_UIC1_ER (DCRN_UIC1_BASE + 0x2) +#define DCRN_UIC1_CR (DCRN_UIC1_BASE + 0x3) +#define DCRN_UIC1_PR (DCRN_UIC1_BASE + 0x4) +#define DCRN_UIC1_TR (DCRN_UIC1_BASE + 0x5) +#define DCRN_UIC1_MSR (DCRN_UIC1_BASE + 0x6) +#define DCRN_UIC1_VR (DCRN_UIC1_BASE + 0x7) +#define DCRN_UIC1_VCR (DCRN_UIC1_BASE + 0x8) +#endif + +#ifdef DCRN_SDRAM0_BASE +#define DCRN_SDRAM0_CFGADDR (DCRN_SDRAM0_BASE + 0x0) /* Memory Controller Address */ +#define DCRN_SDRAM0_CFGDATA (DCRN_SDRAM0_BASE + 0x1) /* Memory Controller Data */ +#endif + +#ifdef DCRN_OCM0_BASE +#define DCRN_OCMISARC (DCRN_OCM0_BASE + 0x0) /* OCM Instr Side Addr Range Compare */ +#define DCRN_OCMISCR (DCRN_OCM0_BASE + 0x1) /* OCM Instr Side Control */ +#define DCRN_OCMDSARC (DCRN_OCM0_BASE + 0x2) /* OCM Data Side Addr Range Compare */ +#define DCRN_OCMDSCR (DCRN_OCM0_BASE + 0x3) /* OCM Data Side Control */ +#endif + +#endif /* __ASM_IBM403_H__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ibm4xx.h b/include/asm-ppc/ibm4xx.h new file mode 100644 index 000000000000..587e13328212 --- /dev/null +++ b/include/asm-ppc/ibm4xx.h @@ -0,0 +1,100 @@ +/* + * + * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> + * + * Module name: ibm4xx.h + * + * Description: + * A generic include file which pulls in appropriate include files + * for specific board types based on configuration settings. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASM_IBM4XX_H__ +#define __ASM_IBM4XX_H__ + +#include <linux/config.h> + +#ifdef CONFIG_4xx + +#if defined(CONFIG_ASH) +#include <platforms/ash.h> +#endif + +#if defined (CONFIG_CEDER) +#include <platforms/ceder.h> +#endif + +#if defined(CONFIG_CPCI405) +#include <platforms/cpci405.h> +#endif + +#if defined(CONFIG_EP405) +#include <platforms/ep405.h> +#endif + +#if defined(CONFIG_OAK) +#include <platforms/oak.h> +#endif + +#if defined(CONFIG_REDWOOD_4) +#include <platforms/redwood.h> +#endif + +#if defined(CONFIG_REDWOOD_5) +#include <platforms/redwood5.h> +#endif + +#if defined(CONFIG_WALNUT) +#include <platforms/walnut.h> +#endif + +#ifndef PPC4xx_MACHINE_NAME +#define PPC4xx_MACHINE_NAME "Unidentified 4xx class" +#endif + +#ifndef NR_BOARD_IRQS +#define NR_BOARD_IRQS 0 +#endif + +/* IO_BASE is for PCI I/O. + * ISA not supported, just here to resolve copilation. + */ + +#ifndef _IO_BASE +#define _IO_BASE 0xe8000000 /* The PCI address window */ +#define _ISA_MEM_BASE 0 +#define PCI_DRAM_OFFSET 0 +#endif + +/* + * The "residual" board information structure the boot loader passes + * into the kernel. + */ +#ifndef __ASSEMBLY__ +extern unsigned char __res[]; + +/* Device Control Registers */ + +#define stringify(s) tostring(s) +#define tostring(s) #s + +#define mfdcr(rn) mfdcr_or_dflt(rn, 0) + +#define mfdcr_or_dflt(rn,default_rval) \ + ({unsigned int rval; \ + if (rn == 0) \ + rval = default_rval; \ + else \ + asm volatile("mfdcr %0," stringify(rn) : "=r" (rval)); \ + rval;}) + +#define mtdcr(rn, v) \ + {if (rn != 0) \ + asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v));} + +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_4xx */ +#endif /* __ASM_IBM4XX_H__ */ +#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ide.h b/include/asm-ppc/ide.h index 4906bffc816d..6b0daa2d0d99 100644 --- a/include/asm-ppc/ide.h +++ b/include/asm-ppc/ide.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.ide.h 1.16 09/28/01 07:54:24 trini + * BK Id: %F% %I% %G% %U% %#% */ /* * linux/include/asm-ppc/ide.h @@ -73,10 +73,29 @@ static __inline__ ide_ioreg_t ide_default_io_base(int index) return 0; } +/* + * This is only used for PC-style IDE controllers (e.g. as on PReP) + * or for PCI IDE devices, not for other types of IDE interface such + * as the pmac IDE interfaces. + */ static __inline__ void ide_init_hwif_ports(hw_regs_t *hw, ide_ioreg_t data_port, ide_ioreg_t ctrl_port, int *irq) { + ide_ioreg_t reg = data_port; + int i; + + for (i = IDE_DATA_OFFSET; i <= IDE_STATUS_OFFSET; i++) + hw->io_ports[i] = reg++; + if (ctrl_port) { + hw->io_ports[IDE_CONTROL_OFFSET] = ctrl_port; + } else { + hw->io_ports[IDE_CONTROL_OFFSET] = + hw->io_ports[IDE_DATA_OFFSET] + 0x206; + } + if (irq != NULL) + *irq = 0; + hw->io_ports[IDE_IRQ_OFFSET] = 0; if (ppc_ide_md.ide_init_hwif != NULL) ppc_ide_md.ide_init_hwif(hw, data_port, ctrl_port, irq); } diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index a5cba1f1bb99..5df8a80aa626 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -1,12 +1,14 @@ /* - * BK Id: SCCS/s.io.h 1.14 10/16/01 15:58:42 trini + * BK Id: %F% %I% %G% %U% %#% */ + #ifdef __KERNEL__ #ifndef _PPC_IO_H #define _PPC_IO_H #include <linux/config.h> #include <linux/types.h> + #include <asm/page.h> #include <asm/byteorder.h> @@ -25,24 +27,40 @@ #define PREP_PCI_DRAM_OFFSET 0x80000000 #if defined(CONFIG_4xx) -#include <asm/ppc4xx.h> +#include <asm/ibm4xx.h> #elif defined(CONFIG_8xx) #include <asm/mpc8xx.h> #elif defined(CONFIG_8260) #include <asm/mpc8260.h> #elif defined(CONFIG_APUS) -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 +#define _IO_BASE 0 +#define _ISA_MEM_BASE 0 #define PCI_DRAM_OFFSET 0 #else /* Everyone else */ -extern unsigned long isa_io_base; -extern unsigned long isa_mem_base; -extern unsigned long pci_dram_offset; #define _IO_BASE isa_io_base #define _ISA_MEM_BASE isa_mem_base #define PCI_DRAM_OFFSET pci_dram_offset #endif /* Platform-dependant I/O */ +extern unsigned long isa_io_base; +extern unsigned long isa_mem_base; +extern unsigned long pci_dram_offset; + +#if defined(CONFIG_PPC_ISERIES) +#include <asm/iSeries.h> +#if defined(CONFIG_PCI) + #include <asm/iSeries/iSeries_io.h> + #endif /* defined(CONFIG_PCI) */ +#endif /* CONFIG_PPC_ISERIES */ + +#if defined(CONFIG_PPC_ISERIES) && defined(CONFIG_PCI) +#define readb(addr) iSeries_Readb((u32*)(addr)) +#define readw(addr) iSeries_Readw((u32*)(addr)) +#define readl(addr) iSeries_Readl((u32*)(addr)) +#define writeb(data, addr) iSeries_Writeb(data,(u32*)(addr)) +#define writew(data, addr) iSeries_Writew(data,(u32*)(addr)) +#define writel(data, addr) iSeries_Writel(data,(u32*)(addr)) +#else #define readb(addr) in_8((volatile u8 *)(addr)) #define writeb(b,addr) out_8((volatile u8 *)(addr), (b)) #if defined(CONFIG_APUS) @@ -56,6 +74,7 @@ extern unsigned long pci_dram_offset; #define writew(b,addr) out_le16((volatile u16 *)(addr),(b)) #define writel(b,addr) out_le32((volatile u32 *)(addr),(b)) #endif +#endif /* CONFIG_PPC_ISERIES && defined(CONFIG_PCI) */ #define __raw_readb(addr) (*(volatile unsigned char *)(addr)) @@ -80,9 +99,22 @@ extern unsigned long pci_dram_offset; #ifdef CONFIG_ALL_PPC /* - * We have to handle possible machine checks here on powermacs - * and potentially some CHRPs -- paulus. + * On powermacs, we will get a machine check exception if we + * try to read data from a non-existent I/O port. Because the + * machine check is an asynchronous exception, it isn't + * well-defined which instruction SRR0 will point to when the + * exception occurs. + * With the sequence below (twi; isync; nop), we have found that + * the machine check occurs on one of the three instructions on + * all PPC implementations tested so far. The twi and isync are + * needed on the 601 (in fact twi; sync works too), the isync and + * nop are needed on 604[e|r], and any of twi, sync or isync will + * work on 603[e], 750, 74x0. + * The twi creates an explicit data dependency on the returned + * value which seems to be needed to make the 601 wait for the + * load to finish. */ + #define __do_in_asm(name, op) \ extern __inline__ unsigned int name(unsigned int port) \ { \ @@ -137,6 +169,14 @@ __do_out_asm(outl, "stwbrx") #define inl(port) in_be32((u32 *)((port)+_IO_BASE)) #define outl(val, port) out_be32((u32 *)((port)+_IO_BASE), (val)) +#elif defined(CONFIG_PPC_ISERIES) && defined(CONFIG_PCI) +#define inb(addr) iSeries_Readb((u32*)(addr)) +#define inw(addr) iSeries_Readw((u32*)(addr)) +#define inl(addr) iSeries_Readl((u32*)(addr)) +#define outb(data,addr) iSeries_Writeb(data,(u32*)(addr)) +#define outw(data,addr) iSeries_Writew(data,(u32*)(addr)) +#define outl(data,addr) iSeries_Writel(data,(u32*)(addr)) + #else /* not APUS or ALL_PPC */ #define inb(port) in_8((u8 *)((port)+_IO_BASE)) #define outb(val, port) out_8((u8 *)((port)+_IO_BASE), (val)) @@ -178,8 +218,13 @@ extern void _outsl_ns(volatile u32 *port, const void *buf, int nl); #define IO_SPACE_LIMIT ~0 #define memset_io(a,b,c) memset((void *)(a),(b),(c)) +#ifdef CONFIG_PPC_ISERIES +#define memcpy_fromio(a,b,c) iSeries_memcpy_fromio((void *)(a), (void *)(b), (c)) +#define memcpy_toio(a,b,c) iSeries_memcpy_toio((void *)(a), (void *)(b), (c)) +#else #define memcpy_fromio(a,b,c) memcpy((a),(void *)(b),(c)) #define memcpy_toio(a,b,c) memcpy((void *)(a),(b),(c)) +#endif #ifdef __KERNEL__ /* @@ -265,7 +310,7 @@ extern inline void eieio(void) __asm__ __volatile__ ("eieio" : : : "memory"); } -/* Enforce in-order execution of data I/O. +/* Enforce in-order execution of data I/O. * No distinction between read/write on PPC; use eieio for all three. */ #define iobarrier_rw() eieio() diff --git a/include/asm-ppc/irq.h b/include/asm-ppc/irq.h index fdfc96e8aa0d..bfff1e29f847 100644 --- a/include/asm-ppc/irq.h +++ b/include/asm-ppc/irq.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.irq.h 1.9 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _ASM_IRQ_H @@ -14,7 +14,7 @@ extern void disable_irq_nosync(unsigned int); extern void enable_irq(unsigned int); #if defined(CONFIG_4xx) - +#include <asm/ibm4xx.h> /* * The PowerPC 403 cores' Asynchronous Interrupt Controller (AIC) has * 32 possible interrupts, a majority of which are not implemented on @@ -29,23 +29,19 @@ extern void enable_irq(unsigned int); * */ -#define NR_IRQS 32 +#define NR_AIC_IRQS 32 +#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) -#define AIC_INT0 (0) -#define AIC_INT4 (4) -#define AIC_INT5 (5) -#define AIC_INT6 (6) -#define AIC_INT7 (7) -#define AIC_INT8 (8) -#define AIC_INT9 (9) -#define AIC_INT10 (10) -#define AIC_INT11 (11) -#define AIC_INT27 (27) -#define AIC_INT28 (28) -#define AIC_INT29 (29) -#define AIC_INT30 (30) -#define AIC_INT31 (31) +static __inline__ int +irq_cannonicalize(int irq) +{ + return (irq); +} +#elif defined (CONFIG_NP405) + +#define NR_AIC_IRQS 32 +#define NR_IRQS (NR_AIC_IRQS + NR_BOARD_IRQS) static __inline__ int irq_cannonicalize(int irq) @@ -124,48 +120,6 @@ static __inline__ int irq_cannonicalize(int irq) } #else /* CONFIG_4xx + CONFIG_8xx */ - -#if defined(CONFIG_APUS) -/* - * This structure is used to chain together the ISRs for a particular - * interrupt source (if it supports chaining). - */ -typedef struct irq_node { - void (*handler)(int, void *, struct pt_regs *); - unsigned long flags; - void *dev_id; - const char *devname; - struct irq_node *next; -} irq_node_t; - -/* - * This structure has only 4 elements for speed reasons - */ -typedef struct irq_handler { - void (*handler)(int, void *, struct pt_regs *); - unsigned long flags; - void *dev_id; - const char *devname; -} irq_handler_t; - -/* count of spurious interrupts */ -extern volatile unsigned int num_spurious; - -extern int sys_request_irq(unsigned int, - void (*)(int, void *, struct pt_regs *), - unsigned long, const char *, void *); -extern void sys_free_irq(unsigned int, void *); - -/* - * This function returns a new irq_node_t - */ -extern irq_node_t *new_irq_node(void); - -/* Number of m68k interrupts */ -#define SYS_IRQS 8 - -#endif /* CONFIG_APUS */ - /* * this is the # irq's for all ppc arch's (pmac/chrp/prep) * so it is the max of them all @@ -211,19 +165,14 @@ extern irq_node_t *new_irq_node(void); static __inline__ int irq_cannonicalize(int irq) { if (ppc_md.irq_cannonicalize) - { return ppc_md.irq_cannonicalize(irq); - } - else - { - return irq; - } + return irq; } #endif #define NR_MASK_WORDS ((NR_IRQS + 31) / 32) -/* pendatic: these are long because they are used with set_bit --RR */ +/* pedantic: these are long because they are used with set_bit --RR */ extern unsigned long ppc_cached_irq_mask[NR_MASK_WORDS]; extern unsigned long ppc_lost_interrupts[NR_MASK_WORDS]; extern atomic_t ppc_n_lost_interrupts; diff --git a/include/asm-ppc/ivms8.h b/include/asm-ppc/ivms8.h deleted file mode 100644 index 37c48cbc1c38..000000000000 --- a/include/asm-ppc/ivms8.h +++ /dev/null @@ -1,59 +0,0 @@ -/* - * BK Id: SCCS/s.ivms8.h 1.8 10/26/01 10:14:09 trini - */ -/* - * Speech Design Integrated Voicemail board specific definitions - * - IVMS8 (small, 8 channels) - * - IVML24 (large, 24 channels) - * - * In 2.5 when we force a new bootloader, we can merge these two, and add - * in _MACH_'s for them. -- Tom - * - * Copyright (c) 2000, 2001 Wolfgang Denk (wd@denx.de) - */ - -#ifdef __KERNEL__ -#ifndef __ASM_IVMS8_H__ -#define __ASM_IVMS8_H__ - -#include <linux/config.h> - -#include <asm/ppcboot.h> - -#define IVMS_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ -#define IVMS_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR IVMS_IMMR_BASE /* phys. base address of IMMR area */ -#define IMAP_SIZE IVMS_IMAP_SIZE /* mapped size of IMMR area */ - -#define PCMCIA_MEM_ADDR ((uint)0xFE100000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define FEC_INTERRUPT 9 /* = SIU_LEVEL4 */ -#define IDE0_INTERRUPT 10 /* = IRQ5 */ -#define CPM_INTERRUPT 11 /* = SIU_LEVEL5 (was: SIU_LEVEL2) */ -#define PHY_INTERRUPT 12 /* = IRQ6 */ - -/* override the default number of IDE hardware interfaces */ -#define MAX_HWIFS 1 - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */ -#define IDE0_DATA_REG_OFFSET 0x0000 -#define IDE0_ERROR_REG_OFFSET 0x0081 -#define IDE0_NSECTOR_REG_OFFSET 0x0082 -#define IDE0_SECTOR_REG_OFFSET 0x0083 -#define IDE0_LCYL_REG_OFFSET 0x0084 -#define IDE0_HCYL_REG_OFFSET 0x0085 -#define IDE0_SELECT_REG_OFFSET 0x0086 -#define IDE0_STATUS_REG_OFFSET 0x0087 -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -/* We don't use the 8259. */ -#define NR_8259_INTS 0 - -#endif /* __ASM_IVMS8_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/keyboard.h b/include/asm-ppc/keyboard.h index d8e414c84cb3..4d6b0aab4ddb 100644 --- a/include/asm-ppc/keyboard.h +++ b/include/asm-ppc/keyboard.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.keyboard.h 1.11 08/29/01 10:07:29 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * linux/include/asm-ppc/keyboard.h @@ -13,8 +13,8 @@ * like the intel pc for prep systems, different for power macs. */ -#ifndef __ASMPPC_KEYBOARD_H -#define __ASMPPC_KEYBOARD_H +#ifndef __ASM_KEYBOARD_H__ +#define __ASM_KEYBOARD_H__ #ifdef __KERNEL__ @@ -25,8 +25,14 @@ #include <linux/ioport.h> #include <linux/kd.h> #include <asm/io.h> +/* IBM Spruce platform is different. */ +#ifdef CONFIG_SPRUCE +#include <platforms/spruce.h> +#endif +#ifndef KEYBOARD_IRQ #define KEYBOARD_IRQ 1 +#endif #define DISABLE_KBD_DURING_INTERRUPTS 0 #define INIT_KBD @@ -85,10 +91,12 @@ extern unsigned long SYSRQ_KEY; "keyboard", NULL) /* How to access the keyboard macros on this platform. */ +#ifndef kbd_read_input #define kbd_read_input() inb(KBD_DATA_REG) #define kbd_read_status() inb(KBD_STATUS_REG) #define kbd_write_output(val) outb(val, KBD_DATA_REG) #define kbd_write_command(val) outb(val, KBD_CNTL_REG) +#endif /* Some stoneage hardware needs delays after some operations. */ #define kbd_pause() do { } while(0) @@ -97,7 +105,9 @@ extern unsigned long SYSRQ_KEY; * Machine specific bits for the PS/2 driver */ +#ifndef AUX_IRQ #define AUX_IRQ 12 +#endif #define aux_request_irq(hand, dev_id) \ request_irq(AUX_IRQ, hand, SA_SHIRQ, "PS/2 Mouse", dev_id) @@ -105,5 +115,4 @@ extern unsigned long SYSRQ_KEY; #define aux_free_irq(dev_id) free_irq(AUX_IRQ, dev_id) #endif /* __KERNEL__ */ - -#endif /* __ASMPPC_KEYBOARD_H */ +#endif /* __ASM_KEYBOARD_H__ */ diff --git a/include/asm-ppc/keylargo.h b/include/asm-ppc/keylargo.h index c07b525f5a98..a0bd3eb6fcbe 100644 --- a/include/asm-ppc/keylargo.h +++ b/include/asm-ppc/keylargo.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.keylargo.h 1.13 08/19/01 22:23:04 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * keylargo.h: definitions for using the "KeyLargo" I/O controller chip. @@ -27,14 +27,18 @@ #define KEYLARGO_GPIO_EXTINT_CNT 18 #define KEYLARGO_GPIO_0 0x6A #define KEYLARGO_GPIO_CNT 17 +#define KEYLARGO_GPIO_EXTINT_DUAL_EDGE 0x80 #define KEYLARGO_GPIO_OUTPUT_ENABLE 0x04 #define KEYLARGO_GPIO_OUTOUT_DATA 0x01 +#define KEYLARGO_GPIO_INPUT_DATA 0x02 /* Specific GPIO regs */ -#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03) /* Pangea */ +#define KL_GPIO_MODEM_RESET (KEYLARGO_GPIO_0+0x03) #define KL_GPIO_MODEM_POWER (KEYLARGO_GPIO_0+0x02) /* Pangea */ +#define KL_GPIO_SOUND_POWER (KEYLARGO_GPIO_0+0x05) + /* Hrm... this one is only to be used on Pismo. It seeem to also * control the timebase enable on other machines. Still to be * experimented... --BenH. @@ -54,7 +58,9 @@ #define KL_GPIO_RESET_CPU3 (KEYLARGO_GPIO_EXTINT_0+0x10) #define KL_GPIO_PMU_MESSAGE_IRQ (KEYLARGO_GPIO_EXTINT_0+0x09) -#define KL_GPIO_PMU_MESSAGE_BIT 0x02 +#define KL_GPIO_PMU_MESSAGE_BIT KEYLARGO_GPIO_INPUT_DATA + +#define KL_GPIO_MEDIABAY_IRQ (KEYLARGO_GPIO_EXTINT_0+0x0e) #define KL_GPIO_AIRPORT_0 (KEYLARGO_GPIO_EXTINT_0+0x0a) #define KL_GPIO_AIRPORT_1 (KEYLARGO_GPIO_EXTINT_0+0x0d) @@ -65,43 +71,47 @@ /* * Bits in feature control register */ -#define KL_MBCR_MB0_DEV_ENABLE 0x00001000 +#define KL_MBCR_MB0_PCI_ENABLE 0x00000800 /* exist ? */ +#define KL_MBCR_MB0_IDE_ENABLE 0x00001000 +#define KL_MBCR_MB0_FLOPPY_ENABLE 0x00002000 /* exist ? */ +#define KL_MBCR_MB0_SOUND_ENABLE 0x00004000 /* hrm... */ +#define KL_MBCR_MB0_DEV_MASK 0x00007800 #define KL_MBCR_MB0_DEV_POWER 0x00000400 #define KL_MBCR_MB0_DEV_RESET 0x00000200 #define KL_MBCR_MB0_ENABLE 0x00000100 -#define KL_MBCR_MB1_DEV_ENABLE 0x10000000 +#define KL_MBCR_MB1_PCI_ENABLE 0x08000000 /* exist ? */ +#define KL_MBCR_MB1_IDE_ENABLE 0x10000000 +#define KL_MBCR_MB1_FLOPPY_ENABLE 0x20000000 /* exist ? */ +#define KL_MBCR_MB1_SOUND_ENABLE 0x40000000 /* hrm... */ +#define KL_MBCR_MB1_DEV_MASK 0x78000000 #define KL_MBCR_MB1_DEV_POWER 0x04000000 #define KL_MBCR_MB1_DEV_RESET 0x02000000 #define KL_MBCR_MB1_ENABLE 0x01000000 -#define KL0_SCC_B_INTF_ENABLE 0x00000001 /* ??? */ -#define KL0_SCC_A_INTF_ENABLE 0x00000002 /* ??? */ +#define KL0_SCC_B_INTF_ENABLE 0x00000001 +#define KL0_SCC_A_INTF_ENABLE 0x00000002 #define KL0_SCC_SLOWPCLK 0x00000004 #define KL0_SCC_RESET 0x00000008 #define KL0_SCCA_ENABLE 0x00000010 #define KL0_SCCB_ENABLE 0x00000020 #define KL0_SCC_CELL_ENABLE 0x00000040 +#define KL0_IRDA_HIGH_BAND 0x00000100 +#define KL0_IRDA_SOURCE2_SEL 0x00000200 +#define KL0_IRDA_SOURCE1_SEL 0x00000400 +#define KL0_IRDA_RESET 0x00000800 +#define KL0_IRDA_DEFAULT1 0x00001000 +#define KL0_IRDA_DEFAULT0 0x00002000 +#define KL0_IRDA_FAST_CONNECT 0x00004000 +#define KL0_IRDA_ENABLE 0x00008000 +#define KL0_IRDA_CLK32_ENABLE 0x00010000 +#define KL0_IRDA_CLK19_ENABLE 0x00020000 #define KL0_USB0_PAD_SUSPEND0 0x00040000 #define KL0_USB0_PAD_SUSPEND1 0x00080000 #define KL0_USB0_CELL_ENABLE 0x00100000 #define KL0_USB1_PAD_SUSPEND0 0x00400000 #define KL0_USB1_PAD_SUSPEND1 0x00800000 #define KL0_USB1_CELL_ENABLE 0x01000000 -/* KL id 0x22 only */ #define KL0_USB_REF_SUSPEND 0x10000000 -#define KL0_IRDA_ENABLE 0x00008000 -#define KL0_IRDA_CLK32_ENABLE 0x00010000 -#define KL0_IRDA_CLK19_ENABLE 0x00020000 -/* KL id 0x25 (pangea) only */ -#define KL0_USB1_PAD_SUSPEND_SEL 0x00020000 -#define KL0_USB1_REF_SUSPEND 0x00010000 -#define KL0_USB1_REF_SUSPEND_SEL 0x00008000 -#define KL0_USB1_PMI 0x00004000 -#define KL0_USB0_PAD_SUSPEND_SEL 0x00002000 -#define KL0_USB0_REF_SUSPEND 0x00001000 -#define KL0_USB0_REF_SUSPEND_SEL 0x00000800 -#define KL0_USB0_PMI 0x00000400 - #define KL0_SERIAL_ENABLE (KL0_SCC_B_INTF_ENABLE | \ KL0_SCC_SLOWPCLK | \ @@ -128,8 +138,9 @@ #define KL2_IOBUS_ENABLE 0x00000002 #define KL2_SLEEP_STATE_BIT 0x00000100 #define KL2_MPIC_ENABLE 0x00020000 -#define KL2_MODEM_POWER_N 0x02000000 -#define KL2_AIRPORT_RESET_N 0x08000000 /* Or power ? */ +#define KL2_ALT_DATA_OUT 0x02000000 +#define KL2_MEM_IS_BIG 0x04000000 +#define KL2_CARDSEL_16 0x08000000 #define KL3_SHUTDOWN_PLL_TOTAL 0x00000001 #define KL3_SHUTDOWN_PLLKW6 0x00000002 @@ -149,11 +160,11 @@ #define KL3_STOPPING33_ENABLED 0x00080000 /* Port 0,1 : bus 0, port 2,3 : bus 1 */ -#define KL4_SET_PORT_ENABLE(p) (0x00000008 << ((p)<<3)) -#define KL4_SET_PORT_RESUME(p) (0x00000004 << ((p)<<3)) -#define KL4_SET_PORT_CONNECT(p) (0x00000002 << ((p)<<3)) -#define KL4_SET_PORT_DISCONNECT(p) (0x00000001 << ((p)<<3)) -#define KL4_GET_PORT_RESUME(p) (0x00000040 << ((p)<<3)) -#define KL4_GET_PORT_CONNECT(p) (0x00000020 << ((p)<<3)) -#define KL4_GET_PORT_DISCONNECT(p) (0x00000010 << ((p)<<3)) +#define KL4_PORT_WAKEUP_ENABLE(p) (0x00000008 << ((p)<<3)) +#define KL4_PORT_RESUME_WAKE_EN(p) (0x00000004 << ((p)<<3)) +#define KL4_PORT_CONNECT_WAKE_EN(p) (0x00000002 << ((p)<<3)) +#define KL4_PORT_DISCONNECT_WAKE_EN(p) (0x00000001 << ((p)<<3)) +#define KL4_PORT_RESUME_STAT(p) (0x00000040 << ((p)<<3)) +#define KL4_PORT_CONNECT_STAT(p) (0x00000020 << ((p)<<3)) +#define KL4_PORT_DISCONNECT_STAT(p) (0x00000010 << ((p)<<3)) diff --git a/include/asm-ppc/kgdb.h b/include/asm-ppc/kgdb.h index 04bb95b621dc..9ac89318acca 100644 --- a/include/asm-ppc/kgdb.h +++ b/include/asm-ppc/kgdb.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.kgdb.h 1.5 05/17/01 18:14:24 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * kgdb.h: Defines and declarations for serial line source level @@ -38,8 +38,6 @@ int kgdb_sstep(struct pt_regs *regs); void kgdb(struct pt_regs *regs); int kgdb_iabr_match(struct pt_regs *regs); int kgdb_dabr_match(struct pt_regs *regs); -static void kgdb_fault_handler(struct pt_regs *regs); -static void handle_exception (struct pt_regs *regs); /* * external low-level support routines (ie macserial.c) diff --git a/include/asm-ppc/machdep.h b/include/asm-ppc/machdep.h index 184e7cc8d1af..6dd6a1ee526f 100644 --- a/include/asm-ppc/machdep.h +++ b/include/asm-ppc/machdep.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.machdep.h 1.25 11/13/01 21:26:07 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _PPC_MACHDEP_H @@ -16,6 +16,11 @@ struct pci_bus; struct pci_dev; struct seq_file; +/* We export this macro for external modules like Alsa to know if + * ppc_md.feature_call is implemented or not + */ +#define CONFIG_PPC_HAS_FEATURE_CALLS + struct machdep_calls { void (*setup_arch)(void); /* Optional, may be NULL. */ @@ -95,6 +100,12 @@ struct machdep_calls { /* this is for modules, since _machine can be a define -- Cort */ int ppc_machine; + /* Motherboard/chipset features. This is a kind of general purpose + * hook used to control some machine specific features (like reset + * lines, chip power control, etc...). + */ + int (*feature_call)(unsigned int feature, ...); + #ifdef CONFIG_SMP /* functions for dealing with other cpus */ struct smp_ops_t *smp_ops; diff --git a/include/asm-ppc/mbx.h b/include/asm-ppc/mbx.h deleted file mode 100644 index e4896dd357f3..000000000000 --- a/include/asm-ppc/mbx.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * BK Id: SCCS/s.mbx.h 1.11 08/17/01 15:23:17 paulus - */ -/* - * A collection of structures, addresses, and values associated with - * the Motorola MBX boards. This was originally created for the - * MBX860, and probably needs revisions for other boards (like the 821). - * When this file gets out of control, we can split it up into more - * meaningful pieces. - * - * Copyright (c) 1997 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __MACH_MBX_DEFS -#define __MACH_MBX_DEFS - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * EPPC-Bug starts it up. - */ -typedef struct bd_info { - unsigned int bi_tag; /* Should be 0x42444944 "BDID" */ - unsigned int bi_size; /* Size of this structure */ - unsigned int bi_revision; /* revision of this structure */ - unsigned int bi_bdate; /* EPPCbug date, i.e. 0x11061997 */ - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned int bi_clun; /* Boot device controller */ - unsigned int bi_dlun; /* Boot device logical dev */ - - /* These fields are not part of the board information structure - * provided by the boot rom. They are filled in by embed_config.c - * so we have the information consistent with other platforms. - */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -/* Memory map for the MBX as configured by EPPC-Bug. We could reprogram - * The SIU and PCI bridge, and try to use larger MMU pages, but the - * performance gain is not measureable and it certainly complicates the - * generic MMU model. - * - * In a effort to minimize memory usage for embedded applications, any - * PCI driver or ISA driver must request or map the region required by - * the device. For convenience (and since we can map up to 4 Mbytes with - * a single page table page), the MMU initialization will map the - * NVRAM, Status/Control registers, CPM Dual Port RAM, and the PCI - * Bridge CSRs 1:1 into the kernel address space. - */ -#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) -#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) -#define PCI_IDE_ADDR ((unsigned)0x81000000) -#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) -#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0xe0000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024 * 1024)) -#define PCMCIA_DMA_ADDR ((uint)0xe4000000) -#define PCMCIA_DMA_SIZE ((uint)(64 * 1024 * 1024)) -#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000) -#define PCMCIA_ATTRB_SIZE ((uint)(64 * 1024 * 1024)) -#define PCMCIA_IO_ADDR ((uint)0xec000000) -#define PCMCIA_IO_SIZE ((uint)(64 * 1024 * 1024)) -#define NVRAM_ADDR ((uint)0xfa000000) -#define NVRAM_SIZE ((uint)(1 * 1024 * 1024)) -#define MBX_CSR_ADDR ((uint)0xfa100000) -#define MBX_CSR_SIZE ((uint)(1 * 1024 * 1024)) -#define IMAP_ADDR ((uint)0xfa200000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCI_CSR_ADDR ((uint)0xfa210000) -#define PCI_CSR_SIZE ((uint)(64 * 1024)) - -/* Map additional physical space into well known virtual addresses. Due - * to virtual address mapping, these physical addresses are not accessible - * in a 1:1 virtual to physical mapping. - */ -#define ISA_IO_VIRT_ADDR ((uint)0xfa220000) -#define ISA_IO_VIRT_SIZE ((uint)64 * 1024) - -/* Interrupt assignments. - * These are defined (and fixed) by the MBX hardware implementation. - */ -#define POWER_FAIL_INT SIU_IRQ0 /* Power fail */ -#define TEMP_HILO_INT SIU_IRQ1 /* Temperature sensor */ -#define QSPAN_INT SIU_IRQ2 /* PCI Bridge (DMA CTLR?) */ -#define ISA_BRIDGE_INT SIU_IRQ3 /* All those PC things */ -#define COMM_L_INT SIU_IRQ6 /* MBX Comm expansion connector pin */ -#define STOP_ABRT_INT SIU_IRQ7 /* Stop/Abort header pin */ -#endif /* !__ASSEMBLY__ */ - -/* The MBX uses the 8259. -*/ -#define NR_8259_INTS 16 - -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mediabay.h b/include/asm-ppc/mediabay.h index 26e9bd5663be..ee700af0ede3 100644 --- a/include/asm-ppc/mediabay.h +++ b/include/asm-ppc/mediabay.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.mediabay.h 1.5 05/17/01 18:14:25 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * mediabay.h: definitions for using the media bay @@ -12,10 +12,13 @@ #ifdef __KERNEL__ -#define MB_FD 0 /* media bay contains floppy drive */ -#define MB_FD1 1 /* media bay contains floppy drive */ -#define MB_CD 3 /* media bay contains ATA drive such as CD */ -#define MB_NO 7 /* media bay contains nothing */ +#define MB_FD 0 /* media bay contains floppy drive (automatic eject ?) */ +#define MB_FD1 1 /* media bay contains floppy drive (manual eject ?) */ +#define MB_SOUND 2 /* sound device ? */ +#define MB_CD 3 /* media bay contains ATA drive such as CD or ZIP */ +#define MB_PCI 5 /* media bay contains a PCI device */ +#define MB_POWER 6 /* media bay contains a Power device (???) */ +#define MB_NO 7 /* media bay contains nothing */ void media_bay_init(void); int check_media_bay(struct device_node *which_bay, int what); diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index d89f9d16c96c..16d5497aa597 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.mmu.h 1.10 06/28/01 15:50:17 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * PowerPC memory management structures @@ -115,9 +115,6 @@ typedef struct _P601_BAT { P601_BATL batl; /* Lower register */ } P601_BAT; -extern void _tlbie(unsigned long va); /* invalidate a TLB entry */ -extern void _tlbia(void); /* invalidate all TLB entries */ - #endif /* __ASSEMBLY__ */ /* Block size masks */ diff --git a/include/asm-ppc/mmu_context.h b/include/asm-ppc/mmu_context.h index 58b4d6179855..f6628d78af92 100644 --- a/include/asm-ppc/mmu_context.h +++ b/include/asm-ppc/mmu_context.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.mmu_context.h 1.18 09/26/01 16:02:49 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef __PPC_MMU_CONTEXT_H @@ -10,6 +10,25 @@ #include <asm/bitops.h> #include <asm/mmu.h> +#if MAX_RT_PRIO != 128 || MAX_PRIO != 168 +# error update this function. +#endif + +static inline int sched_find_first_bit(unsigned long *b) +{ + if (unlikely(b[0])) + return __ffs(b[0]); + if (unlikely(b[1])) + return __ffs(b[1]) + 32; + if (unlikely(b[2])) + return __ffs(b[2]) + 64; + if (unlikely(b[3])) + return __ffs(b[3]) + 96; + if (b[4]) + return __ffs(b[4]) + 128; + return __ffs(b[5]) + 32 + 128; +} + /* * On 32-bit PowerPC 6xx/7xx/7xxx CPUs, we use a set of 16 VSIDs * (virtual segment identifiers) for each context. Although the diff --git a/include/asm-ppc/mpc10x.h b/include/asm-ppc/mpc10x.h new file mode 100644 index 000000000000..d04367d673a3 --- /dev/null +++ b/include/asm-ppc/mpc10x.h @@ -0,0 +1,166 @@ +/* + * arch/ppc/kernel/mpc10x.h + * + * Common routines for the Motorola SPS MPC106/8240/107 Host bridge/Mem + * ctlr/EPIC/etc. + * + * Author: Mark A. Greer + * mgreer@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ +#ifndef __PPC_KERNEL_MPC10X_H +#define __PPC_KERNEL_MPC10X_H + +#include <linux/pci_ids.h> +#include <asm/pci-bridge.h> + +/* + * The values here don't completely map everything but should work in most + * cases. + * + * MAP A (PReP Map) + * Processor: 0x80000000 - 0x807fffff -> PCI I/O: 0x00000000 - 0x007fffff + * Processor: 0xc0000000 - 0xdfffffff -> PCI MEM: 0x00000000 - 0x1fffffff + * PCI MEM: 0x80000000 -> Processor System Memory: 0x00000000 + * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) + * + * MAP B (CHRP Map) + * Processor: 0xfe000000 - 0xfebfffff -> PCI I/O: 0x00000000 - 0x00bfffff + * Processor: 0x80000000 - 0xbfffffff -> PCI MEM: 0x80000000 - 0xbfffffff + * PCI MEM: 0x00000000 -> Processor System Memory: 0x00000000 + * EUMB mapped to: ioremap_base - 0x00100000 (ioremap_base - 1 MB) + */ + +/* + * Define the vendor/device IDs for the various bridges--should be added to + * <linux/pci_ids.h> + */ +#define MPC10X_BRIDGE_106 ((PCI_DEVICE_ID_MOTOROLA_MPC106 << 16) | \ + PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8240 ((0x0003 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_107 ((0x0004 << 16) | PCI_VENDOR_ID_MOTOROLA) +#define MPC10X_BRIDGE_8245 ((0x0006 << 16) | PCI_VENDOR_ID_MOTOROLA) + +/* Define the type of map to use */ +#define MPC10X_MEM_MAP_A 1 +#define MPC10X_MEM_MAP_B 2 + +/* Map A (PReP Map) Defines */ +#define MPC10X_MAPA_CNFG_ADDR 0x80000cf8 +#define MPC10X_MAPA_CNFG_DATA 0x80000cfc + +#define MPC10X_MAPA_ISA_IO_BASE 0x80000000 +#define MPC10X_MAPA_ISA_MEM_BASE 0xc0000000 +#define MPC10X_MAPA_DRAM_OFFSET 0x80000000 + +#define MPC10X_MAPA_PCI_IO_START 0x00000000 +#define MPC10X_MAPA_PCI_IO_END (0x00800000 - 1) +#define MPC10X_MAPA_PCI_MEM_START 0x00000000 +#define MPC10X_MAPA_PCI_MEM_END (0x20000000 - 1) + +#define MPC10X_MAPA_PCI_MEM_OFFSET (MPC10X_MAPA_ISA_MEM_BASE - \ + MPC10X_MAPA_PCI_MEM_START) + +/* Map B (CHRP Map) Defines */ +#define MPC10X_MAPB_CNFG_ADDR 0xfec00000 +#define MPC10X_MAPB_CNFG_DATA 0xfee00000 + +#define MPC10X_MAPB_ISA_IO_BASE 0xfe000000 +#define MPC10X_MAPB_ISA_MEM_BASE 0x80000000 +#define MPC10X_MAPB_DRAM_OFFSET 0x00000000 + +#define MPC10X_MAPB_PCI_IO_START 0x00000000 +#define MPC10X_MAPB_PCI_IO_END (0x00c00000 - 1) +#define MPC10X_MAPB_PCI_MEM_START 0x80000000 +#define MPC10X_MAPB_PCI_MEM_END (0xc0000000 - 1) + +#define MPC10X_MAPB_PCI_MEM_OFFSET (MPC10X_MAPB_ISA_MEM_BASE - \ + MPC10X_MAPB_PCI_MEM_START) + +/* Set hose members to values appropriate for the mem map used */ +#define MPC10X_SETUP_HOSE(hose, map) { \ + (hose)->pci_mem_offset = MPC10X_MAP##map##_PCI_MEM_OFFSET; \ + (hose)->io_space.start = MPC10X_MAP##map##_PCI_IO_START; \ + (hose)->io_space.end = MPC10X_MAP##map##_PCI_IO_END; \ + (hose)->mem_space.start = MPC10X_MAP##map##_PCI_MEM_START; \ + (hose)->mem_space.end = MPC10X_MAP##map##_PCI_MEM_END; \ + (hose)->io_base_virt = (void *)MPC10X_MAP##map##_ISA_IO_BASE; \ +} + + +/* Miscellaneous Configuration register offsets */ +#define MPC10X_CFG_PIR_REG 0x09 +#define MPC10X_CFG_PIR_HOST_BRIDGE 0x00 +#define MPC10X_CFG_PIR_AGENT 0x01 + +#define MPC10X_CFG_EUMBBAR 0x78 + +#define MPC10X_CFG_PICR1_REG 0xa8 +#define MPC10X_CFG_PICR1_ADDR_MAP_MASK 0x00010000 +#define MPC10X_CFG_PICR1_ADDR_MAP_A 0x00010000 +#define MPC10X_CFG_PICR1_ADDR_MAP_B 0x00000000 +#define MPC10X_CFG_PICR1_ST_GATH_EN 0x00000040 + +#define MPC10X_CFG_MAPB_OPTIONS_REG 0xe0 +#define MPC10X_CFG_MAPB_OPTIONS_CFAE 0x80 /* CPU_FD_ALIAS_EN */ +#define MPC10X_CFG_MAPB_OPTIONS_PFAE 0x40 /* PCI_FD_ALIAS_EN */ +#define MPC10X_CFG_MAPB_OPTIONS_DR 0x20 /* DLL_RESET */ +#define MPC10X_CFG_MAPB_OPTIONS_PCICH 0x80 /* PCI_COMPATIBILITY_HOLE */ +#define MPC10X_CFG_MAPB_OPTIONS_PROCCH 0x40 /* PROC_COMPATIBILITY_HOLE */ + +/* Define offsets for the memory controller registers in the config space */ +#define MPC10X_MCTLR_MEM_START_1 0x80 /* Banks 0-3 */ +#define MPC10X_MCTLR_MEM_START_2 0x84 /* Banks 4-7 */ +#define MPC10X_MCTLR_EXT_MEM_START_1 0x88 /* Banks 0-3 */ +#define MPC10X_MCTLR_EXT_MEM_START_2 0x8c /* Banks 4-7 */ + +#define MPC10X_MCTLR_MEM_END_1 0x90 /* Banks 0-3 */ +#define MPC10X_MCTLR_MEM_END_2i 0x94 /* Banks 4-7 */ +#define MPC10X_MCTLR_EXT_MEM_END_1 0x98 /* Banks 0-3 */ +#define MPC10X_MCTLR_EXT_MEM_END_2 0x9c /* Banks 4-7 */ + +#define MPC10X_MCTLR_MEM_BANK_ENABLES 0xa0 + +/* Define some offset in the EUMB */ +#define MPC10X_EUMB_SIZE 0x00100000 /* Total EUMB size (1MB) */ + +#define MPC10X_EUMB_MU_OFFSET 0x00000000 /* Msg Unit reg offset */ +#define MPC10X_EUMB_MU_SIZE 0x00001000 /* Msg Unit reg size */ +#define MPC10X_EUMB_DMA_OFFSET 0x00001000 /* DMA Unit reg offset */ +#define MPC10X_EUMB_DMA_SIZE 0x00001000 /* DMA Unit reg size */ +#define MPC10X_EUMB_ATU_OFFSET 0x00002000 /* Addr xlate reg offset */ +#define MPC10X_EUMB_ATU_SIZE 0x00001000 /* Addr xlate reg size */ +#define MPC10X_EUMB_I2C_OFFSET 0x00003000 /* I2C Unit reg offset */ +#define MPC10X_EUMB_I2C_SIZE 0x00001000 /* I2C Unit reg size */ +#define MPC10X_EUMB_DUART_OFFSET 0x00004000 /* DUART Unit reg offset (8245) */ +#define MPC10X_EUMB_DUART_SIZE 0x00001000 /* DUART Unit reg size (8245) */ +#define MPC10X_EUMB_EPIC_OFFSET 0x00040000 /* EPIC offset in EUMB */ +#define MPC10X_EUMB_EPIC_SIZE 0x00030000 /* EPIC size */ +#define MPC10X_EUMB_PM_OFFSET 0x000fe000 /* Performance Monitor reg offset (8245) */ +#define MPC10X_EUMB_PM_SIZE 0x00001000 /* Performance Monitor reg size (8245) */ +#define MPC10X_EUMB_WP_OFFSET 0x000ff000 /* Data path diagnostic, watchpoint reg offset */ +#define MPC10X_EUMB_WP_SIZE 0x00001000 /* Data path diagnostic, watchpoint reg size */ + +/* + * Define some recommended places to put the EUMB regs. + * For both maps, recommend putting the EUMB from 0xeff00000 to 0xefffffff. + */ +extern unsigned long ioremap_base; +#define MPC10X_MAPA_EUMB_BASE (ioremap_base - MPC10X_EUMB_SIZE) +#define MPC10X_MAPB_EUMB_BASE MPC10X_MAPA_EUMB_BASE + + +int mpc10x_bridge_init(struct pci_controller *hose, + uint current_map, + uint new_map, + uint phys_eumb_base); +unsigned long mpc10x_get_mem_size(uint mem_map); +int mpc10x_enable_store_gathering(struct pci_controller *hose); + +#endif /* __PPC_KERNEL_MPC10X_H */ diff --git a/include/asm-ppc/mpc8260.h b/include/asm-ppc/mpc8260.h index 17bd1350611a..46e37c8c1cec 100644 --- a/include/asm-ppc/mpc8260.h +++ b/include/asm-ppc/mpc8260.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.mpc8260.h 1.5 05/17/01 18:14:25 cort + * BK Id: %F% %I% %G% %U% %#% */ /* This is the single file included by all MPC8260 build options. @@ -17,7 +17,23 @@ #ifdef CONFIG_8260 #ifdef CONFIG_EST8260 -#include <asm/est8260.h> +#include <platforms/est8260.h> +#endif + +#ifdef CONFIG_SBS8260 +#include <platforms/sbs8260.h> +#endif + +#ifdef CONFIG_RPX6 +#include <platforms/rpxsuper.h> +#endif + +#ifdef CONFIG_WILLOW +#include <platforms/willow.h> +#endif + +#ifdef CONFIG_TQM8260 +#include <platforms/tqm8260.h> #endif /* I don't yet have the ISA or PCI stuff done....no 8260 with @@ -43,5 +59,5 @@ extern int request_8xxirq(unsigned int irq, void *dev_id); #endif /* CONFIG_8260 */ -#endif +#endif /* !__CONFIG_8260_DEFS */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/mpc8xx.h b/include/asm-ppc/mpc8xx.h index 4006d56fb3a0..c0022d65fd10 100644 --- a/include/asm-ppc/mpc8xx.h +++ b/include/asm-ppc/mpc8xx.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.mpc8xx.h 1.15 11/01/01 12:48:53 trini + * BK Id: %F% %I% %G% %U% %#% */ /* This is the single file included by all MPC8xx build options. @@ -17,40 +17,60 @@ #ifdef CONFIG_8xx #ifdef CONFIG_MBX -#include <asm/mbx.h> +#include <platforms/mbx.h> #endif #ifdef CONFIG_FADS -#include <asm/fads.h> +#include <platforms/fads.h> #endif #ifdef CONFIG_RPXLITE -#include <asm/rpxlite.h> +#include <platforms/rpxlite.h> #endif #ifdef CONFIG_BSEIP -#include <asm/bseip.h> +#include <platforms/bseip.h> #endif #ifdef CONFIG_RPXCLASSIC -#include <asm/rpxclassic.h> +#include <platforms/rpxclassic.h> #endif #if defined(CONFIG_TQM8xxL) -#include <asm/tqm8xx.h> +#include <platforms/tqm8xx.h> #endif #if defined(CONFIG_SPD823TS) -#include <asm/spd8xx.h> +#include <platforms/spd8xx.h> #endif #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) -#include <asm/ivms8.h> +#include <platforms/ivms8.h> #endif -/* I need this to get pt_regs....... -*/ -#include <asm/ptrace.h> +#if defined(CONFIG_HERMES_PRO) +#include <platforms/hermes.h> +#endif + +#if defined(CONFIG_IP860) +#include <platforms/ip860.h> +#endif + +#if defined(CONFIG_LWMON) +#include <platforms/lwmon.h> +#endif + +#if defined(CONFIG_PCU_E) +#include <platforms/pcu_e.h> +#endif + +#if defined(CONFIG_CCM) +#include <platforms/ccm.h> +#endif + +#if defined(CONFIG_LANTEC) +#include <platforms/lantec.h> +#endif /* Currently, all 8xx boards that support a processor to PCI/ISA bridge * use the same memory map. @@ -74,15 +94,12 @@ #endif #ifndef __ASSEMBLY__ -extern unsigned long isa_io_base; -extern unsigned long isa_mem_base; -extern unsigned long pci_dram_offset; - /* The "residual" data board information structure the boot loader * hands to us. */ extern unsigned char __res[]; +struct pt_regs; extern int request_8xxirq(unsigned int irq, void (*handler)(int, void *, struct pt_regs *), unsigned long flags, @@ -90,5 +107,5 @@ extern int request_8xxirq(unsigned int irq, void *dev_id); #endif /* !__ASSEMBLY__ */ #endif /* CONFIG_8xx */ -#endif +#endif /* __CONFIG_8xx_DEFS */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/oak.h b/include/asm-ppc/oak.h deleted file mode 100644 index 713978ef2688..000000000000 --- a/include/asm-ppc/oak.h +++ /dev/null @@ -1,65 +0,0 @@ -/* - * BK Id: SCCS/s.oak.h 1.12 10/11/01 13:05:07 trini - */ -/* - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: oak.h - * - * Description: - * Macros, definitions, and data structures specific to the IBM PowerPC - * 403G{A,B,C,CX} "Oak" evaluation board. Anything specific to the pro- - * cessor itself is defined elsewhere. - * - */ - -#ifdef __KERNEL__ -#ifndef __OAK_H__ -#define __OAK_H__ - -#define _IO_BASE 0 -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 - -/* Memory map for the "Oak" evaluation board */ - -#define PPC403SPU_IO_BASE 0x40000000 /* 403 On-chip serial port */ -#define PPC403SPU_IO_SIZE 0x00000008 -#define OAKSERIAL_IO_BASE 0x7E000000 /* NS16550DV serial port */ -#define OAKSERIAL_IO_SIZE 0x00000008 -#define OAKNET_IO_BASE 0xF4000000 /* NS83902AV Ethernet */ -#define OAKNET_IO_SIZE 0x00000040 -#define OAKPROM_IO_BASE 0xFFFE0000 /* AMD 29F010 Flash ROM */ -#define OAKPROM_IO_SIZE 0x00020000 - - -/* Interrupt assignments fixed by the hardware implementation */ - -/* This is annoying kbuild-2.4 problem. -- Tom */ - -#define PPC403SPU_RX_INT 4 /* AIC_INT4 */ -#define PPC403SPU_TX_INT 5 /* AIC_INT5 */ -#define OAKNET_INT 27 /* AIC_INT27 */ -#define OAKSERIAL_INT 28 /* AIC_INT28 */ - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Oak" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Ethernet MAC address */ - unsigned int bi_intfreq; /* Processor speed, in Hz */ - unsigned int bi_busfreq; /* Bus speed, in Hz */ -} bd_t; - -#endif /* !__ASSEMBLY__ */ -#endif /* __OAK_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ohare.h b/include/asm-ppc/ohare.h index 0f3b01ae1163..daf5789c7323 100644 --- a/include/asm-ppc/ohare.h +++ b/include/asm-ppc/ohare.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.ohare.h 1.5 05/17/01 18:14:25 cort + * BK Id: %F% %I% %G% %U% %#% */ /* * ohare.h: definitions for using the "O'Hare" I/O controller chip. @@ -11,7 +11,8 @@ */ /* offset from ohare base for feature control register */ -#define OHARE_FEATURE_REG 0x38 +#define OHARE_MBCR 0x34 +#define OHARE_FCR 0x38 /* * Bits in feature control register. @@ -25,6 +26,7 @@ #define OH_BAY_FLOPPY_ENABLE 0x10 #define OH_IDE0_ENABLE 0x20 #define OH_IDE0_RESET_N 0x40 /* a guess */ +#define OH_BAY_DEV_MASK 0x1c #define OH_BAY_RESET_N 0x80 #define OH_IOBUS_ENABLE 0x100 /* IOBUS seems to be IDE */ #define OH_SCC_ENABLE 0x200 diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h new file mode 100644 index 000000000000..b042d29875a2 --- /dev/null +++ b/include/asm-ppc/open_pic.h @@ -0,0 +1,70 @@ +/* + * BK Id: %F% %I% %G% %U% %#% + */ +/* + * arch/ppc/kernel/open_pic.h -- OpenPIC Interrupt Handling + * + * Copyright (C) 1997 Geert Uytterhoeven + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file COPYING in the main directory of this archive + * for more details. + * + */ + +#ifndef _PPC_KERNEL_OPEN_PIC_H +#define _PPC_KERNEL_OPEN_PIC_H + +#include <linux/config.h> +#include <linux/irq.h> + +#define OPENPIC_SIZE 0x40000 + +/* + * Non-offset'ed vector numbers + */ + +#define OPENPIC_VEC_TIMER 64 /* and up */ +#define OPENPIC_VEC_IPI 72 /* and up */ +#define OPENPIC_VEC_SPURIOUS 127 + +/* OpenPIC IRQ controller structure */ +extern struct hw_interrupt_type open_pic; + +/* OpenPIC IPI controller structure */ +#ifdef CONFIG_SMP +extern struct hw_interrupt_type open_pic_ipi; +#endif /* CONFIG_SMP */ + +extern u_int OpenPIC_NumInitSenses; +extern u_char *OpenPIC_InitSenses; +extern void* OpenPIC_Addr; + +/* Exported functions */ +extern void openpic_set_sources(int first_irq, int num_irqs, void *isr); +extern void openpic_init(int, int, unsigned char *, int); +extern u_int openpic_irq(void); +extern void openpic_eoi(void); +extern void openpic_request_IPIs(void); +extern void do_openpic_setup_cpu(void); +extern int openpic_get_irq(struct pt_regs *regs); +extern void openpic_reset_processor_phys(u_int cpumask); +extern void openpic_setup_ISU(int isu_num, unsigned long addr); +extern void openpic_cause_IPI(u_int ipi, u_int cpumask); +extern void smp_openpic_message_pass(int target, int msg, unsigned long data, + int wait); + +extern inline int openpic_to_irq(int irq) +{ + /* IRQ 0 usually means 'disabled'.. don't mess with it + * exceptions to this (sandpoint maybe?) + * shouldn't use openpic_to_irq + */ + if (irq != 0){ + return irq += NUM_8259_INTERRUPTS; + } else { + return 0; + } +} +/*extern int open_pic_irq_offset;*/ +#endif /* _PPC_KERNEL_OPEN_PIC_H */ diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h index 3da22a960ce0..76456dfdc8d7 100644 --- a/include/asm-ppc/page.h +++ b/include/asm-ppc/page.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.page.h 1.8 08/19/01 20:06:47 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifndef _PPC_PAGE_H #define _PPC_PAGE_H @@ -13,7 +13,11 @@ #include <linux/config.h> /* Be sure to change arch/ppc/Makefile to match */ +#ifdef CONFIG_KERNEL_START_BOOL +#define PAGE_OFFSET CONFIG_KERNEL_START +#else #define PAGE_OFFSET 0xc0000000 +#endif /* CONFIG_KERNEL_START_BOOL */ #define KERNELBASE PAGE_OFFSET #ifndef __ASSEMBLY__ @@ -83,9 +87,20 @@ typedef unsigned long pgprot_t; extern void clear_page(void *page); extern void copy_page(void *to, void *from); -#define clear_user_page(page, vaddr) clear_page(page) -#define copy_user_page(to, from, vaddr) copy_page(to, from) +extern void clear_user_page(void *page, unsigned long vaddr); +extern void copy_user_page(void *to, void *from, unsigned long vaddr); + +extern unsigned long ppc_memstart; +extern unsigned long ppc_memoffset; +#ifndef CONFIG_APUS +#define PPC_MEMSTART 0 +#define PPC_MEMOFFSET PAGE_OFFSET +#else +#define PPC_MEMSTART ppc_memstart +#define PPC_MEMOFFSET ppc_memoffset +#endif +#if defined(CONFIG_APUS) && !defined(MODULE) /* map phys->virtual and virtual->phys for RAM pages */ static inline unsigned long ___pa(unsigned long v) { @@ -113,8 +128,13 @@ static inline void* ___va(unsigned long p) return (void*) v; } -#define __pa(x) ___pa ((unsigned long)(x)) -#define __va(x) ___va ((unsigned long)(x)) +#else +#define ___pa(vaddr) ((vaddr)-PPC_MEMOFFSET) +#define ___va(paddr) ((paddr)+PPC_MEMOFFSET) +#endif + +#define __pa(x) ___pa((unsigned long)(x)) +#define __va(x) ((void *)(___va((unsigned long)(x)))) #define MAP_PAGE_RESERVED (1<<15) #define virt_to_page(kaddr) (mem_map + (((unsigned long)kaddr-PAGE_OFFSET) >> PAGE_SHIFT)) diff --git a/include/asm-ppc/pc_serial.h b/include/asm-ppc/pc_serial.h new file mode 100644 index 000000000000..61020a34f930 --- /dev/null +++ b/include/asm-ppc/pc_serial.h @@ -0,0 +1,129 @@ +/* + * BK Id: %F% %I% %G% %U% %#% + * + * include/asm-ppc/pc_serial.h + * + * This is basically a copy of include/asm-i386/serial.h. + * It is used on platforms which have an ISA bus and thus are likely + * to have PC-style serial ports at the legacy I/O port addresses. + * It also includes the definitions for the fourport, accent, boca + * and hub6 multiport serial cards, although I have never heard of + * anyone using any of those on a PPC platform. -- paulus + */ + +#include <linux/config.h> + +/* + * This assumes you have a 1.8432 MHz clock for your UART. + * + * It'd be nice if someone built a serial card with a 24.576 MHz + * clock, since the 16550A is capable of handling a top speed of 1.5 + * megabits/second; but this requires the faster clock. + */ +#define BASE_BAUD ( 1843200 / 16 ) + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define RS_TABLE_SIZE 64 +#else +#define RS_TABLE_SIZE 4 +#endif + +/* Standard COM flags (except for COM4, because of the 8514 problem) */ +#ifdef CONFIG_SERIAL_DETECT_IRQ +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) +#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) +#else +#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) +#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF +#endif + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define FOURPORT_FLAGS ASYNC_FOURPORT +#define ACCENT_FLAGS 0 +#define BOCA_FLAGS 0 +#define HUB6_FLAGS 0 +#endif + +/* + * The following define the access methods for the HUB6 card. All + * access is through two ports for all 24 possible chips. The card is + * selected through the high 2 bits, the port on that card with the + * "middle" 3 bits, and the register on that port with the bottom + * 3 bits. + * + * While the access port and interrupt is configurable, the default + * port locations are 0x302 for the port control register, and 0x303 + * for the data read/write register. Normally, the interrupt is at irq3 + * but can be anything from 3 to 7 inclusive. Note that using 3 will + * require disabling com2. + */ + +#define C_P(card,port) (((card)<<6|(port)<<3) + 1) + +#define STD_SERIAL_PORT_DEFNS \ + /* UART CLK PORT IRQ FLAGS */ \ + { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ + { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ + { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ + { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ + + +#ifdef CONFIG_SERIAL_MANY_PORTS +#define EXTRA_SERIAL_PORT_DEFNS \ + { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ + { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \ + { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \ + { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \ + { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \ + { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \ + { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \ + { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \ + { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \ + { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \ + { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \ + { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \ + { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \ + { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \ + { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \ + { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \ + { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \ + { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \ + { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \ + { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \ + { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \ + { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \ + { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \ + { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \ + { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \ + { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \ + { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \ + { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */ +#else +#define EXTRA_SERIAL_PORT_DEFNS +#endif + +/* You can have up to four HUB6's in the system, but I've only + * included two cards here for a total of twelve ports. + */ +#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS)) +#define HUB6_SERIAL_PORT_DFNS \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \ + { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */ +#else +#define HUB6_SERIAL_PORT_DFNS +#endif + +#define SERIAL_PORT_DFNS \ + STD_SERIAL_PORT_DEFNS \ + EXTRA_SERIAL_PORT_DEFNS \ + HUB6_SERIAL_PORT_DFNS diff --git a/include/asm-ppc/pci-bridge.h b/include/asm-ppc/pci-bridge.h index 659789948d49..b97852c0a8bc 100644 --- a/include/asm-ppc/pci-bridge.h +++ b/include/asm-ppc/pci-bridge.h @@ -1,10 +1,13 @@ /* - * BK Id: SCCS/s.pci-bridge.h 1.11 05/21/01 01:31:30 cort + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _ASM_PCI_BRIDGE_H #define _ASM_PCI_BRIDGE_H +#include <linux/ioport.h> +#include <linux/pci.h> + struct device_node; struct pci_controller; @@ -16,12 +19,20 @@ extern void *pci_bus_io_base(unsigned int bus); extern unsigned long pci_bus_io_base_phys(unsigned int bus); extern unsigned long pci_bus_mem_base_phys(unsigned int bus); +/* Allocate a new PCI host bridge structure */ +extern struct pci_controller* pcibios_alloc_controller(void); + +/* Helper function for setting up resources */ +extern void pci_init_resource(struct resource *res, unsigned long start, + unsigned long end, int flags, char *name); + /* * PCI <-> OF matching functions */ extern int pci_device_from_OF_node(struct device_node *node, u8* bus, u8* devfn); extern struct device_node* pci_device_to_OF_node(struct pci_dev *); +extern void pci_create_OF_bus_map(void); /* Get the PCI host controller for a bus */ extern struct pci_controller* pci_bus_to_hose(int bus); @@ -46,6 +57,7 @@ struct pci_controller { int first_busno; int last_busno; + int bus_offset; void *io_base_virt; unsigned long io_base_phys; @@ -65,16 +77,64 @@ struct pci_controller { struct resource io_resource; struct resource mem_resources[3]; int mem_resource_count; + + /* Host bridge I/O and Memory space + * Used for BAR placement algorithms + */ + struct resource io_space; + struct resource mem_space; }; /* These are used for config access before all the PCI probing has been done. */ -int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, int where, u8 *val); -int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, int where, u16 *val); -int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, int where, u32 *val); -int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, int where, u8 val); -int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, int where, u16 val); -int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, int where, u32 val); +int early_read_config_byte(struct pci_controller *hose, int bus, int dev_fn, + int where, u8 *val); +int early_read_config_word(struct pci_controller *hose, int bus, int dev_fn, + int where, u16 *val); +int early_read_config_dword(struct pci_controller *hose, int bus, int dev_fn, + int where, u32 *val); +int early_write_config_byte(struct pci_controller *hose, int bus, int dev_fn, + int where, u8 val); +int early_write_config_word(struct pci_controller *hose, int bus, int dev_fn, + int where, u16 val); +int early_write_config_dword(struct pci_controller *hose, int bus, int dev_fn, + int where, u32 val); + +extern void setup_indirect_pci(struct pci_controller* hose, + u32 cfg_addr, u32 cfg_data); +extern void setup_grackle(struct pci_controller *hose); + +extern unsigned char common_swizzle(struct pci_dev *, unsigned char *); + +/* + * The following code swizzles for exactly one bridge. The routine + * common_swizzle below handles multiple bridges. But there are a + * some boards that don't follow the PCI spec's suggestion so we + * break this piece out separately. + */ +static inline unsigned char bridge_swizzle(unsigned char pin, + unsigned char idsel) +{ + return (((pin-1) + idsel) % 4) + 1; +} + +/* + * The following macro is used to lookup irqs in a standard table + * format for those PPC systems that do not already have PCI + * interrupts properly routed. + */ +/* FIXME - double check this */ +#define PCI_IRQ_TABLE_LOOKUP \ +({ long _ctl_ = -1; \ + if (idsel >= min_idsel && idsel <= max_idsel && pin <= irqs_per_slot) \ + _ctl_ = pci_irq_table[idsel - min_idsel][pin-1]; \ + _ctl_; }) + +/* + * Scan the buses below a given PCI host bridge and assign suitable + * resources to all devices found. + */ +extern int pciauto_bus_scan(struct pci_controller *, int); #endif #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/pci.h b/include/asm-ppc/pci.h index 7a28e8bad5ac..532776aa8687 100644 --- a/include/asm-ppc/pci.h +++ b/include/asm-ppc/pci.h @@ -1,10 +1,19 @@ /* - * BK Id: SCCS/s.pci.h 1.16 10/15/01 22:51:33 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifndef __PPC_PCI_H #define __PPC_PCI_H #ifdef __KERNEL__ +#include <linux/types.h> +#include <linux/slab.h> +#include <linux/string.h> +#include <linux/mm.h> +#include <asm/scatterlist.h> +#include <asm/io.h> + +struct pci_dev; + /* Values for the `which' argument to sys_pciconfig_iobase syscall. */ #define IOBASE_BRIDGE_NUMBER 0 #define IOBASE_MEMORY 1 @@ -12,8 +21,13 @@ #define IOBASE_ISA_IO 3 #define IOBASE_ISA_MEM 4 +/* + * Set this to 1 if you want the kernel to re-assign all PCI + * bus numbers + */ +extern int pci_assign_all_busses; -extern int pcibios_assign_all_busses(void); +#define pcibios_assign_all_busses() (pci_assign_all_busses) #define PCIBIOS_MIN_IO 0x1000 #define PCIBIOS_MIN_MEM 0x10000000 @@ -159,7 +173,6 @@ static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg, for (i = 0; i < nents; i++) { if (!sg[i].page) BUG(); - sg[i].dma_address = page_to_bus(sg[i].page) + sg[i].offset; } @@ -251,14 +264,6 @@ pci_dac_dma_sync_single(struct pci_dev *pdev, dma64_addr_t dma_addr, size_t len, /* Nothing to do. */ } -/* These macros should be used after a pci_map_sg call has been done - * to get bus addresses of each of the SG entries and their lengths. - * You should only work with the number of sg entries pci_map_sg - * returns. - */ -#define sg_dma_address(sg) ((sg)->dma_address) -#define sg_dma_len(sg) ((sg)->length) - /* Return the index of the PCI controller for device PDEV. */ extern int pci_controller_num(struct pci_dev *pdev); diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h index 8093049039f4..e92aaf0f0661 100644 --- a/include/asm-ppc/pgtable.h +++ b/include/asm-ppc/pgtable.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.pgtable.h 1.15 09/22/01 11:26:52 trini + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _PPC_PGTABLE_H @@ -14,16 +14,26 @@ #include <asm/mmu.h> #include <asm/page.h> +extern void _tlbie(unsigned long address); +extern void _tlbia(void); + #if defined(CONFIG_4xx) -extern void local_flush_tlb_all(void); -extern void local_flush_tlb_mm(struct mm_struct *mm); -extern void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr); -extern void local_flush_tlb_range(struct vm_area_struct *vma, unsigned long start, - unsigned long end); +#define __tlbia() asm volatile ("tlbia; sync" : : : "memory") + +static inline void local_flush_tlb_all(void) + { __tlbia(); } +static inline void local_flush_tlb_mm(struct mm_struct *mm) + { __tlbia(); } +static inline void local_flush_tlb_page(struct vm_area_struct *vma, + unsigned long vmaddr) + { _tlbie(vmaddr); } +static inline void local_flush_tlb_range(struct mm_struct *mm, + unsigned long start, unsigned long end) + { __tlbia(); } #define update_mmu_cache(vma, addr, pte) do { } while (0) #elif defined(CONFIG_8xx) -#define __tlbia() asm volatile ("tlbia" : : ) +#define __tlbia() asm volatile ("tlbia; sync" : : : "memory") static inline void local_flush_tlb_all(void) { __tlbia(); } @@ -31,8 +41,8 @@ static inline void local_flush_tlb_mm(struct mm_struct *mm) { __tlbia(); } static inline void local_flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) - { __tlbia(); } -static inline void local_flush_tlb_range(struct vm_area_struct *vma, + { _tlbie(vmaddr); } +static inline void local_flush_tlb_range(struct mm_struct *mm, unsigned long start, unsigned long end) { __tlbia(); } #define update_mmu_cache(vma, addr, pte) do { } while (0) @@ -82,13 +92,14 @@ static inline void flush_tlb_pgtables(struct mm_struct *mm, #define flush_cache_mm(mm) do { } while (0) #define flush_cache_range(vma, a, b) do { } while (0) #define flush_cache_page(vma, p) do { } while (0) -#define flush_icache_page(vma, page) do { } while (0) +#define flush_page_to_ram(page) do { } while (0) +extern void flush_icache_user_range(struct vm_area_struct *vma, + struct page *page, unsigned long addr, int len); extern void flush_icache_range(unsigned long, unsigned long); -extern void __flush_page_to_ram(unsigned long page_va); -extern void flush_page_to_ram(struct page *page); - -#define flush_dcache_page(page) do { } while (0) +extern void __flush_dcache_icache(void *page_va); +extern void flush_dcache_page(struct page *page); +extern void flush_icache_page(struct vm_area_struct *vma, struct page *page); extern unsigned long va_to_phys(unsigned long address); extern pte_t *va_to_pte(unsigned long address); @@ -126,6 +137,12 @@ extern unsigned long ioremap_bot, ioremap_base; * that is where it exists in the MD_TWC, and bit 26 for writethrough. * These will get masked from the level 2 descriptor at TLB load time, and * copied to the MD_TWC before it gets loaded. + * Large page sizes added. We currently support two sizes, 4K and 8M. + * This also allows a TLB hander optimization because we can directly + * load the PMD into MD_TWC. The 8M pages are only used for kernel + * mapping of well known areas. The PMD (PGD) entries contain control + * flags in addition to the address, so care must be taken that the + * software no longer assumes these are only pointers. */ /* @@ -196,17 +213,44 @@ extern unsigned long ioremap_bot, ioremap_base; */ #if defined(CONFIG_4xx) + +/* There are several potential gotchas here. The 4xx hardware TLBLO + field looks like this: + + 0 1 2 3 4 ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31 + RPN..................... 0 0 EX WR ZSEL....... W I M G + + Where possible we make the Linux PTE bits match up with this + + - bits 20 and 21 must be cleared, because we use 4k pages (4xx can + support down to 1k pages), this is done in the TLBMiss exception + handler. + - We use only zones 0 (for kernel pages) and 1 (for user pages) + of the 16 available. Bit 24-26 of the TLB are cleared in the TLB + miss handler. Bit 27 is PAGE_USER, thus selecting the correct + zone. + - PRESENT *must* be in the bottom two bits because swap cache + entries use the top 30 bits. Because 4xx doesn't support SMP + anyway, M is irrelevant so we borrow it for PAGE_PRESENT. Bit 30 + is cleared in the TLB miss handler before the TLB entry is loaded. + - All other bits of the PTE are loaded into TLBLO without + modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for + software PTE bits. We actually use use bits 20, 24, 25, 26, and + 30 respectively for the software bits: ACCESSED, DIRTY, RW, EXEC, + PRESENT. +*/ + /* Definitions for 4xx embedded chips. */ #define _PAGE_GUARDED 0x001 /* G: page is guarded from prefetch */ -#define _PAGE_COHERENT 0x002 /* M: enforece memory coherence */ +#define _PAGE_PRESENT 0x002 /* software: PTE contains a translation */ #define _PAGE_NO_CACHE 0x004 /* I: caching is inhibited */ #define _PAGE_WRITETHRU 0x008 /* W: caching is write-through */ #define _PAGE_USER 0x010 /* matches one of the zone permission bits */ -#define _PAGE_EXEC 0x020 /* software: i-cache coherency required */ -#define _PAGE_PRESENT 0x040 /* software: PTE contains a translation */ -#define _PAGE_DIRTY 0x100 /* C: page changed */ -#define _PAGE_RW 0x200 /* Writes permitted */ -#define _PAGE_ACCESSED 0x400 /* R: page referenced */ +#define _PAGE_RW 0x040 /* software: Writes permitted */ +#define _PAGE_DIRTY 0x080 /* software: dirty page */ +#define _PAGE_HWWRITE 0x100 /* hardware: Dirty & RW, set in exception */ +#define _PAGE_HWEXEC 0x200 /* hardware: EX permission */ +#define _PAGE_ACCESSED 0x400 /* software: R: page referenced */ #elif defined(CONFIG_8xx) /* Definitions for 8xx embedded chips. */ @@ -219,14 +263,21 @@ extern unsigned long ioremap_bot, ioremap_base; */ #define _PAGE_EXEC 0x0008 /* software: i-cache coherency required */ #define _PAGE_GUARDED 0x0010 /* software: guarded access */ -#define _PAGE_WRITETHRU 0x0020 /* software: use writethrough cache */ +#define _PAGE_DIRTY 0x0020 /* software: page changed */ #define _PAGE_RW 0x0040 /* software: user write access allowed */ #define _PAGE_ACCESSED 0x0080 /* software: page referenced */ +/* Setting any bits in the nibble with the follow two controls will + * require a TLB exception handler change. It is assumed unused bits + * are always zero. + */ #define _PAGE_HWWRITE 0x0100 /* h/w write enable: never set in Linux PTE */ -#define _PAGE_DIRTY 0x0200 /* software: page changed */ #define _PAGE_USER 0x0800 /* One of the PP bits, the other is USER&~RW */ +#define _PMD_PRESENT 0x0001 +#define _PMD_PAGE_MASK 0x000c +#define _PMD_PAGE_8M 0x000c + #else /* CONFIG_6xx */ /* Definitions for 60x, 740/750, etc. */ #define _PAGE_PRESENT 0x001 /* software: pte contains a translation */ @@ -262,14 +313,11 @@ extern unsigned long ioremap_bot, ioremap_base; #ifndef _PAGE_HWWRITE #define _PAGE_HWWRITE 0 #endif - -/* We can't use _PAGE_HWWRITE on any SMP due to the lack of ability - * to atomically manage _PAGE_HWWRITE and it's coordination flags, - * _PAGE_DIRTY or _PAGE_RW. The SMP systems must manage HWWRITE - * or its logical equivalent in the MMU management software. - */ -#if CONFIG_SMP && _PAGE_HWWRITE -#error "You can't configure SMP and HWWRITE" +#ifndef _PAGE_HWEXEC +#define _PAGE_HWEXEC 0 +#endif +#ifndef _PAGE_EXEC +#define _PAGE_EXEC 0 #endif #define _PAGE_CHG_MASK (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY) @@ -281,9 +329,9 @@ extern unsigned long ioremap_bot, ioremap_base; * another purpose. -- paulus. */ #define _PAGE_BASE _PAGE_PRESENT | _PAGE_ACCESSED -#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY +#define _PAGE_WRENABLE _PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE -#define _PAGE_KERNEL _PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED +#define _PAGE_KERNEL _PAGE_BASE | _PAGE_WRENABLE | _PAGE_SHARED | _PAGE_HWEXEC #define _PAGE_IO _PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED #define PAGE_NONE __pgprot(_PAGE_BASE) @@ -345,7 +393,7 @@ extern unsigned long empty_zero_page[1024]; * Permanent address of a page. */ #define page_address(page) ((page)->virtual) -#define pte_page(x) (mem_map+(unsigned long)((pte_val(x) >> PAGE_SHIFT))) +#define pte_page(x) (mem_map+(unsigned long)((pte_val(x)-PPC_MEMSTART) >> PAGE_SHIFT)) #ifndef __ASSEMBLY__ /* @@ -411,7 +459,7 @@ static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot) #define mk_pte(page,pgprot) \ ({ \ pte_t pte; \ - pte_val(pte) = ((page - mem_map) << PAGE_SHIFT) | pgprot_val(pgprot); \ + pte_val(pte) = (((page - mem_map) << PAGE_SHIFT) + PPC_MEMSTART) | pgprot_val(pgprot); \ pte; \ }) @@ -435,8 +483,9 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr, __asm__ __volatile__("\ 1: lwarx %0,0,%3\n\ andc %1,%0,%4\n\ - or %1,%1,%5\n\ - stwcx. %1,0,%3\n\ + or %1,%1,%5\n" + PPC405_ERR77(0,%3) +" stwcx. %1,0,%3\n\ bne- 1b" : "=&r" (old), "=&r" (tmp), "=m" (*p) : "r" (p), "r" (clr), "r" (set), "m" (*p) @@ -445,10 +494,18 @@ static inline unsigned long pte_update(pte_t *p, unsigned long clr, } /* - * Writing a new value into the PTE doesn't disturb the state of the - * _PAGE_HASHPTE bit, on those machines which use an MMU hash table. + * set_pte stores a linux PTE into the linux page table. + * On machines which use an MMU hash table we avoid changing the + * _PAGE_HASHPTE bit. */ -extern void set_pte(pte_t *ptep, pte_t pte); +static inline void set_pte(pte_t *ptep, pte_t pte) +{ +#if _PAGE_HASHPTE != 0 + pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE); +#else + *ptep = pte; +#endif +} static inline int ptep_test_and_clear_young(pte_t *ptep) { @@ -477,7 +534,7 @@ static inline void ptep_mkdirty(pte_t *ptep) #define pte_same(A,B) (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0) -#define pmd_page(pmd) (pmd_val(pmd)) +#define pmd_page(pmd) (pmd_val(pmd) & PAGE_MASK) /* to find an entry in a kernel page-table-directory */ #define pgd_offset_k(address) pgd_offset(&init_mm, address) diff --git a/include/asm-ppc/pmac_feature.h b/include/asm-ppc/pmac_feature.h new file mode 100644 index 000000000000..3670cde23854 --- /dev/null +++ b/include/asm-ppc/pmac_feature.h @@ -0,0 +1,253 @@ +/* + * Definition of platform feature hooks for PowerMacs + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + * + * Copyright (C) 1998 Paul Mackerras & + * Ben. Herrenschmidt. + * + * + * Note: I removed media-bay details from the feature stuff, I beleive it's + * not worth it, the media-bay driver can directly use the mac-io + * ASIC registers. + * + * Implementation note: Currently, none of these functions will block. + * However, they may internally protect themselves with a spinlock + * for way too long. Be prepared for at least some of these to block + * in the future. + * + * Unless specifically defined, the result code is assumed to be an + * error when negative, 0 is the default success result. Some functions + * may return additional positive result values. + * + * To keep implementation simple, all feature calls are assumed to have + * the prototype parameters (struct device_node* node, int value). + * When either is not used, pass 0. + */ + +#ifdef __KERNEL__ +#ifndef __PPC_ASM_PMAC_FEATURE_H +#define __PPC_ASM_PMAC_FEATURE_H + +/* + * Known Mac motherboard models + * + * Please, report any error here to benh@kernel.crashing.org, thanks ! + */ + +/* PowerSurge are the first generation of PCI Pmacs. This include + * all of the Grand-Central based machines + */ +#define PMAC_TYPE_PSURGE 0x10 /* PowerSurge */ + +/* Here is the infamous serie of OHare based machines + */ +#define PMAC_TYPE_COMET 0x20 /* Beleived to be PowerBook 2400 */ +#define PMAC_TYPE_HOOPER 0x21 /* Beleived to be PowerBook 3400 */ +#define PMAC_TYPE_KANGA 0x22 /* PowerBook 3500 (first G3) */ +#define PMAC_TYPE_ALCHEMY 0x23 /* Alchemy motherboard base */ +#define PMAC_TYPE_GAZELLE 0x24 /* Spartacus, some 5xxx/6xxx */ +#define PMAC_TYPE_UNKNOWN_OHARE 0x2f /* Unknown, but OHare based */ + +/* Here are the Heathrow based machines + * FIXME: Differenciate wallstreet,mainstreet,wallstreetII + */ +#define PMAC_TYPE_GOSSAMER 0x30 /* Gossamer motherboard */ +#define PMAC_TYPE_SILK 0x31 /* Desktop PowerMac G3 */ +#define PMAC_TYPE_WALLSTREET 0x32 /* Wallstreet/Mainstreet PowerBook*/ +#define PMAC_TYPE_UNKNOWN_HEATHROW 0x3f /* Unknown but heathrow based */ + +/* Here are newworld machines based on Paddington (heathrow derivative) + */ +#define PMAC_TYPE_101_PBOOK 0x40 /* 101 PowerBook (aka Lombard) */ +#define PMAC_TYPE_ORIG_IMAC 0x41 /* First generation iMac */ +#define PMAC_TYPE_YOSEMITE 0x42 /* B&W G3 */ +#define PMAC_TYPE_YIKES 0x43 /* Yikes G4 (PCI graphics) */ +#define PMAC_TYPE_UNKNOWN_PADDINGTON 0x4f /* Unknown but paddington based */ + +/* Core99 machines based on UniNorth 1.0 and 1.5 + * + * Note: A single entry here may cover several actual models according + * to the device-tree. (Sawtooth is most tower G4s, FW_IMAC is most + * FireWire based iMacs, etc...). Those machines are too similar to be + * distinguished here, when they need to be differencied, use the + * device-tree "model" or "compatible" property. + */ +#define PMAC_TYPE_ORIG_IBOOK 0x40 /* First iBook model (no firewire) */ +#define PMAC_TYPE_SAWTOOTH 0x41 /* Desktop G4s */ +#define PMAC_TYPE_FW_IMAC 0x42 /* FireWire iMacs (except Pangea based) */ +#define PMAC_TYPE_FW_IBOOK 0x43 /* FireWire iBooks (except iBook2) */ +#define PMAC_TYPE_CUBE 0x44 /* Cube PowerMac */ +#define PMAC_TYPE_QUICKSILVER 0x45 /* QuickSilver G4s */ +#define PMAC_TYPE_PISMO 0x46 /* Pismo PowerBook */ +#define PMAC_TYPE_TITANIUM 0x47 /* Titanium PowerBook */ +#define PMAC_TYPE_TITANIUM2 0x48 /* Titanium II PowerBook */ +#define PMAC_TYPE_UNKNOWN_CORE99 0x5f + +/* MacRISC2 machines based on the Pangea chipset + */ +#define PMAC_TYPE_PANGEA_IMAC 0x100 /* Flower Power iMac */ +#define PMAC_TYPE_IBOOK2 0x101 /* iBook2 (polycarbonate) */ +#define PMAC_TYPE_FLAT_PANEL_IMAC 0x102 /* Flat panel iMac */ +#define PMAC_TYPE_UNKNOWN_PANGEA 0x10f + +/* + * Motherboard flags + */ + +#define PMAC_MB_CAN_SLEEP 0x00000001 +#define PMAC_MB_HAS_FW_POWER 0x00000002 + +/* + * Feature calls supported on pmac + * + */ + +/* + * Use this inline wrapper + */ +struct device_node; + +static inline int pmac_call_feature(int selector, struct device_node* node, + int param, int value) +{ + if (!ppc_md.feature_call) + return -ENODEV; + return ppc_md.feature_call(selector, node, param, value); +} + +/* PMAC_FTR_SERIAL_ENABLE (struct device_node* node, int param, int value) + * enable/disable an SCC side. Pass the node corresponding to the + * channel side as a parameter. + * param is the type of port + * if param is ored with PMAC_SCC_FLAG_XMON, then the SCC is locked enabled + * for use by xmon. + */ +#define PMAC_FTR_SCC_ENABLE PMAC_FTR_DEF(0) + #define PMAC_SCC_ASYNC 0 + #define PMAC_SCC_IRDA 1 + #define PMAC_SCC_I2S1 2 + #define PMAC_SCC_FLAG_XMON 0x00001000 + +/* PMAC_FTR_MODEM_ENABLE (struct device_node* node, 0, int value) + * enable/disable the internal modem. + */ +#define PMAC_FTR_MODEM_ENABLE PMAC_FTR_DEF(1) + +/* PMAC_FTR_SWIM3_ENABLE (struct device_node* node, 0,int value) + * enable/disable the swim3 (floppy) cell of a mac-io ASIC + */ +#define PMAC_FTR_SWIM3_ENABLE PMAC_FTR_DEF(2) + +/* PMAC_FTR_MESH_ENABLE (struct device_node* node, 0, int value) + * enable/disable the mesh (scsi) cell of a mac-io ASIC + */ +#define PMAC_FTR_MESH_ENABLE PMAC_FTR_DEF(3) + +/* PMAC_FTR_IDE_ENABLE (struct device_node* node, int busID, int value) + * enable/disable an IDE port of a mac-io ASIC + * pass the busID parameter + */ +#define PMAC_FTR_IDE_ENABLE PMAC_FTR_DEF(4) + +/* PMAC_FTR_IDE_RESET (struct device_node* node, int busID, int value) + * assert(1)/release(0) an IDE reset line (mac-io IDE only) + */ +#define PMAC_FTR_IDE_RESET PMAC_FTR_DEF(5) + +/* PMAC_FTR_BMAC_ENABLE (struct device_node* node, 0, int value) + * enable/disable the bmac (ethernet) cell of a mac-io ASIC, also drive + * it's reset line + */ +#define PMAC_FTR_BMAC_ENABLE PMAC_FTR_DEF(6) + +/* PMAC_FTR_GMAC_ENABLE (struct device_node* node, 0, int value) + * enable/disable the gmac (ethernet) cell of an uninorth ASIC. This + * control the cell's clock. + */ +#define PMAC_FTR_GMAC_ENABLE PMAC_FTR_DEF(7) + +/* PMAC_FTR_GMAC_PHY_RESET (struct device_node* node, 0, 0) + * Perform a HW reset of the PHY connected to a gmac controller. + * Pass the gmac device node, not the PHY node. + */ +#define PMAC_FTR_GMAC_PHY_RESET PMAC_FTR_DEF(8) + +/* PMAC_FTR_SOUND_CHIP_ENABLE (struct device_node* node, 0, int value) + * enable/disable the sound chip, whatever it is and provided it can + * acually be controlled + */ +#define PMAC_FTR_SOUND_CHIP_ENABLE PMAC_FTR_DEF(9) + +/* -- add various tweaks related to sound routing -- */ + +/* PMAC_FTR_AIRPORT_ENABLE (struct device_node* node, 0, int value) + * enable/disable the airport card + */ +#define PMAC_FTR_AIRPORT_ENABLE PMAC_FTR_DEF(10) + +/* PMAC_FTR_RESET_CPU (NULL, int cpu_nr, 0) + * toggle the reset line of a CPU on an uninorth-based SMP machine + */ +#define PMAC_FTR_RESET_CPU PMAC_FTR_DEF(11) + +/* PMAC_FTR_USB_ENABLE (struct device_node* node, 0, int value) + * enable/disable an USB cell, along with the power of the USB "pad" + * on keylargo based machines + */ +#define PMAC_FTR_USB_ENABLE PMAC_FTR_DEF(12) + +/* PMAC_FTR_1394_ENABLE (struct device_node* node, 0, int value) + * enable/disable the firewire cell of an uninorth ASIC. + */ +#define PMAC_FTR_1394_ENABLE PMAC_FTR_DEF(13) + +/* PMAC_FTR_1394_CABLE_POWER (struct device_node* node, 0, int value) + * enable/disable the firewire cable power supply of the uninorth + * firewire cell + */ +#define PMAC_FTR_1394_CABLE_POWER PMAC_FTR_DEF(14) + +/* PMAC_FTR_SLEEP_STATE (struct device_node* node, 0, int value) + * set the sleep state of the motherboard. + * Pass -1 as value to query for sleep capability + */ +#define PMAC_FTR_SLEEP_STATE PMAC_FTR_DEF(15) + +/* PMAC_FTR_GET_MB_INFO (NULL, selector, 0) + * + * returns some motherboard infos. + * selector: 0 - model id + * 1 - model flags (capabilities) + * 2 - model name (cast to const char *) + */ +#define PMAC_FTR_GET_MB_INFO PMAC_FTR_DEF(16) +#define PMAC_MB_INFO_MODEL 0 +#define PMAC_MB_INFO_FLAGS 1 +#define PMAC_MB_INFO_NAME 2 + +/* PMAC_FTR_READ_GPIO (NULL, int index, 0) + * + * read a GPIO from a mac-io controller of type KeyLargo or Pangea. + * the value returned is a byte (positive), or a negative error code + */ +#define PMAC_FTR_READ_GPIO PMAC_FTR_DEF(17) + +/* PMAC_FTR_WRITE_GPIO (NULL, int index, int value) + * + * write a GPIO of a mac-io controller of type KeyLargo or Pangea. + */ +#define PMAC_FTR_WRITE_GPIO PMAC_FTR_DEF(18) + + +/* Don't use those directly, they are for the sake of pmac_setup.c */ +extern int pmac_do_feature_call(unsigned int selector, ...); +extern void pmac_feature_init(void); +extern void pmac_feature_late_init(void); + +#define PMAC_FTR_DEF(x) ((_MACH_Pmac << 16) | (x)) + +#endif /* __PPC_ASM_PMAC_FEATURE_H */ +#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/posix_types.h b/include/asm-ppc/posix_types.h index 23571b92fb1a..0a44935561ee 100644 --- a/include/asm-ppc/posix_types.h +++ b/include/asm-ppc/posix_types.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.posix_types.h 1.5 05/17/01 18:14:25 cort + * BK Id: %F% %I% %G% %U% %#% */ #ifndef _PPC_POSIX_TYPES_H #define _PPC_POSIX_TYPES_H @@ -11,7 +11,7 @@ */ typedef unsigned int __kernel_dev_t; -typedef unsigned int __kernel_ino_t; +typedef unsigned long __kernel_ino_t; typedef unsigned int __kernel_mode_t; typedef unsigned short __kernel_nlink_t; typedef long __kernel_off_t; diff --git a/include/asm-ppc/ppc405_dma.h b/include/asm-ppc/ppc405_dma.h new file mode 100755 index 000000000000..eabdb2502e4a --- /dev/null +++ b/include/asm-ppc/ppc405_dma.h @@ -0,0 +1,1275 @@ +/* + * + * Copyright 2000 MontaVista Software Inc. + * PPC405 modifications + * Author: MontaVista Software, Inc. + * ppopov@mvista.com or source@mvista.com + * + * + * Module name: ppc405_dma.h + * + * Description: + * Data structures specific to the IBM PowerPC 405 on-chip DMA controller + * and API. + * + */ + +#ifdef __KERNEL__ +#ifndef __ASMPPC_405_DMA_H +#define __ASMPPC_405_DMA_H + +#include <linux/types.h> + +/* #define DEBUG_405DMA */ + +#define TRUE 1 +#define FALSE 0 + +#define SGL_LIST_SIZE 4096 +/* #define PCI_ALLOC_IS_NONCONSISTENT */ + +#define MAX_405GP_DMA_CHANNELS 4 + +/* The maximum address that we can perform a DMA transfer to on this platform */ +/* Doesn't really apply... */ +#define MAX_DMA_ADDRESS 0xFFFFFFFF + +extern unsigned long ISA_DMA_THRESHOLD; + +#define dma_outb outb +#define dma_inb inb + + +/* + * Function return status codes + * These values are used to indicate whether or not the function + * call was successful, or a bad/invalid parameter was passed. + */ +#define DMA_STATUS_GOOD 0 +#define DMA_STATUS_BAD_CHANNEL 1 +#define DMA_STATUS_BAD_HANDLE 2 +#define DMA_STATUS_BAD_MODE 3 +#define DMA_STATUS_NULL_POINTER 4 +#define DMA_STATUS_OUT_OF_MEMORY 5 +#define DMA_STATUS_SGL_LIST_EMPTY 6 +#define DMA_STATUS_GENERAL_ERROR 7 + + +/* + * These indicate status as returned from the DMA Status Register. + */ +#define DMA_STATUS_NO_ERROR 0 +#define DMA_STATUS_CS 1 /* Count Status */ +#define DMA_STATUS_TS 2 /* Transfer Status */ +#define DMA_STATUS_DMA_ERROR 3 /* DMA Error Occurred */ +#define DMA_STATUS_DMA_BUSY 4 /* The channel is busy */ + + +/* + * Transfer Modes + * These modes are defined in a way that makes it possible to + * simply "or" in the value in the control register. + */ +#define DMA_MODE_READ DMA_TD /* Peripheral to Memory */ +#define DMA_MODE_WRITE 0 /* Memory to Peripheral */ +#define DMA_MODE_MM (SET_DMA_TM(TM_S_MM)) /* memory to memory */ + + /* Device-paced memory to memory, */ + /* device is at source address */ +#define DMA_MODE_MM_DEVATSRC (DMA_TD | SET_DMA_TM(TM_D_MM)) + + /* Device-paced memory to memory, */ + /* device is at destination address */ +#define DMA_MODE_MM_DEVATDST (SET_DMA_TM(TM_D_MM)) + + +/* + * DMA Polarity Configuration Register + */ +#define DMAReq0_ActiveLow (1<<31) +#define DMAAck0_ActiveLow (1<<30) +#define EOT0_ActiveLow (1<<29) /* End of Transfer */ + +#define DMAReq1_ActiveLow (1<<28) +#define DMAAck1_ActiveLow (1<<27) +#define EOT1_ActiveLow (1<<26) + +#define DMAReq2_ActiveLow (1<<25) +#define DMAAck2_ActiveLow (1<<24) +#define EOT2_ActiveLow (1<<23) + +#define DMAReq3_ActiveLow (1<<22) +#define DMAAck3_ActiveLow (1<<21) +#define EOT3_ActiveLow (1<<20) + +/* + * DMA Sleep Mode Register + */ +#define SLEEP_MODE_ENABLE (1<<21) + + +/* + * DMA Status Register + */ +#define DMA_CS0 (1<<31) /* Terminal Count has been reached */ +#define DMA_CS1 (1<<30) +#define DMA_CS2 (1<<29) +#define DMA_CS3 (1<<28) + +#define DMA_TS0 (1<<27) /* End of Transfer has been requested */ +#define DMA_TS1 (1<<26) +#define DMA_TS2 (1<<25) +#define DMA_TS3 (1<<24) + +#define DMA_CH0_ERR (1<<23) /* DMA Chanel 0 Error */ +#define DMA_CH1_ERR (1<<22) +#define DMA_CH2_ERR (1<<21) +#define DMA_CH3_ERR (1<<20) + +#define DMA_IN_DMA_REQ0 (1<<19) /* Internal DMA Request is pending */ +#define DMA_IN_DMA_REQ1 (1<<18) +#define DMA_IN_DMA_REQ2 (1<<17) +#define DMA_IN_DMA_REQ3 (1<<16) + +#define DMA_EXT_DMA_REQ0 (1<<15) /* External DMA Request is pending */ +#define DMA_EXT_DMA_REQ1 (1<<14) +#define DMA_EXT_DMA_REQ2 (1<<13) +#define DMA_EXT_DMA_REQ3 (1<<12) + +#define DMA_CH0_BUSY (1<<11) /* DMA Channel 0 Busy */ +#define DMA_CH1_BUSY (1<<10) +#define DMA_CH2_BUSY (1<<9) +#define DMA_CH3_BUSY (1<<8) + +#define DMA_SG0 (1<<7) /* DMA Channel 0 Scatter/Gather in progress */ +#define DMA_SG1 (1<<6) +#define DMA_SG2 (1<<5) +#define DMA_SG3 (1<<4) + + + +/* + * DMA Channel Control Registers + */ +#define DMA_CH_ENABLE (1<<31) /* DMA Channel Enable */ +#define SET_DMA_CH_ENABLE(x) (((x)&0x1)<<31) +#define GET_DMA_CH_ENABLE(x) (((x)&DMA_CH_ENABLE)>>31) + +#define DMA_CIE_ENABLE (1<<30) /* DMA Channel Interrupt Enable */ +#define SET_DMA_CIE_ENABLE(x) (((x)&0x1)<<30) +#define GET_DMA_CIE_ENABLE(x) (((x)&DMA_CIE_ENABLE)>>30) + +#define DMA_TD (1<<29) +#define SET_DMA_TD(x) (((x)&0x1)<<29) +#define GET_DMA_TD(x) (((x)&DMA_TD)>>29) + +#define DMA_PL (1<<28) /* Peripheral Location */ +#define SET_DMA_PL(x) (((x)&0x1)<<28) +#define GET_DMA_PL(x) (((x)&DMA_PL)>>28) + +#define EXTERNAL_PERIPHERAL 0 +#define INTERNAL_PERIPHERAL 1 + + +#define SET_DMA_PW(x) (((x)&0x3)<<26) /* Peripheral Width */ +#define DMA_PW_MASK SET_DMA_PW(3) +#define PW_8 0 +#define PW_16 1 +#define PW_32 2 +#define PW_64 3 +#define GET_DMA_PW(x) (((x)&DMA_PW_MASK)>>26) + +#define DMA_DAI (1<<25) /* Destination Address Increment */ +#define SET_DMA_DAI(x) (((x)&0x1)<<25) + +#define DMA_SAI (1<<24) /* Source Address Increment */ +#define SET_DMA_SAI(x) (((x)&0x1)<<24) + +#define DMA_BEN (1<<23) /* Buffer Enable */ +#define SET_DMA_BEN(x) (((x)&0x1)<<23) + +#define SET_DMA_TM(x) (((x)&0x3)<<21) /* Transfer Mode */ +#define DMA_TM_MASK SET_DMA_TM(3) +#define TM_PERIPHERAL 0 /* Peripheral */ +#define TM_RESERVED 1 /* Reserved */ +#define TM_S_MM 2 /* Memory to Memory */ +#define TM_D_MM 3 /* Device Paced Memory to Memory */ +#define GET_DMA_TM(x) (((x)&DMA_TM_MASK)>>21) + +#define SET_DMA_PSC(x) (((x)&0x3)<<19) /* Peripheral Setup Cycles */ +#define DMA_PSC_MASK SET_DMA_PSC(3) +#define GET_DMA_PSC(x) (((x)&DMA_PSC_MASK)>>19) + +#define SET_DMA_PWC(x) (((x)&0x3F)<<13) /* Peripheral Wait Cycles */ +#define DMA_PWC_MASK SET_DMA_PWC(0x3F) +#define GET_DMA_PWC(x) (((x)&DMA_PWC_MASK)>>13) + +#define SET_DMA_PHC(x) (((x)&0x7)<<10) /* Peripheral Hold Cycles */ +#define DMA_PHC_MASK SET_DMA_PHC(0x7) +#define GET_DMA_PHC(x) (((x)&DMA_PHC_MASK)>>10) + +#define DMA_ETD_OUTPUT (1<<9) /* EOT pin is a TC output */ +#define SET_DMA_ETD(x) (((x)&0x1)<<9) + +#define DMA_TCE_ENABLE (1<<8) +#define SET_DMA_TCE(x) (((x)&0x1)<<8) + +#define SET_DMA_PRIORITY(x) (((x)&0x3)<<6) /* DMA Channel Priority */ +#define DMA_PRIORITY_MASK SET_DMA_PRIORITY(3) +#define PRIORITY_LOW 0 +#define PRIORITY_MID_LOW 1 +#define PRIORITY_MID_HIGH 2 +#define PRIORITY_HIGH 3 +#define GET_DMA_PRIORITY(x) (((x)&DMA_PRIORITY_MASK)>>6) + +#define SET_DMA_PREFETCH(x) (((x)&0x3)<<4) /* Memory Read Prefetch */ +#define DMA_PREFETCH_MASK SET_DMA_PREFETCH(3) +#define PREFETCH_1 0 /* Prefetch 1 Double Word */ +#define PREFETCH_2 1 +#define PREFETCH_4 2 +#define GET_DMA_PREFETCH(x) (((x)&DMA_PREFETCH_MASK)>>4) + +#define DMA_PCE (1<<3) /* Parity Check Enable */ +#define SET_DMA_PCE(x) (((x)&0x1)<<3) +#define GET_DMA_PCE(x) (((x)&DMA_PCE)>>3) + +#define DMA_DEC (1<<2) /* Address Decrement */ +#define SET_DMA_DEC(x) (((x)&0x1)<<2) +#define GET_DMA_DEC(x) (((x)&DMA_DEC)>>2) + +/* + * DMA SG Command Register + */ +#define SSG0_ENABLE (1<<31) /* Start Scatter Gather */ +#define SSG1_ENABLE (1<<30) +#define SSG2_ENABLE (1<<29) +#define SSG3_ENABLE (1<<28) +#define SSG0_MASK_ENABLE (1<<15) /* Enable writing to SSG0 bit */ +#define SSG1_MASK_ENABLE (1<<14) +#define SSG2_MASK_ENABLE (1<<13) +#define SSG3_MASK_ENABLE (1<<12) + + +/* + * DMA Scatter/Gather Descriptor Bit fields + */ +#define SG_LINK (1<<31) /* Link */ +#define SG_TCI_ENABLE (1<<29) /* Enable Terminal Count Interrupt */ +#define SG_ETI_ENABLE (1<<28) /* Enable End of Transfer Interrupt */ +#define SG_ERI_ENABLE (1<<27) /* Enable Error Interrupt */ +#define SG_COUNT_MASK 0xFFFF /* Count Field */ + + + + +typedef uint32_t sgl_handle_t; + +typedef struct { + + /* + * Valid polarity settings: + * DMAReq0_ActiveLow + * DMAAck0_ActiveLow + * EOT0_ActiveLow + * + * DMAReq1_ActiveLow + * DMAAck1_ActiveLow + * EOT1_ActiveLow + * + * DMAReq2_ActiveLow + * DMAAck2_ActiveLow + * EOT2_ActiveLow + * + * DMAReq3_ActiveLow + * DMAAck3_ActiveLow + * EOT3_ActiveLow + */ + unsigned int polarity; + + char buffer_enable; /* Boolean: buffer enable */ + char tce_enable; /* Boolean: terminal count enable */ + char etd_output; /* Boolean: eot pin is a tc output */ + char pce; /* Boolean: parity check enable */ + + /* + * Peripheral location: + * INTERNAL_PERIPHERAL (UART0 on the 405GP) + * EXTERNAL_PERIPHERAL + */ + char pl; /* internal/external peripheral */ + + /* + * Valid pwidth settings: + * PW_8 + * PW_16 + * PW_32 + * PW_64 + */ + unsigned int pwidth; + + char dai; /* Boolean: dst address increment */ + char sai; /* Boolean: src address increment */ + + /* + * Valid psc settings: 0-3 + */ + unsigned int psc; /* Peripheral Setup Cycles */ + + /* + * Valid pwc settings: + * 0-63 + */ + unsigned int pwc; /* Peripheral Wait Cycles */ + + /* + * Valid phc settings: + * 0-7 + */ + unsigned int phc; /* Peripheral Hold Cycles */ + + /* + * Valid cp (channel priority) settings: + * PRIORITY_LOW + * PRIORITY_MID_LOW + * PRIORITY_MID_HIGH + * PRIORITY_HIGH + */ + unsigned int cp; /* channel priority */ + + /* + * Valid pf (memory read prefetch) settings: + * + * PREFETCH_1 + * PREFETCH_2 + * PREFETCH_4 + */ + unsigned int pf; /* memory read prefetch */ + + /* + * Boolean: channel interrupt enable + * NOTE: for sgl transfers, only the last descriptor will be setup to + * interrupt. + */ + char int_enable; + + char shift; /* easy access to byte_count shift, based on */ + /* the width of the channel */ + + uint32_t control; /* channel control word */ + + + /* These variabled are used ONLY in single dma transfers */ + unsigned int mode; /* transfer mode */ + dma_addr_t addr; + +} ppc_dma_ch_t; + + +typedef struct { + uint32_t control; + uint32_t src_addr; + uint32_t dst_addr; + uint32_t control_count; + uint32_t next; +} ppc_sgl_t; + + + +typedef struct { + unsigned int dmanr; + uint32_t control; /* channel ctrl word; loaded from each descrptr */ + uint32_t sgl_control; /* LK, TCI, ETI, and ERI bits in sgl descriptor */ + dma_addr_t dma_addr; /* dma (physical) address of this list */ + ppc_sgl_t *phead; + ppc_sgl_t *ptail; + +} sgl_list_info_t; + + +typedef struct { + unsigned int *src_addr; + unsigned int *dst_addr; + dma_addr_t dma_src_addr; + dma_addr_t dma_dst_addr; +} pci_alloc_desc_t; + + +extern ppc_dma_ch_t dma_channels[]; + +/* + * + * DMA API inline functions + * These functions are implemented here as inline functions for + * performance reasons. + * + */ + +static __inline__ int get_405gp_dma_status(void) +{ + return (mfdcr(DCRN_DMASR)); +} + + +static __inline__ int enable_405gp_dma(unsigned int dmanr) +{ + unsigned int control; + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + +#ifdef DEBUG_405DMA + if (dmanr >= MAX_405GP_DMA_CHANNELS) { + printk("enable_dma: bad channel: %d\n", dmanr); + return DMA_STATUS_BAD_CHANNEL; + } +#endif + + + switch (dmanr) { + case 0: + if (p_dma_ch->mode == DMA_MODE_READ) { + /* peripheral to memory */ + mtdcr(DCRN_DMASA0, NULL); + mtdcr(DCRN_DMADA0, p_dma_ch->addr); + } + else if (p_dma_ch->mode == DMA_MODE_WRITE) { + /* memory to peripheral */ + mtdcr(DCRN_DMASA0, p_dma_ch->addr); + mtdcr(DCRN_DMADA0, NULL); + } + /* for other xfer modes, the addresses are already set */ + control = mfdcr(DCRN_DMACR0); + control &= ~(DMA_TM_MASK | DMA_TD); /* clear all mode bits */ + control |= (p_dma_ch->mode | DMA_CH_ENABLE); + mtdcr(DCRN_DMACR0, control); + break; + case 1: + if (p_dma_ch->mode == DMA_MODE_READ) { + mtdcr(DCRN_DMASA1, NULL); + mtdcr(DCRN_DMADA1, p_dma_ch->addr); + } else if (p_dma_ch->mode == DMA_MODE_WRITE) { + mtdcr(DCRN_DMASA1, p_dma_ch->addr); + mtdcr(DCRN_DMADA1, NULL); + } + control = mfdcr(DCRN_DMACR1); + control &= ~(DMA_TM_MASK | DMA_TD); + control |= (p_dma_ch->mode | DMA_CH_ENABLE); + mtdcr(DCRN_DMACR1, control); + break; + case 2: + if (p_dma_ch->mode == DMA_MODE_READ) { + mtdcr(DCRN_DMASA2, NULL); + mtdcr(DCRN_DMADA2, p_dma_ch->addr); + } else if (p_dma_ch->mode == DMA_MODE_WRITE) { + mtdcr(DCRN_DMASA2, p_dma_ch->addr); + mtdcr(DCRN_DMADA2, NULL); + } + control = mfdcr(DCRN_DMACR2); + control &= ~(DMA_TM_MASK | DMA_TD); + control |= (p_dma_ch->mode | DMA_CH_ENABLE); + mtdcr(DCRN_DMACR2, control); + break; + case 3: + if (p_dma_ch->mode == DMA_MODE_READ) { + mtdcr(DCRN_DMASA3, NULL); + mtdcr(DCRN_DMADA3, p_dma_ch->addr); + } else if (p_dma_ch->mode == DMA_MODE_WRITE) { + mtdcr(DCRN_DMASA3, p_dma_ch->addr); + mtdcr(DCRN_DMADA3, NULL); + } + control = mfdcr(DCRN_DMACR3); + control &= ~(DMA_TM_MASK | DMA_TD); + control |= (p_dma_ch->mode | DMA_CH_ENABLE); + mtdcr(DCRN_DMACR3, control); + break; + default: + return DMA_STATUS_BAD_CHANNEL; + } + return DMA_STATUS_GOOD; +} + + + +static __inline__ void disable_405gp_dma(unsigned int dmanr) +{ + unsigned int control; + + switch (dmanr) { + case 0: + control = mfdcr(DCRN_DMACR0); + control &= ~DMA_CH_ENABLE; + mtdcr(DCRN_DMACR0, control); + break; + case 1: + control = mfdcr(DCRN_DMACR1); + control &= ~DMA_CH_ENABLE; + mtdcr(DCRN_DMACR1, control); + break; + case 2: + control = mfdcr(DCRN_DMACR2); + control &= ~DMA_CH_ENABLE; + mtdcr(DCRN_DMACR2, control); + break; + case 3: + control = mfdcr(DCRN_DMACR3); + control &= ~DMA_CH_ENABLE; + mtdcr(DCRN_DMACR3, control); + break; + default: +#ifdef DEBUG_405DMA + printk("disable_dma: bad channel: %d\n", dmanr); +#endif + } +} + + + +/* + * Sets the dma mode for single DMA transfers only. + * For scatter/gather transfers, the mode is passed to the + * alloc_dma_handle() function as one of the parameters. + * + * The mode is simply saved and used later. This allows + * the driver to call set_dma_mode() and set_dma_addr() in + * any order. + * + * Valid mode values are: + * + * DMA_MODE_READ peripheral to memory + * DMA_MODE_WRITE memory to peripheral + * DMA_MODE_MM memory to memory + * DMA_MODE_MM_DEVATSRC device-paced memory to memory, device at src + * DMA_MODE_MM_DEVATDST device-paced memory to memory, device at dst + */ +static __inline__ int set_405gp_dma_mode(unsigned int dmanr, unsigned int mode) +{ + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + +#ifdef DEBUG_405DMA + switch (mode) { + case DMA_MODE_READ: + case DMA_MODE_WRITE: + case DMA_MODE_MM: + case DMA_MODE_MM_DEVATSRC: + case DMA_MODE_MM_DEVATDST: + break; + default: + printk("set_dma_mode: bad mode 0x%x\n", mode); + return DMA_STATUS_BAD_MODE; + } + if (dmanr >= MAX_405GP_DMA_CHANNELS) { + printk("set_dma_mode: bad channel 0x%x\n", dmanr); + return DMA_STATUS_BAD_CHANNEL; + } +#endif + + p_dma_ch->mode = mode; + return DMA_STATUS_GOOD; +} + + + +/* + * Sets the DMA Count register. Note that 'count' is in bytes. + * However, the DMA Count register counts the number of "transfers", + * where each transfer is equal to the bus width. Thus, count + * MUST be a multiple of the bus width. + */ +static __inline__ void +set_405gp_dma_count(unsigned int dmanr, unsigned int count) +{ + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + +#ifdef DEBUG_405DMA + { + int error = 0; + switch(p_dma_ch->pwidth) { + case PW_8: + break; + case PW_16: + if (count & 0x1) + error = 1; + break; + case PW_32: + if (count & 0x3) + error = 1; + break; + case PW_64: + if (count & 0x7) + error = 1; + break; + default: + printk("set_dma_count: invalid bus width: 0x%x\n", + p_dma_ch->pwidth); + return; + } + if (error) + printk("Warning: set_dma_count count 0x%x bus width %d\n", + count, p_dma_ch->pwidth); + } +#endif + + count = count >> p_dma_ch->shift; + switch (dmanr) { + case 0: + mtdcr(DCRN_DMACT0, count); + break; + case 1: + mtdcr(DCRN_DMACT1, count); + break; + case 2: + mtdcr(DCRN_DMACT2, count); + break; + case 3: + mtdcr(DCRN_DMACT3, count); + break; + default: +#ifdef DEBUG_405DMA + printk("set_dma_count: bad channel: %d\n", dmanr); +#endif + } +} + + + +/* + * Returns the number of bytes left to be transfered. + * After a DMA transfer, this should return zero. + * Reading this while a DMA transfer is still in progress will return + * unpredictable results. + */ +static __inline__ int get_405gp_dma_residue(unsigned int dmanr) +{ + unsigned int count; + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + + switch (dmanr) { + case 0: + count = mfdcr(DCRN_DMACT0); + break; + case 1: + count = mfdcr(DCRN_DMACT1); + break; + case 2: + count = mfdcr(DCRN_DMACT2); + break; + case 3: + count = mfdcr(DCRN_DMACT3); + break; + default: +#ifdef DEBUG_405DMA + printk("get_dma_residue: bad channel: %d\n", dmanr); +#endif + return 0; + } + + return (count << p_dma_ch->shift); +} + + + +/* + * Sets the DMA address for a memory to peripheral or peripheral + * to memory transfer. The address is just saved in the channel + * structure for now and used later in enable_dma(). + */ +static __inline__ void set_405gp_dma_addr(unsigned int dmanr, dma_addr_t addr) +{ + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; +#ifdef DEBUG_405DMA + { + int error = 0; + switch(p_dma_ch->pwidth) { + case PW_8: + break; + case PW_16: + if ((unsigned)addr & 0x1) + error = 1; + break; + case PW_32: + if ((unsigned)addr & 0x3) + error = 1; + break; + case PW_64: + if ((unsigned)addr & 0x7) + error = 1; + break; + default: + printk("set_dma_addr: invalid bus width: 0x%x\n", + p_dma_ch->pwidth); + return; + } + if (error) + printk("Warning: set_dma_addr addr 0x%x bus width %d\n", + addr, p_dma_ch->pwidth); + } +#endif + + /* save dma address and program it later after we know the xfer mode */ + p_dma_ch->addr = addr; +} + + + + +/* + * Sets both DMA addresses for a memory to memory transfer. + * For memory to peripheral or peripheral to memory transfers + * the function set_dma_addr() should be used instead. + */ +static __inline__ void +set_405gp_dma_addr2(unsigned int dmanr, dma_addr_t src_dma_addr, + dma_addr_t dst_dma_addr) +{ +#ifdef DEBUG_405DMA + { + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + int error = 0; + switch(p_dma_ch->pwidth) { + case PW_8: + break; + case PW_16: + if (((unsigned)src_dma_addr & 0x1) || + ((unsigned)dst_dma_addr & 0x1) + ) + error = 1; + break; + case PW_32: + if (((unsigned)src_dma_addr & 0x3) || + ((unsigned)dst_dma_addr & 0x3) + ) + error = 1; + break; + case PW_64: + if (((unsigned)src_dma_addr & 0x7) || + ((unsigned)dst_dma_addr & 0x7) + ) + error = 1; + break; + default: + printk("set_dma_addr2: invalid bus width: 0x%x\n", + p_dma_ch->pwidth); + return; + } + if (error) + printk("Warning: set_dma_addr2 src 0x%x dst 0x%x bus width %d\n", + src_dma_addr, dst_dma_addr, p_dma_ch->pwidth); + } +#endif + + switch (dmanr) { + case 0: + mtdcr(DCRN_DMASA0, src_dma_addr); + mtdcr(DCRN_DMADA0, dst_dma_addr); + break; + case 1: + mtdcr(DCRN_DMASA1, src_dma_addr); + mtdcr(DCRN_DMADA1, dst_dma_addr); + break; + case 2: + mtdcr(DCRN_DMASA2, src_dma_addr); + mtdcr(DCRN_DMADA2, dst_dma_addr); + break; + case 3: + mtdcr(DCRN_DMASA3, src_dma_addr); + mtdcr(DCRN_DMADA3, dst_dma_addr); + break; + default: +#ifdef DEBUG_405DMA + printk("set_dma_addr2: bad channel: %d\n", dmanr); +#endif + } +} + + + +/* + * Enables the channel interrupt. + * + * If performing a scatter/gatter transfer, this function + * MUST be called before calling alloc_dma_handle() and building + * the sgl list. Otherwise, interrupts will not be enabled, if + * they were previously disabled. + */ +static __inline__ int +enable_405gp_dma_interrupt(unsigned int dmanr) +{ + unsigned int control; + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + + p_dma_ch->int_enable = TRUE; + switch (dmanr) { + case 0: + control = mfdcr(DCRN_DMACR0); + control|= DMA_CIE_ENABLE; /* Channel Interrupt Enable */ + mtdcr(DCRN_DMACR0, control); + break; + case 1: + control = mfdcr(DCRN_DMACR1); + control|= DMA_CIE_ENABLE; + mtdcr(DCRN_DMACR1, control); + break; + case 2: + control = mfdcr(DCRN_DMACR2); + control|= DMA_CIE_ENABLE; + mtdcr(DCRN_DMACR2, control); + break; + case 3: + control = mfdcr(DCRN_DMACR3); + control|= DMA_CIE_ENABLE; + mtdcr(DCRN_DMACR3, control); + break; + default: +#ifdef DEBUG_405DMA + printk("enable_dma_interrupt: bad channel: %d\n", dmanr); +#endif + return DMA_STATUS_BAD_CHANNEL; + } + return DMA_STATUS_GOOD; +} + + + +/* + * Disables the channel interrupt. + * + * If performing a scatter/gatter transfer, this function + * MUST be called before calling alloc_dma_handle() and building + * the sgl list. Otherwise, interrupts will not be disabled, if + * they were previously enabled. + */ +static __inline__ int +disable_405gp_dma_interrupt(unsigned int dmanr) +{ + unsigned int control; + ppc_dma_ch_t *p_dma_ch = &dma_channels[dmanr]; + + p_dma_ch->int_enable = TRUE; + switch (dmanr) { + case 0: + control = mfdcr(DCRN_DMACR0); + control &= ~DMA_CIE_ENABLE; /* Channel Interrupt Enable */ + mtdcr(DCRN_DMACR0, control); + break; + case 1: + control = mfdcr(DCRN_DMACR1); + control &= ~DMA_CIE_ENABLE; + mtdcr(DCRN_DMACR1, control); + break; + case 2: + control = mfdcr(DCRN_DMACR2); + control &= ~DMA_CIE_ENABLE; + mtdcr(DCRN_DMACR2, control); + break; + case 3: + control = mfdcr(DCRN_DMACR3); + control &= ~DMA_CIE_ENABLE; + mtdcr(DCRN_DMACR3, control); + break; + default: +#ifdef DEBUG_405DMA + printk("enable_dma_interrupt: bad channel: %d\n", dmanr); +#endif + return DMA_STATUS_BAD_CHANNEL; + } + return DMA_STATUS_GOOD; +} + + +#ifdef DCRNCAP_DMA_SG + +/* + * Add a new sgl descriptor to the end of a scatter/gather list + * which was created by alloc_dma_handle(). + * + * For a memory to memory transfer, both dma addresses must be + * valid. For a peripheral to memory transfer, one of the addresses + * must be set to NULL, depending on the direction of the transfer: + * memory to peripheral: set dst_addr to NULL, + * peripheral to memory: set src_addr to NULL. + */ +static __inline__ int +add_405gp_dma_sgl(sgl_handle_t handle, dma_addr_t src_addr, dma_addr_t dst_addr, + unsigned int count) +{ + sgl_list_info_t *psgl = (sgl_list_info_t *)handle; + ppc_dma_ch_t *p_dma_ch; + + if (!handle) { +#ifdef DEBUG_405DMA + printk("add_dma_sgl: null handle\n"); +#endif + return DMA_STATUS_BAD_HANDLE; + } + +#ifdef DEBUG_405DMA + if (psgl->dmanr >= MAX_405GP_DMA_CHANNELS) { + printk("add_dma_sgl error: psgl->dmanr == %d\n", psgl->dmanr); + return DMA_STATUS_BAD_CHANNEL; + } +#endif + + p_dma_ch = &dma_channels[psgl->dmanr]; + +#ifdef DEBUG_405DMA + { + int error = 0; + unsigned int aligned = (unsigned)src_addr | (unsigned)dst_addr | count; + switch(p_dma_ch->pwidth) { + case PW_8: + break; + case PW_16: + if (aligned & 0x1) + error = 1; + break; + case PW_32: + if (aligned & 0x3) + error = 1; + break; + case PW_64: + if (aligned & 0x7) + error = 1; + break; + default: + printk("add_dma_sgl: invalid bus width: 0x%x\n", + p_dma_ch->pwidth); + return DMA_STATUS_GENERAL_ERROR; + } + if (error) + printk("Alignment warning: add_dma_sgl src 0x%x dst 0x%x count 0x%x bus width var %d\n", + src_addr, dst_addr, count, p_dma_ch->pwidth); + + } +#endif + + if ((unsigned)(psgl->ptail + 1) >= ((unsigned)psgl + SGL_LIST_SIZE)) { +#ifdef DEBUG_405DMA + printk("sgl handle out of memory \n"); +#endif + return DMA_STATUS_OUT_OF_MEMORY; + } + + + if (!psgl->ptail) { + psgl->phead = (ppc_sgl_t *) + ((unsigned)psgl + sizeof(sgl_list_info_t)); + psgl->ptail = psgl->phead; + } else { + psgl->ptail->next = virt_to_bus(psgl->ptail + 1); + psgl->ptail++; + } + + psgl->ptail->control = psgl->control; + psgl->ptail->src_addr = src_addr; + psgl->ptail->dst_addr = dst_addr; + psgl->ptail->control_count = (count >> p_dma_ch->shift) | + psgl->sgl_control; + psgl->ptail->next = (uint32_t)NULL; + + return DMA_STATUS_GOOD; +} + + + +/* + * Enable (start) the DMA described by the sgl handle. + */ +static __inline__ void enable_405gp_dma_sgl(sgl_handle_t handle) +{ + sgl_list_info_t *psgl = (sgl_list_info_t *)handle; + ppc_dma_ch_t *p_dma_ch; + uint32_t sg_command; + +#ifdef DEBUG_405DMA + if (!handle) { + printk("enable_dma_sgl: null handle\n"); + return; + } else if (psgl->dmanr > (MAX_405GP_DMA_CHANNELS - 1)) { + printk("enable_dma_sgl: bad channel in handle %d\n", + psgl->dmanr); + return; + } else if (!psgl->phead) { + printk("enable_dma_sgl: sg list empty\n"); + return; + } +#endif + + p_dma_ch = &dma_channels[psgl->dmanr]; + psgl->ptail->control_count &= ~SG_LINK; /* make this the last dscrptr */ + sg_command = mfdcr(DCRN_ASGC); + + switch(psgl->dmanr) { + case 0: + mtdcr(DCRN_ASG0, virt_to_bus(psgl->phead)); + sg_command |= SSG0_ENABLE; + break; + case 1: + mtdcr(DCRN_ASG1, virt_to_bus(psgl->phead)); + sg_command |= SSG1_ENABLE; + break; + case 2: + mtdcr(DCRN_ASG2, virt_to_bus(psgl->phead)); + sg_command |= SSG2_ENABLE; + break; + case 3: + mtdcr(DCRN_ASG3, virt_to_bus(psgl->phead)); + sg_command |= SSG3_ENABLE; + break; + default: +#ifdef DEBUG_405DMA + printk("enable_dma_sgl: bad channel: %d\n", psgl->dmanr); +#endif + } + +#if 0 /* debug */ + printk("\n\nenable_dma_sgl at dma_addr 0x%x\n", + virt_to_bus(psgl->phead)); + { + ppc_sgl_t *pnext, *sgl_addr; + + pnext = psgl->phead; + while (pnext) { + printk("dma descriptor at 0x%x, dma addr 0x%x\n", + (unsigned)pnext, (unsigned)virt_to_bus(pnext)); + printk("control 0x%x src 0x%x dst 0x%x c_count 0x%x, next 0x%x\n", + (unsigned)pnext->control, (unsigned)pnext->src_addr, + (unsigned)pnext->dst_addr, + (unsigned)pnext->control_count, (unsigned)pnext->next); + + (unsigned)pnext = bus_to_virt(pnext->next); + } + printk("sg_command 0x%x\n", sg_command); + } +#endif + +#ifdef PCI_ALLOC_IS_NONCONSISTENT + /* + * This is temporary only, until pci_alloc_consistent() really does + * return "consistent" memory. + */ + flush_dcache_range((unsigned)handle, (unsigned)handle + SGL_LIST_SIZE); +#endif + + mtdcr(DCRN_ASGC, sg_command); /* start transfer */ +} + + + +/* + * Halt an active scatter/gather DMA operation. + */ +static __inline__ void disable_405gp_dma_sgl(sgl_handle_t handle) +{ + sgl_list_info_t *psgl = (sgl_list_info_t *)handle; + uint32_t sg_command; + +#ifdef DEBUG_405DMA + if (!handle) { + printk("enable_dma_sgl: null handle\n"); + return; + } else if (psgl->dmanr > (MAX_405GP_DMA_CHANNELS - 1)) { + printk("enable_dma_sgl: bad channel in handle %d\n", + psgl->dmanr); + return; + } +#endif + sg_command = mfdcr(DCRN_ASGC); + switch(psgl->dmanr) { + case 0: + sg_command &= ~SSG0_ENABLE; + break; + case 1: + sg_command &= ~SSG1_ENABLE; + break; + case 2: + sg_command &= ~SSG2_ENABLE; + break; + case 3: + sg_command &= ~SSG3_ENABLE; + break; + default: +#ifdef DEBUG_405DMA + printk("enable_dma_sgl: bad channel: %d\n", psgl->dmanr); +#endif + } + + mtdcr(DCRN_ASGC, sg_command); /* stop transfer */ +} + + + +/* + * Returns number of bytes left to be transferred from the entire sgl list. + * *src_addr and *dst_addr get set to the source/destination address of + * the sgl descriptor where the DMA stopped. + * + * An sgl transfer must NOT be active when this function is called. + */ +static __inline__ int +get_405gp_dma_sgl_residue(sgl_handle_t handle, dma_addr_t *src_addr, + dma_addr_t *dst_addr) +{ + sgl_list_info_t *psgl = (sgl_list_info_t *)handle; + ppc_dma_ch_t *p_dma_ch; + ppc_sgl_t *pnext, *sgl_addr; + uint32_t count_left; + +#ifdef DEBUG_405DMA + if (!handle) { + printk("get_dma_sgl_residue: null handle\n"); + return DMA_STATUS_BAD_HANDLE; + } else if (psgl->dmanr > (MAX_405GP_DMA_CHANNELS - 1)) { + printk("get_dma_sgl_residue: bad channel in handle %d\n", + psgl->dmanr); + return DMA_STATUS_BAD_CHANNEL; + } +#endif + + switch(psgl->dmanr) { + case 0: + sgl_addr = (ppc_sgl_t *)bus_to_virt(mfdcr(DCRN_ASG0)); + count_left = mfdcr(DCRN_DMACT0); + break; + case 1: + sgl_addr = (ppc_sgl_t *)bus_to_virt(mfdcr(DCRN_ASG1)); + count_left = mfdcr(DCRN_DMACT1); + break; + case 2: + sgl_addr = (ppc_sgl_t *)bus_to_virt(mfdcr(DCRN_ASG2)); + count_left = mfdcr(DCRN_DMACT2); + break; + case 3: + sgl_addr = (ppc_sgl_t *)bus_to_virt(mfdcr(DCRN_ASG3)); + count_left = mfdcr(DCRN_DMACT3); + break; + default: +#ifdef DEBUG_405DMA + printk("get_dma_sgl_residue: bad channel: %d\n", psgl->dmanr); +#endif + goto error; + } + + if (!sgl_addr) { +#ifdef DEBUG_405DMA + printk("get_dma_sgl_residue: sgl addr register is null\n"); +#endif + goto error; + } + + pnext = psgl->phead; + while (pnext && + ((unsigned)pnext < ((unsigned)psgl + SGL_LIST_SIZE) && + (pnext != sgl_addr)) + ) { + pnext = pnext++; + } + + if (pnext == sgl_addr) { /* found the sgl descriptor */ + + *src_addr = pnext->src_addr; + *dst_addr = pnext->dst_addr; + + /* + * Now search the remaining descriptors and add their count. + * We already have the remaining count from this descriptor in + * count_left. + */ + pnext++; + + while ((pnext != psgl->ptail) && + ((unsigned)pnext < ((unsigned)psgl + SGL_LIST_SIZE)) + ) { + count_left += pnext->control_count & SG_COUNT_MASK; + } + + if (pnext != psgl->ptail) { /* should never happen */ +#ifdef DEBUG_405DMA + printk("get_dma_sgl_residue error (1) psgl->ptail 0x%x handle 0x%x\n", + (unsigned int)psgl->ptail, + (unsigned int)handle); +#endif + goto error; + } + + /* success */ + p_dma_ch = &dma_channels[psgl->dmanr]; + return (count_left << p_dma_ch->shift); /* count in bytes */ + + } else { + /* this shouldn't happen */ +#ifdef DEBUG_405DMA + printk("get_dma_sgl_residue, unable to match current address 0x%x, handle 0x%x\n", + (unsigned int)sgl_addr, (unsigned int)handle); + +#endif + } + + +error: + *src_addr = (dma_addr_t)NULL; + *dst_addr = (dma_addr_t)NULL; + return 0; +} + + + + +/* + * Returns the address(es) of the buffer(s) contained in the head element of + * the scatter/gather list. The element is removed from the scatter/gather + * list and the next element becomes the head. + * + * This function should only be called when the DMA is not active. + */ +static __inline__ int +delete_405gp_dma_sgl_element(sgl_handle_t handle, dma_addr_t *src_dma_addr, + dma_addr_t *dst_dma_addr) +{ + sgl_list_info_t *psgl = (sgl_list_info_t *)handle; + +#ifdef DEBUG_405DMA + if (!handle) { + printk("delete_sgl_element: null handle\n"); + return DMA_STATUS_BAD_HANDLE; + } else if (psgl->dmanr > (MAX_405GP_DMA_CHANNELS - 1)) { + printk("delete_sgl_element: bad channel in handle %d\n", + psgl->dmanr); + return DMA_STATUS_BAD_CHANNEL; + } +#endif + + if (!psgl->phead) { +#ifdef DEBUG_405DMA + printk("delete_sgl_element: sgl list empty\n"); +#endif + *src_dma_addr = (dma_addr_t)NULL; + *dst_dma_addr = (dma_addr_t)NULL; + return DMA_STATUS_SGL_LIST_EMPTY; + } + + *src_dma_addr = (dma_addr_t)psgl->phead->src_addr; + *dst_dma_addr = (dma_addr_t)psgl->phead->dst_addr; + + if (psgl->phead == psgl->ptail) { + /* last descriptor on the list */ + psgl->phead = NULL; + psgl->ptail = NULL; + } else { + psgl->phead++; + } + + return DMA_STATUS_GOOD; +} + +#endif /* DCRNCAP_DMA_SG */ + +/* + * The rest of the DMA API, in ppc405_dma.c + */ +extern int hw_init_dma_channel(unsigned int, ppc_dma_ch_t *); +extern int get_channel_config(unsigned int, ppc_dma_ch_t *); +extern int set_channel_priority(unsigned int, unsigned int); +extern unsigned int get_peripheral_width(unsigned int); +extern int alloc_dma_handle(sgl_handle_t *, unsigned int, unsigned int); +extern void free_dma_handle(sgl_handle_t); + +#endif +#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc4xx.h b/include/asm-ppc/ppc4xx.h deleted file mode 100644 index b5cbfc203037..000000000000 --- a/include/asm-ppc/ppc4xx.h +++ /dev/null @@ -1,285 +0,0 @@ -/* - * BK Id: SCCS/s.ppc4xx.h 1.3 05/17/01 18:14:25 cort - */ -/* - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Module name: ppc4xx.h - * - * Description: - * A generic include file which pulls in appropriate include files - * for specific board types based on configuration settings. - * - */ - -#ifdef __KERNEL__ -#ifndef __PPC4XX_H__ -#define __PPC4XX_H__ - -#include <linux/config.h> - -#ifndef __ASSEMBLY__ - -#if defined(CONFIG_OAK) -#include <asm/oak.h> -#endif - -#if defined(CONFIG_WALNUT) -#include <asm/walnut.h> -#endif - -/* IO_BASE is for PCI I/O. - * ISA not supported, just here to resolve copilation. - */ - -#define _IO_BASE 0xe8000000 /* The PCI address window */ -#define _ISA_MEM_BASE 0 -#define PCI_DRAM_OFFSET 0 - -extern unsigned long isa_io_base; - -/* - * The "residual" board information structure the boot loader passes - * into the kernel. - */ -extern unsigned char __res[]; - -/* I don't know if this is general to 4xx, or unique to a specific - * processor or board. In any case it is easy to move. - */ -#define PPC4xx_PCI_IO_ADDR ((uint)0xe8000000) -#define PPC4xx_PCI_IO_SIZE ((uint)64*1024) -#define PPC4xx_PCI_CFG_ADDR ((uint)0xeec00000) -#define PPC4xx_PCI_CFG_SIZE ((uint)4*1024) -#define PPC4xx_PCI_LCFG_ADDR ((uint)0xef400000) -#define PPC4xx_PCI_LCFG_SIZE ((uint)4*1024) -#define PPC4xx_ONB_IO_ADDR ((uint)0xef600000) -#define PPC4xx_ONB_IO_SIZE ((uint)4*1024) - -#endif /* __ASSEMBLY__ */ - -/* Device Control Registers unique to 4xx */ - -#define DCRN_BEAR 0x090 /* Bus Error Address Register */ -#define DCRN_BESR 0x091 /* Bus Error Syndrome Register */ -#define BESR_DSES 0x80000000 /* Data-Side Error Status */ -#define BESR_DMES 0x40000000 /* DMA Error Status */ -#define BESR_RWS 0x20000000 /* Read/Write Status */ -#define BESR_ETMASK 0x1C000000 /* Error Type */ -#define ET_PROT 0 -#define ET_PARITY 1 -#define ET_NCFG 2 -#define ET_BUSERR 4 -#define ET_BUSTO 6 -#define DCRN_CHCR0 0x0B1 /* Chip Control Register 1 */ -#define DCRN_CHCR1 0x0B2 /* Chip Control Register 2 */ -#define DCRN_CHPSR 0x0B4 /* Chip Pin Strapping */ -#define DCRN_CPMER 0x0B9 /* CPM Enable */ -#define DCRN_CPMFR 0x0BA /* CPM Force */ -#define CPM_IIC 0x80000000 /* IIC interface */ -#define CPM_PCI 0x40000000 /* PCI bridge */ -#define CPM_CPU 0x20000000 /* processor core */ -#define CPM_DMA 0x10000000 /* DMA controller */ -#define CPM_BRG 0x08000000 /* PLB to OPB bridge */ -#define CPM_DCP 0x04000000 /* CodePack */ -#define CPM_EBC 0x02000000 /* ROM/SRAM peripheral controller */ -#define CPM_SDRAM 0x01000000 /* SDRAM memory controller */ -#define CPM_PLB 0x00800000 /* PLB bus arbiter */ -#define CPM_GPIO 0x00400000 /* General Purpose IO (??) */ -#define CPM_UART0 0x00200000 /* serial port 0 */ -#define CPM_UART1 0x00100000 /* serial port 1 */ -#define CPM_UIC 0x00080000 /* Universal Interrupt Controller */ -#define CPM_TMRCLK 0x00040000 /* CPU timers */ -#define CPM_EMAC_MM 0x00020000 /* on-chip ethernet MM unit */ -#define CPM_EMAC_RM 0x00010000 /* on-chip ethernet RM unit */ -#define CPM_EMAC_TM 0x00008000 /* on-chip ethernet TM unit */ -#define DCRN_CPMSR 0x0B8 /* CPM Status */ - -#define DCRN_DMACR0 0x100 /* DMA Channel Control Register 0 */ -#define DCRN_DMACT0 0x101 /* DMA Count Register 0 */ -#define DCRN_DMADA0 0x102 /* DMA Destination Address Register 0 */ -#define DCRN_DMASA0 0x103 /* DMA Source Address Register 0 */ -#define DCRN_ASG0 0x104 /* DMA Scatter/Gather Descriptor Addr 0 */ - -#define DCRN_DMACR1 0x108 /* DMA Channel Control Register 1 */ -#define DCRN_DMACT1 0x109 /* DMA Count Register 1 */ -#define DCRN_DMADA1 0x10A /* DMA Destination Address Register 1 */ -#define DCRN_DMASA1 0x10B /* DMA Source Address Register 1 */ -#define DCRN_ASG1 0x10C /* DMA Scatter/Gather Descriptor Addr 1 */ - -#define DCRN_DMACR2 0x110 /* DMA Channel Control Register 2 */ -#define DCRN_DMACT2 0x111 /* DMA Count Register 2 */ -#define DCRN_DMADA2 0x112 /* DMA Destination Address Register 2 */ -#define DCRN_DMASA2 0x113 /* DMA Source Address Register 2 */ -#define DCRN_ASG2 0x114 /* DMA Scatter/Gather Descriptor Addr 2 */ - -#define DCRN_DMACR3 0x118 /* DMA Channel Control Register 3 */ -#define DCRN_DMACT3 0x119 /* DMA Count Register 3 */ -#define DCRN_DMADA3 0x11A /* DMA Destination Address Register 3 */ -#define DCRN_DMASA3 0x11B /* DMA Source Address Register 3 */ -#define DCRN_ASG3 0x11C /* DMA Scatter/Gather Descriptor Addr 3 */ - -#define DCRN_DMASR 0x120 /* DMA Status Register */ -#define DCRN_ASGC 0x123 /* DMA Scatter/Gather Command */ -#define DCRN_ADR 0x124 /* DMA Address Decode */ - -#define DCRN_SLP 0x125 /* DMA Sleep Register */ -#define DCRN_POL 0x126 /* DMA Polarity Register */ - - -#define DCRN_EBCCFGADR 0x012 /* Peripheral Controller Address */ -#define DCRN_EBCCFGDATA 0x013 /* Peripheral Controller Data */ -#define DCRN_EXISR 0x040 /* External Interrupt Status Register */ -#define DCRN_EXIER 0x042 /* External Interrupt Enable Register */ -#define EXIER_CIE 0x80000000 /* Critical Interrupt Enable */ -#define EXIER_SRIE 0x08000000 /* Serial Port Rx Int. Enable */ -#define EXIER_STIE 0x04000000 /* Serial Port Tx Int. Enable */ -#define EXIER_JRIE 0x02000000 /* JTAG Serial Port Rx Int. Enable */ -#define EXIER_JTIE 0x01000000 /* JTAG Serial Port Tx Int. Enable */ -#define EXIER_D0IE 0x00800000 /* DMA Channel 0 Interrupt Enable */ -#define EXIER_D1IE 0x00400000 /* DMA Channel 1 Interrupt Enable */ -#define EXIER_D2IE 0x00200000 /* DMA Channel 2 Interrupt Enable */ -#define EXIER_D3IE 0x00100000 /* DMA Channel 3 Interrupt Enable */ -#define EXIER_E0IE 0x00000010 /* External Interrupt 0 Enable */ -#define EXIER_E1IE 0x00000008 /* External Interrupt 1 Enable */ -#define EXIER_E2IE 0x00000004 /* External Interrupt 2 Enable */ -#define EXIER_E3IE 0x00000002 /* External Interrupt 3 Enable */ -#define EXIER_E4IE 0x00000001 /* External Interrupt 4 Enable */ -#define DCRN_IOCR 0x0A0 /* Input/Output Configuration Register */ -#define IOCR_E0TE 0x80000000 -#define IOCR_E0LP 0x40000000 -#define IOCR_E1TE 0x20000000 -#define IOCR_E1LP 0x10000000 -#define IOCR_E2TE 0x08000000 -#define IOCR_E2LP 0x04000000 -#define IOCR_E3TE 0x02000000 -#define IOCR_E3LP 0x01000000 -#define IOCR_E4TE 0x00800000 -#define IOCR_E4LP 0x00400000 -#define IOCR_EDT 0x00080000 -#define IOCR_SOR 0x00040000 -#define IOCR_EDO 0x00008000 -#define IOCR_2XC 0x00004000 -#define IOCR_ATC 0x00002000 -#define IOCR_SPD 0x00001000 -#define IOCR_BEM 0x00000800 -#define IOCR_PTD 0x00000400 -#define IOCR_ARE 0x00000080 -#define IOCR_DRC 0x00000020 -#define IOCR_RDM(x) (((x) & 0x3) << 3) -#define IOCR_TCS 0x00000004 -#define IOCR_SCS 0x00000002 -#define IOCR_SPC 0x00000001 -#define DCRN_KIAR 0x014 /* Decompression Controller Address */ -#define DCRN_KIDR 0x015 /* Decompression Controller Data */ -#define DCRN_MALCR 0x180 /* MAL Configuration */ -#define MALCR_MMSR 0x80000000 /* MAL Software reset */ -#define MALCR_PLBP_1 0x00400000 /* MAL reqest priority: */ -#define MALCR_PLBP_2 0x00800000 /* lowsest is 00 */ -#define MALCR_PLBP_3 0x00C00000 /* highest */ -#define MALCR_GA 0x00200000 /* Guarded Active Bit */ -#define MALCR_OA 0x00100000 /* Ordered Active Bit */ -#define MALCR_PLBLE 0x00080000 /* PLB Lock Error Bit */ -#define MALCR_PLBLT_1 0x00040000 /* PLB Latency Timer */ -#define MALCR_PLBLT_2 0x00020000 -#define MALCR_PLBLT_3 0x00010000 -#define MALCR_PLBLT_4 0x00008000 -#define MALCR_PLBLT_DEFAULT 0x00078000 /* JSP: Is this a valid default?? */ -#define MALCR_PLBB 0x00004000 /* PLB Burst Deactivation Bit */ -#define MALCR_OPBBL 0x00000080 /* OPB Lock Bit */ -#define MALCR_EOPIE 0x00000004 /* End Of Packet Interrupt Enable */ -#define MALCR_LEA 0x00000002 /* Locked Error Active */ -#define MALCR_MSD 0x00000001 /* MAL Scroll Descriptor Bit */ -#define DCRN_MALDBR 0x183 /* Debug Register */ -#define DCRN_MALESR 0x181 /* Error Status */ -#define MALESR_EVB 0x80000000 /* Error Valid Bit */ -#define MALESR_CID 0x40000000 /* Channel ID Bit for channel 0 */ -#define MALESR_DE 0x00100000 /* Descriptor Error */ -#define MALESR_OEN 0x00080000 /* OPB Non-Fullword Error */ -#define MALESR_OTE 0x00040000 /* OPB Timeout Error */ -#define MALESR_OSE 0x00020000 /* OPB Slave Error */ -#define MALESR_PEIN 0x00010000 /* PLB Bus Error Indication */ -#define MALESR_DEI 0x00000010 /* Descriptor Error Interrupt */ -#define MALESR_ONEI 0x00000008 /* OPB Non-Fullword Error Interrupt */ -#define MALESR_OTEI 0x00000004 /* OPB Timeout Error Interrupt */ -#define MALESR_OSEI 0x00000002 /* OPB Slace Error Interrupt */ -#define MALESR_PBEI 0x00000001 /* PLB Bus Error Interrupt */ -#define DCRN_MALIER 0x182 /* Interrupt Enable */ -#define MALIER_DE 0x00000010 /* Descriptor Error Interrupt Enable */ -#define MALIER_NE 0x00000008 /* OPB Non-word Transfer Int Enable */ -#define MALIER_TE 0x00000004 /* OPB Time Out Error Interrupt Enable */ -#define MALIER_OPBE 0x00000002 /* OPB Slave Error Interrupt Enable */ -#define MALIER_PLBE 0x00000001 /* PLB Error Interrupt Enable */ -#define DCRN_MALTXCARR 0x185 /* TX Channed Active Reset Register */ -#define DCRN_MALTXCASR 0x184 /* TX Channel Active Set Register */ -#define DCRN_MALTXDEIR 0x187 /* Tx Descriptor Error Interrupt */ -#define DCRN_MALTXEOBISR 0x186 /* Tx End of Buffer Interrupt Status */ -#define MALOBISR_CH0 0x80000000 /* EOB channel 1 bit */ -#define MALOBISR_CH2 0x40000000 /* EOB channel 2 bit */ -#define DCRN_MALRXCARR 0x191 /* RX Channed Active Reset Register */ -#define DCRN_MALRXCASR 0x190 /* RX Channel Active Set Register */ -#define DCRN_MALRXDEIR 0x193 /* Rx Descriptor Error Interrupt */ -#define DCRN_MALRXEOBISR 0x192 /* Rx End of Buffer Interrupt Status */ -#define DCRN_MALRXCTP0R 0x1C0 /* Channel Rx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP0R 0x1A0 /* Channel Tx 0 Channel Table Pointer */ -#define DCRN_MALTXCTP1R 0x1A1 /* Channel Tx 1 Channel Table Pointer */ -#define DCRN_MALRCBS0 0x1E0 /* Channel Rx 0 Channel Buffer Size */ -#define DCRN_MEMCFGADR 0x010 /* Memory Controller Address */ -#define DCRN_MEMCFGDATA 0x011 /* Memory Controller Data */ -#define DCRN_OCMISARC 0x018 /* OCM Instr Side Addr Range Compare */ -#define DCRN_OCMISCR 0x019 /* OCM Instr Side Control */ -#define DCRN_OCMDSARC 0x01A /* OCM Data Side Addr Range Compare */ -#define DCRN_OCMDSCR 0x01B /* OCM Data Side Control */ -#define DCRN_PLB0_ACR 0x087 /* PLB Arbiter Control */ -#define DCRN_PLB0_BEAR 0x086 /* PLB Error Address */ -#define DCRN_PLB0_BESR 0x084 /* PLB Error Status */ -#define DCRN_PLLMR 0x0B0 /* PLL Mode */ -#define DCRN_POB0_BEAR 0x0A2 /* PLB to OPB Error Address */ -#define DCRN_POB0_BESR0 0x0A0 /* PLB to OPB Error Status Register 1 */ -#define DCRN_POB0_BESR1 0x0A4 /* PLB to OPB Error Status Register 1 */ -#define DCRN_UICCR 0x0C3 /* UIC Critical */ -#define DCRN_UICER 0x0C2 /* UIC Enable */ -#define DCRN_UICPR 0x0C4 /* UIC Polarity */ -#define DCRN_UICSR 0x0C0 /* UIC Status */ -#define DCRN_UICTR 0x0C5 /* UIC Triggering */ -#define DCRN_UICMSR 0x0C6 /* UIC Masked Status */ -#define DCRN_UICVR 0x0C7 /* UIC Vector */ -#define DCRN_UICVCR 0x0C8 /* UIC Vector Configuration */ -#define UIC_U0 0x80000000 /* UART0 */ -#define UIC_U1 0x40000000 /* UART1 */ -#define UIC_IIC 0x20000000 /* IIC */ -#define UIC_EM 0x10000000 /* External Master */ -#define UIC_PCI 0x08000000 /* PCI */ -#define UIC_D0 0x04000000 /* DMA Channel 0 */ -#define UIC_D1 0x02000000 /* DMA Channel 1 */ -#define UIC_D2 0x01000000 /* DMA Channel 2 */ -#define UIC_D3 0x00800000 /* DMA Channel 3 */ -#define UIC_EW 0x00400000 /* Ethernet Wake-up */ -#define UIC_MS 0x00200000 /* MAL SERR */ -#define UIC_MTE 0x00100000 /* MAL TX EOB */ -#define UIC_MRE 0x00080000 /* MAL RX EOB */ -#define UIC_MTD 0x00040000 /* MAL TX DE */ -#define UIC_MRD 0x00020000 /* MAL RX DE */ -#define UIC_E 0x00010000 /* Ethernet */ -#define UIC_EPS 0x00008000 /* External PCI SERR */ -#define UIC_EC 0x00004000 /* ECC Correctable Error */ -#define UIC_PPM 0x00002000 /* PCI Power Management */ -/* -** 0x00001000 reserved -** 0x00000800 reserved -** 0x00000400 reserved -** 0x00000200 reserved -** 0x00000100 reserved -** 0x00000080 reserved -*/ -#define UIC_EIR0 0x00000040 /* External IRQ 0 */ -#define UIC_EIR1 0x00000020 /* External IRQ 0 */ -#define UIC_EIR2 0x00000010 /* External IRQ 0 */ -#define UIC_EIR3 0x00000008 /* External IRQ 0 */ -#define UIC_EIR4 0x00000004 /* External IRQ 0 */ -#define UIC_EIR5 0x00000002 /* External IRQ 0 */ -#define UIC_EIR6 0x00000001 /* External IRQ 0 */ - -#endif /* __PPC4XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc4xx_pic.h b/include/asm-ppc/ppc4xx_pic.h new file mode 100644 index 000000000000..f572b180a4b8 --- /dev/null +++ b/include/asm-ppc/ppc4xx_pic.h @@ -0,0 +1,30 @@ +/* + * BK Id: %F% %I% %G% %U% %#% + */ +/* + * + * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> + * + * Module name: ppc4xx_pic.h + * + * Description: + * Interrupt controller driver for PowerPC 4xx-based processors. + */ + +#ifndef __PPC4XX_PIC_H__ +#define __PPC4XX_PIC_H__ + +#include <linux/config.h> +#include <linux/irq.h> + +/* External Global Variables */ + +extern struct hw_interrupt_type *ppc4xx_pic; + + +/* Function Prototypes */ + +extern void ppc4xx_pic_init(void); +extern int ppc4xx_pic_get_irq(struct pt_regs *regs); + +#endif /* __PPC4XX_PIC_H__ */ diff --git a/include/asm-ppc/ppc4xx_serial.h b/include/asm-ppc/ppc4xx_serial.h deleted file mode 100644 index 718775c8e47f..000000000000 --- a/include/asm-ppc/ppc4xx_serial.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * BK Id: SCCS/s.ppc4xx_serial.h 1.3 05/17/01 18:14:25 cort - */ -/* - * Copyright 2000 MontaVista Software Inc. - * PPC405GP modifications - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * - * Module name: ppc405_serial.h - * - * Description: - * Macros, definitions, and data structures specific to the IBM PowerPC - * 405 on-chip serial port devices. - */ - -#ifdef __KERNEL__ -#ifndef __ASMPPC_PPC4xx_SERIAL_H -#define __ASMPPC_PPC4xx_SERIAL_H - -#include <linux/config.h> - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -#define PPC405GP_UART0_INT 0 -#define PPC405GP_UART1_INT 1 - -/* -** 405GP UARTs are *not* PCI devices, so need to specify a non-pci memory -** address and an io_type of SERIAL_IO_MEM. -*/ - -#define PPC405GP_UART0_IO_BASE (u8 *) 0xef600300 -#define PPC405GP_UART1_IO_BASE (u8 *) 0xef600400 - -/* -** - there is no config option for this -** - this name could be more informative -** - also see arch/ppc/kernel/ppc405_serial.c -** -** #define CONFIG_PPC405GP_INTERNAL_CLOCK -*/ -#ifdef CONFIG_PPC405GP_INTERNAL_CLOCK -#define BASE_BAUD 201600 -#else -#define BASE_BAUD 691200 -#endif - - -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF) -#endif - - -#ifdef CONFIG_STB03XXX - -#define UART0_IO_BASE 0x40040000 -#define UART0_INT 20 - -#define STD_SERIAL_PORT_DFNS \ - /* ttyS0 */ \ - { 0, BASE_BAUD, 0, UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, - -#elif defined(CONFIG_UART1_DFLT_CONSOLE) - -#define STD_SERIAL_PORT_DFNS \ - /* ttyS1 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART1_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART1_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, \ - /* ttyS0 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, - -#else - -#define STD_SERIAL_PORT_DFNS \ - /* ttyS0 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART0_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART0_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, \ - /* ttyS1 */ \ - { 0, BASE_BAUD, 0, PPC405GP_UART1_INT, STD_COM_FLAGS, 0, 0, 0, 0, 0, 0, 0, \ - PPC405GP_UART1_IO_BASE, 0, 0, 0, {}, {}, {}, SERIAL_IO_MEM, NULL }, - -#endif - - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DFNS \ - {} - - - -#endif /* __ASMPPC_PPC4xx_SERIAL_H */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h new file mode 100644 index 000000000000..d80c6ea8081a --- /dev/null +++ b/include/asm-ppc/ppc_asm.h @@ -0,0 +1,313 @@ +/* + * BK Id: %F% %I% %G% %U% %#% + */ +/* + * include/asm-ppc/ppc_asm.h + * + * Definitions used by various bits of low-level assembly code on PowerPC. + * + * Copyright (C) 1995-1999 Gary Thomas, Paul Mackerras, Cort Dougan. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + */ + +#include <linux/config.h> + +/* + * Macros for storing registers into and loading registers from + * exception frames. + */ +#define SAVE_GPR(n, base) stw n,GPR0+4*(n)(base) +#define SAVE_2GPRS(n, base) SAVE_GPR(n, base); SAVE_GPR(n+1, base) +#define SAVE_4GPRS(n, base) SAVE_2GPRS(n, base); SAVE_2GPRS(n+2, base) +#define SAVE_8GPRS(n, base) SAVE_4GPRS(n, base); SAVE_4GPRS(n+4, base) +#define SAVE_10GPRS(n, base) SAVE_8GPRS(n, base); SAVE_2GPRS(n+8, base) +#define REST_GPR(n, base) lwz n,GPR0+4*(n)(base) +#define REST_2GPRS(n, base) REST_GPR(n, base); REST_GPR(n+1, base) +#define REST_4GPRS(n, base) REST_2GPRS(n, base); REST_2GPRS(n+2, base) +#define REST_8GPRS(n, base) REST_4GPRS(n, base); REST_4GPRS(n+4, base) +#define REST_10GPRS(n, base) REST_8GPRS(n, base); REST_2GPRS(n+8, base) + +#define SAVE_FPR(n, base) stfd n,THREAD_FPR0+8*(n)(base) +#define SAVE_2FPRS(n, base) SAVE_FPR(n, base); SAVE_FPR(n+1, base) +#define SAVE_4FPRS(n, base) SAVE_2FPRS(n, base); SAVE_2FPRS(n+2, base) +#define SAVE_8FPRS(n, base) SAVE_4FPRS(n, base); SAVE_4FPRS(n+4, base) +#define SAVE_16FPRS(n, base) SAVE_8FPRS(n, base); SAVE_8FPRS(n+8, base) +#define SAVE_32FPRS(n, base) SAVE_16FPRS(n, base); SAVE_16FPRS(n+16, base) +#define REST_FPR(n, base) lfd n,THREAD_FPR0+8*(n)(base) +#define REST_2FPRS(n, base) REST_FPR(n, base); REST_FPR(n+1, base) +#define REST_4FPRS(n, base) REST_2FPRS(n, base); REST_2FPRS(n+2, base) +#define REST_8FPRS(n, base) REST_4FPRS(n, base); REST_4FPRS(n+4, base) +#define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) +#define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) + +/* + * Once a version of gas that understands the AltiVec instructions + * is freely available, we can do this the normal way... - paulus + */ +#define LVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(103<<1) +#define STVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(231<<1) +#define MFVSCR(r) .long (4<<26)+((r)<<21)+(770<<1) +#define MTVSCR(r) .long (4<<26)+((r)<<11)+(802<<1) + +#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); STVX(n,b,base) +#define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) +#define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base) +#define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base) +#define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base) +#define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base) +#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); LVX(n,b,base) +#define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) +#define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base) +#define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base) +#define REST_16VR(n,b,base) REST_8VR(n,b,base); REST_8VR(n+8,b,base) +#define REST_32VR(n,b,base) REST_16VR(n,b,base); REST_16VR(n+16,b,base) + +#ifdef CONFIG_PPC601_SYNC_FIX +#define SYNC \ +BEGIN_FTR_SECTION \ + sync; \ + isync; \ +END_FTR_SECTION_IFSET(CPU_FTR_601) +#define SYNC_601 \ +BEGIN_FTR_SECTION \ + sync; \ +END_FTR_SECTION_IFSET(CPU_FTR_601) +#define ISYNC_601 \ +BEGIN_FTR_SECTION \ + isync; \ +END_FTR_SECTION_IFSET(CPU_FTR_601) +#else +#define SYNC +#define SYNC_601 +#define ISYNC_601 +#endif + +#ifndef CONFIG_SMP +#define TLBSYNC +#else /* CONFIG_SMP */ +/* tlbsync is not implemented on 601 */ +#define TLBSYNC \ +BEGIN_FTR_SECTION \ + tlbsync; \ + sync; \ +END_FTR_SECTION_IFCLR(CPU_FTR_601) +#endif + +/* + * This instruction is not implemented on the PPC 603 or 601; however, on + * the 403GCX and 405GP tlbia IS defined and tlbie is not. + * All of these instructions exist in the 8xx, they have magical powers, + * and they must be used. + */ + +#if !defined(CONFIG_4xx) && !defined(CONFIG_8xx) +#define tlbia \ + li r4,1024; \ + mtctr r4; \ + lis r4,KERNELBASE@h; \ +0: tlbie r4; \ + addi r4,r4,0x1000; \ + bdnz 0b +#endif + +#ifndef CONFIG_PPC_ISERIES +/* + * On APUS (Amiga PowerPC cpu upgrade board), we don't know the + * physical base address of RAM at compile time. + */ +#define tophys(rd,rs) \ +0: addis rd,rs,-KERNELBASE@h; \ + .section ".vtop_fixup","aw"; \ + .align 1; \ + .long 0b; \ + .previous + +#define tovirt(rd,rs) \ +0: addis rd,rs,KERNELBASE@h; \ + .section ".ptov_fixup","aw"; \ + .align 1; \ + .long 0b; \ + .previous +#else /* CONFIG_PPC_ISERIES */ + +#define tophys(rd,rs) \ + mr rd,rs + +#define tovirt(rd,rs) \ + mr rd,rs + +/* Macros to adjust thread priority for iSeries hardware multi-threading */ +#define HMT_LOW or 1,1,1 +#define HMT_MEDIUM or 2,2,2 +#define HMT_HIGH or 3,3,3 + +#endif /* CONFIG_PPC_ISERIES */ + +/* + * On 64-bit cpus, we use the rfid instruction instead of rfi, but + * we then have to make sure we preserve the top 32 bits except for + * the 64-bit mode bit, which we clear. + */ +#ifdef CONFIG_PPC64BRIDGE +#define FIX_SRR1(ra, rb) \ + mr rb,ra; \ + mfmsr ra; \ + clrldi ra,ra,1; /* turn off 64-bit mode */ \ + rldimi ra,rb,0,32 +#define RFI .long 0x4c000024 /* rfid instruction */ +#define MTMSRD(r) .long (0x7c000164 + ((r) << 21)) /* mtmsrd */ +#define CLR_TOP32(r) rlwinm (r),(r),0,0,31 /* clear top 32 bits */ + +#else +#define FIX_SRR1(ra, rb) +#define RFI rfi +#define MTMSRD(r) mtmsr r +#define CLR_TOP32(r) +#endif /* CONFIG_PPC64BRIDGE */ + +#ifdef CONFIG_PPC_ISERIES +#define HMT_LOW or 1,1,1 +#define HMT_MEDIUM or 2,2,2 +#define HMT_HIGH or 3,3,3 +#else /* CONFIG_PPC_ISERIES */ +#define HMT_LOW /* nothing */ +#define HMT_MEDIUM /* nothing */ +#define HMT_HIGH /* nothing */ + +#endif /* CONFIG_PPC_ISERIES */ + +#ifdef CONFIG_IBM405_ERR77 +#define PPC405_ERR77(ra,rb) dcbt ra, rb; +#define PPC405_ERR77_SYNC sync; +#else +#define PPC405_ERR77(ra,rb) +#define PPC405_ERR77_SYNC +#endif + +/* The boring bits... */ + +/* Condition Register Bit Fields */ + +#define cr0 0 +#define cr1 1 +#define cr2 2 +#define cr3 3 +#define cr4 4 +#define cr5 5 +#define cr6 6 +#define cr7 7 + + +/* General Purpose Registers (GPRs) */ + +#define r0 0 +#define r1 1 +#define r2 2 +#define r3 3 +#define r4 4 +#define r5 5 +#define r6 6 +#define r7 7 +#define r8 8 +#define r9 9 +#define r10 10 +#define r11 11 +#define r12 12 +#define r13 13 +#define r14 14 +#define r15 15 +#define r16 16 +#define r17 17 +#define r18 18 +#define r19 19 +#define r20 20 +#define r21 21 +#define r22 22 +#define r23 23 +#define r24 24 +#define r25 25 +#define r26 26 +#define r27 27 +#define r28 28 +#define r29 29 +#define r30 30 +#define r31 31 + + +/* Floating Point Registers (FPRs) */ + +#define fr0 0 +#define fr1 1 +#define fr2 2 +#define fr3 3 +#define fr4 4 +#define fr5 5 +#define fr6 6 +#define fr7 7 +#define fr8 8 +#define fr9 9 +#define fr10 10 +#define fr11 11 +#define fr12 12 +#define fr13 13 +#define fr14 14 +#define fr15 15 +#define fr16 16 +#define fr17 17 +#define fr18 18 +#define fr19 19 +#define fr20 20 +#define fr21 21 +#define fr22 22 +#define fr23 23 +#define fr24 24 +#define fr25 25 +#define fr26 26 +#define fr27 27 +#define fr28 28 +#define fr29 29 +#define fr30 30 +#define fr31 31 + +#define vr0 0 +#define vr1 1 +#define vr2 2 +#define vr3 3 +#define vr4 4 +#define vr5 5 +#define vr6 6 +#define vr7 7 +#define vr8 8 +#define vr9 9 +#define vr10 10 +#define vr11 11 +#define vr12 12 +#define vr13 13 +#define vr14 14 +#define vr15 15 +#define vr16 16 +#define vr17 17 +#define vr18 18 +#define vr19 19 +#define vr20 20 +#define vr21 21 +#define vr22 22 +#define vr23 23 +#define vr24 24 +#define vr25 25 +#define vr26 26 +#define vr27 27 +#define vr28 28 +#define vr29 29 +#define vr30 30 +#define vr31 31 + +/* some stab codes */ +#define N_FUN 36 +#define N_RSYM 64 +#define N_SLINE 68 +#define N_SO 100 diff --git a/include/asm-ppc/pplus.h b/include/asm-ppc/pplus.h new file mode 100644 index 000000000000..fd2bb02d7af1 --- /dev/null +++ b/include/asm-ppc/pplus.h @@ -0,0 +1,94 @@ +/* + * arch/ppc/kernel/pplus.h + * + * Definitions for Motorola MCG Falcon/Raven & HAWK North Bridge & Memory ctlr. + * + * Author: Mark A. Greer + * mgreer@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +#ifndef __ASMPPC_PPLUS_H +#define __ASMPPC_PPLUS_H + +#include <asm/pci-bridge.h> + +/* + * The Falcon/Raven and HAWK have 4 sets of registers: + * 1) PPC Registers which define the mappings from PPC bus to PCI bus, + * etc. + * 2) PCI Registers which define the mappings from PCI bus to PPC bus and the + * MPIC base address. + * 3) MPIC registers + * 4) System Memory Controller (SMC) registers. + */ + +#define PPLUS_RAVEN_VEND_DEV_ID 0x48011057 +#define PPLUS_HAWK_VEND_DEV_ID 0x48031057 + +#define PPLUS_PCI_CONFIG_ADDR_OFF 0x00000cf8 +#define PPLUS_PCI_CONFIG_DATA_OFF 0x00000cfc + +#define PPLUS_MPIC_SIZE 0x00040000U +#define PPLUS_SMC_SIZE 0x00001000U + +/* + * Define PPC register offsets. + */ +#define PPLUS_PPC_XSADD0_OFF 0x40 +#define PPLUS_PPC_XSOFF0_OFF 0x44 +#define PPLUS_PPC_XSADD1_OFF 0x48 +#define PPLUS_PPC_XSOFF1_OFF 0x4c +#define PPLUS_PPC_XSADD2_OFF 0x50 +#define PPLUS_PPC_XSOFF2_OFF 0x54 +#define PPLUS_PPC_XSADD3_OFF 0x58 +#define PPLUS_PPC_XSOFF3_OFF 0x5c + +/* + * Define PCI register offsets. + */ +#define PPLUS_PCI_PSADD0_OFF 0x80 +#define PPLUS_PCI_PSOFF0_OFF 0x84 +#define PPLUS_PCI_PSADD1_OFF 0x88 +#define PPLUS_PCI_PSOFF1_OFF 0x8c +#define PPLUS_PCI_PSADD2_OFF 0x90 +#define PPLUS_PCI_PSOFF2_OFF 0x94 +#define PPLUS_PCI_PSADD3_OFF 0x98 +#define PPLUS_PCI_PSOFF3_OFF 0x9c + +/* + * Define the System Memory Controller (SMC) register offsets. + */ +#define PPLUS_SMC_RAM_A_SIZE_REG_OFF 0x10 +#define PPLUS_SMC_RAM_B_SIZE_REG_OFF 0x11 +#define PPLUS_SMC_RAM_C_SIZE_REG_OFF 0x12 +#define PPLUS_SMC_RAM_D_SIZE_REG_OFF 0x13 +#define PPLUS_SMC_RAM_E_SIZE_REG_OFF 0xc0 /* HAWK Only */ +#define PPLUS_SMC_RAM_F_SIZE_REG_OFF 0xc1 /* HAWK Only */ +#define PPLUS_SMC_RAM_G_SIZE_REG_OFF 0xc2 /* HAWK Only */ +#define PPLUS_SMC_RAM_H_SIZE_REG_OFF 0xc3 /* HAWK Only */ + +#define PPLUS_FALCON_SMC_REG_COUNT 4 +#define PPLUS_HAWK_SMC_REG_COUNT 8 + + + +int pplus_init(struct pci_controller *hose, + uint ppc_reg_base, + ulong processor_pci_mem_start, + ulong processor_pci_mem_end, + ulong processor_pci_io_start, + ulong processor_pci_io_end, + ulong processor_mpic_base); + +unsigned long pplus_get_mem_size(uint smc_base); + +int pplus_mpic_init(unsigned int pci_mem_offset); + +#endif /* __ASMPPC_PPLUS_H */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index f5b55b80e247..0ed0a0070075 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.processor.h 1.31 10/05/01 16:26:22 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef __ASM_PPC_PROCESSOR_H @@ -12,6 +12,7 @@ #define current_text_addr() ({ __label__ _l; _l: &&_l;}) #include <linux/config.h> +#include <linux/stringify.h> #include <asm/ptrace.h> #include <asm/types.h> @@ -136,10 +137,32 @@ #define DBCR_JOI 0x00000002 /* JTAG Serial Outbound Int. Enable */ #define DBCR_JII 0x00000001 /* JTAG Serial Inbound Int. Enable */ #define SPRN_DBCR0 0x3F2 /* Debug Control Register 0 */ -#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ -#define SPRN_DBSR 0x3F0 /* Debug Status Register */ -#define DBSR_IC 0x80000000 /* Instruction Completion */ -#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ +#define DBCR0_EDM 0x80000000 /* External Debug Mode */ +#define DBCR0_IDM 0x40000000 /* Internal Debug Mode */ +#define DBCR0_RST 0x30000000 /* all the bits in the RST field */ +#define DBCR0_RST_SYSTEM 0x30000000 /* System Reset */ +#define DBCR0_RST_CHIP 0x20000000 /* Chip Reset */ +#define DBCR0_RST_CORE 0x10000000 /* Core Reset */ +#define DBCR0_RST_NONE 0x00000000 /* No Reset */ +#define DBCR0_IC 0x08000000 /* Instruction Completion */ +#define DBCR0_BT 0x04000000 /* Branch Taken */ +#define DBCR0_EDE 0x02000000 /* Exception Debug Event */ +#define DBCR0_TDE 0x01000000 /* TRAP Debug Event */ +#define DBCR0_IA1 0x00800000 /* Instr Addr compare 1 enable */ +#define DBCR0_IA2 0x00400000 /* Instr Addr compare 2 enable */ +#define DBCR0_IA12 0x00200000 /* Instr Addr 1-2 range enable */ +#define DBCR0_IA12X 0x00100000 /* Instr Addr 1-2 range eXclusive */ +#define DBCR0_IA3 0x00080000 /* Instr Addr compare 3 enable */ +#define DBCR0_IA4 0x00040000 /* Instr Addr compare 4 enable */ +#define DBCR0_IA34 0x00020000 /* Instr Addr 3-4 range Enable */ +#define DBCR0_IA34X 0x00010000 /* Instr Addr 3-4 range eXclusive */ +#define DBCR0_IA12T 0x00008000 /* Instr Addr 1-2 range Toggle */ +#define DBCR0_IA34T 0x00004000 /* Instr Addr 3-4 range Toggle */ +#define DBCR0_FT 0x00000001 /* Freeze Timers on debug event */ +#define SPRN_DBCR1 0x3BD /* Debug Control Register 1 */ +#define SPRN_DBSR 0x3F0 /* Debug Status Register */ +#define DBSR_IC 0x80000000 /* Instruction Completion */ +#define DBSR_TIE 0x10000000 /* Trap Instruction debug Event */ #define SPRN_DCCR 0x3FA /* Data Cache Cacheability Register */ #define DCCR_NOCACHE 0 /* Noncacheable */ #define DCCR_CACHE 1 /* Cacheable */ @@ -191,12 +214,17 @@ #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ #define HID0_SBCLK (1<<27) #define HID0_EICE (1<<26) +#define HID0_TBEN (1<<26) /* Timebase enable - 7450 */ #define HID0_ECLK (1<<25) #define HID0_PAR (1<<24) +#define HID0_STEN (1<<24) /* S/W Tablewalk enable - 7450 */ #define HID0_DOZE (1<<23) #define HID0_NAP (1<<22) #define HID0_SLEEP (1<<21) #define HID0_DPM (1<<20) +#define HID0_BHTCLR (1<<18) /* Clear branch history table - 7450 */ +#define HID0_XAEN (1<<17) /* Extended addressing enable - 7450 */ +#define HID0_NHR (1<<16) /* Not hard reset (software bit-7450)*/ #define HID0_ICE (1<<15) /* Instruction Cache Enable */ #define HID0_DCE (1<<14) /* Data Cache Enable */ #define HID0_ILOCK (1<<13) /* Instruction Cache Lock */ @@ -207,11 +235,23 @@ #define HID0_SGE (1<<7) /* Store Gathering Enable */ #define HID0_SIED (1<<7) /* Serial Instr. Execution [Disable] */ #define HID0_DFCA (1<<6) /* Data Cache Flush Assist */ -#define HID0_BTIC (1<<5) /* Branch Target Instruction Cache Enable */ +#define HID0_BTIC (1<<5) /* Branch Target Instr Cache Enable */ +#define HID0_LRSTK (1<<4) /* Link Stack enable - 7450 */ #define HID0_ABE (1<<3) /* Address Broadcast Enable */ +#define HID0_FOLD (1<<3) /* Branch Folding enable - 7450 */ #define HID0_BHTE (1<<2) /* Branch History Table Enable */ #define HID0_BTCD (1<<1) /* Branch target cache disable */ +#define HID0_NOPDST (1<<1) /* No-op dst, dstt, etc. instr. */ +#define HID0_NOPTI (1<<0) /* No-op dcbt and dcbst instr. */ + #define SPRN_HID1 0x3F1 /* Hardware Implementation Register 1 */ +#define HID1_EMCP (1<<31) /* 7450 Machine Check Pin Enable */ +#define HID1_PC0 (1<<16) /* 7450 PLL_CFG[0] */ +#define HID1_PC1 (1<<15) /* 7450 PLL_CFG[1] */ +#define HID1_PC2 (1<<14) /* 7450 PLL_CFG[2] */ +#define HID1_PC3 (1<<13) /* 7450 PLL_CFG[3] */ +#define HID1_SYNCBE (1<<11) /* 7450 ABE for sync, eieio */ +#define HID1_ABE (1<<10) /* 7450 Address Broadcast Enable */ #define SPRN_IABR 0x3F2 /* Instruction Address Breakpoint Register */ #define SPRN_IAC1 0x3F4 /* Instruction Address Compare 1 */ #define SPRN_IAC2 0x3F5 /* Instruction Address Compare 2 */ @@ -229,6 +269,10 @@ #define SPRN_ICDBDR 0x3D3 /* Instruction Cache Debug Data Register */ #define SPRN_ICMP 0x3D5 /* Instruction TLB Compare Register */ #define SPRN_ICTC 0x3FB /* Instruction Cache Throttling Control Reg */ +#define SPRN_ICTRL 0x3F3 /* 1011 7450 icache and interrupt ctrl */ +#define ICTRL_EICE 0x08000000 /* enable icache parity errs */ +#define ICTRL_EDCE 0x04000000 /* enable dcache parity errs */ +#define ICTRL_EICP 0x00000100 /* enable icache par. check */ #define SPRN_IMISS 0x3D4 /* Instruction TLB Miss Register */ #define SPRN_IMMR 0x27E /* Internal Memory Map Register */ #define SPRN_L2CR 0x3F9 /* Level 2 Cache Control Regsiter */ @@ -261,6 +305,13 @@ #define L2CR_L2DF 0x00004000 /* L2 differential clock */ #define L2CR_L2BYP 0x00002000 /* L2 DLL bypass */ #define L2CR_L2IP 0x00000001 /* L2 GI in progress */ +#define SPRN_L2CR2 0x3f8 +#define SPRN_L3CR 0x3FA /* Level 3 Cache Control Regsiter (7450) */ +#define L3CR_L3E 0x80000000 /* L3 enable */ +#define SPRN_MSSCR0 0x3f6 /* Memory Subsystem Control Register 0 */ +#define SPRN_MSSSR0 0x3f7 /* Memory Subsystem Status Register 1 */ +#define SPRN_LDSTCR 0x3f8 /* Load/Store control register */ +#define SPRN_LDSTDB 0x3f4 /* */ #define SPRN_LR 0x008 /* Link Register */ #define SPRN_MMCR0 0x3B8 /* Monitor Mode Control Register 0 */ #define SPRN_MMCR1 0x3BC /* Monitor Mode Control Register 1 */ @@ -275,6 +326,8 @@ #define SPRN_PMC2 0x3BA /* Performance Counter Register 2 */ #define SPRN_PMC3 0x3BD /* Performance Counter Register 3 */ #define SPRN_PMC4 0x3BE /* Performance Counter Register 4 */ +#define SPRN_PTEHI 0x3D5 /* 981 7450 PTE HI word (S/W TLB load) */ +#define SPRN_PTELO 0x3D6 /* 982 7450 PTE LO word (S/W TLB load) */ #define SPRN_PVR 0x11F /* Processor Version Register */ #define SPRN_RPA 0x3D6 /* Required Physical Address Register */ #define SPRN_SDA 0x3BF /* Sampled Data Address Register */ @@ -295,17 +348,23 @@ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ #define SPRN_SRR3 0x3DF /* Save/Restore Register 3 */ +#define SPRN_TBHI 0x3DC /* Time Base High (4xx) */ +#define SPRN_TBHU 0x3CC /* Time Base High User-mode (4xx) */ +#define SPRN_TBLO 0x3DD /* Time Base Low (4xx) */ +#define SPRN_TBLU 0x3CD /* Time Base Low User-mode (4xx) */ #define SPRN_TBRL 0x10C /* Time Base Read Lower Register (user, R/O) */ #define SPRN_TBRU 0x10D /* Time Base Read Upper Register (user, R/O) */ -#define SPRN_TBWL 0x11C /* Time Base Lower Register (supervisor, R/W) */ -#define SPRN_TBWU 0x11D /* Time Base Upper Register (supervisor, R/W) */ +#define SPRN_TBWL 0x11C /* Time Base Lower Register (super, R/W) */ +#define SPRN_TBWU 0x11D /* Time Base Upper Register (super, R/W) */ #define SPRN_TCR 0x3DA /* Timer Control Register */ #define TCR_WP(x) (((x)&0x3)<<30) /* WDT Period */ +#define TCR_WP_MASK TCR_WP(3) #define WP_2_17 0 /* 2^17 clocks */ #define WP_2_21 1 /* 2^21 clocks */ #define WP_2_25 2 /* 2^25 clocks */ #define WP_2_29 3 /* 2^29 clocks */ #define TCR_WRC(x) (((x)&0x3)<<28) /* WDT Reset Control */ +#define TCR_WRC_MASK TCR_WRC(3) #define WRC_NONE 0 /* No reset will occur */ #define WRC_CORE 1 /* Core reset will occur */ #define WRC_CHIP 2 /* Chip reset will occur */ @@ -313,6 +372,7 @@ #define TCR_WIE 0x08000000 /* WDT Interrupt Enable */ #define TCR_PIE 0x04000000 /* PIT Interrupt Enable */ #define TCR_FP(x) (((x)&0x3)<<24) /* FIT Period */ +#define TCR_FP_MASK TCR_FP(3) #define FP_2_9 0 /* 2^9 clocks */ #define FP_2_13 1 /* 2^13 clocks */ #define FP_2_17 2 /* 2^17 clocks */ @@ -331,6 +391,7 @@ #define SPRN_THRM2 0x3FD /* Thermal Management Register 2 */ #define SPRN_THRM3 0x3FE /* Thermal Management Register 3 */ #define THRM3_E (1<<0) +#define SPRN_TLBMISS 0x3D4 /* 980 7450 TLB Miss Register */ #define SPRN_TSR 0x3D8 /* Timer Status Register */ #define TSR_ENW 0x80000000 /* Enable Next Watchdog */ #define TSR_WIS 0x40000000 /* WDT Interrupt Status */ @@ -387,6 +448,7 @@ #define IMISS SPRN_IMISS /* Instruction TLB Miss Register */ #define IMMR SPRN_IMMR /* PPC 860/821 Internal Memory Map Register */ #define L2CR SPRN_L2CR /* PPC 750 L2 control register */ +#define L3CR SPRN_L3CR /* PPC 7450 L3 Cache control register */ #define LR SPRN_LR #define PVR SPRN_PVR /* Processor Version */ #define RPA SPRN_RPA /* Required Physical Address Register */ @@ -445,7 +507,9 @@ #define PVR_403GC 0x00200200 #define PVR_403GCX 0x00201400 #define PVR_405GP 0x40110000 -#define PVR_STB03XXX 0x40310000 +#define PVR_STB03XXX 0x40310000 +#define PVR_NP405H 0x41410000 +#define PVR_NP405L 0x41610000 #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 @@ -462,6 +526,7 @@ #define PVR_750P PVR_740P #define PVR_7400 0x000C0000 #define PVR_7410 0x800C0000 +#define PVR_7450 0x80000000 /* * For the 8xx processors, all of them report the same PVR family for * the PowerPC core. The various versions of these processors must be @@ -473,6 +538,7 @@ #define PVR_850 PVR_821 #define PVR_860 PVR_821 #define PVR_8240 0x00810100 +#define PVR_8245 0x80811014 #define PVR_8260 PVR_8240 /* We only need to define a new _MACH_xxx for machines which are part of @@ -494,6 +560,7 @@ #define _CHRP_IBM 0x05 /* IBM chrp, the longtrail and longtrail 2 */ #define _GLOBAL(n)\ + .stabs __stringify(n:F-1),N_FUN,0,0,n;\ .globl n;\ n: @@ -502,11 +569,6 @@ n: #define stringify(s) tostring(s) #define tostring(s) #s -#define mfdcr(rn) ({unsigned int rval; \ - asm volatile("mfdcr %0," stringify(rn) \ - : "=r" (rval)); rval;}) -#define mtdcr(rn, v) asm volatile("mtdcr " stringify(rn) ",%0" : : "r" (v)) - #define mfmsr() ({unsigned int rval; \ asm volatile("mfmsr %0" : "=r" (rval)); rval;}) #define mtmsr(v) asm volatile("mtmsr %0" : : "r" (v)) @@ -516,6 +578,35 @@ n: : "=r" (rval)); rval;}) #define mtspr(rn, v) asm volatile("mtspr " stringify(rn) ",%0" : : "r" (v)) +#define mfsrin(v) ({unsigned int rval; \ + asm volatile("mfsrin %0,%1" : "=r" (rval) : "r" (v)); \ + rval;}) + +#define proc_trap() asm volatile("trap") + +#ifdef CONFIG_PPC_ISERIES +/* Macros for adjusting thread priority (hardware multi-threading) */ +#define HMT_PRIO_LOW "or 1,1,1\n" /* low prio, used for spin loops */ +#define HMT_PRIO_MED "or 2,2,2\n" /* medium prio, for normal code */ +#define HMT_PRIO_HIGH "or 3,3,3\n" /* high priority */ + +#define HMT_low() asm volatile("or 1,1,1") +#define HMT_medium() asm volatile("or 2,2,2") +#define HMT_high() asm volatile("or 3,3,3") + +/* iSeries CTRL register (for runlatch) */ + +#define CTRLT 0x098 +#define CTRLF 0x088 +#define RUNLATCH 0x0001 + +#else /* !CONFIG_PPC_ISERIES */ +#define HMT_PRIO_LOW +#define HMT_PRIO_MED +#define HMT_PRIO_HIGH + +#endif /* CONFIG_PPC_ISERIES */ + /* Segment Registers */ #define SR0 0 @@ -580,7 +671,11 @@ extern struct task_struct *last_task_used_altivec; * as soon as I get around to remapping the io areas with the BATs * to match the mac we can raise this. -- Cort */ +#ifdef CONFIG_TASK_SIZE_BOOL +#define TASK_SIZE CONFIG_TASK_SIZE +#else #define TASK_SIZE (0x80000000UL) +#endif /* This decides where the kernel will search for a free chunk of vm * space during mmap's. @@ -593,10 +688,10 @@ typedef struct { struct thread_struct { unsigned long ksp; /* Kernel stack pointer */ - unsigned long wchan; /* Event task is sleeping on */ struct pt_regs *regs; /* Pointer to saved register state */ mm_segment_t fs; /* for get_fs() validation */ void *pgdir; /* root of page-table tree */ + int fpexc_mode; /* floating-point exception mode */ signed long last_syscall; double fpr[32]; /* Complete floating point set */ unsigned long fpscr_pad; /* fpr ... fpscr must be contiguous */ @@ -611,13 +706,9 @@ struct thread_struct { #define INIT_SP (sizeof(init_stack) + (unsigned long) &init_stack) #define INIT_THREAD { \ - INIT_SP, /* ksp */ \ - 0, /* wchan */ \ - 0, /* regs */ \ - KERNEL_DS, /*fs*/ \ - swapper_pg_dir, /* pgdir */ \ - 0, /* last_syscall */ \ - {0}, 0, 0 \ + ksp: INIT_SP, \ + fs: KERNEL_DS, \ + pgdir: swapper_pg_dir, \ } /* @@ -636,25 +727,31 @@ unsigned long get_wchan(struct task_struct *p); #define KSTK_EIP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->nip: 0) #define KSTK_ESP(tsk) ((tsk)->thread.regs? (tsk)->thread.regs->gpr[1]: 0) -/* - * NOTE! The task struct and the stack go together - */ -#define THREAD_SIZE (2*PAGE_SIZE) -#define alloc_task_struct() \ - ((struct task_struct *) __get_free_pages(GFP_KERNEL,1)) -#define free_task_struct(p) free_pages((unsigned long)(p),1) -#define get_task_struct(tsk) atomic_inc(&virt_to_page(tsk)->count) +/* Get/set floating-point exception mode */ +#define GET_FP_EXC_MODE(tsk) __unpack_fe01((tsk)->thread.fpexc_mode) +#define SET_FP_EXC_MODE(tsk, val) set_fpexc_mode((tsk), (val)) + +extern int set_fpexc_mode(struct task_struct *tsk, unsigned int val); + +static inline unsigned int __unpack_fe01(unsigned int msr_bits) +{ + return ((msr_bits & MSR_FE0) >> 10) | ((msr_bits & MSR_FE1) >> 8); +} + +static inline unsigned int __pack_fe01(unsigned int fpmode) +{ + return ((fpmode << 10) & MSR_FE0) | ((fpmode << 8) & MSR_FE1); +} /* in process.c - for early bootup debug -- Cort */ int ll_printk(const char *, ...); void ll_puts(const char *); -#define init_task (init_task_union.task) -#define init_stack (init_task_union.stack) - /* In misc.c */ void _nmask_and_or_msr(unsigned long nmask, unsigned long or_val); +#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac) + #define cpu_relax() do { } while (0) /* @@ -678,7 +775,5 @@ extern inline void prefetchw(const void *x) #endif /* !__ASSEMBLY__ */ -#define have_of (_machine == _MACH_chrp || _machine == _MACH_Pmac) - #endif /* __ASM_PPC_PROCESSOR_H */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/prom.h b/include/asm-ppc/prom.h index c27ff56c059a..99a9980d3cfe 100644 --- a/include/asm-ppc/prom.h +++ b/include/asm-ppc/prom.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.prom.h 1.19 08/17/01 15:23:17 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * Definitions for talking to the Open Firmware PROM on @@ -86,6 +86,10 @@ extern void prom_get_irq_senses(unsigned char *, int, int); extern int prom_n_addr_cells(struct device_node* np); extern int prom_n_size_cells(struct device_node* np); +extern struct resource* +request_OF_resource(struct device_node* node, int index, const char* name_postfix); +extern int release_OF_resource(struct device_node* node, int index); + extern void print_properties(struct device_node *node); extern int call_rtas(const char *service, int nargs, int nret, unsigned long *outputs, ...); @@ -103,10 +107,11 @@ extern int call_rtas(const char *service, int nargs, int nret, * pointer values. See arch/ppc/kernel/prom.c for how these are used. */ extern unsigned long reloc_offset(void); +extern unsigned long add_reloc_offset(unsigned long); +extern unsigned long sub_reloc_offset(unsigned long); -#define PTRRELOC(x) ((typeof(x))((unsigned long)(x) + offset)) -#define PTRUNRELOC(x) ((typeof(x))((unsigned long)(x) - offset)) -#define RELOC(x) (*PTRRELOC(&(x))) +#define PTRRELOC(x) ((typeof(x))add_reloc_offset((unsigned long)(x))) +#define PTRUNRELOC(x) ((typeof(x))sub_reloc_offset((unsigned long)(x))) #endif /* _PPC_PROM_H */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/ptrace.h b/include/asm-ppc/ptrace.h index f2eddc88dce7..e8e7aa3d0b99 100644 --- a/include/asm-ppc/ptrace.h +++ b/include/asm-ppc/ptrace.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.ptrace.h 1.5 05/17/01 18:14:25 cort + * BK Id: %F% %I% %G% %U% %#% */ #ifndef _PPC_PTRACE_H #define _PPC_PTRACE_H @@ -39,6 +39,9 @@ struct pt_regs { }; #endif +/* iSeries uses mq field for soft enable flag */ +#define softEnable mq + #ifdef __KERNEL__ #define STACK_FRAME_OVERHEAD 16 /* size of minimum stack frame */ @@ -103,5 +106,8 @@ struct pt_regs { #define PT_FPR31 (PT_FPR0 + 2*31) #define PT_FPSCR (PT_FPR0 + 2*32 + 1) -#endif +/* Get/set all the altivec registers vr0..vr31, vscr, vrsave, in one go */ +#define PTRACE_GETVRREGS 18 +#define PTRACE_SETVRREGS 19 +#endif diff --git a/include/asm-ppc/rpxclassic.h b/include/asm-ppc/rpxclassic.h deleted file mode 100644 index ec65383b1c43..000000000000 --- a/include/asm-ppc/rpxclassic.h +++ /dev/null @@ -1,104 +0,0 @@ -/* - * BK Id: SCCS/s.rpxclassic.h 1.11 08/17/01 15:23:17 paulus - */ - -/* - * A collection of structures, addresses, and values associated with - * the RPCG RPX-Classic board. Copied from the RPX-Lite stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __MACH_RPX_DEFS -#define __MACH_RPX_DEFS - -#include <linux/config.h> - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -extern bd_t m8xx_board_info; - -/* Memory map is configured by the PROM startup. - * We just map a few things we need. The CSR is actually 4 byte-wide - * registers that can be accessed as 8-, 16-, or 32-bit values. - */ -#define PCI_ISA_IO_ADDR ((unsigned)0x80000000) -#define PCI_ISA_IO_SIZE ((uint)(512 * 1024 * 1024)) -#define PCI_ISA_MEM_ADDR ((unsigned)0xc0000000) -#define PCI_ISA_MEM_SIZE ((uint)(512 * 1024 * 1024)) -#define RPX_CSR_ADDR ((uint)0xfa400000) -#define RPX_CSR_SIZE ((uint)(4 * 1024)) -#define IMAP_ADDR ((uint)0xfa200000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCI_CSR_ADDR ((uint)0x80000000) -#define PCI_CSR_SIZE ((uint)(64 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0xe0000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) -#define PCMCIA_IO_ADDR ((uint)0xe4000000) -#define PCMCIA_IO_SIZE ((uint)(4 * 1024)) -#define PCMCIA_ATTRB_ADDR ((uint)0xe8000000) -#define PCMCIA_ATTRB_SIZE ((uint)(4 * 1024)) - -/* Things of interest in the CSR. -*/ -#define BCSR0_ETHEN ((uint)0x80000000) -#define BCSR0_ETHLPBK ((uint)0x40000000) -#define BCSR0_COLTESTDIS ((uint)0x20000000) -#define BCSR0_FULLDPLXDIS ((uint)0x10000000) -#define BCSR0_ENFLSHSEL ((uint)0x04000000) -#define BCSR0_FLASH_SEL ((uint)0x02000000) -#define BCSR0_ENMONXCVR ((uint)0x01000000) - -#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) /* CLLF */ -#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) /* CLLF */ -#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) /* CLLF */ - -#define BCSR1_IPB5SEL ((uint)0x00100000) -#define BCSR1_PCVCTL4 ((uint)0x00080000) -#define BCSR1_PCVCTL5 ((uint)0x00040000) -#define BCSR1_PCVCTL6 ((uint)0x00020000) -#define BCSR1_PCVCTL7 ((uint)0x00010000) - -#define BCSR2_EN232XCVR ((uint)0x00008000) -#define BCSR2_QSPACESEL ((uint)0x00004000) -#define BCSR2_FETHLEDMODE ((uint)0x00000800) /* CLLF */ - -#if defined(CONFIG_HTDMSOUND) -#include <asm/rpxhiox.h> -#endif - -/* define IO_BASE for pcmcia, CLLF only */ -#if !defined(CONFIG_PCI) -#define _IO_BASE 0x80000000 -#define _IO_BASE_SIZE 0x1000 - -/* for pcmcia sandisk */ -#ifdef CONFIG_IDE -#define MAX_HWIFS 1 -#define ide_request_irq(irq,hand,flg,dev,id) request_8xxirq((irq),(hand),(flg),(dev),(id)) -#endif -#endif - -/* Interrupt level assignments. -*/ -#define FEC_INTERRUPT SIU_LEVEL1 /* FEC interrupt */ - -#endif /* !__ASSEMBLY__ */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/rpxhiox.h b/include/asm-ppc/rpxhiox.h deleted file mode 100644 index 848e4eb6fd1e..000000000000 --- a/include/asm-ppc/rpxhiox.h +++ /dev/null @@ -1,45 +0,0 @@ -/* - * BK Id: SCCS/s.rpxhiox.h 1.3 05/17/01 18:14:25 cort - */ - -/* - * The Embedded Planet HIOX expansion card definitions. - * There were a few different versions of these cards, but only - * the one that escaped real production is defined here. - * - * Copyright (c) 2000 Dan Malek (dmalek@jlc.net) - */ -#ifndef __MACH_RPX_HIOX_DEFS -#define __MACH_RPX_HIOX_DEFS - -#define HIOX_CSR_ADDR ((uint)0xfac00000) -#define HIOX_CSR_SIZE ((uint)(4 * 1024)) -#define HIOX_CSR0_ADDR HIOX_CSR_ADDR -#define HIOX_CSR4_ADDR ((uint)0xfac00004) - -#define HIOX_CSR0_DEFAULT ((uint)0x380f3c00) -#define HIOX_CSR0_ENSCC2 ((uint)0x80000000) -#define HIOX_CSR0_ENSMC2 ((uint)0x04000000) -#define HIOX_CSR0_ENVDOCLK ((uint)0x02000000) -#define HIOX_CSR0_VDORST_HL ((uint)0x01000000) -#define HIOX_CSR0_RS232SEL ((uint)0x0000c000) -#define HIOX_CSR0_SCC3SEL ((uint)0x0000c000) -#define HIOX_CSR0_SMC1SEL ((uint)0x00008000) -#define HIOX_CSR0_SCC1SEL ((uint)0x00004000) -#define HIOX_CSR0_ENTOUCH ((uint)0x00000080) -#define HIOX_CSR0_PDOWN100 ((uint)0x00000060) -#define HIOX_CSR0_PDOWN10 ((uint)0x00000040) -#define HIOX_CSR0_PDOWN1 ((uint)0x00000020) -#define HIOX_CSR0_TSELSPI ((uint)0x00000010) -#define HIOX_CSR0_TIRQSTAT ((uint)0x00000008) -#define HIOX_CSR4_DEFAULT ((uint)0x00000000) -#define HIOX_CSR4_ENTIRQ2 ((uint)0x20000000) -#define HIOX_CSR4_ENTIRQ3 ((uint)0x10000000) -#define HIOX_CSR4_ENAUDIO ((uint)0x00000080) -#define HIOX_CSR4_RSTAUDIO ((uint)0x00000040) /* 0 == reset */ -#define HIOX_CSR4_AUDCLKHI ((uint)0x00000020) -#define HIOX_CSR4_AUDSPISEL ((uint)0x00000010) -#define HIOX_CSR4_AUDIRQSTAT ((uint)0x00000008) -#define HIOX_CSR4_AUDCLKSEL ((uint)0x00000007) - -#endif diff --git a/include/asm-ppc/rpxlite.h b/include/asm-ppc/rpxlite.h deleted file mode 100644 index 2f24dcc74ab2..000000000000 --- a/include/asm-ppc/rpxlite.h +++ /dev/null @@ -1,84 +0,0 @@ -/* - * BK Id: SCCS/s.rpxlite.h 1.11 08/17/01 15:23:17 paulus - */ - -/* - * A collection of structures, addresses, and values associated with - * the RPCG RPX-Lite board. Copied from the MBX stuff. - * - * Copyright (c) 1998 Dan Malek (dmalek@jlc.net) - */ -#ifdef __KERNEL__ -#ifndef __MACH_RPX_DEFS -#define __MACH_RPX_DEFS - -#include <linux/config.h> - -#ifndef __ASSEMBLY__ -/* A Board Information structure that is given to a program when - * prom starts it up. - */ -typedef struct bd_info { - unsigned int bi_memstart; /* Memory start address */ - unsigned int bi_memsize; /* Memory (end) size in bytes */ - unsigned int bi_intfreq; /* Internal Freq, in Hz */ - unsigned int bi_busfreq; /* Bus Freq, in Hz */ - unsigned char bi_enetaddr[6]; - unsigned int bi_baudrate; -} bd_t; - -extern bd_t m8xx_board_info; - -/* Memory map is configured by the PROM startup. - * We just map a few things we need. The CSR is actually 4 byte-wide - * registers that can be accessed as 8-, 16-, or 32-bit values. - */ -#define RPX_CSR_ADDR ((uint)0xfa400000) -#define RPX_CSR_SIZE ((uint)(4 * 1024)) -#define IMAP_ADDR ((uint)0xfa200000) -#define IMAP_SIZE ((uint)(64 * 1024)) -#define PCMCIA_MEM_ADDR ((uint)0x04000000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) -#define PCMCIA_IO_ADDR ((uint)0x04400000) -#define PCMCIA_IO_SIZE ((uint)(4 * 1024)) - -/* Things of interest in the CSR. -*/ -#define BCSR0_ETHEN ((uint)0x80000000) -#define BCSR0_ETHLPBK ((uint)0x40000000) -#define BCSR0_COLTESTDIS ((uint)0x20000000) -#define BCSR0_FULLDPLXDIS ((uint)0x10000000) -#define BCSR0_LEDOFF ((uint)0x08000000) -#define BCSR0_USBDISABLE ((uint)0x04000000) -#define BCSR0_USBHISPEED ((uint)0x02000000) -#define BCSR0_USBPWREN ((uint)0x01000000) -#define BCSR0_PCMCIAVOLT ((uint)0x000f0000) -#define BCSR0_PCMCIA3VOLT ((uint)0x000a0000) -#define BCSR0_PCMCIA5VOLT ((uint)0x00060000) - -#define BCSR1_IPB5SEL ((uint)0x00100000) -#define BCSR1_PCVCTL4 ((uint)0x00080000) -#define BCSR1_PCVCTL5 ((uint)0x00040000) -#define BCSR1_PCVCTL6 ((uint)0x00020000) -#define BCSR1_PCVCTL7 ((uint)0x00010000) - -#if defined(CONFIG_HTDMSOUND) -#include <asm/rpxhiox.h> -#endif -#endif /* !__ASSEMBLY__ */ - -/* define IO_BASE for pcmcia */ -#define _IO_BASE 0x80000000 -#define _IO_BASE_SIZE 0x1000 - -#ifdef CONFIG_IDE -#define MAX_HWIFS 1 -#define ide_request_irq(irq,hand,flg,dev,id) request_8xxirq((irq),(hand),(flg),(dev),(id)) -#endif - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/scatterlist.h b/include/asm-ppc/scatterlist.h index 80be401b513f..5f34a504e038 100644 --- a/include/asm-ppc/scatterlist.h +++ b/include/asm-ppc/scatterlist.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.scatterlist.h 1.9 10/15/01 22:51:33 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _PPC_SCATTERLIST_H @@ -8,11 +8,10 @@ #include <asm/dma.h> struct scatterlist { - struct page * page; - unsigned int offset; - - dma_addr_t dma_address; /* phys/bus dma address */ - unsigned int length; /* length */ + struct page *page; + unsigned int offset; + dma_addr_t dma_address; + unsigned int length; }; /* diff --git a/include/asm-ppc/serial.h b/include/asm-ppc/serial.h index f130fba59516..321294003be3 100644 --- a/include/asm-ppc/serial.h +++ b/include/asm-ppc/serial.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.serial.h 1.15 10/23/01 08:09:35 trini + * BK Id: %F% %I% %G% %U% %#% */ /* * include/asm-ppc/serial.h @@ -11,130 +11,43 @@ #include <linux/config.h> -#ifdef CONFIG_GEMINI -#include <asm/gemini_serial.h> +#if defined(CONFIG_EV64260) +#include <platforms/ev64260.h> +#elif defined(CONFIG_GEMINI) +#include <platforms/gemini_serial.h> +#elif defined(CONFIG_POWERPMC250) +#include <platforms/powerpmc250_serial.h> +#elif defined(CONFIG_LOPEC) +#include <platforms/lopec_serial.h> +#elif defined(CONFIG_MCPN765) +#include <platforms/mcpn765_serial.h> +#elif defined(CONFIG_MVME5100) +#include <platforms/mvme5100_serial.h> +#elif defined(CONFIG_PRPMC750) +#include <platforms/prpmc750_serial.h> +#elif defined(CONFIG_PRPMC800) +#include <platforms/prpmc800_serial.h> +#elif defined(CONFIG_SANDPOINT) +#include <platforms/sandpoint_serial.h> +#elif defined(CONFIG_SPRUCE) +#include <platforms/spruce_serial.h> +#elif defined(CONFIG_ZX4500) +#include <platforms/zx4500_serial.h> #elif defined(CONFIG_4xx) -#include <asm/ppc4xx_serial.h> +#include <asm/ibm4xx.h> #else /* - * This assumes you have a 1.8432 MHz clock for your UART. - * - * It'd be nice if someone built a serial card with a 24.576 MHz - * clock, since the 16550A is capable of handling a top speed of 1.5 - * megabits/second; but this requires the faster clock. + * XXX Assume for now it has PC-style ISA serial ports. + * This is true for PReP and CHRP at least. */ -#define BASE_BAUD ( 1843200 / 16 ) +#include <asm/pc_serial.h> +#include <asm/processor.h> -#ifdef CONFIG_SERIAL_MANY_PORTS -#define RS_TABLE_SIZE 64 -#else -#define RS_TABLE_SIZE 4 -#endif - -/* Standard COM flags (except for COM4, because of the 8514 problem) */ -#ifdef CONFIG_SERIAL_DETECT_IRQ -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ) -#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ) -#else -#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST) -#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF -#endif - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define FOURPORT_FLAGS ASYNC_FOURPORT -#define ACCENT_FLAGS 0 -#define BOCA_FLAGS 0 -#define HUB6_FLAGS 0 -#endif - -/* - * The following define the access methods for the HUB6 card. All - * access is through two ports for all 24 possible chips. The card is - * selected through the high 2 bits, the port on that card with the - * "middle" 3 bits, and the register on that port with the bottom - * 3 bits. - * - * While the access port and interrupt is configurable, the default - * port locations are 0x302 for the port control register, and 0x303 - * for the data read/write register. Normally, the interrupt is at irq3 - * but can be anything from 3 to 7 inclusive. Note that using 3 will - * require disabling com2. - */ - -#define C_P(card,port) (((card)<<6|(port)<<3) + 1) - -#define STD_SERIAL_PORT_DEFNS \ - /* UART CLK PORT IRQ FLAGS */ \ - { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \ - { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS }, /* ttyS1 */ \ - { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS }, /* ttyS2 */ \ - { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS }, /* ttyS3 */ - - -#ifdef CONFIG_SERIAL_MANY_PORTS -#define EXTRA_SERIAL_PORT_DEFNS \ - { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \ - { 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \ - { 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \ - { 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \ - { 0, BASE_BAUD, 0x2A0, 5, FOURPORT_FLAGS }, /* ttyS8 */ \ - { 0, BASE_BAUD, 0x2A8, 5, FOURPORT_FLAGS }, /* ttyS9 */ \ - { 0, BASE_BAUD, 0x2B0, 5, FOURPORT_FLAGS }, /* ttyS10 */ \ - { 0, BASE_BAUD, 0x2B8, 5, FOURPORT_FLAGS }, /* ttyS11 */ \ - { 0, BASE_BAUD, 0x330, 4, ACCENT_FLAGS }, /* ttyS12 */ \ - { 0, BASE_BAUD, 0x338, 4, ACCENT_FLAGS }, /* ttyS13 */ \ - { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS14 (spare) */ \ - { 0, BASE_BAUD, 0x000, 0, 0 }, /* ttyS15 (spare) */ \ - { 0, BASE_BAUD, 0x100, 12, BOCA_FLAGS }, /* ttyS16 */ \ - { 0, BASE_BAUD, 0x108, 12, BOCA_FLAGS }, /* ttyS17 */ \ - { 0, BASE_BAUD, 0x110, 12, BOCA_FLAGS }, /* ttyS18 */ \ - { 0, BASE_BAUD, 0x118, 12, BOCA_FLAGS }, /* ttyS19 */ \ - { 0, BASE_BAUD, 0x120, 12, BOCA_FLAGS }, /* ttyS20 */ \ - { 0, BASE_BAUD, 0x128, 12, BOCA_FLAGS }, /* ttyS21 */ \ - { 0, BASE_BAUD, 0x130, 12, BOCA_FLAGS }, /* ttyS22 */ \ - { 0, BASE_BAUD, 0x138, 12, BOCA_FLAGS }, /* ttyS23 */ \ - { 0, BASE_BAUD, 0x140, 12, BOCA_FLAGS }, /* ttyS24 */ \ - { 0, BASE_BAUD, 0x148, 12, BOCA_FLAGS }, /* ttyS25 */ \ - { 0, BASE_BAUD, 0x150, 12, BOCA_FLAGS }, /* ttyS26 */ \ - { 0, BASE_BAUD, 0x158, 12, BOCA_FLAGS }, /* ttyS27 */ \ - { 0, BASE_BAUD, 0x160, 12, BOCA_FLAGS }, /* ttyS28 */ \ - { 0, BASE_BAUD, 0x168, 12, BOCA_FLAGS }, /* ttyS29 */ \ - { 0, BASE_BAUD, 0x170, 12, BOCA_FLAGS }, /* ttyS30 */ \ - { 0, BASE_BAUD, 0x178, 12, BOCA_FLAGS }, /* ttyS31 */ -#else -#define EXTRA_SERIAL_PORT_DEFNS -#endif - -/* You can have up to four HUB6's in the system, but I've only - * included two cards here for a total of twelve ports. - */ -#if (defined(CONFIG_HUB6) && defined(CONFIG_SERIAL_MANY_PORTS)) -#define HUB6_SERIAL_PORT_DFNS \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,0) }, /* ttyS32 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,1) }, /* ttyS33 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,2) }, /* ttyS34 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,3) }, /* ttyS35 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,4) }, /* ttyS36 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(0,5) }, /* ttyS37 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,0) }, /* ttyS38 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,1) }, /* ttyS39 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,2) }, /* ttyS40 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,3) }, /* ttyS41 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,4) }, /* ttyS42 */ \ - { 0, BASE_BAUD, 0x302, 3, HUB6_FLAGS, C_P(1,5) }, /* ttyS43 */ -#else -#define HUB6_SERIAL_PORT_DFNS +#if defined(CONFIG_MAC_SERIAL) +#define SERIAL_DEV_OFFSET ((_machine == _MACH_prep || _machine == _MACH_chrp) ? 0 : 2) #endif -#define MCA_SERIAL_PORT_DFNS - -#define SERIAL_PORT_DFNS \ - STD_SERIAL_PORT_DEFNS \ - EXTRA_SERIAL_PORT_DEFNS \ - HUB6_SERIAL_PORT_DFNS \ - MCA_SERIAL_PORT_DFNS - #endif /* !CONFIG_GEMINI and others */ #endif /* __ASM_SERIAL_H__ */ #endif /* __KERNEL__ */ diff --git a/include/asm-ppc/smp.h b/include/asm-ppc/smp.h index 2454352aba27..7c93fdeafb26 100644 --- a/include/asm-ppc/smp.h +++ b/include/asm-ppc/smp.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.smp.h 1.12 08/16/01 07:49:31 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* smp.h: PPC specific SMP stuff. * @@ -48,7 +48,7 @@ extern void smp_local_timer_interrupt(struct pt_regs *); #define cpu_logical_map(cpu) (cpu) #define cpu_number_map(x) (x) -#define smp_processor_id() (current->processor) +#define smp_processor_id() (current_thread_info()->cpu) extern int smp_hw_index[NR_CPUS]; #define hard_smp_processor_id() (smp_hw_index[smp_processor_id()]) diff --git a/include/asm-ppc/spd8xx.h b/include/asm-ppc/spd8xx.h deleted file mode 100644 index b6c93bdfd10f..000000000000 --- a/include/asm-ppc/spd8xx.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * BK Id: SCCS/s.spd8xx.h 1.8 10/27/01 13:39:41 trini - */ -/* - * Speech Design SPD8xxTS board specific definitions - * - * Copyright (c) 2000,2001 Wolfgang Denk (wd@denx.de) - */ - -#ifdef __KERNEL__ -#ifndef __ASM_SPD8XX_H__ -#define __ASM_SPD8XX_H__ - -#include <linux/config.h> - -#include <asm/ppcboot.h> - -#define SPD_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ -#define SPD_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR SPD_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE SPD_IMAP_SIZE /* mapped size of IMMR area */ - -#define PCMCIA_MEM_ADDR ((uint)0xFE100000) -#define PCMCIA_MEM_SIZE ((uint)(64 * 1024)) - -#define IDE0_INTERRUPT 10 /* = IRQ5 */ -#define IDE1_INTERRUPT 12 /* = IRQ6 */ -#define CPM_INTERRUPT 13 /* = SIU_LEVEL6 (was: SIU_LEVEL2) */ - -/* override the default number of IDE hardware interfaces */ -#define MAX_HWIFS 2 - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0x0000 /* Offset in PCMCIA memory */ -#define IDE0_DATA_REG_OFFSET 0x0000 -#define IDE0_ERROR_REG_OFFSET 0x0081 -#define IDE0_NSECTOR_REG_OFFSET 0x0082 -#define IDE0_SECTOR_REG_OFFSET 0x0083 -#define IDE0_LCYL_REG_OFFSET 0x0084 -#define IDE0_HCYL_REG_OFFSET 0x0085 -#define IDE0_SELECT_REG_OFFSET 0x0086 -#define IDE0_STATUS_REG_OFFSET 0x0087 -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -/* - * Definitions for IDE1 Interface - */ -#define IDE1_BASE_OFFSET 0x0C00 /* Offset in PCMCIA memory */ -#define IDE1_DATA_REG_OFFSET 0x0000 -#define IDE1_ERROR_REG_OFFSET 0x0081 -#define IDE1_NSECTOR_REG_OFFSET 0x0082 -#define IDE1_SECTOR_REG_OFFSET 0x0083 -#define IDE1_LCYL_REG_OFFSET 0x0084 -#define IDE1_HCYL_REG_OFFSET 0x0085 -#define IDE1_SELECT_REG_OFFSET 0x0086 -#define IDE1_STATUS_REG_OFFSET 0x0087 -#define IDE1_CONTROL_REG_OFFSET 0x0106 -#define IDE1_IRQ_REG_OFFSET 0x000A /* not used */ - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __ASM_SPD8XX_H__ */ -#endif /* __KERNEL__ */ diff --git a/include/asm-ppc/spinlock.h b/include/asm-ppc/spinlock.h index 10d82555a428..7c18ccfe1552 100644 --- a/include/asm-ppc/spinlock.h +++ b/include/asm-ppc/spinlock.h @@ -1,10 +1,11 @@ /* - * BK Id: SCCS/s.spinlock.h 1.9 08/21/01 16:07:48 trini + * BK Id: %F% %I% %G% %U% %#% */ #ifndef __ASM_SPINLOCK_H #define __ASM_SPINLOCK_H #include <asm/system.h> +#include <asm/processor.h> #undef SPINLOCK_DEBUG @@ -40,14 +41,17 @@ static inline void spin_lock(spinlock_t *lock) unsigned long tmp; __asm__ __volatile__( - "b 1f # spin_lock\n\ -2: lwzx %0,0,%1\n\ + "b 1f # spin_lock\n\ +2:" HMT_PRIO_LOW +" lwzx %0,0,%1\n\ cmpwi 0,%0,0\n\ - bne+ 2b\n\ -1: lwarx %0,0,%1\n\ + bne+ 2b\n" + HMT_PRIO_MED +"1: lwarx %0,0,%1\n\ cmpwi 0,%0,0\n\ - bne- 2b\n\ - stwcx. %2,0,%1\n\ + bne- 2b\n" + PPC405_ERR77(0,%1) +" stwcx. %2,0,%1\n\ bne- 2b\n\ isync" : "=&r"(tmp) @@ -108,15 +112,18 @@ static __inline__ void read_lock(rwlock_t *rw) unsigned int tmp; __asm__ __volatile__( - "b 2f # read_lock\n\ -1: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - blt+ 1b\n\ -2: lwarx %0,0,%1\n\ - addic. %0,%0,1\n\ - ble- 1b\n\ - stwcx. %0,0,%1\n\ - bne- 2b\n\ + "b 2f # read_lock\n\ +1:" HMT_PRIO_LOW +" lwzx %0,0,%1\n\ + cmpwi 0,%0,0\n\ + blt+ 1b\n" + HMT_PRIO_MED +"2: lwarx %0,0,%1\n\ + addic. %0,%0,1\n\ + ble- 1b\n" + PPC405_ERR77(0,%1) +" stwcx. %0,0,%1\n\ + bne- 2b\n\ isync" : "=&r"(tmp) : "r"(&rw->lock) @@ -128,11 +135,12 @@ static __inline__ void read_unlock(rwlock_t *rw) unsigned int tmp; __asm__ __volatile__( - "eieio # read_unlock\n\ -1: lwarx %0,0,%1\n\ - addic %0,%0,-1\n\ - stwcx. %0,0,%1\n\ - bne- 1b" + "eieio # read_unlock\n\ +1: lwarx %0,0,%1\n\ + addic %0,%0,-1\n" + PPC405_ERR77(0,%1) +" stwcx. %0,0,%1\n\ + bne- 1b" : "=&r"(tmp) : "r"(&rw->lock) : "cr0", "memory"); @@ -143,15 +151,18 @@ static __inline__ void write_lock(rwlock_t *rw) unsigned int tmp; __asm__ __volatile__( - "b 2f # write_lock\n\ -1: lwzx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne+ 1b\n\ -2: lwarx %0,0,%1\n\ - cmpwi 0,%0,0\n\ - bne- 1b\n\ - stwcx. %2,0,%1\n\ - bne- 2b\n\ + "b 2f # write_lock\n\ +1:" HMT_PRIO_LOW +" lwzx %0,0,%1\n\ + cmpwi 0,%0,0\n\ + bne+ 1b\n" + HMT_PRIO_MED +"2: lwarx %0,0,%1\n\ + cmpwi 0,%0,0\n\ + bne- 1b\n" + PPC405_ERR77(0,%1) +" stwcx. %2,0,%1\n\ + bne- 2b\n\ isync" : "=&r"(tmp) : "r"(&rw->lock), "r"(-1) diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index 95f2d4ede8af..a99c75adf062 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.system.h 1.14 08/20/01 14:34:41 paulus + * BK Id: %F% %I% %G% %U% %#% */ /* * Copyright (C) 1999 Cort Dougan <cort@cs.nmt.edu> @@ -59,7 +59,7 @@ extern void poweroff_now(void); extern long _get_L2CR(void); extern void _set_L2CR(unsigned long); #else -#define _get_L2CR() 0 +#define _get_L2CR() 0L #define _set_L2CR(val) do { } while(0) #endif extern void via_cuda_init(void); @@ -120,18 +120,15 @@ extern void __global_restore_flags(unsigned long); #define local_irq_save(flags) __save_and_cli(flags) #define local_irq_restore(flags) __restore_flags(flags) -#endif /* __KERNEL__ */ - -#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr)))) - static __inline__ unsigned long xchg_u32(volatile void *p, unsigned long val) { unsigned long prev; __asm__ __volatile__ ("\n\ -1: lwarx %0,0,%2 \n\ - stwcx. %3,0,%2 \n\ +1: lwarx %0,0,%2 \n" + PPC405_ERR77(0,%2) +" stwcx. %3,0,%2 \n\ bne- 1b" : "=&r" (prev), "=m" (*(volatile unsigned long *)p) : "r" (p), "r" (val), "m" (*(volatile unsigned long *)p) @@ -181,8 +178,9 @@ __cmpxchg_u32(volatile int *p, int old, int new) __asm__ __volatile__ ("\n\ 1: lwarx %0,0,%2 \n\ cmpw 0,%0,%3 \n\ - bne 2f \n\ - stwcx. %4,0,%2 \n\ + bne 2f \n" + PPC405_ERR77(0,%2) +" stwcx. %4,0,%2 \n\ bne- 1b\n" #ifdef CONFIG_SMP " sync\n" @@ -222,4 +220,5 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size) (unsigned long)_n_, sizeof(*(ptr))); \ }) +#endif /* __KERNEL__ */ #endif /* __PPC_SYSTEM_H */ diff --git a/include/asm-ppc/thread_info.h b/include/asm-ppc/thread_info.h new file mode 100644 index 000000000000..caeda7e3bbfb --- /dev/null +++ b/include/asm-ppc/thread_info.h @@ -0,0 +1,76 @@ +/* thread_info.h: PPC low-level thread information + * adapted from the i386 version by Paul Mackerras + * + * Copyright (C) 2002 David Howells (dhowells@redhat.com) + * - Incorporating suggestions made by Linus Torvalds and Dave Miller + */ + +#ifndef _ASM_THREAD_INFO_H +#define _ASM_THREAD_INFO_H + +#ifdef __KERNEL__ + +#ifndef __ASSEMBLY__ +#include <asm/processor.h> + +/* + * low level task data. + */ +struct thread_info { + struct task_struct *task; /* main task structure */ + struct exec_domain *exec_domain; /* execution domain */ + unsigned long flags; /* low level flags */ + int cpu; /* cpu we're on */ +}; + +/* + * macros/functions for gaining access to the thread information structure + */ +#define INIT_THREAD_INFO(tsk) \ +{ \ + task: &tsk, \ + exec_domain: &default_exec_domain, \ + flags: 0, \ + cpu: 0, \ +} + +#define init_thread_info (init_thread_union.thread_info) +#define init_stack (init_thread_union.stack) + +/* how to get the thread information struct from C */ +static inline struct thread_info *current_thread_info(void) +{ + struct thread_info *ti; + __asm__("rlwinm %0,1,0,0,18" : "=r"(ti)); + return ti; +} + +/* thread information allocation */ +#define alloc_thread_info() ((struct thread_info *) \ + __get_free_pages(GFP_KERNEL, 1)) +#define free_thread_info(ti) free_pages((unsigned long) (ti), 1) +#define get_thread_info(ti) get_task_struct((ti)->task) +#define put_thread_info(ti) put_task_struct((ti)->task) +#define THREAD_SIZE (2*PAGE_SIZE) +#endif /* __ASSEMBLY__ */ + +/* + * thread information flag bit numbers + */ +#define TIF_SYSCALL_TRACE 0 /* syscall trace active */ +#define TIF_NOTIFY_RESUME 1 /* resumption notification requested */ +#define TIF_SIGPENDING 2 /* signal pending */ +#define TIF_NEED_RESCHED 3 /* rescheduling necessary */ +#define TIF_POLLING_NRFLAG 4 /* true if poll_idle() is polling + TIF_NEED_RESCHED */ + +/* as above, but as bit values */ +#define _TIF_SYSCALL_TRACE (1<<TIF_SYSCALL_TRACE) +#define _TIF_NOTIFY_RESUME (1<<TIF_NOTIFY_RESUME) +#define _TIF_SIGPENDING (1<<TIF_SIGPENDING) +#define _TIF_NEED_RESCHED (1<<TIF_NEED_RESCHED) +#define _TIF_POLLING_NRFLAG (1<<TIF_POLLING_NRFLAG) + +#endif /* __KERNEL__ */ + +#endif /* _ASM_THREAD_INFO_H */ diff --git a/include/asm-ppc/time.h b/include/asm-ppc/time.h index a1d7a4100fb4..f4398a47f352 100644 --- a/include/asm-ppc/time.h +++ b/include/asm-ppc/time.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.time.h 1.17 10/23/01 08:09:35 trini + * BK Id: %F% %I% %G% %U% %#% */ /* * Common time prototypes and such for all ppc machines. @@ -16,6 +16,10 @@ #include <linux/mc146818rtc.h> #include <linux/threads.h> +#ifdef CONFIG_PPC_ISERIES +#include <asm/iSeries/Paca.h> +#include <asm/iSeries/HvCall.h> +#endif #include <asm/processor.h> /* time.c */ @@ -52,6 +56,24 @@ static __inline__ void set_dec(unsigned int val) return; /* Have to let it auto-reload */ #elif defined(CONFIG_8xx_CPU6) set_dec_cpu6(val); +#elif defined(CONFIG_PPC_ISERIES) +/* + * Add code here to set the virtual decrementer in + * ItLpPaca if we have shared processors and to + * invoke the hypervisor as needed. + */ + struct Paca * paca; + int cur_dec; + + paca = (struct Paca *)mfspr(SPRG1); + if ( paca->xLpPaca.xSharedProc ) { + paca->xLpPaca.xVirtualDecr = val; + cur_dec = get_dec(); + if ( cur_dec > val ) + HvCall_setVirtualDecr(); + } + else + mtspr(SPRN_DEC, val); #else mtspr(SPRN_DEC, val); #endif @@ -69,13 +91,21 @@ extern __inline__ int const __USE_RTC(void) { extern __inline__ unsigned long get_tbl(void) { unsigned long tbl; +#if defined(CONFIG_403GCX) + asm volatile("mfspr %0, 0x3dd" : "=r" (tbl)); +#else asm volatile("mftb %0" : "=r" (tbl)); +#endif return tbl; } extern __inline__ unsigned long get_tbu(void) { unsigned long tbl; +#if defined(CONFIG_403GCX) + asm volatile("mfspr %0, 0x3dc" : "=r" (tbl)); +#else asm volatile("mftbu %0" : "=r" (tbl)); +#endif return tbl; } diff --git a/include/asm-ppc/todc.h b/include/asm-ppc/todc.h new file mode 100644 index 000000000000..9b4d58e9efeb --- /dev/null +++ b/include/asm-ppc/todc.h @@ -0,0 +1,380 @@ +/* + * include/asm-ppc/todc.h + * + * Definitions for the M48Txx and mc146818 series of Time of day/Real Time + * Clock chips. + * + * Author: Mark A. Greer + * mgreer@mvista.com + * + * Copyright 2001 MontaVista Software Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/* + * Support for the M48T37/M48T59/.../mc146818 Real Time Clock chips. + * Purpose is to make one generic file that handles all of these chips instead + * of every platform implementing the same code over & over again. + */ + +#ifndef __PPC_KERNEL_TODC_H +#define __PPC_KERNEL_TODC_H + +typedef struct { + uint rtc_type; /* your particular chip */ + + /* + * Following are the addresses of the AS0, AS1, and DATA registers + * of these chips. Note that these are board-specific. + */ + unsigned char *nvram_as0; + unsigned char *nvram_as1; + unsigned char *nvram_data; + + /* + * Define bits to stop external set of regs from changing so + * the chip can be read/written reliably. + */ + unsigned char enable_read; + unsigned char enable_write; + + /* + * Following is the number of AS0 address bits. This is normally + * 8 but some bad hardware routes address lines incorrectly. + */ + int as0_bits; + + /* Following are the register offsets for the particular chip */ + int year; + int month; + int day_of_month; + int day_of_week; + int hours; + int minutes; + int seconds; + int control_b; + int control_a; + int watchdog; + int interrupts; + int alarm_date; + int alarm_hour; + int alarm_minutes; + int alarm_seconds; + int century; + int flags; +} todc_info_t; + +/* + * Define the types of TODC/RTC variants that are supported in + * arch/ppc/kernel/todc_time.c + * Make a new one of these for any chip somehow differs from what's already + * defined. That way, if you ever need to put in code to touch those + * bits/registers in todc_time.c, you can put it inside an + * 'if (todc_info->rtc_type == TODC_TYPE_XXX)' so you won't break + * anyone else. + */ +#define TODC_TYPE_MK48T35 1 +#define TODC_TYPE_MK48T37 2 +#define TODC_TYPE_MK48T59 3 +#define TODC_TYPE_DS1693 4 /* Dallas DS1693 RTC */ +#define TODC_TYPE_DS1743 5 /* Dallas DS1743 RTC */ +#define TODC_TYPE_DS1746 6 /* Dallas DS1746 RTC */ +#define TODC_TYPE_DS1747 7 /* Dallas DS1747 RTC */ +#define TODC_TYPE_DS1501 8 /* Dallas DS1501 RTC */ +#define TODC_TYPE_DS1643 9 /* Dallas DS1643 RTC */ +#define TODC_TYPE_PC97307 10 /* PC97307 internal RTC */ +#define TODC_TYPE_DS1557 11 /* Dallas DS1557 RTC */ +#define TODC_TYPE_MC146818 100 /* Leave room for more m48txx's */ + +/* + * Bit to clear/set to enable reads/writes to the chip + */ +#define TODC_MK48TXX_CNTL_A_R 0x40 +#define TODC_MK48TXX_CNTL_A_W 0x80 +#define TODC_MK48TXX_DAY_CB 0x80 + +#define TODC_DS1501_CNTL_B_TE 0x80 + +/* + * Define the values for the various RTC's that should to into the todc_info + * table. + */ +#define TODC_TYPE_MK48T35_YEAR 0x7fff +#define TODC_TYPE_MK48T35_MONTH 0x7ffe +#define TODC_TYPE_MK48T35_DOM 0x7ffd /* Day of Month */ +#define TODC_TYPE_MK48T35_DOW 0x7ffc /* Day of Week */ +#define TODC_TYPE_MK48T35_HOURS 0x7ffb +#define TODC_TYPE_MK48T35_MINUTES 0x7ffa +#define TODC_TYPE_MK48T35_SECONDS 0x7ff9 +#define TODC_TYPE_MK48T35_CNTL_B 0x7ff9 +#define TODC_TYPE_MK48T35_CNTL_A 0x7ff8 +#define TODC_TYPE_MK48T35_WATCHDOG 0x0000 +#define TODC_TYPE_MK48T35_INTERRUPTS 0x0000 +#define TODC_TYPE_MK48T35_ALARM_DATE 0x0000 +#define TODC_TYPE_MK48T35_ALARM_HOUR 0x0000 +#define TODC_TYPE_MK48T35_ALARM_MINUTES 0x0000 +#define TODC_TYPE_MK48T35_ALARM_SECONDS 0x0000 +#define TODC_TYPE_MK48T35_CENTURY 0x0000 +#define TODC_TYPE_MK48T35_FLAGS 0x0000 + +#define TODC_TYPE_MK48T37_YEAR 0x7fff +#define TODC_TYPE_MK48T37_MONTH 0x7ffe +#define TODC_TYPE_MK48T37_DOM 0x7ffd /* Day of Month */ +#define TODC_TYPE_MK48T37_DOW 0x7ffc /* Day of Week */ +#define TODC_TYPE_MK48T37_HOURS 0x7ffb +#define TODC_TYPE_MK48T37_MINUTES 0x7ffa +#define TODC_TYPE_MK48T37_SECONDS 0x7ff9 +#define TODC_TYPE_MK48T37_CNTL_B 0x7ff9 +#define TODC_TYPE_MK48T37_CNTL_A 0x7ff8 +#define TODC_TYPE_MK48T37_WATCHDOG 0x7ff7 +#define TODC_TYPE_MK48T37_INTERRUPTS 0x7ff6 +#define TODC_TYPE_MK48T37_ALARM_DATE 0x7ff5 +#define TODC_TYPE_MK48T37_ALARM_HOUR 0x7ff4 +#define TODC_TYPE_MK48T37_ALARM_MINUTES 0x7ff3 +#define TODC_TYPE_MK48T37_ALARM_SECONDS 0x7ff2 +#define TODC_TYPE_MK48T37_CENTURY 0x7ff1 +#define TODC_TYPE_MK48T37_FLAGS 0x7ff0 + +#define TODC_TYPE_MK48T59_YEAR 0x1fff +#define TODC_TYPE_MK48T59_MONTH 0x1ffe +#define TODC_TYPE_MK48T59_DOM 0x1ffd /* Day of Month */ +#define TODC_TYPE_MK48T59_DOW 0x1ffc /* Day of Week */ +#define TODC_TYPE_MK48T59_HOURS 0x1ffb +#define TODC_TYPE_MK48T59_MINUTES 0x1ffa +#define TODC_TYPE_MK48T59_SECONDS 0x1ff9 +#define TODC_TYPE_MK48T59_CNTL_B 0x1ff9 +#define TODC_TYPE_MK48T59_CNTL_A 0x1ff8 +#define TODC_TYPE_MK48T59_WATCHDOG 0x1fff +#define TODC_TYPE_MK48T59_INTERRUPTS 0x1fff +#define TODC_TYPE_MK48T59_ALARM_DATE 0x1fff +#define TODC_TYPE_MK48T59_ALARM_HOUR 0x1fff +#define TODC_TYPE_MK48T59_ALARM_MINUTES 0x1fff +#define TODC_TYPE_MK48T59_ALARM_SECONDS 0x1fff +#define TODC_TYPE_MK48T59_CENTURY 0x1fff +#define TODC_TYPE_MK48T59_FLAGS 0x1fff + +#define TODC_TYPE_DS1501_YEAR 0x06 +#define TODC_TYPE_DS1501_MONTH 0x05 +#define TODC_TYPE_DS1501_DOM 0x04 /* Day of Month */ +#define TODC_TYPE_DS1501_DOW 0x03 /* Day of Week */ +#define TODC_TYPE_DS1501_HOURS 0x02 +#define TODC_TYPE_DS1501_MINUTES 0x01 +#define TODC_TYPE_DS1501_SECONDS 0x00 +#define TODC_TYPE_DS1501_CNTL_B 0x0f +#define TODC_TYPE_DS1501_CNTL_A 0x0f +#define TODC_TYPE_DS1501_WATCHDOG 0xff +#define TODC_TYPE_DS1501_INTERRUPTS 0xff +#define TODC_TYPE_DS1501_ALARM_DATE 0x0b +#define TODC_TYPE_DS1501_ALARM_HOUR 0x0a +#define TODC_TYPE_DS1501_ALARM_MINUTES 0x09 +#define TODC_TYPE_DS1501_ALARM_SECONDS 0x08 +#define TODC_TYPE_DS1501_CENTURY 0x07 +#define TODC_TYPE_DS1501_FLAGS 0xff + +#define TODC_TYPE_DS1557_YEAR 0x7ffff +#define TODC_TYPE_DS1557_MONTH 0x7fffe +#define TODC_TYPE_DS1557_DOM 0x7fffd /* Day of Month */ +#define TODC_TYPE_DS1557_DOW 0x7fffc /* Day of Week */ +#define TODC_TYPE_DS1557_HOURS 0x7fffb +#define TODC_TYPE_DS1557_MINUTES 0x7fffa +#define TODC_TYPE_DS1557_SECONDS 0x7fff9 +#define TODC_TYPE_DS1557_CNTL_B 0x7fff9 +#define TODC_TYPE_DS1557_CNTL_A 0x7fff8 /* control_a R/W regs */ +#define TODC_TYPE_DS1557_WATCHDOG 0x7fff7 +#define TODC_TYPE_DS1557_INTERRUPTS 0x7fff6 +#define TODC_TYPE_DS1557_ALARM_DATE 0x7fff5 +#define TODC_TYPE_DS1557_ALARM_HOUR 0x7fff4 +#define TODC_TYPE_DS1557_ALARM_MINUTES 0x7fff3 +#define TODC_TYPE_DS1557_ALARM_SECONDS 0x7fff2 +#define TODC_TYPE_DS1557_CENTURY 0x7fff8 +#define TODC_TYPE_DS1557_FLAGS 0x7fff0 + +#define TODC_TYPE_DS1643_YEAR 0x1fff +#define TODC_TYPE_DS1643_MONTH 0x1ffe +#define TODC_TYPE_DS1643_DOM 0x1ffd /* Day of Month */ +#define TODC_TYPE_DS1643_DOW 0x1ffc /* Day of Week */ +#define TODC_TYPE_DS1643_HOURS 0x1ffb +#define TODC_TYPE_DS1643_MINUTES 0x1ffa +#define TODC_TYPE_DS1643_SECONDS 0x1ff9 +#define TODC_TYPE_DS1643_CNTL_B 0x1ff9 +#define TODC_TYPE_DS1643_CNTL_A 0x1ff8 /* control_a R/W regs */ +#define TODC_TYPE_DS1643_WATCHDOG 0x1fff +#define TODC_TYPE_DS1643_INTERRUPTS 0x1fff +#define TODC_TYPE_DS1643_ALARM_DATE 0x1fff +#define TODC_TYPE_DS1643_ALARM_HOUR 0x1fff +#define TODC_TYPE_DS1643_ALARM_MINUTES 0x1fff +#define TODC_TYPE_DS1643_ALARM_SECONDS 0x1fff +#define TODC_TYPE_DS1643_CENTURY 0x1ff8 +#define TODC_TYPE_DS1643_FLAGS 0x1fff + +#define TODC_TYPE_DS1693_YEAR 0x09 +#define TODC_TYPE_DS1693_MONTH 0x08 +#define TODC_TYPE_DS1693_DOM 0x07 /* Day of Month */ +#define TODC_TYPE_DS1693_DOW 0x06 /* Day of Week */ +#define TODC_TYPE_DS1693_HOURS 0x04 +#define TODC_TYPE_DS1693_MINUTES 0x02 +#define TODC_TYPE_DS1693_SECONDS 0x00 +#define TODC_TYPE_DS1693_CNTL_B 0x0b +#define TODC_TYPE_DS1693_CNTL_A 0x0a +#define TODC_TYPE_DS1693_WATCHDOG 0xff +#define TODC_TYPE_DS1693_INTERRUPTS 0xff +#define TODC_TYPE_DS1693_ALARM_DATE 0x49 +#define TODC_TYPE_DS1693_ALARM_HOUR 0x05 +#define TODC_TYPE_DS1693_ALARM_MINUTES 0x03 +#define TODC_TYPE_DS1693_ALARM_SECONDS 0x01 +#define TODC_TYPE_DS1693_CENTURY 0x48 +#define TODC_TYPE_DS1693_FLAGS 0xff + +#define TODC_TYPE_DS1743_YEAR 0x1fff +#define TODC_TYPE_DS1743_MONTH 0x1ffe +#define TODC_TYPE_DS1743_DOM 0x1ffd /* Day of Month */ +#define TODC_TYPE_DS1743_DOW 0x1ffc /* Day of Week */ +#define TODC_TYPE_DS1743_HOURS 0x1ffb +#define TODC_TYPE_DS1743_MINUTES 0x1ffa +#define TODC_TYPE_DS1743_SECONDS 0x1ff9 +#define TODC_TYPE_DS1743_CNTL_B 0x1ff9 +#define TODC_TYPE_DS1743_CNTL_A 0x1ff8 /* control_a R/W regs */ +#define TODC_TYPE_DS1743_WATCHDOG 0x1fff +#define TODC_TYPE_DS1743_INTERRUPTS 0x1fff +#define TODC_TYPE_DS1743_ALARM_DATE 0x1fff +#define TODC_TYPE_DS1743_ALARM_HOUR 0x1fff +#define TODC_TYPE_DS1743_ALARM_MINUTES 0x1fff +#define TODC_TYPE_DS1743_ALARM_SECONDS 0x1fff +#define TODC_TYPE_DS1743_CENTURY 0x1ff8 +#define TODC_TYPE_DS1743_FLAGS 0x1fff + +#define TODC_TYPE_DS1746_YEAR 0x1ffff +#define TODC_TYPE_DS1746_MONTH 0x1fffe +#define TODC_TYPE_DS1746_DOM 0x1fffd /* Day of Month */ +#define TODC_TYPE_DS1746_DOW 0x1fffc /* Day of Week */ +#define TODC_TYPE_DS1746_HOURS 0x1fffb +#define TODC_TYPE_DS1746_MINUTES 0x1fffa +#define TODC_TYPE_DS1746_SECONDS 0x1fff9 +#define TODC_TYPE_DS1746_CNTL_B 0x1fff9 +#define TODC_TYPE_DS1746_CNTL_A 0x1fff8 /* control_a R/W regs */ +#define TODC_TYPE_DS1746_WATCHDOG 0x00000 +#define TODC_TYPE_DS1746_INTERRUPTS 0x00000 +#define TODC_TYPE_DS1746_ALARM_DATE 0x00000 +#define TODC_TYPE_DS1746_ALARM_HOUR 0x00000 +#define TODC_TYPE_DS1746_ALARM_MINUTES 0x00000 +#define TODC_TYPE_DS1746_ALARM_SECONDS 0x00000 +#define TODC_TYPE_DS1746_CENTURY 0x00000 +#define TODC_TYPE_DS1746_FLAGS 0x00000 + +#define TODC_TYPE_DS1747_YEAR 0x1ffff +#define TODC_TYPE_DS1747_MONTH 0x1fffe +#define TODC_TYPE_DS1747_DOM 0x1fffd /* Day of Month */ +#define TODC_TYPE_DS1747_DOW 0x1fffc /* Day of Week */ +#define TODC_TYPE_DS1747_HOURS 0x1fffb +#define TODC_TYPE_DS1747_MINUTES 0x1fffa +#define TODC_TYPE_DS1747_SECONDS 0x1fff9 +#define TODC_TYPE_DS1747_CNTL_B 0x1fff9 +#define TODC_TYPE_DS1747_CNTL_A 0x1fff8 /* control_a R/W regs */ +#define TODC_TYPE_DS1747_WATCHDOG 0x00000 +#define TODC_TYPE_DS1747_INTERRUPTS 0x00000 +#define TODC_TYPE_DS1747_ALARM_DATE 0x00000 +#define TODC_TYPE_DS1747_ALARM_HOUR 0x00000 +#define TODC_TYPE_DS1747_ALARM_MINUTES 0x00000 +#define TODC_TYPE_DS1747_ALARM_SECONDS 0x00000 +#define TODC_TYPE_DS1747_CENTURY 0x00000 +#define TODC_TYPE_DS1747_FLAGS 0x00000 + +#define TODC_TYPE_MC146818_YEAR 0x09 +#define TODC_TYPE_MC146818_MONTH 0x08 +#define TODC_TYPE_MC146818_DOM 0x07 /* Day of Month */ +#define TODC_TYPE_MC146818_DOW 0x06 /* Day of Week */ +#define TODC_TYPE_MC146818_HOURS 0x04 +#define TODC_TYPE_MC146818_MINUTES 0x02 +#define TODC_TYPE_MC146818_SECONDS 0x00 +#define TODC_TYPE_MC146818_CNTL_B 0x0a +#define TODC_TYPE_MC146818_CNTL_A 0x0b /* control_a R/W regs */ +#define TODC_TYPE_MC146818_WATCHDOG 0x0c +#define TODC_TYPE_MC146818_INTERRUPTS 0x0d +#define TODC_TYPE_MC146818_ALARM_DATE 0xff +#define TODC_TYPE_MC146818_ALARM_HOUR 0x05 +#define TODC_TYPE_MC146818_ALARM_MINUTES 0x03 +#define TODC_TYPE_MC146818_ALARM_SECONDS 0x01 +#define TODC_TYPE_MC146818_CENTURY 0xff +#define TODC_TYPE_MC146818_FLAGS 0xff + +#define TODC_TYPE_PC97307_YEAR 0x09 +#define TODC_TYPE_PC97307_MONTH 0x08 +#define TODC_TYPE_PC97307_DOM 0x07 /* Day of Month */ +#define TODC_TYPE_PC97307_DOW 0x06 /* Day of Week */ +#define TODC_TYPE_PC97307_HOURS 0x04 +#define TODC_TYPE_PC97307_MINUTES 0x02 +#define TODC_TYPE_PC97307_SECONDS 0x00 +#define TODC_TYPE_PC97307_CNTL_B 0x0a +#define TODC_TYPE_PC97307_CNTL_A 0x0b /* control_a R/W regs */ +#define TODC_TYPE_PC97307_WATCHDOG 0x0c +#define TODC_TYPE_PC97307_INTERRUPTS 0x0d +#define TODC_TYPE_PC97307_ALARM_DATE 0xff +#define TODC_TYPE_PC97307_ALARM_HOUR 0x05 +#define TODC_TYPE_PC97307_ALARM_MINUTES 0x03 +#define TODC_TYPE_PC97307_ALARM_SECONDS 0x01 +#define TODC_TYPE_PC97307_CENTURY 0xff +#define TODC_TYPE_PC97307_FLAGS 0xff + +/* + * Define macros to allocate and init the todc_info_t table that will + * be used by the todc_time.c routines. + */ +#define TODC_ALLOC() \ + static todc_info_t todc_info_alloc; \ + todc_info_t *todc_info = &todc_info_alloc; + +#define TODC_INIT(clock_type, as0, as1, data, bits) { \ + todc_info->rtc_type = clock_type; \ + \ + todc_info->nvram_as0 = (unsigned char *)(as0); \ + todc_info->nvram_as1 = (unsigned char *)(as1); \ + todc_info->nvram_data = (unsigned char *)(data); \ + \ + todc_info->as0_bits = (bits); \ + \ + todc_info->year = clock_type ##_YEAR; \ + todc_info->month = clock_type ##_MONTH; \ + todc_info->day_of_month = clock_type ##_DOM; \ + todc_info->day_of_week = clock_type ##_DOW; \ + todc_info->hours = clock_type ##_HOURS; \ + todc_info->minutes = clock_type ##_MINUTES; \ + todc_info->seconds = clock_type ##_SECONDS; \ + todc_info->control_b = clock_type ##_CNTL_B; \ + todc_info->control_a = clock_type ##_CNTL_A; \ + todc_info->watchdog = clock_type ##_WATCHDOG; \ + todc_info->interrupts = clock_type ##_INTERRUPTS; \ + todc_info->alarm_date = clock_type ##_ALARM_DATE; \ + todc_info->alarm_hour = clock_type ##_ALARM_HOUR; \ + todc_info->alarm_minutes = clock_type ##_ALARM_MINUTES; \ + todc_info->alarm_seconds = clock_type ##_ALARM_SECONDS; \ + todc_info->century = clock_type ##_CENTURY; \ + todc_info->flags = clock_type ##_FLAGS; \ +} + +#ifndef BCD_TO_BIN +#define BCD_TO_BIN(val) ((val)=((val)&15) + ((val)>>4)*10) +#endif + +#ifndef BIN_TO_BCD +#define BIN_TO_BCD(val) ((val)=(((val)/10)<<4) + (val)%10) +#endif + +extern todc_info_t *todc_info; + +unsigned char todc_direct_read_val(int addr); +void todc_direct_write_val(int addr, unsigned char val); +unsigned char todc_m48txx_read_val(int addr); +void todc_m48txx_write_val(int addr, unsigned char val); +unsigned char todc_mc146818_read_val(int addr); +void todc_mc146818_write_val(int addr, unsigned char val); + +long todc_time_init(void); +unsigned long todc_get_rtc_time(void); +int todc_set_rtc_time(unsigned long nowtime); +void todc_calibrate_decr(void); + +#endif /* __PPC_KERNEL_TODC_H */ diff --git a/include/asm-ppc/tqm8xx.h b/include/asm-ppc/tqm8xx.h deleted file mode 100644 index fb5b4df54e8a..000000000000 --- a/include/asm-ppc/tqm8xx.h +++ /dev/null @@ -1,54 +0,0 @@ -/* - * BK Id: SCCS/s.tqm8xx.h 1.8 08/30/01 09:01:04 trini - */ -/* - * TQM8xx(L) board specific definitions - * - * Copyright (c) 1999,2000,2001 Wolfgang Denk (wd@denx.de) - */ - -#ifndef __MACH_TQM8xx_H -#define __MACH_TQM8xx_H - -#include <linux/config.h> - -#include <asm/ppcboot.h> - -#define TQM_IMMR_BASE 0xFFF00000 /* phys. addr of IMMR */ -#define TQM_IMAP_SIZE (64 * 1024) /* size of mapped area */ - -#define IMAP_ADDR TQM_IMMR_BASE /* physical base address of IMMR area */ -#define IMAP_SIZE TQM_IMAP_SIZE /* mapped size of IMMR area */ - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define PCMCIA_MEM_SIZE ( 64 << 20 ) - -#define MAX_HWIFS 1 /* overwrite default in include/asm-ppc/ide.h */ - -/* - * Definitions for IDE0 Interface - */ -#define IDE0_BASE_OFFSET 0 -#define IDE0_DATA_REG_OFFSET (PCMCIA_MEM_SIZE + 0x320) -#define IDE0_ERROR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 1) -#define IDE0_NSECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 2) -#define IDE0_SECTOR_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 3) -#define IDE0_LCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 4) -#define IDE0_HCYL_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 5) -#define IDE0_SELECT_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 6) -#define IDE0_STATUS_REG_OFFSET (2 * PCMCIA_MEM_SIZE + 0x320 + 7) -#define IDE0_CONTROL_REG_OFFSET 0x0106 -#define IDE0_IRQ_REG_OFFSET 0x000A /* not used */ - -#define IDE0_INTERRUPT 13 - - -/* We don't use the 8259. -*/ -#define NR_8259_INTS 0 - -#endif /* __MACH_TQM8xx_H */ diff --git a/include/asm-ppc/walnut.h b/include/asm-ppc/walnut.h deleted file mode 100644 index 088e6ec9dc8c..000000000000 --- a/include/asm-ppc/walnut.h +++ /dev/null @@ -1,58 +0,0 @@ -/* - * BK Id: SCCS/s.walnut.h 1.10 09/14/01 17:37:56 trini - */ -/* - * - * Copyright (c) 1999 Grant Erickson <grant@lcse.umn.edu> - * - * Copyright 2000 MontaVista Software Inc. - * PPC405 modifications - * Author: MontaVista Software, Inc. - * frank_rowand@mvista.com or source@mvista.com - * debbie_chu@mvista.com - * - * Module name: ppc405.h - * - * Description: - * Macros, definitions, and data structures specific to the IBM PowerPC - * based boards. - * - * This includes: - * - * 405GP "Walnut" evaluation board - * - */ - -#ifdef __KERNEL__ -#ifndef __WALNUT_H__ -#define __WALNUT_H__ - -#ifndef __ASSEMBLY__ -/* - * Data structure defining board information maintained by the boot - * ROM on IBM's "Walnut" evaluation board. An effort has been made to - * keep the field names consistent with the 8xx 'bd_t' board info - * structures. - */ - -typedef struct board_info { - unsigned char bi_s_version[4]; /* Version of this structure */ - unsigned char bi_r_version[30]; /* Version of the IBM ROM */ - unsigned int bi_memsize; /* DRAM installed, in bytes */ - unsigned char bi_enetaddr[6]; /* Local Ethernet MAC address */ - unsigned char bi_pci_enetaddr[6]; /* PCI Ethernet MAC address */ - unsigned int bi_procfreq; /* Processor speed, in Hz */ - unsigned int bi_plb_busfreq; /* PLB Bus speed, in Hz */ - unsigned int bi_pci_busfreq; /* PCI Bus speed, in Hz */ -} bd_t; - -#endif /* !__ASSEMBLY__ */ - -/* Memory map for the IBM "Walnut" 405GP evaluation board. - * Generic 4xx plus RTC. - */ -#define WALNUT_RTC_ADDR ((uint)0xf0001000) -#define WALNUT_RTC_SIZE ((uint)4*1024) - -#endif /* __WALNUT_H__ */ -#endif /* __KERNEL__ */ |