diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-ppc/commproc.h | 207 | ||||
| -rw-r--r-- | include/asm-ppc/open_pic.h | 3 | ||||
| -rw-r--r-- | include/asm-ppc/page.h | 6 | ||||
| -rw-r--r-- | include/asm-ppc/param.h | 12 | ||||
| -rw-r--r-- | include/asm-ppc/ppc_asm.h | 17 | ||||
| -rw-r--r-- | include/asm-ppc/system.h | 13 | ||||
| -rw-r--r-- | include/asm-ppc/tlbflush.h | 9 | ||||
| -rw-r--r-- | include/asm-ppc/uaccess.h | 8 |
8 files changed, 40 insertions, 235 deletions
diff --git a/include/asm-ppc/commproc.h b/include/asm-ppc/commproc.h index 46284e91f571..5b80101564ee 100644 --- a/include/asm-ppc/commproc.h +++ b/include/asm-ppc/commproc.h @@ -382,213 +382,6 @@ typedef struct scc_enet { ushort sen_taddrl; /* temp address (LSB) */ } scc_enet_t; -/*** MBX ************************************************************/ - -#ifdef CONFIG_MBX -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_MBX */ - -/*** RPXLITE ********************************************************/ - -#ifdef CONFIG_RPXLITE -/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) -#endif /* CONFIG_RPXLITE */ - -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_BSEIP -/* This ENET stuff is for the MPC823 with ethernet on SCC2. - * This is unique to the BSE ip-Engine board. - */ -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -/* BSE uses port B and C bits for PHY control also. -*/ -#define PB_BSE_POWERUP ((uint)0x00000004) -#define PB_BSE_FDXDIS ((uint)0x00008000) -#define PC_BSE_LOOPBACK ((ushort)0x0800) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002c00) -#endif /* CONFIG_BSEIP */ - -/*** RPXCLASSIC *****************************************************/ - -#ifdef CONFIG_RPXCLASSIC -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_RPXCLASSIC */ - -/*** TQM823L, TQM850L ***********************************************/ - -#if defined(CONFIG_TQM823L) || defined(CONFIG_TQM850L) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_TQM823L, CONFIG_TQM850L */ - -/*** FPS850L *********************************************************/ - -#ifdef CONFIG_FPS850L -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_FPS850L */ - -/*** TQM860L ********************************************************/ - -#ifdef CONFIG_TQM860L -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) -#endif /* CONFIG_TQM860L */ - -/*** SPD823TS *******************************************************/ - -#ifdef CONFIG_SPD823TS -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ -#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_SPD823TS */ - - -/*** SM850 *********************************************************/ - -/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ - -#ifdef CONFIG_SM850 -#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ -#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ -#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00260000) -#endif /* CONFIG_SM850 */ - -/*********************************************************************/ - /* SCC Event register as used by Ethernet. */ #define SCCE_ENET_GRA ((ushort)0x0080) /* Graceful stop complete */ diff --git a/include/asm-ppc/open_pic.h b/include/asm-ppc/open_pic.h index e7469eae6796..b22bf942b63d 100644 --- a/include/asm-ppc/open_pic.h +++ b/include/asm-ppc/open_pic.h @@ -55,7 +55,8 @@ extern void* OpenPIC_Addr; /* Exported functions */ extern void openpic_set_sources(int first_irq, int num_irqs, void *isr); -extern void openpic_init(int, int, int); +extern void openpic_init(int linux_irq_offset); +extern void openpic_init_nmi_irq(u_int irq); extern u_int openpic_irq(void); extern void openpic_eoi(void); extern void openpic_request_IPIs(void); diff --git a/include/asm-ppc/page.h b/include/asm-ppc/page.h index 3c24d005f8e4..4a2d88d43724 100644 --- a/include/asm-ppc/page.h +++ b/include/asm-ppc/page.h @@ -85,10 +85,12 @@ typedef unsigned long pgprot_t; /* to align the pointer to the (next) page boundary */ #define PAGE_ALIGN(addr) (((addr)+PAGE_SIZE-1)&PAGE_MASK) +struct page; extern void clear_page(void *page); extern void copy_page(void *to, void *from); -extern void clear_user_page(void *page, unsigned long vaddr); -extern void copy_user_page(void *to, void *from, unsigned long vaddr); +extern void clear_user_page(void *page, unsigned long vaddr, struct page *pg); +extern void copy_user_page(void *to, void *from, unsigned long vaddr, + struct page *pg); #ifndef CONFIG_APUS #define PPC_MEMSTART 0 diff --git a/include/asm-ppc/param.h b/include/asm-ppc/param.h index 259af01bbe8d..3d399e0f5b07 100644 --- a/include/asm-ppc/param.h +++ b/include/asm-ppc/param.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.param.h 1.8 08/20/01 22:50:29 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifndef _ASM_PPC_PARAM_H #define _ASM_PPC_PARAM_H @@ -8,6 +8,12 @@ #define HZ 100 #endif +#ifdef __KERNEL__ +#define HZ 100 /* internal timer frequency */ +#define USER_HZ 100 /* for user interfaces in "ticks" */ +#define CLOCKS_PER_SEC (USER_HZ) /* frequency at which times() counts */ +#endif + #define EXEC_PAGESIZE 4096 #ifndef NGROUPS @@ -20,8 +26,4 @@ #define MAXHOSTNAMELEN 64 /* max length of hostname */ -#ifdef __KERNEL__ -# define CLOCKS_PER_SEC HZ /* frequency at which times() counts */ -#endif - #endif diff --git a/include/asm-ppc/ppc_asm.h b/include/asm-ppc/ppc_asm.h index 0c33c12f3939..fc8516cb4f12 100644 --- a/include/asm-ppc/ppc_asm.h +++ b/include/asm-ppc/ppc_asm.h @@ -49,22 +49,13 @@ #define REST_16FPRS(n, base) REST_8FPRS(n, base); REST_8FPRS(n+8, base) #define REST_32FPRS(n, base) REST_16FPRS(n, base); REST_16FPRS(n+16, base) -/* - * Once a version of gas that understands the AltiVec instructions - * is freely available, we can do this the normal way... - paulus - */ -#define LVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(103<<1) -#define STVX(r,a,b) .long (31<<26)+((r)<<21)+((a)<<16)+((b)<<11)+(231<<1) -#define MFVSCR(r) .long (4<<26)+((r)<<21)+(770<<1) -#define MTVSCR(r) .long (4<<26)+((r)<<11)+(802<<1) - -#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); STVX(n,b,base) +#define SAVE_VR(n,b,base) li b,THREAD_VR0+(16*(n)); stvx n,b,base #define SAVE_2VR(n,b,base) SAVE_VR(n,b,base); SAVE_VR(n+1,b,base) #define SAVE_4VR(n,b,base) SAVE_2VR(n,b,base); SAVE_2VR(n+2,b,base) #define SAVE_8VR(n,b,base) SAVE_4VR(n,b,base); SAVE_4VR(n+4,b,base) #define SAVE_16VR(n,b,base) SAVE_8VR(n,b,base); SAVE_8VR(n+8,b,base) #define SAVE_32VR(n,b,base) SAVE_16VR(n,b,base); SAVE_16VR(n+16,b,base) -#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); LVX(n,b,base) +#define REST_VR(n,b,base) li b,THREAD_VR0+(16*(n)); lvx n,b,base #define REST_2VR(n,b,base) REST_VR(n,b,base); REST_VR(n+1,b,base) #define REST_4VR(n,b,base) REST_2VR(n,b,base); REST_2VR(n+2,b,base) #define REST_8VR(n,b,base) REST_4VR(n,b,base); REST_4VR(n+4,b,base) @@ -169,7 +160,11 @@ END_FTR_SECTION_IFCLR(CPU_FTR_601) #else #define FIX_SRR1(ra, rb) +#ifndef CONFIG_40x #define RFI rfi +#else +#define RFI rfi; b . /* Prevent prefetch past rfi */ +#endif #define MTMSRD(r) mtmsr r #define CLR_TOP32(r) #endif /* CONFIG_PPC64BRIDGE */ diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h index abd9620c9950..920752c47576 100644 --- a/include/asm-ppc/system.h +++ b/include/asm-ppc/system.h @@ -57,10 +57,14 @@ extern void hard_reset_now(void); extern void poweroff_now(void); #ifdef CONFIG_6xx extern long _get_L2CR(void); +extern long _get_L3CR(void); extern void _set_L2CR(unsigned long); +extern void _set_L3CR(unsigned long); #else #define _get_L2CR() 0L +#define _get_L3CR() 0L #define _set_L2CR(val) do { } while(0) +#define _set_L3CR(val) do { } while(0) #endif extern void via_cuda_init(void); extern void pmac_nvram_init(void); @@ -79,9 +83,14 @@ extern void cacheable_memzero(void *p, unsigned int nb); struct device_node; extern void note_scsi_host(struct device_node *, void *); +#define prepare_arch_schedule(prev) do { } while(0) +#define finish_arch_schedule(prev) do { } while(0) +#define prepare_arch_switch(rq) do { } while(0) +#define finish_arch_switch(rq) spin_unlock_irq(&(rq)->lock) + struct task_struct; -#define prepare_to_switch() do { } while(0) -extern void switch_to(struct task_struct *, struct task_struct *); +extern void __switch_to(struct task_struct *, struct task_struct *); +#define switch_to(prev, next, last) __switch_to((prev), (next)) struct thread_struct; extern struct task_struct *_switch(struct thread_struct *prev, diff --git a/include/asm-ppc/tlbflush.h b/include/asm-ppc/tlbflush.h index 83e6f1ae6c35..af4295e46861 100644 --- a/include/asm-ppc/tlbflush.h +++ b/include/asm-ppc/tlbflush.h @@ -21,21 +21,20 @@ extern void _tlbie(unsigned long address); extern void _tlbia(void); #if defined(CONFIG_4xx) -#define __tlbia() asm volatile ("tlbia; sync" : : : "memory") static inline void flush_tlb_all(void) - { __tlbia(); } + { _tlbia(); } static inline void flush_tlb_mm(struct mm_struct *mm) - { __tlbia(); } + { _tlbia(); } static inline void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr) { _tlbie(vmaddr); } static inline void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, unsigned long end) - { __tlbia(); } + { _tlbia(); } static inline void flush_tlb_kernel_range(unsigned long start, unsigned long end) - { __tlbia(); } + { _tlbia(); } #define update_mmu_cache(vma, addr, pte) do { } while (0) #elif defined(CONFIG_8xx) diff --git a/include/asm-ppc/uaccess.h b/include/asm-ppc/uaccess.h index 21462ee88b4b..0087efbb0d6a 100644 --- a/include/asm-ppc/uaccess.h +++ b/include/asm-ppc/uaccess.h @@ -1,5 +1,5 @@ /* - * BK Id: SCCS/s.uaccess.h 1.8 09/11/01 18:10:06 paulus + * BK Id: %F% %I% %G% %U% %#% */ #ifdef __KERNEL__ #ifndef _PPC_UACCESS_H @@ -272,7 +272,11 @@ clear_user(void *addr, unsigned long size) { if (access_ok(VERIFY_WRITE, addr, size)) return __clear_user(addr, size); - return size? -EFAULT: 0; + if ((unsigned long)addr < TASK_SIZE) { + unsigned long over = (unsigned long)addr + size - TASK_SIZE; + return __clear_user(addr, size - over) + over; + } + return size; } extern int __strncpy_from_user(char *dst, const char *src, long count); |