shared/runtime/gchelper: Add RISC-V RV64I native gchelper.

Add native gchelper support for 64 bits RISC-V RV64I targets.

Now that RV64 is under CI, this also enables platform-specific ghelper
in the Unix port.

Also changes the data type holding the register contents to something more
appropriate, so in the remote eventuality somebody wants to use this with
RV128 all they have to do is update the `__riscv_xlen` check.

Signed-off-by: Alessandro Gatti <a.gatti@frob.it>

1 files changed, 15 insertions, 14 deletions

diff --git a/shared/runtime/gchelper_generic.c b/shared/runtime/gchelper_generic.c
index f1087e199..093723137 100644
--- a/shared/runtime/gchelper_generic.c
+++ b/shared/runtime/gchelper_generic.c
@@ -150,23 +150,24 @@ static void gc_helper_get_regs(gc_helper_regs_t arr) {
     arr[10] = x29;
 }
 
-#elif defined(__riscv) && defined(__riscv_xlen) && (__riscv_xlen == 32)
+#elif defined(__riscv) && (__riscv_xlen <= 64)
 
-// Fallback implementation for RV32I, prefer gchelper_rv32i.s
+// Fallback implementation for RV32I and RV64I, prefer gchelper_rv32i.s
+// for RV32I targets or gchelper_rv64i.s for RV64I targets.
 
 static void gc_helper_get_regs(gc_helper_regs_t arr) {
-    register long s0 asm ("x8");
-    register long s1 asm ("x9");
-    register long s2 asm ("x18");
-    register long s3 asm ("x19");
-    register long s4 asm ("x20");
-    register long s5 asm ("x21");
-    register long s6 asm ("x22");
-    register long s7 asm ("x23");
-    register long s8 asm ("x24");
-    register long s9 asm ("x25");
-    register long s10 asm ("x26");
-    register long s11 asm ("x27");
+    register uintptr_t s0 asm ("x8");
+    register uintptr_t s1 asm ("x9");
+    register uintptr_t s2 asm ("x18");
+    register uintptr_t s3 asm ("x19");
+    register uintptr_t s4 asm ("x20");
+    register uintptr_t s5 asm ("x21");
+    register uintptr_t s6 asm ("x22");
+    register uintptr_t s7 asm ("x23");
+    register uintptr_t s8 asm ("x24");
+    register uintptr_t s9 asm ("x25");
+    register uintptr_t s10 asm ("x26");
+    register uintptr_t s11 asm ("x27");
     arr[0] = s0;
     arr[1] = s1;
     arr[2] = s2;