15 files changed, 91 insertions, 163 deletions
diff --git a/tests/extmod/machine_uart_irq_txidle.py b/tests/extmod/machine_uart_irq_txidle.py
index 084e98257..a56f6e3cf 100644
--- a/tests/extmod/machine_uart_irq_txidle.py
+++ b/tests/extmod/machine_uart_irq_txidle.py
@@ -10,32 +10,7 @@ except (ImportError, AttributeError):
     raise SystemExit
 
 import time, sys
-
-# Configure pins based on the target.
-if "alif" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-elif "rp2" in sys.platform:
-    uart_id = 0
-    tx_pin = "GPIO0"
-    rx_pin = "GPIO1"
-elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
-    uart_id = 0
-    tx_pin = "D1"
-    rx_pin = "D0"
-elif "samd" in sys.platform and "ItsyBitsy M4" in sys.implementation._machine:
-    uart_id = 3
-    tx_pin = "D1"
-    rx_pin = "D0"
-elif "mimxrt" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-elif "nrf" in sys.platform:
-    uart_id = 0
-    tx_pin = None
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 
 def irq(u):
@@ -46,11 +21,7 @@ text = "Hello World" * 20
 
 # Test that the IRQ is called after the write has completed.
 for bits_per_s in (2400, 9600, 115200):
-    if tx_pin is None:
-        uart = UART(uart_id, bits_per_s)
-    else:
-        uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
-
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
     uart.irq(irq, uart.IRQ_TXIDLE)
 
     # The IRQ_TXIDLE shall trigger after the message has been sent. Thus
diff --git a/tests/extmod/machine_uart_tx.py b/tests/extmod/machine_uart_tx.py
index 85bf7e9fb..70d57be46 100644
--- a/tests/extmod/machine_uart_tx.py
+++ b/tests/extmod/machine_uart_tx.py
@@ -8,50 +8,35 @@ except ImportError:
     raise SystemExit
 
 import time, sys
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 initial_delay_ms = 0
 bit_margin = 0
 timing_margin_us = 100
 
-# Configure pins based on the target.
+# Tune test parameters based on the target.
 if "alif" in sys.platform:
-    uart_id = 1
-    pins = {}
     bit_margin = 1
 elif "esp32" in sys.platform:
-    uart_id = 1
-    pins = {}
     timing_margin_us = 400
 elif "mimxrt" in sys.platform:
-    uart_id = 1
-    pins = {}
     initial_delay_ms = 20  # UART sends idle frame after init, so wait for that
     bit_margin = 1
+elif "nrf" in sys.platform:
+    timing_margin_us = 130
 elif "pyboard" in sys.platform:
-    if "STM32WB" in sys.implementation._machine:
-        uart_id = "LP1"
-    else:
-        uart_id = 4
-    pins = {}
     initial_delay_ms = 50  # UART sends idle frame after init, so wait for that
     bit_margin = 1  # first start-bit must wait to sync with the UART clock
 elif "rp2" in sys.platform:
-    uart_id = 0
-    pins = {"tx": "GPIO0", "rx": "GPIO1"}
     timing_margin_us = 180
 elif "samd" in sys.platform:
-    uart_id = 2
-    pins = {"tx": "D1", "rx": "D0"}
     timing_margin_us = 300
     bit_margin = 1
-else:
-    print("SKIP")
-    raise SystemExit
 
 # Test that write+flush takes the expected amount of time to execute.
 for bits_per_s in (2400, 9600, 115200):
     text = "Hello World"
-    uart = UART(uart_id, bits_per_s, bits=8, parity=None, stop=1, **pins)
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
     time.sleep_ms(initial_delay_ms)
 
     start_us = time.ticks_us()
diff --git a/tests/extmod_hardware/machine_uart_irq_break.py b/tests/extmod_hardware/machine_uart_irq_break.py
index 879f9cee6..1832d9883 100644
--- a/tests/extmod_hardware/machine_uart_irq_break.py
+++ b/tests/extmod_hardware/machine_uart_irq_break.py
@@ -12,23 +12,7 @@ except (ImportError, AttributeError):
     raise SystemExit
 
 import time, sys
-
-# Configure pins based on the target.
-if "esp32" in sys.platform:
-    _machine = sys.implementation._machine
-    if "ESP32S2" in _machine or "ESP32C3" in _machine or "ESP32C6" in _machine:
-        print("SKIP")
-        raise SystemExit
-    uart_id = 1
-    tx_pin = 4
-    rx_pin = 5
-elif "rp2" in sys.platform:
-    uart_id = 0
-    tx_pin = "GPIO0"
-    rx_pin = "GPIO1"
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 
 def irq(u):
@@ -37,7 +21,7 @@ def irq(u):
 
 # Test that the IRQ is called for each break received.
 for bits_per_s in (2400, 9600, 57600):
-    uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
     uart.irq(irq, uart.IRQ_BREAK)
 
     print("write", bits_per_s)
diff --git a/tests/extmod_hardware/machine_uart_irq_rx.py b/tests/extmod_hardware/machine_uart_irq_rx.py
index 3602c260e..92fe21883 100644
--- a/tests/extmod_hardware/machine_uart_irq_rx.py
+++ b/tests/extmod_hardware/machine_uart_irq_rx.py
@@ -13,49 +13,14 @@ except (ImportError, AttributeError):
 
 import time, sys
 
-byte_by_byte = False
-# Configure pins based on the target.
-if "alif" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-    rx_pin = None
-elif "esp32" in sys.platform:
-    uart_id = 1
-    tx_pin = 4
-    rx_pin = 5
-elif "pyboard" in sys.platform:
-    if "STM32WB" in sys.implementation._machine:
-        # LPUART(1) is on PA2/PA3
-        uart_id = "LP1"
-    else:
-        # UART(4) is on PA0/PA1
-        uart_id = 4
-    tx_pin = None
-    rx_pin = None
-elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
-    uart_id = 0
-    tx_pin = "D1"
-    rx_pin = "D0"
-    byte_by_byte = True
-elif "samd" in sys.platform and "ItsyBitsy M4" in sys.implementation._machine:
-    uart_id = 3
-    tx_pin = "D1"
-    rx_pin = "D0"
-elif "nrf" in sys.platform:
-    uart_id = 0
-    tx_pin = None
-    rx_pin = None
-elif "renesas-ra" in sys.platform:
-    uart_id = 9
-    tx_pin = None  # P602 @ RA6M2
-    rx_pin = None  # P601 @ RA6M2
-elif "CC3200" in sys.implementation._machine:
+if "CC3200" in sys.implementation._machine:
     # CC3200 doesn't work because it's too slow and has an allocation error in the handler.
     print("SKIP")
     raise SystemExit
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
+
+byte_by_byte = "ItsyBitsy M0" in sys.implementation._machine
 
 
 def irq(u):
@@ -67,11 +32,7 @@ text = "1234"
 # Test that the IRQ is called for each byte received.
 # Use slow baudrates so that the IRQ has time to run.
 for bits_per_s in (2400, 9600):
-    if tx_pin is None:
-        uart = UART(uart_id, bits_per_s)
-    else:
-        uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
-
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
     uart.irq(irq, uart.IRQ_RX)
 
     print("write", bits_per_s)
diff --git a/tests/extmod_hardware/machine_uart_irq_rxidle.py b/tests/extmod_hardware/machine_uart_irq_rxidle.py
index 3c743c9e0..40f781d07 100644
--- a/tests/extmod_hardware/machine_uart_irq_rxidle.py
+++ b/tests/extmod_hardware/machine_uart_irq_rxidle.py
@@ -12,52 +12,10 @@ except (ImportError, AttributeError):
     raise SystemExit
 
 import time, sys
+from target_wiring import uart_loopback_args, uart_loopback_kwargs
 
 # Target tuning options.
-tune_wait_initial_rxidle = False
-
-# Configure pins based on the target.
-if "alif" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-    rx_pin = None
-elif "esp32" in sys.platform:
-    uart_id = 1
-    tx_pin = 4
-    rx_pin = 5
-elif "mimxrt" in sys.platform:
-    uart_id = 1
-    tx_pin = None
-elif "pyboard" in sys.platform:
-    tune_wait_initial_rxidle = True
-    if "STM32WB" in sys.implementation._machine:
-        # LPUART(1) is on PA2/PA3
-        uart_id = "LP1"
-    else:
-        # UART(4) is on PA0/PA1
-        uart_id = 4
-    tx_pin = None
-    rx_pin = None
-elif "renesas-ra" in sys.platform:
-    uart_id = 9
-    tx_pin = None  # P602 @ RA6M2
-    rx_pin = None  # P601 @ RA6M2
-elif "rp2" in sys.platform:
-    uart_id = 0
-    tx_pin = "GPIO0"
-    rx_pin = "GPIO1"
-elif "samd" in sys.platform and "ItsyBitsy M0" in sys.implementation._machine:
-    uart_id = 0
-    tx_pin = "D1"
-    rx_pin = "D0"
-    byte_by_byte = True
-elif "samd" in sys.platform and "ItsyBitsy M4" in sys.implementation._machine:
-    uart_id = 3
-    tx_pin = "D1"
-    rx_pin = "D0"
-else:
-    print("Please add support for this test on this platform.")
-    raise SystemExit
+tune_wait_initial_rxidle = sys.platform == "pyboard"
 
 
 def irq(u):
@@ -71,10 +29,7 @@ for bits_per_s in (2400, 9600, 115200):
     print("========")
     print("bits_per_s:", bits_per_s)
 
-    if tx_pin is None:
-        uart = UART(uart_id, bits_per_s)
-    else:
-        uart = UART(uart_id, bits_per_s, tx=tx_pin, rx=rx_pin)
+    uart = UART(*uart_loopback_args, baudrate=bits_per_s, **uart_loopback_kwargs)
 
     # Ignore a possible initial RXIDLE condition after creating UART.
     if tune_wait_initial_rxidle:
diff --git a/tests/run-tests.py b/tests/run-tests.py
index feeaa9822..c3017542c 100755
--- a/tests/run-tests.py
+++ b/tests/run-tests.py
@@ -217,7 +217,13 @@ platform_tests_to_skip = {
 }
 
 # Tests that require `import target_wiring` to work.
-tests_requiring_target_wiring = ()
+tests_requiring_target_wiring = (
+    "extmod/machine_uart_irq_txidle.py",
+    "extmod/machine_uart_tx.py",
+    "extmod_hardware/machine_uart_irq_break.py",
+    "extmod_hardware/machine_uart_irq_rx.py",
+    "extmod_hardware/machine_uart_irq_rxidle.py",
+)
 
 
 def rm_f(fname):
diff --git a/tests/target_wiring/EK_RA6M2.py b/tests/target_wiring/EK_RA6M2.py
new file mode 100644
index 000000000..7d4a8cbbd
--- /dev/null
+++ b/tests/target_wiring/EK_RA6M2.py
@@ -0,0 +1,8 @@
+# Target wiring for EK_RA6M2.
+#
+# Connect:
+# - P601 to P602
+
+# UART(9) is on P602/P601.
+uart_loopback_args = (9,)
+uart_loopback_kwargs = {}
diff --git a/tests/target_wiring/NUCLEO_WB55.py b/tests/target_wiring/NUCLEO_WB55.py
new file mode 100644
index 000000000..ad7c120d3
--- /dev/null
+++ b/tests/target_wiring/NUCLEO_WB55.py
@@ -0,0 +1,8 @@
+# Target wiring for NUCLEO_WB55.
+#
+# Connect:
+# - PA2 to PA3
+
+# LPUART(1) is on PA2/PA3.
+uart_loopback_args = ("LP1",)
+uart_loopback_kwargs = {}
diff --git a/tests/target_wiring/PYBx.py b/tests/target_wiring/PYBx.py
new file mode 100644
index 000000000..10ce520ef
--- /dev/null
+++ b/tests/target_wiring/PYBx.py
@@ -0,0 +1,8 @@
+# Target wiring for PYBV10, PYBV11, PYBLITEV10, PYBD_SF2, PYBD_SF3, PYBD_SF6.
+#
+# Connect:
+# - X1 to X2
+
+# UART("XA") is on X1/X2  (usually UART(4) on PA0/PA1).
+uart_loopback_args = ("XA",)
+uart_loopback_kwargs = {}
diff --git a/tests/target_wiring/alif.py b/tests/target_wiring/alif.py
new file mode 100644
index 000000000..18f3cbe7e
--- /dev/null
+++ b/tests/target_wiring/alif.py
@@ -0,0 +1,7 @@
+# Target wiring for general alif board.
+#
+# Connect:
+# - UART1 TX and RX, usually P0_5 and P0_4
+
+uart_loopback_args = (1,)
+uart_loopback_kwargs = {}
diff --git a/tests/target_wiring/esp32.py b/tests/target_wiring/esp32.py
new file mode 100644
index 000000000..63d7a81a2
--- /dev/null
+++ b/tests/target_wiring/esp32.py
@@ -0,0 +1,7 @@
+# Target wiring for general esp32 board.
+#
+# Connect:
+# - GPIO4 to GPIO5
+
+uart_loopback_args = (1,)
+uart_loopback_kwargs = {"tx": 4, "rx": 5}
diff --git a/tests/target_wiring/mimxrt.py b/tests/target_wiring/mimxrt.py
new file mode 100644
index 000000000..669e90959
--- /dev/null
+++ b/tests/target_wiring/mimxrt.py
@@ -0,0 +1,7 @@
+# Target wiring for general mimxrt board.
+#
+# Connect:
+# - UART1 TX and RX, usually D0 and D1
+
+uart_loopback_args = (1,)
+uart_loopback_kwargs = {}
diff --git a/tests/target_wiring/nrf.py b/tests/target_wiring/nrf.py
new file mode 100644
index 000000000..6979dd28e
--- /dev/null
+++ b/tests/target_wiring/nrf.py
@@ -0,0 +1,7 @@
+# Target wiring for general nrf board.
+#
+# Connect:
+# - UART0 TX and RX
+
+uart_loopback_args = (0,)
+uart_loopback_kwargs = {}
diff --git a/tests/target_wiring/rp2.py b/tests/target_wiring/rp2.py
new file mode 100644
index 000000000..cb0fa0d62
--- /dev/null
+++ b/tests/target_wiring/rp2.py
@@ -0,0 +1,7 @@
+# Target wiring for general rp2 board.
+#
+# Connect:
+# - GPIO0 to GPIO1
+
+uart_loopback_args = (0,)
+uart_loopback_kwargs = {"tx": "GPIO0", "rx": "GPIO1"}
diff --git a/tests/target_wiring/samd.py b/tests/target_wiring/samd.py
new file mode 100644
index 000000000..887c43a24
--- /dev/null
+++ b/tests/target_wiring/samd.py
@@ -0,0 +1,7 @@
+# Target wiring for general samd board.
+#
+# Connect:
+# - D0 to D1
+
+uart_loopback_args = ()
+uart_loopback_kwargs = {"tx": "D1", "rx": "D0"}